1 | /* |
2 | * SuperH on-chip PCIC emulation. |
3 | * |
4 | * Copyright (c) 2008 Takashi YOSHII |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "hw/sysbus.h" |
27 | #include "hw/sh4/sh.h" |
28 | #include "hw/irq.h" |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_host.h" |
31 | #include "qemu/bswap.h" |
32 | #include "qemu/module.h" |
33 | #include "exec/address-spaces.h" |
34 | |
35 | #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" |
36 | |
37 | #define SH_PCI_HOST_BRIDGE(obj) \ |
38 | OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE) |
39 | |
40 | typedef struct SHPCIState { |
41 | PCIHostState parent_obj; |
42 | |
43 | PCIDevice *dev; |
44 | qemu_irq irq[4]; |
45 | MemoryRegion memconfig_p4; |
46 | MemoryRegion memconfig_a7; |
47 | MemoryRegion isa; |
48 | uint32_t par; |
49 | uint32_t mbr; |
50 | uint32_t iobr; |
51 | } SHPCIState; |
52 | |
53 | static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, |
54 | unsigned size) |
55 | { |
56 | SHPCIState *pcic = p; |
57 | PCIHostState *phb = PCI_HOST_BRIDGE(pcic); |
58 | |
59 | switch(addr) { |
60 | case 0 ... 0xfc: |
61 | stl_le_p(pcic->dev->config + addr, val); |
62 | break; |
63 | case 0x1c0: |
64 | pcic->par = val; |
65 | break; |
66 | case 0x1c4: |
67 | pcic->mbr = val & 0xff000001; |
68 | break; |
69 | case 0x1c8: |
70 | if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { |
71 | memory_region_del_subregion(get_system_memory(), &pcic->isa); |
72 | pcic->iobr = val & 0xfffc0001; |
73 | memory_region_add_subregion(get_system_memory(), |
74 | pcic->iobr & 0xfffc0000, &pcic->isa); |
75 | } |
76 | break; |
77 | case 0x220: |
78 | pci_data_write(phb->bus, pcic->par, val, 4); |
79 | break; |
80 | } |
81 | } |
82 | |
83 | static uint64_t sh_pci_reg_read (void *p, hwaddr addr, |
84 | unsigned size) |
85 | { |
86 | SHPCIState *pcic = p; |
87 | PCIHostState *phb = PCI_HOST_BRIDGE(pcic); |
88 | |
89 | switch(addr) { |
90 | case 0 ... 0xfc: |
91 | return ldl_le_p(pcic->dev->config + addr); |
92 | case 0x1c0: |
93 | return pcic->par; |
94 | case 0x1c4: |
95 | return pcic->mbr; |
96 | case 0x1c8: |
97 | return pcic->iobr; |
98 | case 0x220: |
99 | return pci_data_read(phb->bus, pcic->par, 4); |
100 | } |
101 | return 0; |
102 | } |
103 | |
104 | static const MemoryRegionOps sh_pci_reg_ops = { |
105 | .read = sh_pci_reg_read, |
106 | .write = sh_pci_reg_write, |
107 | .endianness = DEVICE_NATIVE_ENDIAN, |
108 | .valid = { |
109 | .min_access_size = 4, |
110 | .max_access_size = 4, |
111 | }, |
112 | }; |
113 | |
114 | static int sh_pci_map_irq(PCIDevice *d, int irq_num) |
115 | { |
116 | return (d->devfn >> 3); |
117 | } |
118 | |
119 | static void sh_pci_set_irq(void *opaque, int irq_num, int level) |
120 | { |
121 | qemu_irq *pic = opaque; |
122 | |
123 | qemu_set_irq(pic[irq_num], level); |
124 | } |
125 | |
126 | static void sh_pci_device_realize(DeviceState *dev, Error **errp) |
127 | { |
128 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
129 | SHPCIState *s = SH_PCI_HOST_BRIDGE(dev); |
130 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
131 | int i; |
132 | |
133 | for (i = 0; i < 4; i++) { |
134 | sysbus_init_irq(sbd, &s->irq[i]); |
135 | } |
136 | phb->bus = pci_register_root_bus(DEVICE(dev), "pci" , |
137 | sh_pci_set_irq, sh_pci_map_irq, |
138 | s->irq, |
139 | get_system_memory(), |
140 | get_system_io(), |
141 | PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS); |
142 | memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s, |
143 | "sh_pci" , 0x224); |
144 | memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2" , |
145 | &s->memconfig_p4, 0, 0x224); |
146 | memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa" , |
147 | get_system_io(), 0, 0x40000); |
148 | sysbus_init_mmio(sbd, &s->memconfig_p4); |
149 | sysbus_init_mmio(sbd, &s->memconfig_a7); |
150 | s->iobr = 0xfe240000; |
151 | memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); |
152 | |
153 | s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host" ); |
154 | } |
155 | |
156 | static void sh_pci_host_realize(PCIDevice *d, Error **errp) |
157 | { |
158 | pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); |
159 | pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | |
160 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
161 | } |
162 | |
163 | static void sh_pci_host_class_init(ObjectClass *klass, void *data) |
164 | { |
165 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
166 | DeviceClass *dc = DEVICE_CLASS(klass); |
167 | |
168 | k->realize = sh_pci_host_realize; |
169 | k->vendor_id = PCI_VENDOR_ID_HITACHI; |
170 | k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R; |
171 | /* |
172 | * PCI-facing part of the host bridge, not usable without the |
173 | * host-facing part, which can't be device_add'ed, yet. |
174 | */ |
175 | dc->user_creatable = false; |
176 | } |
177 | |
178 | static const TypeInfo sh_pci_host_info = { |
179 | .name = "sh_pci_host" , |
180 | .parent = TYPE_PCI_DEVICE, |
181 | .instance_size = sizeof(PCIDevice), |
182 | .class_init = sh_pci_host_class_init, |
183 | .interfaces = (InterfaceInfo[]) { |
184 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
185 | { }, |
186 | }, |
187 | }; |
188 | |
189 | static void sh_pci_device_class_init(ObjectClass *klass, void *data) |
190 | { |
191 | DeviceClass *dc = DEVICE_CLASS(klass); |
192 | |
193 | dc->realize = sh_pci_device_realize; |
194 | } |
195 | |
196 | static const TypeInfo sh_pci_device_info = { |
197 | .name = TYPE_SH_PCI_HOST_BRIDGE, |
198 | .parent = TYPE_PCI_HOST_BRIDGE, |
199 | .instance_size = sizeof(SHPCIState), |
200 | .class_init = sh_pci_device_class_init, |
201 | }; |
202 | |
203 | static void sh_pci_register_types(void) |
204 | { |
205 | type_register_static(&sh_pci_device_info); |
206 | type_register_static(&sh_pci_host_info); |
207 | } |
208 | |
209 | type_init(sh_pci_register_types) |
210 | |