1 | /* |
2 | * QEMU Sun4v/Niagara System Emulator |
3 | * |
4 | * Copyright (c) 2016 Artyom Tarasenko |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qemu/units.h" |
27 | #include "cpu.h" |
28 | #include "hw/boards.h" |
29 | #include "hw/char/serial.h" |
30 | #include "hw/misc/unimp.h" |
31 | #include "hw/loader.h" |
32 | #include "hw/sparc/sparc64.h" |
33 | #include "hw/timer/sun4v-rtc.h" |
34 | #include "exec/address-spaces.h" |
35 | #include "sysemu/block-backend.h" |
36 | #include "qemu/error-report.h" |
37 | #include "sysemu/qtest.h" |
38 | #include "sysemu/sysemu.h" |
39 | |
40 | typedef struct NiagaraBoardState { |
41 | MemoryRegion hv_ram; |
42 | MemoryRegion partition_ram; |
43 | MemoryRegion nvram; |
44 | MemoryRegion md_rom; |
45 | MemoryRegion hv_rom; |
46 | MemoryRegion vdisk_ram; |
47 | MemoryRegion prom; |
48 | } NiagaraBoardState; |
49 | |
50 | #define NIAGARA_HV_RAM_BASE 0x100000ULL |
51 | #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */ |
52 | |
53 | #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL |
54 | |
55 | #define NIAGARA_UART_BASE 0x1f10000000ULL |
56 | |
57 | #define NIAGARA_NVRAM_BASE 0x1f11000000ULL |
58 | #define NIAGARA_NVRAM_SIZE 0x2000 |
59 | |
60 | #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL |
61 | #define NIAGARA_MD_ROM_SIZE 0x2000 |
62 | |
63 | #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL |
64 | #define NIAGARA_HV_ROM_SIZE 0x2000 |
65 | |
66 | #define NIAGARA_IOBBASE 0x9800000000ULL |
67 | #define NIAGARA_IOBSIZE 0x0100000000ULL |
68 | |
69 | #define NIAGARA_VDISK_BASE 0x1f40000000ULL |
70 | #define NIAGARA_RTC_BASE 0xfff0c1fff8ULL |
71 | #define NIAGARA_UART_BASE 0x1f10000000ULL |
72 | |
73 | /* Firmware layout |
74 | * |
75 | * |------------------| |
76 | * | openboot.bin | |
77 | * |------------------| PROM_ADDR + OBP_OFFSET |
78 | * | q.bin | |
79 | * |------------------| PROM_ADDR + Q_OFFSET |
80 | * | reset.bin | |
81 | * |------------------| PROM_ADDR |
82 | */ |
83 | #define NIAGARA_PROM_BASE 0xfff0000000ULL |
84 | #define NIAGARA_Q_OFFSET 0x10000ULL |
85 | #define NIAGARA_OBP_OFFSET 0x80000ULL |
86 | #define PROM_SIZE_MAX (4 * MiB) |
87 | |
88 | static void add_rom_or_fail(const char *file, const hwaddr addr) |
89 | { |
90 | /* XXX remove qtest_enabled() check once firmware files are |
91 | * in the qemu tree |
92 | */ |
93 | if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) { |
94 | error_report("Unable to load a firmware for -M niagara" ); |
95 | exit(1); |
96 | } |
97 | |
98 | } |
99 | /* Niagara hardware initialisation */ |
100 | static void niagara_init(MachineState *machine) |
101 | { |
102 | NiagaraBoardState *s = g_new(NiagaraBoardState, 1); |
103 | DriveInfo *dinfo = drive_get_next(IF_PFLASH); |
104 | MemoryRegion *sysmem = get_system_memory(); |
105 | |
106 | /* init CPUs */ |
107 | sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE); |
108 | /* set up devices */ |
109 | memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram" , |
110 | NIAGARA_HV_RAM_SIZE); |
111 | memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram); |
112 | |
113 | memory_region_allocate_system_memory(&s->partition_ram, NULL, |
114 | "sun4v-partition.ram" , |
115 | machine->ram_size); |
116 | memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE, |
117 | &s->partition_ram); |
118 | |
119 | memory_region_allocate_system_memory(&s->nvram, NULL, |
120 | "sun4v.nvram" , NIAGARA_NVRAM_SIZE); |
121 | memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram); |
122 | memory_region_allocate_system_memory(&s->md_rom, NULL, |
123 | "sun4v-md.rom" , NIAGARA_MD_ROM_SIZE); |
124 | memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom); |
125 | memory_region_allocate_system_memory(&s->hv_rom, NULL, |
126 | "sun4v-hv.rom" , NIAGARA_HV_ROM_SIZE); |
127 | memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom); |
128 | memory_region_allocate_system_memory(&s->prom, NULL, |
129 | "sun4v.prom" , PROM_SIZE_MAX); |
130 | memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom); |
131 | |
132 | add_rom_or_fail("nvram1" , NIAGARA_NVRAM_BASE); |
133 | add_rom_or_fail("1up-md.bin" , NIAGARA_MD_ROM_BASE); |
134 | add_rom_or_fail("1up-hv.bin" , NIAGARA_HV_ROM_BASE); |
135 | |
136 | add_rom_or_fail("reset.bin" , NIAGARA_PROM_BASE); |
137 | add_rom_or_fail("q.bin" , NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET); |
138 | add_rom_or_fail("openboot.bin" , NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET); |
139 | |
140 | /* the virtual ramdisk is kind of initrd, but it resides |
141 | outside of the partition RAM */ |
142 | if (dinfo) { |
143 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); |
144 | int size = blk_getlength(blk); |
145 | if (size > 0) { |
146 | memory_region_allocate_system_memory(&s->vdisk_ram, NULL, |
147 | "sun4v_vdisk.ram" , size); |
148 | memory_region_add_subregion(get_system_memory(), |
149 | NIAGARA_VDISK_BASE, &s->vdisk_ram); |
150 | dinfo->is_default = 1; |
151 | rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1); |
152 | } else { |
153 | error_report("could not load ram disk '%s'" , |
154 | blk_bs(blk)->filename); |
155 | exit(1); |
156 | } |
157 | } |
158 | if (serial_hd(0)) { |
159 | serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200, |
160 | serial_hd(0), DEVICE_BIG_ENDIAN); |
161 | } |
162 | create_unimplemented_device("sun4v-iob" , NIAGARA_IOBBASE, NIAGARA_IOBSIZE); |
163 | sun4v_rtc_init(NIAGARA_RTC_BASE); |
164 | } |
165 | |
166 | static void niagara_class_init(ObjectClass *oc, void *data) |
167 | { |
168 | MachineClass *mc = MACHINE_CLASS(oc); |
169 | |
170 | mc->desc = "Sun4v platform, Niagara" ; |
171 | mc->init = niagara_init; |
172 | mc->max_cpus = 1; /* XXX for now */ |
173 | mc->default_boot_order = "c" ; |
174 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1" ); |
175 | } |
176 | |
177 | static const TypeInfo niagara_type = { |
178 | .name = MACHINE_TYPE_NAME("niagara" ), |
179 | .parent = TYPE_MACHINE, |
180 | .class_init = niagara_class_init, |
181 | }; |
182 | |
183 | static void niagara_register_types(void) |
184 | { |
185 | type_register_static(&niagara_type); |
186 | } |
187 | |
188 | type_init(niagara_register_types) |
189 | |