1 | /* |
2 | * Samsung exynos4210 Real Time Clock |
3 | * |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
5 | * Ogurtsov Oleg <o.ogurtsov@samsung.com> |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License as published by the |
9 | * Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
15 | * for more details. |
16 | * |
17 | * You should have received a copy of the GNU General Public License along |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
19 | * |
20 | */ |
21 | |
22 | /* Description: |
23 | * Register RTCCON: |
24 | * CLKSEL Bit[1] not used |
25 | * CLKOUTEN Bit[9] not used |
26 | */ |
27 | |
28 | #include "qemu/osdep.h" |
29 | #include "qemu-common.h" |
30 | #include "qemu/log.h" |
31 | #include "qemu/main-loop.h" |
32 | #include "qemu/module.h" |
33 | #include "hw/sysbus.h" |
34 | #include "migration/vmstate.h" |
35 | #include "qemu/timer.h" |
36 | #include "qemu/bcd.h" |
37 | #include "hw/ptimer.h" |
38 | |
39 | #include "hw/irq.h" |
40 | |
41 | #include "hw/arm/exynos4210.h" |
42 | |
43 | #define DEBUG_RTC 0 |
44 | |
45 | #if DEBUG_RTC |
46 | #define DPRINTF(fmt, ...) \ |
47 | do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \ |
48 | ## __VA_ARGS__); } while (0) |
49 | #else |
50 | #define DPRINTF(fmt, ...) do {} while (0) |
51 | #endif |
52 | |
53 | #define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100 |
54 | |
55 | #define INTP 0x0030 |
56 | #define RTCCON 0x0040 |
57 | #define TICCNT 0x0044 |
58 | #define RTCALM 0x0050 |
59 | #define ALMSEC 0x0054 |
60 | #define ALMMIN 0x0058 |
61 | #define ALMHOUR 0x005C |
62 | #define ALMDAY 0x0060 |
63 | #define ALMMON 0x0064 |
64 | #define ALMYEAR 0x0068 |
65 | #define BCDSEC 0x0070 |
66 | #define BCDMIN 0x0074 |
67 | #define BCDHOUR 0x0078 |
68 | #define BCDDAY 0x007C |
69 | #define BCDDAYWEEK 0x0080 |
70 | #define BCDMON 0x0084 |
71 | #define BCDYEAR 0x0088 |
72 | #define CURTICNT 0x0090 |
73 | |
74 | #define TICK_TIMER_ENABLE 0x0100 |
75 | #define TICNT_THRESHOLD 2 |
76 | |
77 | |
78 | #define RTC_ENABLE 0x0001 |
79 | |
80 | #define INTP_TICK_ENABLE 0x0001 |
81 | #define INTP_ALM_ENABLE 0x0002 |
82 | |
83 | #define ALARM_INT_ENABLE 0x0040 |
84 | |
85 | #define RTC_BASE_FREQ 32768 |
86 | |
87 | #define TYPE_EXYNOS4210_RTC "exynos4210.rtc" |
88 | #define EXYNOS4210_RTC(obj) \ |
89 | OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC) |
90 | |
91 | typedef struct Exynos4210RTCState { |
92 | SysBusDevice parent_obj; |
93 | |
94 | MemoryRegion iomem; |
95 | |
96 | /* registers */ |
97 | uint32_t reg_intp; |
98 | uint32_t reg_rtccon; |
99 | uint32_t reg_ticcnt; |
100 | uint32_t reg_rtcalm; |
101 | uint32_t reg_almsec; |
102 | uint32_t reg_almmin; |
103 | uint32_t reg_almhour; |
104 | uint32_t reg_almday; |
105 | uint32_t reg_almmon; |
106 | uint32_t reg_almyear; |
107 | uint32_t reg_curticcnt; |
108 | |
109 | ptimer_state *ptimer; /* tick timer */ |
110 | ptimer_state *ptimer_1Hz; /* clock timer */ |
111 | uint32_t freq; |
112 | |
113 | qemu_irq tick_irq; /* Time Tick Generator irq */ |
114 | qemu_irq alm_irq; /* alarm irq */ |
115 | |
116 | struct tm current_tm; /* current time */ |
117 | } Exynos4210RTCState; |
118 | |
119 | #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4) |
120 | |
121 | /*** VMState ***/ |
122 | static const VMStateDescription vmstate_exynos4210_rtc_state = { |
123 | .name = "exynos4210.rtc" , |
124 | .version_id = 1, |
125 | .minimum_version_id = 1, |
126 | .fields = (VMStateField[]) { |
127 | VMSTATE_UINT32(reg_intp, Exynos4210RTCState), |
128 | VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState), |
129 | VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState), |
130 | VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState), |
131 | VMSTATE_UINT32(reg_almsec, Exynos4210RTCState), |
132 | VMSTATE_UINT32(reg_almmin, Exynos4210RTCState), |
133 | VMSTATE_UINT32(reg_almhour, Exynos4210RTCState), |
134 | VMSTATE_UINT32(reg_almday, Exynos4210RTCState), |
135 | VMSTATE_UINT32(reg_almmon, Exynos4210RTCState), |
136 | VMSTATE_UINT32(reg_almyear, Exynos4210RTCState), |
137 | VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState), |
138 | VMSTATE_PTIMER(ptimer, Exynos4210RTCState), |
139 | VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState), |
140 | VMSTATE_UINT32(freq, Exynos4210RTCState), |
141 | VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState), |
142 | VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState), |
143 | VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState), |
144 | VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState), |
145 | VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState), |
146 | VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState), |
147 | VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState), |
148 | VMSTATE_END_OF_LIST() |
149 | } |
150 | }; |
151 | |
152 | #define BCD3DIGITS(x) \ |
153 | ((uint32_t)to_bcd((uint8_t)(x % 100)) + \ |
154 | ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8)) |
155 | |
156 | static void check_alarm_raise(Exynos4210RTCState *s) |
157 | { |
158 | unsigned int alarm_raise = 0; |
159 | struct tm stm = s->current_tm; |
160 | |
161 | if ((s->reg_rtcalm & 0x01) && |
162 | (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) { |
163 | alarm_raise = 1; |
164 | } |
165 | if ((s->reg_rtcalm & 0x02) && |
166 | (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) { |
167 | alarm_raise = 1; |
168 | } |
169 | if ((s->reg_rtcalm & 0x04) && |
170 | (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) { |
171 | alarm_raise = 1; |
172 | } |
173 | if ((s->reg_rtcalm & 0x08) && |
174 | (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) { |
175 | alarm_raise = 1; |
176 | } |
177 | if ((s->reg_rtcalm & 0x10) && |
178 | (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) { |
179 | alarm_raise = 1; |
180 | } |
181 | if ((s->reg_rtcalm & 0x20) && |
182 | (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) { |
183 | alarm_raise = 1; |
184 | } |
185 | |
186 | if (alarm_raise) { |
187 | DPRINTF("ALARM IRQ\n" ); |
188 | /* set irq status */ |
189 | s->reg_intp |= INTP_ALM_ENABLE; |
190 | qemu_irq_raise(s->alm_irq); |
191 | } |
192 | } |
193 | |
194 | /* |
195 | * RTC update frequency |
196 | * Parameters: |
197 | * reg_value - current RTCCON register or his new value |
198 | */ |
199 | static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, |
200 | uint32_t reg_value) |
201 | { |
202 | uint32_t freq; |
203 | |
204 | freq = s->freq; |
205 | /* set frequncy for time generator */ |
206 | s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value)); |
207 | |
208 | if (freq != s->freq) { |
209 | ptimer_set_freq(s->ptimer, s->freq); |
210 | DPRINTF("freq=%dHz\n" , s->freq); |
211 | } |
212 | } |
213 | |
214 | /* month is between 0 and 11. */ |
215 | static int get_days_in_month(int month, int year) |
216 | { |
217 | static const int days_tab[12] = { |
218 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
219 | }; |
220 | int d; |
221 | if ((unsigned)month >= 12) { |
222 | return 31; |
223 | } |
224 | d = days_tab[month]; |
225 | if (month == 1) { |
226 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) { |
227 | d++; |
228 | } |
229 | } |
230 | return d; |
231 | } |
232 | |
233 | /* update 'tm' to the next second */ |
234 | static void rtc_next_second(struct tm *tm) |
235 | { |
236 | int days_in_month; |
237 | |
238 | tm->tm_sec++; |
239 | if ((unsigned)tm->tm_sec >= 60) { |
240 | tm->tm_sec = 0; |
241 | tm->tm_min++; |
242 | if ((unsigned)tm->tm_min >= 60) { |
243 | tm->tm_min = 0; |
244 | tm->tm_hour++; |
245 | if ((unsigned)tm->tm_hour >= 24) { |
246 | tm->tm_hour = 0; |
247 | /* next day */ |
248 | tm->tm_wday++; |
249 | if ((unsigned)tm->tm_wday >= 7) { |
250 | tm->tm_wday = 0; |
251 | } |
252 | days_in_month = get_days_in_month(tm->tm_mon, |
253 | tm->tm_year + 1900); |
254 | tm->tm_mday++; |
255 | if (tm->tm_mday < 1) { |
256 | tm->tm_mday = 1; |
257 | } else if (tm->tm_mday > days_in_month) { |
258 | tm->tm_mday = 1; |
259 | tm->tm_mon++; |
260 | if (tm->tm_mon >= 12) { |
261 | tm->tm_mon = 0; |
262 | tm->tm_year++; |
263 | } |
264 | } |
265 | } |
266 | } |
267 | } |
268 | } |
269 | |
270 | /* |
271 | * tick handler |
272 | */ |
273 | static void exynos4210_rtc_tick(void *opaque) |
274 | { |
275 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
276 | |
277 | DPRINTF("TICK IRQ\n" ); |
278 | /* set irq status */ |
279 | s->reg_intp |= INTP_TICK_ENABLE; |
280 | /* raise IRQ */ |
281 | qemu_irq_raise(s->tick_irq); |
282 | |
283 | /* restart timer */ |
284 | ptimer_set_count(s->ptimer, s->reg_ticcnt); |
285 | ptimer_run(s->ptimer, 1); |
286 | } |
287 | |
288 | /* |
289 | * 1Hz clock handler |
290 | */ |
291 | static void exynos4210_rtc_1Hz_tick(void *opaque) |
292 | { |
293 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
294 | |
295 | rtc_next_second(&s->current_tm); |
296 | /* DPRINTF("1Hz tick\n"); */ |
297 | |
298 | /* raise IRQ */ |
299 | if (s->reg_rtcalm & ALARM_INT_ENABLE) { |
300 | check_alarm_raise(s); |
301 | } |
302 | |
303 | ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); |
304 | ptimer_run(s->ptimer_1Hz, 1); |
305 | } |
306 | |
307 | /* |
308 | * RTC Read |
309 | */ |
310 | static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, |
311 | unsigned size) |
312 | { |
313 | uint32_t value = 0; |
314 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
315 | |
316 | switch (offset) { |
317 | case INTP: |
318 | value = s->reg_intp; |
319 | break; |
320 | case RTCCON: |
321 | value = s->reg_rtccon; |
322 | break; |
323 | case TICCNT: |
324 | value = s->reg_ticcnt; |
325 | break; |
326 | case RTCALM: |
327 | value = s->reg_rtcalm; |
328 | break; |
329 | case ALMSEC: |
330 | value = s->reg_almsec; |
331 | break; |
332 | case ALMMIN: |
333 | value = s->reg_almmin; |
334 | break; |
335 | case ALMHOUR: |
336 | value = s->reg_almhour; |
337 | break; |
338 | case ALMDAY: |
339 | value = s->reg_almday; |
340 | break; |
341 | case ALMMON: |
342 | value = s->reg_almmon; |
343 | break; |
344 | case ALMYEAR: |
345 | value = s->reg_almyear; |
346 | break; |
347 | |
348 | case BCDSEC: |
349 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec); |
350 | break; |
351 | case BCDMIN: |
352 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min); |
353 | break; |
354 | case BCDHOUR: |
355 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour); |
356 | break; |
357 | case BCDDAYWEEK: |
358 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday); |
359 | break; |
360 | case BCDDAY: |
361 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday); |
362 | break; |
363 | case BCDMON: |
364 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1); |
365 | break; |
366 | case BCDYEAR: |
367 | value = BCD3DIGITS(s->current_tm.tm_year); |
368 | break; |
369 | |
370 | case CURTICNT: |
371 | s->reg_curticcnt = ptimer_get_count(s->ptimer); |
372 | value = s->reg_curticcnt; |
373 | break; |
374 | |
375 | default: |
376 | qemu_log_mask(LOG_GUEST_ERROR, |
377 | "exynos4210.rtc: bad read offset " TARGET_FMT_plx, |
378 | offset); |
379 | break; |
380 | } |
381 | return value; |
382 | } |
383 | |
384 | /* |
385 | * RTC Write |
386 | */ |
387 | static void exynos4210_rtc_write(void *opaque, hwaddr offset, |
388 | uint64_t value, unsigned size) |
389 | { |
390 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; |
391 | |
392 | switch (offset) { |
393 | case INTP: |
394 | if (value & INTP_ALM_ENABLE) { |
395 | qemu_irq_lower(s->alm_irq); |
396 | s->reg_intp &= (~INTP_ALM_ENABLE); |
397 | } |
398 | if (value & INTP_TICK_ENABLE) { |
399 | qemu_irq_lower(s->tick_irq); |
400 | s->reg_intp &= (~INTP_TICK_ENABLE); |
401 | } |
402 | break; |
403 | case RTCCON: |
404 | if (value & RTC_ENABLE) { |
405 | exynos4210_rtc_update_freq(s, value); |
406 | } |
407 | if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) { |
408 | /* clock timer */ |
409 | ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); |
410 | ptimer_run(s->ptimer_1Hz, 1); |
411 | DPRINTF("run clock timer\n" ); |
412 | } |
413 | if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) { |
414 | /* tick timer */ |
415 | ptimer_stop(s->ptimer); |
416 | /* clock timer */ |
417 | ptimer_stop(s->ptimer_1Hz); |
418 | DPRINTF("stop all timers\n" ); |
419 | } |
420 | if (value & RTC_ENABLE) { |
421 | if ((value & TICK_TIMER_ENABLE) > |
422 | (s->reg_rtccon & TICK_TIMER_ENABLE) && |
423 | (s->reg_ticcnt)) { |
424 | ptimer_set_count(s->ptimer, s->reg_ticcnt); |
425 | ptimer_run(s->ptimer, 1); |
426 | DPRINTF("run tick timer\n" ); |
427 | } |
428 | if ((value & TICK_TIMER_ENABLE) < |
429 | (s->reg_rtccon & TICK_TIMER_ENABLE)) { |
430 | ptimer_stop(s->ptimer); |
431 | } |
432 | } |
433 | s->reg_rtccon = value; |
434 | break; |
435 | case TICCNT: |
436 | if (value > TICNT_THRESHOLD) { |
437 | s->reg_ticcnt = value; |
438 | } else { |
439 | qemu_log_mask(LOG_GUEST_ERROR, |
440 | "exynos4210.rtc: bad TICNT value %u" , |
441 | (uint32_t)value); |
442 | } |
443 | break; |
444 | |
445 | case RTCALM: |
446 | s->reg_rtcalm = value; |
447 | break; |
448 | case ALMSEC: |
449 | s->reg_almsec = (value & 0x7f); |
450 | break; |
451 | case ALMMIN: |
452 | s->reg_almmin = (value & 0x7f); |
453 | break; |
454 | case ALMHOUR: |
455 | s->reg_almhour = (value & 0x3f); |
456 | break; |
457 | case ALMDAY: |
458 | s->reg_almday = (value & 0x3f); |
459 | break; |
460 | case ALMMON: |
461 | s->reg_almmon = (value & 0x1f); |
462 | break; |
463 | case ALMYEAR: |
464 | s->reg_almyear = (value & 0x0fff); |
465 | break; |
466 | |
467 | case BCDSEC: |
468 | if (s->reg_rtccon & RTC_ENABLE) { |
469 | s->current_tm.tm_sec = (int)from_bcd((uint8_t)value); |
470 | } |
471 | break; |
472 | case BCDMIN: |
473 | if (s->reg_rtccon & RTC_ENABLE) { |
474 | s->current_tm.tm_min = (int)from_bcd((uint8_t)value); |
475 | } |
476 | break; |
477 | case BCDHOUR: |
478 | if (s->reg_rtccon & RTC_ENABLE) { |
479 | s->current_tm.tm_hour = (int)from_bcd((uint8_t)value); |
480 | } |
481 | break; |
482 | case BCDDAYWEEK: |
483 | if (s->reg_rtccon & RTC_ENABLE) { |
484 | s->current_tm.tm_wday = (int)from_bcd((uint8_t)value); |
485 | } |
486 | break; |
487 | case BCDDAY: |
488 | if (s->reg_rtccon & RTC_ENABLE) { |
489 | s->current_tm.tm_mday = (int)from_bcd((uint8_t)value); |
490 | } |
491 | break; |
492 | case BCDMON: |
493 | if (s->reg_rtccon & RTC_ENABLE) { |
494 | s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1; |
495 | } |
496 | break; |
497 | case BCDYEAR: |
498 | if (s->reg_rtccon & RTC_ENABLE) { |
499 | /* 3 digits */ |
500 | s->current_tm.tm_year = (int)from_bcd((uint8_t)value) + |
501 | (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100; |
502 | } |
503 | break; |
504 | |
505 | default: |
506 | qemu_log_mask(LOG_GUEST_ERROR, |
507 | "exynos4210.rtc: bad write offset " TARGET_FMT_plx, |
508 | offset); |
509 | break; |
510 | |
511 | } |
512 | } |
513 | |
514 | /* |
515 | * Set default values to timer fields and registers |
516 | */ |
517 | static void exynos4210_rtc_reset(DeviceState *d) |
518 | { |
519 | Exynos4210RTCState *s = EXYNOS4210_RTC(d); |
520 | |
521 | qemu_get_timedate(&s->current_tm, 0); |
522 | |
523 | DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n" , |
524 | s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday, |
525 | s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec); |
526 | |
527 | s->reg_intp = 0; |
528 | s->reg_rtccon = 0; |
529 | s->reg_ticcnt = 0; |
530 | s->reg_rtcalm = 0; |
531 | s->reg_almsec = 0; |
532 | s->reg_almmin = 0; |
533 | s->reg_almhour = 0; |
534 | s->reg_almday = 0; |
535 | s->reg_almmon = 0; |
536 | s->reg_almyear = 0; |
537 | |
538 | s->reg_curticcnt = 0; |
539 | |
540 | exynos4210_rtc_update_freq(s, s->reg_rtccon); |
541 | ptimer_stop(s->ptimer); |
542 | ptimer_stop(s->ptimer_1Hz); |
543 | } |
544 | |
545 | static const MemoryRegionOps exynos4210_rtc_ops = { |
546 | .read = exynos4210_rtc_read, |
547 | .write = exynos4210_rtc_write, |
548 | .endianness = DEVICE_NATIVE_ENDIAN, |
549 | }; |
550 | |
551 | /* |
552 | * RTC timer initialization |
553 | */ |
554 | static void exynos4210_rtc_init(Object *obj) |
555 | { |
556 | Exynos4210RTCState *s = EXYNOS4210_RTC(obj); |
557 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
558 | QEMUBH *bh; |
559 | |
560 | bh = qemu_bh_new(exynos4210_rtc_tick, s); |
561 | s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
562 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); |
563 | exynos4210_rtc_update_freq(s, 0); |
564 | |
565 | bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); |
566 | s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
567 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); |
568 | |
569 | sysbus_init_irq(dev, &s->alm_irq); |
570 | sysbus_init_irq(dev, &s->tick_irq); |
571 | |
572 | memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s, |
573 | "exynos4210-rtc" , EXYNOS4210_RTC_REG_MEM_SIZE); |
574 | sysbus_init_mmio(dev, &s->iomem); |
575 | } |
576 | |
577 | static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) |
578 | { |
579 | DeviceClass *dc = DEVICE_CLASS(klass); |
580 | |
581 | dc->reset = exynos4210_rtc_reset; |
582 | dc->vmsd = &vmstate_exynos4210_rtc_state; |
583 | } |
584 | |
585 | static const TypeInfo exynos4210_rtc_info = { |
586 | .name = TYPE_EXYNOS4210_RTC, |
587 | .parent = TYPE_SYS_BUS_DEVICE, |
588 | .instance_size = sizeof(Exynos4210RTCState), |
589 | .instance_init = exynos4210_rtc_init, |
590 | .class_init = exynos4210_rtc_class_init, |
591 | }; |
592 | |
593 | static void exynos4210_rtc_register_types(void) |
594 | { |
595 | type_register_static(&exynos4210_rtc_info); |
596 | } |
597 | |
598 | type_init(exynos4210_rtc_register_types) |
599 | |