1 | /* |
2 | * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface |
3 | * |
4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5 | * Copyright (c) 2013 Hervé Poussineau |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal |
9 | * in the Software without restriction, including without limitation the rights |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
11 | * copies of the Software, and to permit persons to whom the Software is |
12 | * furnished to do so, subject to the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice shall be included in |
15 | * all copies or substantial portions of the Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
23 | * THE SOFTWARE. |
24 | */ |
25 | |
26 | #include "qemu/osdep.h" |
27 | #include "hw/isa/isa.h" |
28 | #include "hw/qdev-properties.h" |
29 | #include "hw/timer/m48t59.h" |
30 | #include "m48t59-internal.h" |
31 | #include "qemu/module.h" |
32 | |
33 | #define TYPE_M48TXX_ISA "isa-m48txx" |
34 | #define M48TXX_ISA_GET_CLASS(obj) \ |
35 | OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) |
36 | #define M48TXX_ISA_CLASS(klass) \ |
37 | OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) |
38 | #define M48TXX_ISA(obj) \ |
39 | OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) |
40 | |
41 | typedef struct M48txxISAState { |
42 | ISADevice parent_obj; |
43 | M48t59State state; |
44 | uint32_t io_base; |
45 | MemoryRegion io; |
46 | } M48txxISAState; |
47 | |
48 | typedef struct M48txxISADeviceClass { |
49 | ISADeviceClass parent_class; |
50 | M48txxInfo info; |
51 | } M48txxISADeviceClass; |
52 | |
53 | static M48txxInfo m48txx_isa_info[] = { |
54 | { |
55 | .bus_name = "isa-m48t59" , |
56 | .model = 59, |
57 | .size = 0x2000, |
58 | } |
59 | }; |
60 | |
61 | Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
62 | int base_year, int model) |
63 | { |
64 | DeviceState *dev; |
65 | int i; |
66 | |
67 | for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { |
68 | if (m48txx_isa_info[i].size != size || |
69 | m48txx_isa_info[i].model != model) { |
70 | continue; |
71 | } |
72 | |
73 | dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name)); |
74 | qdev_prop_set_uint32(dev, "iobase" , io_base); |
75 | qdev_prop_set_int32(dev, "base-year" , base_year); |
76 | qdev_init_nofail(dev); |
77 | return NVRAM(dev); |
78 | } |
79 | |
80 | assert(false); |
81 | return NULL; |
82 | } |
83 | |
84 | static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) |
85 | { |
86 | M48txxISAState *d = M48TXX_ISA(obj); |
87 | return m48t59_read(&d->state, addr); |
88 | } |
89 | |
90 | static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) |
91 | { |
92 | M48txxISAState *d = M48TXX_ISA(obj); |
93 | m48t59_write(&d->state, addr, val); |
94 | } |
95 | |
96 | static void m48txx_isa_toggle_lock(Nvram *obj, int lock) |
97 | { |
98 | M48txxISAState *d = M48TXX_ISA(obj); |
99 | m48t59_toggle_lock(&d->state, lock); |
100 | } |
101 | |
102 | static Property m48t59_isa_properties[] = { |
103 | DEFINE_PROP_INT32("base-year" , M48txxISAState, state.base_year, 0), |
104 | DEFINE_PROP_UINT32("iobase" , M48txxISAState, io_base, 0x74), |
105 | DEFINE_PROP_END_OF_LIST(), |
106 | }; |
107 | |
108 | static void m48t59_reset_isa(DeviceState *d) |
109 | { |
110 | M48txxISAState *isa = M48TXX_ISA(d); |
111 | M48t59State *NVRAM = &isa->state; |
112 | |
113 | m48t59_reset_common(NVRAM); |
114 | } |
115 | |
116 | static void m48t59_isa_realize(DeviceState *dev, Error **errp) |
117 | { |
118 | M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev); |
119 | ISADevice *isadev = ISA_DEVICE(dev); |
120 | M48txxISAState *d = M48TXX_ISA(dev); |
121 | M48t59State *s = &d->state; |
122 | |
123 | s->model = u->info.model; |
124 | s->size = u->info.size; |
125 | isa_init_irq(isadev, &s->IRQ, 8); |
126 | m48t59_realize_common(s, errp); |
127 | memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59" , 4); |
128 | if (d->io_base != 0) { |
129 | isa_register_ioport(isadev, &d->io, d->io_base); |
130 | } |
131 | } |
132 | |
133 | static void m48txx_isa_class_init(ObjectClass *klass, void *data) |
134 | { |
135 | DeviceClass *dc = DEVICE_CLASS(klass); |
136 | NvramClass *nc = NVRAM_CLASS(klass); |
137 | |
138 | dc->realize = m48t59_isa_realize; |
139 | dc->reset = m48t59_reset_isa; |
140 | dc->props = m48t59_isa_properties; |
141 | nc->read = m48txx_isa_read; |
142 | nc->write = m48txx_isa_write; |
143 | nc->toggle_lock = m48txx_isa_toggle_lock; |
144 | } |
145 | |
146 | static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) |
147 | { |
148 | M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); |
149 | M48txxInfo *info = data; |
150 | |
151 | u->info = *info; |
152 | } |
153 | |
154 | static const TypeInfo m48txx_isa_type_info = { |
155 | .name = TYPE_M48TXX_ISA, |
156 | .parent = TYPE_ISA_DEVICE, |
157 | .instance_size = sizeof(M48txxISAState), |
158 | .abstract = true, |
159 | .class_init = m48txx_isa_class_init, |
160 | .interfaces = (InterfaceInfo[]) { |
161 | { TYPE_NVRAM }, |
162 | { } |
163 | } |
164 | }; |
165 | |
166 | static void m48t59_isa_register_types(void) |
167 | { |
168 | TypeInfo isa_type_info = { |
169 | .parent = TYPE_M48TXX_ISA, |
170 | .class_size = sizeof(M48txxISADeviceClass), |
171 | .class_init = m48txx_isa_concrete_class_init, |
172 | }; |
173 | int i; |
174 | |
175 | type_register_static(&m48txx_isa_type_info); |
176 | |
177 | for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { |
178 | isa_type_info.name = m48txx_isa_info[i].bus_name; |
179 | isa_type_info.class_data = &m48txx_isa_info[i]; |
180 | type_register(&isa_type_info); |
181 | } |
182 | } |
183 | |
184 | type_init(m48t59_isa_register_types) |
185 | |