1 | /* |
2 | * QEMU model of the Milkymist System Controller. |
3 | * |
4 | * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | * |
19 | * |
20 | * Specification available at: |
21 | * http://milkymist.walle.cc/socdoc/sysctl.pdf |
22 | */ |
23 | |
24 | #include "qemu/osdep.h" |
25 | #include "hw/irq.h" |
26 | #include "hw/sysbus.h" |
27 | #include "migration/vmstate.h" |
28 | #include "trace.h" |
29 | #include "qemu/timer.h" |
30 | #include "sysemu/runstate.h" |
31 | #include "hw/ptimer.h" |
32 | #include "hw/qdev-properties.h" |
33 | #include "qemu/error-report.h" |
34 | #include "qemu/main-loop.h" |
35 | #include "qemu/module.h" |
36 | |
37 | enum { |
38 | CTRL_ENABLE = (1<<0), |
39 | CTRL_AUTORESTART = (1<<1), |
40 | }; |
41 | |
42 | enum { |
43 | ICAP_READY = (1<<0), |
44 | }; |
45 | |
46 | enum { |
47 | R_GPIO_IN = 0, |
48 | R_GPIO_OUT, |
49 | R_GPIO_INTEN, |
50 | R_TIMER0_CONTROL = 4, |
51 | R_TIMER0_COMPARE, |
52 | R_TIMER0_COUNTER, |
53 | R_TIMER1_CONTROL = 8, |
54 | R_TIMER1_COMPARE, |
55 | R_TIMER1_COUNTER, |
56 | R_ICAP = 16, |
57 | R_DBG_SCRATCHPAD = 20, |
58 | R_DBG_WRITE_LOCK, |
59 | R_CLK_FREQUENCY = 29, |
60 | R_CAPABILITIES, |
61 | R_SYSTEM_ID, |
62 | R_MAX |
63 | }; |
64 | |
65 | #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl" |
66 | #define MILKYMIST_SYSCTL(obj) \ |
67 | OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL) |
68 | |
69 | struct MilkymistSysctlState { |
70 | SysBusDevice parent_obj; |
71 | |
72 | MemoryRegion regs_region; |
73 | |
74 | QEMUBH *bh0; |
75 | QEMUBH *bh1; |
76 | ptimer_state *ptimer0; |
77 | ptimer_state *ptimer1; |
78 | |
79 | uint32_t freq_hz; |
80 | uint32_t capabilities; |
81 | uint32_t systemid; |
82 | uint32_t strappings; |
83 | |
84 | uint32_t regs[R_MAX]; |
85 | |
86 | qemu_irq gpio_irq; |
87 | qemu_irq timer0_irq; |
88 | qemu_irq timer1_irq; |
89 | }; |
90 | typedef struct MilkymistSysctlState MilkymistSysctlState; |
91 | |
92 | static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value) |
93 | { |
94 | trace_milkymist_sysctl_icap_write(value); |
95 | switch (value & 0xffff) { |
96 | case 0x000e: |
97 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
98 | break; |
99 | } |
100 | } |
101 | |
102 | static uint64_t sysctl_read(void *opaque, hwaddr addr, |
103 | unsigned size) |
104 | { |
105 | MilkymistSysctlState *s = opaque; |
106 | uint32_t r = 0; |
107 | |
108 | addr >>= 2; |
109 | switch (addr) { |
110 | case R_TIMER0_COUNTER: |
111 | r = (uint32_t)ptimer_get_count(s->ptimer0); |
112 | /* milkymist timer counts up */ |
113 | r = s->regs[R_TIMER0_COMPARE] - r; |
114 | break; |
115 | case R_TIMER1_COUNTER: |
116 | r = (uint32_t)ptimer_get_count(s->ptimer1); |
117 | /* milkymist timer counts up */ |
118 | r = s->regs[R_TIMER1_COMPARE] - r; |
119 | break; |
120 | case R_GPIO_IN: |
121 | case R_GPIO_OUT: |
122 | case R_GPIO_INTEN: |
123 | case R_TIMER0_CONTROL: |
124 | case R_TIMER0_COMPARE: |
125 | case R_TIMER1_CONTROL: |
126 | case R_TIMER1_COMPARE: |
127 | case R_ICAP: |
128 | case R_DBG_SCRATCHPAD: |
129 | case R_DBG_WRITE_LOCK: |
130 | case R_CLK_FREQUENCY: |
131 | case R_CAPABILITIES: |
132 | case R_SYSTEM_ID: |
133 | r = s->regs[addr]; |
134 | break; |
135 | |
136 | default: |
137 | error_report("milkymist_sysctl: read access to unknown register 0x" |
138 | TARGET_FMT_plx, addr << 2); |
139 | break; |
140 | } |
141 | |
142 | trace_milkymist_sysctl_memory_read(addr << 2, r); |
143 | |
144 | return r; |
145 | } |
146 | |
147 | static void sysctl_write(void *opaque, hwaddr addr, uint64_t value, |
148 | unsigned size) |
149 | { |
150 | MilkymistSysctlState *s = opaque; |
151 | |
152 | trace_milkymist_sysctl_memory_write(addr, value); |
153 | |
154 | addr >>= 2; |
155 | switch (addr) { |
156 | case R_GPIO_OUT: |
157 | case R_GPIO_INTEN: |
158 | case R_TIMER0_COUNTER: |
159 | case R_TIMER1_COUNTER: |
160 | case R_DBG_SCRATCHPAD: |
161 | s->regs[addr] = value; |
162 | break; |
163 | case R_TIMER0_COMPARE: |
164 | ptimer_set_limit(s->ptimer0, value, 0); |
165 | s->regs[addr] = value; |
166 | break; |
167 | case R_TIMER1_COMPARE: |
168 | ptimer_set_limit(s->ptimer1, value, 0); |
169 | s->regs[addr] = value; |
170 | break; |
171 | case R_TIMER0_CONTROL: |
172 | s->regs[addr] = value; |
173 | if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) { |
174 | trace_milkymist_sysctl_start_timer0(); |
175 | ptimer_set_count(s->ptimer0, |
176 | s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]); |
177 | ptimer_run(s->ptimer0, 0); |
178 | } else { |
179 | trace_milkymist_sysctl_stop_timer0(); |
180 | ptimer_stop(s->ptimer0); |
181 | } |
182 | break; |
183 | case R_TIMER1_CONTROL: |
184 | s->regs[addr] = value; |
185 | if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) { |
186 | trace_milkymist_sysctl_start_timer1(); |
187 | ptimer_set_count(s->ptimer1, |
188 | s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]); |
189 | ptimer_run(s->ptimer1, 0); |
190 | } else { |
191 | trace_milkymist_sysctl_stop_timer1(); |
192 | ptimer_stop(s->ptimer1); |
193 | } |
194 | break; |
195 | case R_ICAP: |
196 | sysctl_icap_write(s, value); |
197 | break; |
198 | case R_DBG_WRITE_LOCK: |
199 | s->regs[addr] = 1; |
200 | break; |
201 | case R_SYSTEM_ID: |
202 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
203 | break; |
204 | |
205 | case R_GPIO_IN: |
206 | case R_CLK_FREQUENCY: |
207 | case R_CAPABILITIES: |
208 | error_report("milkymist_sysctl: write to read-only register 0x" |
209 | TARGET_FMT_plx, addr << 2); |
210 | break; |
211 | |
212 | default: |
213 | error_report("milkymist_sysctl: write access to unknown register 0x" |
214 | TARGET_FMT_plx, addr << 2); |
215 | break; |
216 | } |
217 | } |
218 | |
219 | static const MemoryRegionOps sysctl_mmio_ops = { |
220 | .read = sysctl_read, |
221 | .write = sysctl_write, |
222 | .valid = { |
223 | .min_access_size = 4, |
224 | .max_access_size = 4, |
225 | }, |
226 | .endianness = DEVICE_NATIVE_ENDIAN, |
227 | }; |
228 | |
229 | static void timer0_hit(void *opaque) |
230 | { |
231 | MilkymistSysctlState *s = opaque; |
232 | |
233 | if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) { |
234 | s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE; |
235 | trace_milkymist_sysctl_stop_timer0(); |
236 | ptimer_stop(s->ptimer0); |
237 | } |
238 | |
239 | trace_milkymist_sysctl_pulse_irq_timer0(); |
240 | qemu_irq_pulse(s->timer0_irq); |
241 | } |
242 | |
243 | static void timer1_hit(void *opaque) |
244 | { |
245 | MilkymistSysctlState *s = opaque; |
246 | |
247 | if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) { |
248 | s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE; |
249 | trace_milkymist_sysctl_stop_timer1(); |
250 | ptimer_stop(s->ptimer1); |
251 | } |
252 | |
253 | trace_milkymist_sysctl_pulse_irq_timer1(); |
254 | qemu_irq_pulse(s->timer1_irq); |
255 | } |
256 | |
257 | static void milkymist_sysctl_reset(DeviceState *d) |
258 | { |
259 | MilkymistSysctlState *s = MILKYMIST_SYSCTL(d); |
260 | int i; |
261 | |
262 | for (i = 0; i < R_MAX; i++) { |
263 | s->regs[i] = 0; |
264 | } |
265 | |
266 | ptimer_stop(s->ptimer0); |
267 | ptimer_stop(s->ptimer1); |
268 | |
269 | /* defaults */ |
270 | s->regs[R_ICAP] = ICAP_READY; |
271 | s->regs[R_SYSTEM_ID] = s->systemid; |
272 | s->regs[R_CLK_FREQUENCY] = s->freq_hz; |
273 | s->regs[R_CAPABILITIES] = s->capabilities; |
274 | s->regs[R_GPIO_IN] = s->strappings; |
275 | } |
276 | |
277 | static void milkymist_sysctl_init(Object *obj) |
278 | { |
279 | MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj); |
280 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
281 | |
282 | sysbus_init_irq(dev, &s->gpio_irq); |
283 | sysbus_init_irq(dev, &s->timer0_irq); |
284 | sysbus_init_irq(dev, &s->timer1_irq); |
285 | |
286 | s->bh0 = qemu_bh_new(timer0_hit, s); |
287 | s->bh1 = qemu_bh_new(timer1_hit, s); |
288 | s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT); |
289 | s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT); |
290 | |
291 | memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s, |
292 | "milkymist-sysctl" , R_MAX * 4); |
293 | sysbus_init_mmio(dev, &s->regs_region); |
294 | } |
295 | |
296 | static void milkymist_sysctl_realize(DeviceState *dev, Error **errp) |
297 | { |
298 | MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev); |
299 | |
300 | ptimer_set_freq(s->ptimer0, s->freq_hz); |
301 | ptimer_set_freq(s->ptimer1, s->freq_hz); |
302 | } |
303 | |
304 | static const VMStateDescription vmstate_milkymist_sysctl = { |
305 | .name = "milkymist-sysctl" , |
306 | .version_id = 1, |
307 | .minimum_version_id = 1, |
308 | .fields = (VMStateField[]) { |
309 | VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX), |
310 | VMSTATE_PTIMER(ptimer0, MilkymistSysctlState), |
311 | VMSTATE_PTIMER(ptimer1, MilkymistSysctlState), |
312 | VMSTATE_END_OF_LIST() |
313 | } |
314 | }; |
315 | |
316 | static Property milkymist_sysctl_properties[] = { |
317 | DEFINE_PROP_UINT32("frequency" , MilkymistSysctlState, |
318 | freq_hz, 80000000), |
319 | DEFINE_PROP_UINT32("capabilities" , MilkymistSysctlState, |
320 | capabilities, 0x00000000), |
321 | DEFINE_PROP_UINT32("systemid" , MilkymistSysctlState, |
322 | systemid, 0x10014d31), |
323 | DEFINE_PROP_UINT32("gpio_strappings" , MilkymistSysctlState, |
324 | strappings, 0x00000001), |
325 | DEFINE_PROP_END_OF_LIST(), |
326 | }; |
327 | |
328 | static void milkymist_sysctl_class_init(ObjectClass *klass, void *data) |
329 | { |
330 | DeviceClass *dc = DEVICE_CLASS(klass); |
331 | |
332 | dc->realize = milkymist_sysctl_realize; |
333 | dc->reset = milkymist_sysctl_reset; |
334 | dc->vmsd = &vmstate_milkymist_sysctl; |
335 | dc->props = milkymist_sysctl_properties; |
336 | } |
337 | |
338 | static const TypeInfo milkymist_sysctl_info = { |
339 | .name = TYPE_MILKYMIST_SYSCTL, |
340 | .parent = TYPE_SYS_BUS_DEVICE, |
341 | .instance_size = sizeof(MilkymistSysctlState), |
342 | .instance_init = milkymist_sysctl_init, |
343 | .class_init = milkymist_sysctl_class_init, |
344 | }; |
345 | |
346 | static void milkymist_sysctl_register_types(void) |
347 | { |
348 | type_register_static(&milkymist_sysctl_info); |
349 | } |
350 | |
351 | type_init(milkymist_sysctl_register_types) |
352 | |