1/*
2 * ARM AMBA PrimeCell PL031 RTC
3 *
4 * Copyright (c) 2007 CodeSourcery
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
12 */
13
14#include "qemu/osdep.h"
15#include "qemu-common.h"
16#include "hw/timer/pl031.h"
17#include "migration/vmstate.h"
18#include "hw/irq.h"
19#include "hw/qdev-properties.h"
20#include "hw/sysbus.h"
21#include "qemu/timer.h"
22#include "sysemu/sysemu.h"
23#include "qemu/cutils.h"
24#include "qemu/log.h"
25#include "qemu/module.h"
26#include "trace.h"
27
28#define RTC_DR 0x00 /* Data read register */
29#define RTC_MR 0x04 /* Match register */
30#define RTC_LR 0x08 /* Data load register */
31#define RTC_CR 0x0c /* Control register */
32#define RTC_IMSC 0x10 /* Interrupt mask and set register */
33#define RTC_RIS 0x14 /* Raw interrupt status register */
34#define RTC_MIS 0x18 /* Masked interrupt status register */
35#define RTC_ICR 0x1c /* Interrupt clear register */
36
37static const unsigned char pl031_id[] = {
38 0x31, 0x10, 0x14, 0x00, /* Device ID */
39 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
40};
41
42static void pl031_update(PL031State *s)
43{
44 uint32_t flags = s->is & s->im;
45
46 trace_pl031_irq_state(flags);
47 qemu_set_irq(s->irq, flags);
48}
49
50static void pl031_interrupt(void * opaque)
51{
52 PL031State *s = (PL031State *)opaque;
53
54 s->is = 1;
55 trace_pl031_alarm_raised();
56 pl031_update(s);
57}
58
59static uint32_t pl031_get_count(PL031State *s)
60{
61 int64_t now = qemu_clock_get_ns(rtc_clock);
62 return s->tick_offset + now / NANOSECONDS_PER_SECOND;
63}
64
65static void pl031_set_alarm(PL031State *s)
66{
67 uint32_t ticks;
68
69 /* The timer wraps around. This subtraction also wraps in the same way,
70 and gives correct results when alarm < now_ticks. */
71 ticks = s->mr - pl031_get_count(s);
72 trace_pl031_set_alarm(ticks);
73 if (ticks == 0) {
74 timer_del(s->timer);
75 pl031_interrupt(s);
76 } else {
77 int64_t now = qemu_clock_get_ns(rtc_clock);
78 timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
79 }
80}
81
82static uint64_t pl031_read(void *opaque, hwaddr offset,
83 unsigned size)
84{
85 PL031State *s = (PL031State *)opaque;
86 uint64_t r;
87
88 switch (offset) {
89 case RTC_DR:
90 r = pl031_get_count(s);
91 break;
92 case RTC_MR:
93 r = s->mr;
94 break;
95 case RTC_IMSC:
96 r = s->im;
97 break;
98 case RTC_RIS:
99 r = s->is;
100 break;
101 case RTC_LR:
102 r = s->lr;
103 break;
104 case RTC_CR:
105 /* RTC is permanently enabled. */
106 r = 1;
107 break;
108 case RTC_MIS:
109 r = s->is & s->im;
110 break;
111 case 0xfe0 ... 0xfff:
112 r = pl031_id[(offset - 0xfe0) >> 2];
113 break;
114 case RTC_ICR:
115 qemu_log_mask(LOG_GUEST_ERROR,
116 "pl031: read of write-only register at offset 0x%x\n",
117 (int)offset);
118 r = 0;
119 break;
120 default:
121 qemu_log_mask(LOG_GUEST_ERROR,
122 "pl031_read: Bad offset 0x%x\n", (int)offset);
123 r = 0;
124 break;
125 }
126
127 trace_pl031_read(offset, r);
128 return r;
129}
130
131static void pl031_write(void * opaque, hwaddr offset,
132 uint64_t value, unsigned size)
133{
134 PL031State *s = (PL031State *)opaque;
135
136 trace_pl031_write(offset, value);
137
138 switch (offset) {
139 case RTC_LR:
140 s->tick_offset += value - pl031_get_count(s);
141 pl031_set_alarm(s);
142 break;
143 case RTC_MR:
144 s->mr = value;
145 pl031_set_alarm(s);
146 break;
147 case RTC_IMSC:
148 s->im = value & 1;
149 pl031_update(s);
150 break;
151 case RTC_ICR:
152 /* The PL031 documentation (DDI0224B) states that the interrupt is
153 cleared when bit 0 of the written value is set. However the
154 arm926e documentation (DDI0287B) states that the interrupt is
155 cleared when any value is written. */
156 s->is = 0;
157 pl031_update(s);
158 break;
159 case RTC_CR:
160 /* Written value is ignored. */
161 break;
162
163 case RTC_DR:
164 case RTC_MIS:
165 case RTC_RIS:
166 qemu_log_mask(LOG_GUEST_ERROR,
167 "pl031: write to read-only register at offset 0x%x\n",
168 (int)offset);
169 break;
170
171 default:
172 qemu_log_mask(LOG_GUEST_ERROR,
173 "pl031_write: Bad offset 0x%x\n", (int)offset);
174 break;
175 }
176}
177
178static const MemoryRegionOps pl031_ops = {
179 .read = pl031_read,
180 .write = pl031_write,
181 .endianness = DEVICE_NATIVE_ENDIAN,
182};
183
184static void pl031_init(Object *obj)
185{
186 PL031State *s = PL031(obj);
187 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
188 struct tm tm;
189
190 memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
191 sysbus_init_mmio(dev, &s->iomem);
192
193 sysbus_init_irq(dev, &s->irq);
194 qemu_get_timedate(&tm, 0);
195 s->tick_offset = mktimegm(&tm) -
196 qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
197
198 s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
199}
200
201static int pl031_pre_save(void *opaque)
202{
203 PL031State *s = opaque;
204
205 /*
206 * The PL031 device model code uses the tick_offset field, which is
207 * the offset between what the guest RTC should read and what the
208 * QEMU rtc_clock reads:
209 * guest_rtc = rtc_clock + tick_offset
210 * and so
211 * tick_offset = guest_rtc - rtc_clock
212 *
213 * We want to migrate this offset, which sounds straightforward.
214 * Unfortunately older versions of QEMU migrated a conversion of this
215 * offset into an offset from the vm_clock. (This was in turn an
216 * attempt to be compatible with even older QEMU versions, but it
217 * has incorrect behaviour if the rtc_clock is not the same as the
218 * vm_clock.) So we put the actual tick_offset into a migration
219 * subsection, and the backwards-compatible time-relative-to-vm_clock
220 * in the main migration state.
221 *
222 * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
223 */
224 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
225 s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
226
227 return 0;
228}
229
230static int pl031_pre_load(void *opaque)
231{
232 PL031State *s = opaque;
233
234 s->tick_offset_migrated = false;
235 return 0;
236}
237
238static int pl031_post_load(void *opaque, int version_id)
239{
240 PL031State *s = opaque;
241
242 /*
243 * If we got the tick_offset subsection, then we can just use
244 * the value in that. Otherwise the source is an older QEMU and
245 * has given us the offset from the vm_clock; convert it back to
246 * an offset from the rtc_clock. This will cause time to incorrectly
247 * go backwards compared to the host RTC, but this is unavoidable.
248 */
249
250 if (!s->tick_offset_migrated) {
251 int64_t delta = qemu_clock_get_ns(rtc_clock) -
252 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
253 s->tick_offset = s->tick_offset_vmstate -
254 delta / NANOSECONDS_PER_SECOND;
255 }
256 pl031_set_alarm(s);
257 return 0;
258}
259
260static int pl031_tick_offset_post_load(void *opaque, int version_id)
261{
262 PL031State *s = opaque;
263
264 s->tick_offset_migrated = true;
265 return 0;
266}
267
268static bool pl031_tick_offset_needed(void *opaque)
269{
270 PL031State *s = opaque;
271
272 return s->migrate_tick_offset;
273}
274
275static const VMStateDescription vmstate_pl031_tick_offset = {
276 .name = "pl031/tick-offset",
277 .version_id = 1,
278 .minimum_version_id = 1,
279 .needed = pl031_tick_offset_needed,
280 .post_load = pl031_tick_offset_post_load,
281 .fields = (VMStateField[]) {
282 VMSTATE_UINT32(tick_offset, PL031State),
283 VMSTATE_END_OF_LIST()
284 }
285};
286
287static const VMStateDescription vmstate_pl031 = {
288 .name = "pl031",
289 .version_id = 1,
290 .minimum_version_id = 1,
291 .pre_save = pl031_pre_save,
292 .pre_load = pl031_pre_load,
293 .post_load = pl031_post_load,
294 .fields = (VMStateField[]) {
295 VMSTATE_UINT32(tick_offset_vmstate, PL031State),
296 VMSTATE_UINT32(mr, PL031State),
297 VMSTATE_UINT32(lr, PL031State),
298 VMSTATE_UINT32(cr, PL031State),
299 VMSTATE_UINT32(im, PL031State),
300 VMSTATE_UINT32(is, PL031State),
301 VMSTATE_END_OF_LIST()
302 },
303 .subsections = (const VMStateDescription*[]) {
304 &vmstate_pl031_tick_offset,
305 NULL
306 }
307};
308
309static Property pl031_properties[] = {
310 /*
311 * True to correctly migrate the tick offset of the RTC. False to
312 * obtain backward migration compatibility with older QEMU versions,
313 * at the expense of the guest RTC going backwards compared with the
314 * host RTC when the VM is saved/restored if using -rtc host.
315 * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
316 * 'false' also permits newer QEMU to migrate to older QEMU.)
317 */
318 DEFINE_PROP_BOOL("migrate-tick-offset",
319 PL031State, migrate_tick_offset, true),
320 DEFINE_PROP_END_OF_LIST()
321};
322
323static void pl031_class_init(ObjectClass *klass, void *data)
324{
325 DeviceClass *dc = DEVICE_CLASS(klass);
326
327 dc->vmsd = &vmstate_pl031;
328 dc->props = pl031_properties;
329}
330
331static const TypeInfo pl031_info = {
332 .name = TYPE_PL031,
333 .parent = TYPE_SYS_BUS_DEVICE,
334 .instance_size = sizeof(PL031State),
335 .instance_init = pl031_init,
336 .class_init = pl031_class_init,
337};
338
339static void pl031_register_types(void)
340{
341 type_register_static(&pl031_info);
342}
343
344type_init(pl031_register_types)
345