1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - savestates.c *
3 * Mupen64Plus homepage: https://mupen64plus.org/ *
4 * Copyright (C) 2012 CasualJames *
5 * Copyright (C) 2009 Olejl Tillin9 *
6 * Copyright (C) 2008 Richard42 Tillin9 *
7 * Copyright (C) 2002 Hacktarux *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
23 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
24
25#include <SDL.h>
26#include <SDL_thread.h>
27#include <stddef.h>
28#include <stdint.h>
29#include <stdio.h>
30#include <stdlib.h>
31#include <string.h>
32#include <sys/types.h>
33#include <zlib.h>
34#include <unzip.h>
35#include <zip.h>
36
37#define M64P_CORE_PROTOTYPES 1
38#include "api/callbacks.h"
39#include "api/config.h"
40#include "api/m64p_config.h"
41#include "api/m64p_types.h"
42#include "backends/api/storage_backend.h"
43#include "device/device.h"
44#include "main/list.h"
45#include "main/main.h"
46#include "osal/preproc.h"
47#include "osd/osd.h"
48#include "plugin/plugin.h"
49#include "rom.h"
50#include "savestates.h"
51#include "util.h"
52#include "workqueue.h"
53
54enum { GB_CART_FINGERPRINT_SIZE = 0x1c };
55enum { GB_CART_FINGERPRINT_OFFSET = 0x134 };
56
57enum { DD_DISK_ID_OFFSET = 0x43670 };
58
59static const char* savestate_magic = "M64+SAVE";
60static const int savestate_latest_version = 0x00010500; /* 1.5 */
61static const unsigned char pj64_magic[4] = { 0xC8, 0xA6, 0xD8, 0x23 };
62
63static savestates_job job = savestates_job_nothing;
64static savestates_type type = savestates_type_unknown;
65static char *fname = NULL;
66
67static unsigned int slot = 0;
68static int autoinc_save_slot = 0;
69
70static SDL_mutex *savestates_lock;
71
72struct savestate_work {
73 char *filepath;
74 char *data;
75 size_t size;
76 struct work_struct work;
77};
78
79/* Returns the malloc'd full path of the currently selected savestate. */
80static char *savestates_generate_path(savestates_type type)
81{
82 if(fname != NULL) /* A specific path was given. */
83 {
84 return strdup(fname);
85 }
86 else /* Use the selected savestate slot */
87 {
88 char *filename;
89 switch (type)
90 {
91 case savestates_type_m64p:
92 filename = formatstr("%s.st%d", ROM_SETTINGS.goodname, slot);
93 break;
94 case savestates_type_pj64_zip:
95 filename = formatstr("%s.pj%d.zip", ROM_PARAMS.headername, slot);
96 break;
97 case savestates_type_pj64_unc:
98 filename = formatstr("%s.pj%d", ROM_PARAMS.headername, slot);
99 break;
100 default:
101 filename = NULL;
102 break;
103 }
104
105 if (filename != NULL)
106 {
107 char *filepath = formatstr("%s%s", get_savestatepath(), filename);
108 free(filename);
109 return filepath;
110 }
111 else
112 return NULL;
113 }
114}
115
116void savestates_select_slot(unsigned int s)
117{
118 if(s>9||s==slot)
119 return;
120 slot = s;
121 ConfigSetParameter(g_CoreConfig, "CurrentStateSlot", M64TYPE_INT, &s);
122 StateChanged(M64CORE_SAVESTATE_SLOT, slot);
123
124 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Selected state slot: %d", slot);
125}
126
127/* Returns the currently selected save slot. */
128unsigned int savestates_get_slot(void)
129{
130 return slot;
131}
132
133/* Sets save state slot autoincrement on or off. */
134void savestates_set_autoinc_slot(int b)
135{
136 autoinc_save_slot = b;
137}
138
139void savestates_inc_slot(void)
140{
141 if(++slot>9)
142 slot = 0;
143 StateChanged(M64CORE_SAVESTATE_SLOT, slot);
144}
145
146savestates_job savestates_get_job(void)
147{
148 return job;
149}
150
151void savestates_set_job(savestates_job j, savestates_type t, const char *fn)
152{
153 if (fname != NULL)
154 {
155 free(fname);
156 fname = NULL;
157 }
158
159 job = j;
160 type = t;
161 if (fn != NULL)
162 fname = strdup(fn);
163}
164
165static void savestates_clear_job(void)
166{
167 savestates_set_job(savestates_job_nothing, savestates_type_unknown, NULL);
168}
169
170#define GETARRAY(buff, type, count) \
171 (to_little_endian_buffer(buff, sizeof(type),count), \
172 buff += count*sizeof(type), \
173 (type *)(buff-count*sizeof(type)))
174#define COPYARRAY(dst, buff, type, count) \
175 memcpy(dst, GETARRAY(buff, type, count), sizeof(type)*count)
176#define GETDATA(buff, type) *GETARRAY(buff, type, 1)
177#define PUTARRAY(src, buff, type, count) \
178 memcpy(buff, src, sizeof(type)*count); \
179 to_little_endian_buffer(buff, sizeof(type), count); \
180 buff += count*sizeof(type);
181
182#define PUTDATA(buff, type, value) \
183 do { type x = value; PUTARRAY(&x, buff, type, 1); } while(0)
184
185static int savestates_load_m64p(struct device* dev, char *filepath)
186{
187 unsigned char header[44];
188 gzFile f;
189 unsigned int version;
190 int i;
191 uint32_t FCR31;
192
193 size_t savestateSize;
194 unsigned char *savestateData, *curr;
195 char queue[1024];
196 unsigned char using_tlb_data[4];
197 unsigned char data_0001_0200[4096]; // 4k for extra state from v1.2
198 uint64_t flashram_status;
199
200 uint32_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
201
202 SDL_LockMutex(savestates_lock);
203
204 f = gzopen(filepath, "rb");
205 if(f==NULL)
206 {
207 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not open state file: %s", filepath);
208 SDL_UnlockMutex(savestates_lock);
209 return 0;
210 }
211
212 /* Read and check Mupen64Plus magic number. */
213 if (gzread(f, header, 44) != 44)
214 {
215 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read header from state file %s", filepath);
216 gzclose(f);
217 SDL_UnlockMutex(savestates_lock);
218 return 0;
219 }
220 curr = header;
221
222 if(strncmp((char *)curr, savestate_magic, 8)!=0)
223 {
224 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State file: %s is not a valid Mupen64plus savestate.", filepath);
225 gzclose(f);
226 SDL_UnlockMutex(savestates_lock);
227 return 0;
228 }
229 curr += 8;
230
231 version = *curr++;
232 version = (version << 8) | *curr++;
233 version = (version << 8) | *curr++;
234 version = (version << 8) | *curr++;
235 if((version >> 16) != (savestate_latest_version >> 16))
236 {
237 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State version (%08x) isn't compatible. Please update Mupen64Plus.", version);
238 gzclose(f);
239 SDL_UnlockMutex(savestates_lock);
240 return 0;
241 }
242
243 if(memcmp((char *)curr, ROM_SETTINGS.MD5, 32))
244 {
245 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State ROM MD5 does not match current ROM.");
246 gzclose(f);
247 SDL_UnlockMutex(savestates_lock);
248 return 0;
249 }
250 curr += 32;
251
252 /* Read the rest of the savestate */
253 savestateSize = 16788244;
254 savestateData = curr = (unsigned char *)malloc(savestateSize);
255 if (savestateData == NULL)
256 {
257 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Insufficient memory to load state.");
258 gzclose(f);
259 SDL_UnlockMutex(savestates_lock);
260 return 0;
261 }
262 if (version == 0x00010000) /* original savestate version */
263 {
264 if (gzread(f, savestateData, savestateSize) != (int)savestateSize ||
265 (gzread(f, queue, sizeof(queue)) % 4) != 0)
266 {
267 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read Mupen64Plus savestate 1.0 data from %s", filepath);
268 free(savestateData);
269 gzclose(f);
270 SDL_UnlockMutex(savestates_lock);
271 return 0;
272 }
273 }
274 else if (version == 0x00010100) // saves entire eventqueue plus 4-byte using_tlb flags
275 {
276 if (gzread(f, savestateData, savestateSize) != (int)savestateSize ||
277 gzread(f, queue, sizeof(queue)) != sizeof(queue) ||
278 gzread(f, using_tlb_data, sizeof(using_tlb_data)) != sizeof(using_tlb_data))
279 {
280 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read Mupen64Plus savestate 1.1 data from %s", filepath);
281 free(savestateData);
282 gzclose(f);
283 SDL_UnlockMutex(savestates_lock);
284 return 0;
285 }
286 }
287 else // version >= 0x00010200 saves entire eventqueue, 4-byte using_tlb flags and extra state
288 {
289 if (gzread(f, savestateData, savestateSize) != (int)savestateSize ||
290 gzread(f, queue, sizeof(queue)) != sizeof(queue) ||
291 gzread(f, using_tlb_data, sizeof(using_tlb_data)) != sizeof(using_tlb_data) ||
292 gzread(f, data_0001_0200, sizeof(data_0001_0200)) != sizeof(data_0001_0200))
293 {
294 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read Mupen64Plus savestate 1.2+ data from %s", filepath);
295 free(savestateData);
296 gzclose(f);
297 SDL_UnlockMutex(savestates_lock);
298 return 0;
299 }
300 }
301
302 gzclose(f);
303 SDL_UnlockMutex(savestates_lock);
304
305 // Parse savestate
306 dev->rdram.regs[0][RDRAM_CONFIG_REG] = GETDATA(curr, uint32_t);
307 dev->rdram.regs[0][RDRAM_DEVICE_ID_REG] = GETDATA(curr, uint32_t);
308 dev->rdram.regs[0][RDRAM_DELAY_REG] = GETDATA(curr, uint32_t);
309 dev->rdram.regs[0][RDRAM_MODE_REG] = GETDATA(curr, uint32_t);
310 dev->rdram.regs[0][RDRAM_REF_INTERVAL_REG] = GETDATA(curr, uint32_t);
311 dev->rdram.regs[0][RDRAM_REF_ROW_REG] = GETDATA(curr, uint32_t);
312 dev->rdram.regs[0][RDRAM_RAS_INTERVAL_REG] = GETDATA(curr, uint32_t);
313 dev->rdram.regs[0][RDRAM_MIN_INTERVAL_REG] = GETDATA(curr, uint32_t);
314 dev->rdram.regs[0][RDRAM_ADDR_SELECT_REG] = GETDATA(curr, uint32_t);
315 dev->rdram.regs[0][RDRAM_DEVICE_MANUF_REG] = GETDATA(curr, uint32_t);
316
317 curr += 4; /* Padding from old implementation */
318 dev->mi.regs[MI_INIT_MODE_REG] = GETDATA(curr, uint32_t);
319 curr += 4; // Duplicate MI init mode flags from old implementation
320 dev->mi.regs[MI_VERSION_REG] = GETDATA(curr, uint32_t);
321 dev->mi.regs[MI_INTR_REG] = GETDATA(curr, uint32_t);
322 dev->mi.regs[MI_INTR_MASK_REG] = GETDATA(curr, uint32_t);
323 curr += 4; /* Padding from old implementation */
324 curr += 8; // Duplicated MI intr flags and padding from old implementation
325
326 dev->pi.regs[PI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
327 dev->pi.regs[PI_CART_ADDR_REG] = GETDATA(curr, uint32_t);
328 dev->pi.regs[PI_RD_LEN_REG] = GETDATA(curr, uint32_t);
329 dev->pi.regs[PI_WR_LEN_REG] = GETDATA(curr, uint32_t);
330 dev->pi.regs[PI_STATUS_REG] = GETDATA(curr, uint32_t);
331 dev->pi.regs[PI_BSD_DOM1_LAT_REG] = GETDATA(curr, uint32_t);
332 dev->pi.regs[PI_BSD_DOM1_PWD_REG] = GETDATA(curr, uint32_t);
333 dev->pi.regs[PI_BSD_DOM1_PGS_REG] = GETDATA(curr, uint32_t);
334 dev->pi.regs[PI_BSD_DOM1_RLS_REG] = GETDATA(curr, uint32_t);
335 dev->pi.regs[PI_BSD_DOM2_LAT_REG] = GETDATA(curr, uint32_t);
336 dev->pi.regs[PI_BSD_DOM2_PWD_REG] = GETDATA(curr, uint32_t);
337 dev->pi.regs[PI_BSD_DOM2_PGS_REG] = GETDATA(curr, uint32_t);
338 dev->pi.regs[PI_BSD_DOM2_RLS_REG] = GETDATA(curr, uint32_t);
339
340 dev->sp.regs[SP_MEM_ADDR_REG] = GETDATA(curr, uint32_t);
341 dev->sp.regs[SP_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
342 dev->sp.regs[SP_RD_LEN_REG] = GETDATA(curr, uint32_t);
343 dev->sp.regs[SP_WR_LEN_REG] = GETDATA(curr, uint32_t);
344 curr += 4; /* Padding from old implementation */
345 dev->sp.regs[SP_STATUS_REG] = GETDATA(curr, uint32_t);
346 curr += 16; // Duplicated SP flags and padding from old implementation
347 dev->sp.regs[SP_DMA_FULL_REG] = GETDATA(curr, uint32_t);
348 dev->sp.regs[SP_DMA_BUSY_REG] = GETDATA(curr, uint32_t);
349 dev->sp.regs[SP_SEMAPHORE_REG] = GETDATA(curr, uint32_t);
350
351 dev->sp.regs2[SP_PC_REG] = GETDATA(curr, uint32_t);
352 dev->sp.regs2[SP_IBIST_REG] = GETDATA(curr, uint32_t);
353
354 dev->si.regs[SI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
355 dev->si.regs[SI_PIF_ADDR_RD64B_REG] = GETDATA(curr, uint32_t);
356 dev->si.regs[SI_PIF_ADDR_WR64B_REG] = GETDATA(curr, uint32_t);
357 dev->si.regs[SI_STATUS_REG] = GETDATA(curr, uint32_t);
358
359 dev->vi.regs[VI_STATUS_REG] = GETDATA(curr, uint32_t);
360 dev->vi.regs[VI_ORIGIN_REG] = GETDATA(curr, uint32_t);
361 dev->vi.regs[VI_WIDTH_REG] = GETDATA(curr, uint32_t);
362 dev->vi.regs[VI_V_INTR_REG] = GETDATA(curr, uint32_t);
363 dev->vi.regs[VI_CURRENT_REG] = GETDATA(curr, uint32_t);
364 dev->vi.regs[VI_BURST_REG] = GETDATA(curr, uint32_t);
365 dev->vi.regs[VI_V_SYNC_REG] = GETDATA(curr, uint32_t);
366 dev->vi.regs[VI_H_SYNC_REG] = GETDATA(curr, uint32_t);
367 dev->vi.regs[VI_LEAP_REG] = GETDATA(curr, uint32_t);
368 dev->vi.regs[VI_H_START_REG] = GETDATA(curr, uint32_t);
369 dev->vi.regs[VI_V_START_REG] = GETDATA(curr, uint32_t);
370 dev->vi.regs[VI_V_BURST_REG] = GETDATA(curr, uint32_t);
371 dev->vi.regs[VI_X_SCALE_REG] = GETDATA(curr, uint32_t);
372 dev->vi.regs[VI_Y_SCALE_REG] = GETDATA(curr, uint32_t);
373 dev->vi.delay = GETDATA(curr, uint32_t);
374 gfx.viStatusChanged();
375 gfx.viWidthChanged();
376
377 dev->ri.regs[RI_MODE_REG] = GETDATA(curr, uint32_t);
378 dev->ri.regs[RI_CONFIG_REG] = GETDATA(curr, uint32_t);
379 dev->ri.regs[RI_CURRENT_LOAD_REG] = GETDATA(curr, uint32_t);
380 dev->ri.regs[RI_SELECT_REG] = GETDATA(curr, uint32_t);
381 dev->ri.regs[RI_REFRESH_REG] = GETDATA(curr, uint32_t);
382 dev->ri.regs[RI_LATENCY_REG] = GETDATA(curr, uint32_t);
383 dev->ri.regs[RI_ERROR_REG] = GETDATA(curr, uint32_t);
384 dev->ri.regs[RI_WERROR_REG] = GETDATA(curr, uint32_t);
385
386 dev->ai.regs[AI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
387 dev->ai.regs[AI_LEN_REG] = GETDATA(curr, uint32_t);
388 dev->ai.regs[AI_CONTROL_REG] = GETDATA(curr, uint32_t);
389 dev->ai.regs[AI_STATUS_REG] = GETDATA(curr, uint32_t);
390 dev->ai.regs[AI_DACRATE_REG] = GETDATA(curr, uint32_t);
391 dev->ai.regs[AI_BITRATE_REG] = GETDATA(curr, uint32_t);
392 dev->ai.fifo[1].duration = GETDATA(curr, uint32_t);
393 dev->ai.fifo[1].length = GETDATA(curr, uint32_t);
394 dev->ai.fifo[0].duration = GETDATA(curr, uint32_t);
395 dev->ai.fifo[0].length = GETDATA(curr, uint32_t);
396 /* best effort initialization of fifo addresses...
397 * You might get a small sound "pop" because address might be wrong.
398 * Proper initialization requires changes to savestate format
399 */
400 dev->ai.fifo[0].address = dev->ai.regs[AI_DRAM_ADDR_REG];
401 dev->ai.fifo[1].address = dev->ai.regs[AI_DRAM_ADDR_REG];
402 dev->ai.samples_format_changed = 1;
403
404 dev->dp.dpc_regs[DPC_START_REG] = GETDATA(curr, uint32_t);
405 dev->dp.dpc_regs[DPC_END_REG] = GETDATA(curr, uint32_t);
406 dev->dp.dpc_regs[DPC_CURRENT_REG] = GETDATA(curr, uint32_t);
407 curr += 4; // Padding from old implementation
408 dev->dp.dpc_regs[DPC_STATUS_REG] = GETDATA(curr, uint32_t);
409 curr += 12; // Duplicated DPC flags and padding from old implementation
410 dev->dp.dpc_regs[DPC_CLOCK_REG] = GETDATA(curr, uint32_t);
411 dev->dp.dpc_regs[DPC_BUFBUSY_REG] = GETDATA(curr, uint32_t);
412 dev->dp.dpc_regs[DPC_PIPEBUSY_REG] = GETDATA(curr, uint32_t);
413 dev->dp.dpc_regs[DPC_TMEM_REG] = GETDATA(curr, uint32_t);
414
415 dev->dp.dps_regs[DPS_TBIST_REG] = GETDATA(curr, uint32_t);
416 dev->dp.dps_regs[DPS_TEST_MODE_REG] = GETDATA(curr, uint32_t);
417 dev->dp.dps_regs[DPS_BUFTEST_ADDR_REG] = GETDATA(curr, uint32_t);
418 dev->dp.dps_regs[DPS_BUFTEST_DATA_REG] = GETDATA(curr, uint32_t);
419
420 COPYARRAY(dev->rdram.dram, curr, uint32_t, RDRAM_MAX_SIZE/4);
421 COPYARRAY(dev->sp.mem, curr, uint32_t, SP_MEM_SIZE/4);
422 COPYARRAY(dev->pif.ram, curr, uint8_t, PIF_RAM_SIZE);
423
424 dev->cart.use_flashram = GETDATA(curr, int32_t);
425 dev->cart.flashram.mode = GETDATA(curr, int32_t);
426 flashram_status = GETDATA(curr, uint64_t);
427 dev->cart.flashram.status[0] = (uint32_t)(flashram_status >> 32);
428 dev->cart.flashram.status[1] = (uint32_t)(flashram_status);
429 dev->cart.flashram.erase_offset = GETDATA(curr, uint32_t);
430 dev->cart.flashram.write_pointer = GETDATA(curr, uint32_t);
431
432 COPYARRAY(dev->r4300.cp0.tlb.LUT_r, curr, uint32_t, 0x100000);
433 COPYARRAY(dev->r4300.cp0.tlb.LUT_w, curr, uint32_t, 0x100000);
434
435 *r4300_llbit(&dev->r4300) = GETDATA(curr, uint32_t);
436 COPYARRAY(r4300_regs(&dev->r4300), curr, int64_t, 32);
437 COPYARRAY(cp0_regs, curr, uint32_t, CP0_REGS_COUNT);
438 *r4300_mult_lo(&dev->r4300) = GETDATA(curr, int64_t);
439 *r4300_mult_hi(&dev->r4300) = GETDATA(curr, int64_t);
440 cp1_reg *cp1_regs = r4300_cp1_regs(&dev->r4300.cp1);
441 COPYARRAY(&cp1_regs->dword, curr, int64_t, 32);
442 *r4300_cp1_fcr0(&dev->r4300.cp1) = GETDATA(curr, uint32_t);
443 FCR31 = GETDATA(curr, uint32_t);
444 *r4300_cp1_fcr31(&dev->r4300.cp1) = FCR31;
445 set_fpr_pointers(&dev->r4300.cp1, cp0_regs[CP0_STATUS_REG]);
446 update_x86_rounding_mode(&dev->r4300.cp1);
447
448 for (i = 0; i < 32; i++)
449 {
450 dev->r4300.cp0.tlb.entries[i].mask = GETDATA(curr, int16_t);
451 curr += 2;
452 dev->r4300.cp0.tlb.entries[i].vpn2 = GETDATA(curr, uint32_t);
453 dev->r4300.cp0.tlb.entries[i].g = GETDATA(curr, char);
454 dev->r4300.cp0.tlb.entries[i].asid = GETDATA(curr, unsigned char);
455 curr += 2;
456 dev->r4300.cp0.tlb.entries[i].pfn_even = GETDATA(curr, uint32_t);
457 dev->r4300.cp0.tlb.entries[i].c_even = GETDATA(curr, char);
458 dev->r4300.cp0.tlb.entries[i].d_even = GETDATA(curr, char);
459 dev->r4300.cp0.tlb.entries[i].v_even = GETDATA(curr, char);
460 curr++;
461 dev->r4300.cp0.tlb.entries[i].pfn_odd = GETDATA(curr, uint32_t);
462 dev->r4300.cp0.tlb.entries[i].c_odd = GETDATA(curr, char);
463 dev->r4300.cp0.tlb.entries[i].d_odd = GETDATA(curr, char);
464 dev->r4300.cp0.tlb.entries[i].v_odd = GETDATA(curr, char);
465 dev->r4300.cp0.tlb.entries[i].r = GETDATA(curr, char);
466
467 dev->r4300.cp0.tlb.entries[i].start_even = GETDATA(curr, uint32_t);
468 dev->r4300.cp0.tlb.entries[i].end_even = GETDATA(curr, uint32_t);
469 dev->r4300.cp0.tlb.entries[i].phys_even = GETDATA(curr, uint32_t);
470 dev->r4300.cp0.tlb.entries[i].start_odd = GETDATA(curr, uint32_t);
471 dev->r4300.cp0.tlb.entries[i].end_odd = GETDATA(curr, uint32_t);
472 dev->r4300.cp0.tlb.entries[i].phys_odd = GETDATA(curr, uint32_t);
473 }
474
475 savestates_load_set_pc(&dev->r4300, GETDATA(curr, uint32_t));
476
477 *r4300_cp0_next_interrupt(&dev->r4300.cp0) = GETDATA(curr, uint32_t);
478 dev->vi.next_vi = GETDATA(curr, uint32_t);
479 dev->vi.field = GETDATA(curr, uint32_t);
480
481 // assert(savestateData+savestateSize == curr)
482
483 to_little_endian_buffer(queue, 4, 256);
484 load_eventqueue_infos(&dev->r4300.cp0, queue);
485
486#ifdef NEW_DYNAREC
487 // Default this to 1, it will be updated by the correct save state version later
488 stop_after_jal = 1;
489
490 if (version >= 0x00010100)
491 {
492 curr = using_tlb_data;
493 using_tlb = GETDATA(curr, uint32_t);
494 }
495#endif
496
497 if (version == 0x00010200)
498 {
499 union
500 {
501 uint8_t bytes[8];
502 uint64_t force_alignment;
503 } aligned;
504
505#define ALIGNED_GETDATA(buff, type) \
506 (COPYARRAY(aligned.bytes, buff, uint8_t, sizeof(type)), *(type*)aligned.bytes)
507
508 curr = data_0001_0200;
509
510 /* extra ai state */
511 dev->ai.last_read = GETDATA(curr, uint32_t);
512 dev->ai.delayed_carry = GETDATA(curr, uint32_t);
513
514 /* extra cart_rom state */
515 dev->cart.cart_rom.last_write = GETDATA(curr, uint32_t);
516 dev->cart.cart_rom.rom_written = GETDATA(curr, uint32_t);
517
518 /* extra sp state */
519 curr += 4; /* here there used to be rsp_task_locked */
520
521 /* extra af-rtc state */
522 dev->cart.af_rtc.control = GETDATA(curr, uint16_t);
523 dev->cart.af_rtc.now = (time_t)ALIGNED_GETDATA(curr, int64_t);
524 dev->cart.af_rtc.last_update_rtc = (time_t)ALIGNED_GETDATA(curr, int64_t);
525
526 /* extra controllers state */
527 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
528 dev->controllers[i].status = GETDATA(curr, uint8_t);
529 }
530
531 /* extra rpak state */
532 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
533 uint8_t rpk_state = GETDATA(curr, uint8_t);
534
535 /* init rumble pak state if enabled and not controlled by the input plugin */
536 if (ROM_SETTINGS.rumble && !Controls[i].RawData) {
537 set_rumble_reg(&dev->rumblepaks[i], rpk_state);
538 }
539 }
540
541 /* extra tpak state */
542 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
543 char gb_fingerprint[GB_CART_FINGERPRINT_SIZE];
544 uint8_t rtc_regs[MBC3_RTC_REGS_COUNT];
545 uint8_t rtc_latched_regs[MBC3_RTC_REGS_COUNT];
546 uint8_t cam_regs[POCKET_CAM_REGS_COUNT];
547 unsigned int rom_bank, ram_bank, ram_enable, mbc1_mode, rtc_latch;
548 time_t rtc_last_time;
549
550 unsigned int enabled = ALIGNED_GETDATA(curr, uint32_t);
551 unsigned int bank = ALIGNED_GETDATA(curr, uint32_t);
552 unsigned int access_mode = ALIGNED_GETDATA(curr, uint32_t);
553 unsigned int access_mode_changed = ALIGNED_GETDATA(curr, uint32_t);
554 COPYARRAY(gb_fingerprint, curr, uint8_t, GB_CART_FINGERPRINT_SIZE);
555 if (gb_fingerprint[0] != 0) {
556 rom_bank = ALIGNED_GETDATA(curr, uint32_t);
557 ram_bank = ALIGNED_GETDATA(curr, uint32_t);
558 ram_enable = ALIGNED_GETDATA(curr, uint32_t);
559 mbc1_mode = ALIGNED_GETDATA(curr, uint32_t);
560 COPYARRAY(rtc_regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
561 rtc_latch = ALIGNED_GETDATA(curr, uint32_t);
562 COPYARRAY(rtc_latched_regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
563 rtc_last_time = (time_t)ALIGNED_GETDATA(curr, int64_t);
564 COPYARRAY(cam_regs, curr, uint8_t, POCKET_CAM_REGS_COUNT);
565 }
566
567 if (ROM_SETTINGS.transferpak && !Controls[i].RawData) {
568
569 /* init transferpak state if enabled and not controlled by input plugin */
570 dev->transferpaks[i].enabled = enabled;
571 dev->transferpaks[i].bank = bank;
572 dev->transferpaks[i].access_mode = access_mode;
573 dev->transferpaks[i].access_mode_changed = access_mode_changed;
574
575 /* if it holds a valid cartridge init gbcart */
576 if (dev->transferpaks[i].gb_cart != NULL
577 && dev->transferpaks[i].gb_cart->irom_storage != NULL) {
578 const uint8_t* rom = dev->transferpaks[i].gb_cart->irom_storage->data
579 (dev->transferpaks[i].gb_cart->rom_storage);
580
581 /* verify that gb cart saved in savestate is the same
582 * as what is currently inserted in transferpak */
583 if (gb_fingerprint[0] != 0
584 && memcmp(gb_fingerprint,
585 rom + GB_CART_FINGERPRINT_OFFSET,
586 GB_CART_FINGERPRINT_SIZE) == 0) {
587
588 /* init gbcart state */
589 dev->transferpaks[i].gb_cart->rom_bank = rom_bank;
590 dev->transferpaks[i].gb_cart->ram_bank = ram_bank;
591 dev->transferpaks[i].gb_cart->ram_enable = ram_enable;
592 dev->transferpaks[i].gb_cart->mbc1_mode = mbc1_mode;
593 dev->transferpaks[i].gb_cart->rtc.latch = rtc_latch;
594 dev->transferpaks[i].gb_cart->rtc.last_time = rtc_last_time;
595
596 memcpy(dev->transferpaks[i].gb_cart->rtc.regs, rtc_regs, MBC3_RTC_REGS_COUNT);
597 memcpy(dev->transferpaks[i].gb_cart->rtc.latched_regs, rtc_latched_regs, MBC3_RTC_REGS_COUNT);
598 memcpy(dev->transferpaks[i].gb_cart->cam.regs, cam_regs, POCKET_CAM_REGS_COUNT);
599 }
600 else {
601 DebugMessage(M64MSG_WARNING,
602 "Savestate GB cart mismatch. Current GB cart: %s. Expected GB cart : %s",
603 (rom[GB_CART_FINGERPRINT_OFFSET] == 0x00) ? "(none)" : (const char*)(rom + GB_CART_FINGERPRINT_OFFSET),
604 (gb_fingerprint[0] == 0x00) ? "(none)" : gb_fingerprint);
605
606 poweron_gb_cart(dev->transferpaks[i].gb_cart);
607 }
608 }
609 }
610 }
611
612 /* extra pif channels state */
613 for (i = 0; i < PIF_CHANNELS_COUNT; ++i) {
614 int offset = GETDATA(curr, int8_t);
615 if (offset >= 0) {
616 setup_pif_channel(&dev->pif.channels[i], dev->pif.ram + offset);
617 }
618 else {
619 disable_pif_channel(&dev->pif.channels[i]);
620 }
621 }
622
623 /* extra vi state */
624 dev->vi.count_per_scanline = ALIGNED_GETDATA(curr, uint32_t);
625
626 /* extra si state */
627 dev->si.dma_dir = GETDATA(curr, uint8_t);
628
629 /* extra dp state */
630 dev->dp.do_on_unfreeze = GETDATA(curr, uint8_t);
631
632 /* extra RDRAM register state */
633 for (i = 1; i < RDRAM_MAX_MODULES_COUNT; ++i) {
634 dev->rdram.regs[i][RDRAM_CONFIG_REG] = ALIGNED_GETDATA(curr, uint32_t);
635 dev->rdram.regs[i][RDRAM_DEVICE_ID_REG] = ALIGNED_GETDATA(curr, uint32_t);
636 dev->rdram.regs[i][RDRAM_DELAY_REG] = ALIGNED_GETDATA(curr, uint32_t);
637 dev->rdram.regs[i][RDRAM_MODE_REG] = ALIGNED_GETDATA(curr, uint32_t);
638 dev->rdram.regs[i][RDRAM_REF_INTERVAL_REG] = ALIGNED_GETDATA(curr, uint32_t);
639 dev->rdram.regs[i][RDRAM_REF_ROW_REG] = ALIGNED_GETDATA(curr, uint32_t);
640 dev->rdram.regs[i][RDRAM_RAS_INTERVAL_REG] = ALIGNED_GETDATA(curr, uint32_t);
641 dev->rdram.regs[i][RDRAM_MIN_INTERVAL_REG] = ALIGNED_GETDATA(curr, uint32_t);
642 dev->rdram.regs[i][RDRAM_ADDR_SELECT_REG] = ALIGNED_GETDATA(curr, uint32_t);
643 dev->rdram.regs[i][RDRAM_DEVICE_MANUF_REG] = ALIGNED_GETDATA(curr, uint32_t);
644 }
645 }
646 else if (version >= 0x00010300)
647 {
648 curr = data_0001_0200;
649
650 /* extra ai state */
651 dev->ai.last_read = GETDATA(curr, uint32_t);
652 dev->ai.delayed_carry = GETDATA(curr, uint32_t);
653
654 /* extra cart_rom state */
655 dev->cart.cart_rom.last_write = GETDATA(curr, uint32_t);
656 dev->cart.cart_rom.rom_written = GETDATA(curr, uint32_t);
657
658 /* extra sp state */
659 curr += 4; /* here there used to be rsp_task_locked */
660
661 /* extra af-rtc state */
662 dev->cart.af_rtc.control = GETDATA(curr, uint16_t);
663 curr += 2; /* padding to keep things 8-byte aligned */
664 dev->cart.af_rtc.now = (time_t)GETDATA(curr, int64_t);
665 dev->cart.af_rtc.last_update_rtc = (time_t)GETDATA(curr, int64_t);
666
667 /* extra controllers state */
668 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
669 dev->controllers[i].status = GETDATA(curr, uint8_t);
670 }
671
672 /* extra rpak state */
673 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
674 uint8_t rpk_state = GETDATA(curr, uint8_t);
675
676 /* init rumble pak state if enabled and not controlled by the input plugin */
677 if (ROM_SETTINGS.rumble && !Controls[i].RawData) {
678 set_rumble_reg(&dev->rumblepaks[i], rpk_state);
679 }
680 }
681
682 /* extra tpak state */
683 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
684 char gb_fingerprint[GB_CART_FINGERPRINT_SIZE];
685 uint8_t rtc_regs[MBC3_RTC_REGS_COUNT];
686 uint8_t rtc_latched_regs[MBC3_RTC_REGS_COUNT];
687 uint8_t cam_regs[POCKET_CAM_REGS_COUNT];
688 unsigned int rom_bank, ram_bank, ram_enable, mbc1_mode, rtc_latch;
689 time_t rtc_last_time;
690
691 unsigned int enabled = GETDATA(curr, uint32_t);
692 unsigned int bank = GETDATA(curr, uint32_t);
693 unsigned int access_mode = GETDATA(curr, uint32_t);
694 unsigned int access_mode_changed = GETDATA(curr, uint32_t);
695 COPYARRAY(gb_fingerprint, curr, uint8_t, GB_CART_FINGERPRINT_SIZE);
696 if (gb_fingerprint[0] != 0) {
697 rom_bank = GETDATA(curr, uint32_t);
698 ram_bank = GETDATA(curr, uint32_t);
699 ram_enable = GETDATA(curr, uint32_t);
700 mbc1_mode = GETDATA(curr, uint32_t);
701 rtc_latch = GETDATA(curr, uint32_t);
702 rtc_last_time = (time_t)GETDATA(curr, int64_t);
703 COPYARRAY(rtc_regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
704 COPYARRAY(rtc_latched_regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
705 COPYARRAY(cam_regs, curr, uint8_t, POCKET_CAM_REGS_COUNT);
706 }
707
708 if (ROM_SETTINGS.transferpak && !Controls[i].RawData) {
709
710 /* init transferpak state if enabled and not controlled by input plugin */
711 dev->transferpaks[i].enabled = enabled;
712 dev->transferpaks[i].bank = bank;
713 dev->transferpaks[i].access_mode = access_mode;
714 dev->transferpaks[i].access_mode_changed = access_mode_changed;
715
716 /* if it holds a valid cartridge init gbcart */
717 if (dev->transferpaks[i].gb_cart != NULL
718 && dev->transferpaks[i].gb_cart->irom_storage != NULL) {
719 const uint8_t* rom = dev->transferpaks[i].gb_cart->irom_storage->data
720 (dev->transferpaks[i].gb_cart->rom_storage);
721
722 /* verify that gb cart saved in savestate is the same
723 * as what is currently inserted in transferpak */
724 if (gb_fingerprint[0] != 0
725 && memcmp(gb_fingerprint,
726 rom + GB_CART_FINGERPRINT_OFFSET,
727 GB_CART_FINGERPRINT_SIZE) == 0) {
728
729 /* init gbcart state */
730 dev->transferpaks[i].gb_cart->rom_bank = rom_bank;
731 dev->transferpaks[i].gb_cart->ram_bank = ram_bank;
732 dev->transferpaks[i].gb_cart->ram_enable = ram_enable;
733 dev->transferpaks[i].gb_cart->mbc1_mode = mbc1_mode;
734 dev->transferpaks[i].gb_cart->rtc.latch = rtc_latch;
735 dev->transferpaks[i].gb_cart->rtc.last_time = rtc_last_time;
736
737 memcpy(dev->transferpaks[i].gb_cart->rtc.regs, rtc_regs, MBC3_RTC_REGS_COUNT);
738 memcpy(dev->transferpaks[i].gb_cart->rtc.latched_regs, rtc_latched_regs, MBC3_RTC_REGS_COUNT);
739 memcpy(dev->transferpaks[i].gb_cart->cam.regs, cam_regs, POCKET_CAM_REGS_COUNT);
740 }
741 else {
742 DebugMessage(M64MSG_WARNING,
743 "Savestate GB cart mismatch. Current GB cart: %s. Expected GB cart : %s",
744 (rom[GB_CART_FINGERPRINT_OFFSET] == 0x00) ? "(none)" : (const char*)(rom + GB_CART_FINGERPRINT_OFFSET),
745 (gb_fingerprint[0] == 0x00) ? "(none)" : gb_fingerprint);
746
747 poweron_gb_cart(dev->transferpaks[i].gb_cart);
748 }
749 }
750 }
751 }
752
753 /* extra pif channels state */
754 for (i = 0; i < PIF_CHANNELS_COUNT; ++i) {
755 int offset = GETDATA(curr, int8_t);
756 if (offset >= 0) {
757 setup_pif_channel(&dev->pif.channels[i], dev->pif.ram + offset);
758 }
759 else {
760 disable_pif_channel(&dev->pif.channels[i]);
761 }
762 }
763
764 /* extra si state */
765 dev->si.dma_dir = GETDATA(curr, uint8_t);
766
767 /* extra dp state */
768 dev->dp.do_on_unfreeze = GETDATA(curr, uint8_t);
769
770 /* extra vi state */
771 dev->vi.count_per_scanline = GETDATA(curr, uint32_t);
772
773 /* extra RDRAM register state */
774 for (i = 1; i < RDRAM_MAX_MODULES_COUNT; ++i) {
775 dev->rdram.regs[i][RDRAM_CONFIG_REG] = GETDATA(curr, uint32_t);
776 dev->rdram.regs[i][RDRAM_DEVICE_ID_REG] = GETDATA(curr, uint32_t);
777 dev->rdram.regs[i][RDRAM_DELAY_REG] = GETDATA(curr, uint32_t);
778 dev->rdram.regs[i][RDRAM_MODE_REG] = GETDATA(curr, uint32_t);
779 dev->rdram.regs[i][RDRAM_REF_INTERVAL_REG] = GETDATA(curr, uint32_t);
780 dev->rdram.regs[i][RDRAM_REF_ROW_REG] = GETDATA(curr, uint32_t);
781 dev->rdram.regs[i][RDRAM_RAS_INTERVAL_REG] = GETDATA(curr, uint32_t);
782 dev->rdram.regs[i][RDRAM_MIN_INTERVAL_REG] = GETDATA(curr, uint32_t);
783 dev->rdram.regs[i][RDRAM_ADDR_SELECT_REG] = GETDATA(curr, uint32_t);
784 dev->rdram.regs[i][RDRAM_DEVICE_MANUF_REG] = GETDATA(curr, uint32_t);
785 }
786
787 if (version >= 0x00010400) {
788 /* verify if DD data is present (and matches what's currently loaded) */
789 uint32_t disk_id = GETDATA(curr, uint32_t);
790
791 uint32_t* current_disk_id = ((dev->dd.rom_size > 0) && dev->dd.idisk != NULL)
792 ? (uint32_t*)(dev->dd.idisk->data(dev->dd.disk) + DD_DISK_ID_OFFSET)
793 : NULL;
794
795 if (current_disk_id != NULL && *current_disk_id == disk_id) {
796 dev->dd.regs[DD_ASIC_DATA] = GETDATA(curr, uint32_t);
797 dev->dd.regs[DD_ASIC_MISC_REG] = GETDATA(curr, uint32_t);
798 dev->dd.regs[DD_ASIC_CMD_STATUS] = GETDATA(curr, uint32_t);
799 dev->dd.regs[DD_ASIC_CUR_TK] = GETDATA(curr, uint32_t);
800 dev->dd.regs[DD_ASIC_BM_STATUS_CTL] = GETDATA(curr, uint32_t);
801 dev->dd.regs[DD_ASIC_ERR_SECTOR] = GETDATA(curr, uint32_t);
802 dev->dd.regs[DD_ASIC_SEQ_STATUS_CTL] = GETDATA(curr, uint32_t);
803 dev->dd.regs[DD_ASIC_CUR_SECTOR] = GETDATA(curr, uint32_t);
804 dev->dd.regs[DD_ASIC_HARD_RESET] = GETDATA(curr, uint32_t);
805 dev->dd.regs[DD_ASIC_C1_S0] = GETDATA(curr, uint32_t);
806 dev->dd.regs[DD_ASIC_HOST_SECBYTE] = GETDATA(curr, uint32_t);
807 dev->dd.regs[DD_ASIC_C1_S2] = GETDATA(curr, uint32_t);
808 dev->dd.regs[DD_ASIC_SEC_BYTE] = GETDATA(curr, uint32_t);
809 dev->dd.regs[DD_ASIC_C1_S4] = GETDATA(curr, uint32_t);
810 dev->dd.regs[DD_ASIC_C1_S6] = GETDATA(curr, uint32_t);
811 dev->dd.regs[DD_ASIC_CUR_ADDR] = GETDATA(curr, uint32_t);
812 dev->dd.regs[DD_ASIC_ID_REG] = GETDATA(curr, uint32_t);
813 dev->dd.regs[DD_ASIC_TEST_REG] = GETDATA(curr, uint32_t);
814 dev->dd.regs[DD_ASIC_TEST_PIN_SEL] = GETDATA(curr, uint32_t);
815
816 /* C2S buffer is expected to be always zero */
817 memset(dev->dd.c2s_buf, 0, 0x400);
818 COPYARRAY(dev->dd.ds_buf, curr, uint8_t, 0x100);
819 COPYARRAY(dev->dd.ms_ram, curr, uint8_t, 0x40);
820
821 dev->dd.rtc.now = (time_t)GETDATA(curr, int64_t);
822 dev->dd.rtc.last_update_rtc = (time_t)GETDATA(curr, int64_t);
823 dev->dd.bm_write = (unsigned char)GETDATA(curr, uint32_t);
824 dev->dd.bm_reset_held = (unsigned char)GETDATA(curr, uint32_t);
825 dev->dd.bm_block = (unsigned char)GETDATA(curr, uint32_t);
826 dev->dd.bm_zone = GETDATA(curr, uint32_t);
827 dev->dd.bm_track_offset = GETDATA(curr, uint32_t);
828 }
829 else {
830 curr += (3+DD_ASIC_REGS_COUNT)*sizeof(uint32_t) + 0x100 + 0x40 + 2*sizeof(int64_t) + 2*sizeof(unsigned int);
831 }
832 }
833
834 if (version >= 0x00010500)
835 {
836#ifdef NEW_DYNAREC
837 stop_after_jal = GETDATA(curr, uint32_t);
838#else
839 curr += sizeof(uint32_t);
840#endif
841 }
842 }
843 else
844 {
845 /* extra ai state */
846 dev->ai.last_read = 0;
847 dev->ai.delayed_carry = 0;
848
849 /* extra cart_rom state */
850 dev->cart.cart_rom.last_write = 0;
851 dev->cart.cart_rom.rom_written = 0;
852
853 /* extra af-rtc state */
854 dev->cart.af_rtc.control = 0x200;
855 dev->cart.af_rtc.now = 0;
856 dev->cart.af_rtc.last_update_rtc = 0;
857
858 /* extra controllers state */
859 for(i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
860 /* skip controllers handled by the input plugin */
861 if (Controls[i].RawData)
862 continue;
863
864 dev->controllers[i].flavor->reset(&dev->controllers[i]);
865
866 if (ROM_SETTINGS.rumble) {
867 poweron_rumblepak(&dev->rumblepaks[i]);
868 }
869 if (ROM_SETTINGS.transferpak) {
870 poweron_transferpak(&dev->transferpaks[i]);
871 }
872 }
873
874 /* extra pif channels state
875 * HACK: Assume PIF was in channel processing mode (and not in CIC challenge mode)
876 * Try to parse pif ram to setup pif channels
877 */
878 setup_channels_format(&dev->pif);
879
880 /* extra vi state */
881 dev->vi.count_per_scanline = (dev->vi.regs[VI_V_SYNC_REG] == 0)
882 ? 1500
883 : ((dev->vi.clock / dev->vi.expected_refresh_rate) / (dev->vi.regs[VI_V_SYNC_REG] + 1));
884
885 /* extra si state */
886 dev->si.dma_dir = SI_NO_DMA;
887
888 /* extra dp state */
889 dev->dp.do_on_unfreeze = 0;
890
891 /* extra rdram state
892 * Best effort, copy values from RDRAM module 0 except for DEVICE_ID
893 * which is set in accordance with the IPL3 procedure with 2M modules.
894 */
895 for (i = 0; i < RDRAM_MAX_MODULES_COUNT; ++i) {
896 memcpy(dev->rdram.regs[i], dev->rdram.regs[0], RDRAM_REGS_COUNT*sizeof(dev->rdram.regs[0][0]));
897 dev->rdram.regs[i][RDRAM_DEVICE_ID_REG] = ri_address_to_id_field(i * 0x200000) << 2;
898 }
899
900 /* dd state */
901 if (dev->dd.rom_size > 0 && dev->dd.idisk != NULL) {
902 poweron_dd(&dev->dd);
903 }
904 }
905
906 /* Zilmar-Spec plugin expect a call with control_id = -1 when RAM processing is done */
907 if (input.controllerCommand) {
908 input.controllerCommand(-1, NULL);
909 }
910
911 /* reset fb state */
912 poweron_fb(&dev->dp.fb);
913
914 dev->sp.rsp_task_locked = 0;
915 dev->r4300.cp0.interrupt_unsafe_state = 0;
916
917 *r4300_cp0_last_addr(&dev->r4300.cp0) = *r4300_pc(&dev->r4300);
918
919 free(savestateData);
920 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State loaded from: %s", namefrompath(filepath));
921 return 1;
922}
923
924static int savestates_load_pj64(struct device* dev,
925 char *filepath, void *handle,
926 int (*read_func)(void *, void *, size_t))
927{
928 char buffer[1024];
929 unsigned int vi_timer, SaveRDRAMSize;
930 size_t i;
931 uint32_t FCR31;
932
933 unsigned char header[8];
934 unsigned char RomHeader[0x40];
935
936 size_t savestateSize;
937 unsigned char *savestateData, *curr;
938
939 uint32_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
940
941 /* Read and check Project64 magic number. */
942 if (!read_func(handle, header, 8))
943 {
944 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read header from Project64 savestate %s", filepath);
945 return 0;
946 }
947
948 curr = header;
949 if (memcmp(curr, pj64_magic, 4) != 0)
950 {
951 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State file: %s is not a valid Project64 savestate. Unrecognized file format.", filepath);
952 return 0;
953 }
954 curr += 4;
955
956 SaveRDRAMSize = GETDATA(curr, uint32_t);
957
958 /* Read the rest of the savestate into memory. */
959 savestateSize = SaveRDRAMSize + 0x2754;
960 savestateData = curr = (unsigned char *)malloc(savestateSize);
961 if (savestateData == NULL)
962 {
963 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Insufficient memory to load state.");
964 return 0;
965 }
966 if (!read_func(handle, savestateData, savestateSize))
967 {
968 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not read savestate data from Project64 savestate %s", filepath);
969 free(savestateData);
970 return 0;
971 }
972
973 // check ROM header
974 COPYARRAY(RomHeader, curr, unsigned int, 0x40/4);
975 if(memcmp(RomHeader, dev->cart.cart_rom.rom, 0x40) != 0)
976 {
977 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State ROM header does not match current ROM.");
978 free(savestateData);
979 return 0;
980 }
981
982 // vi_timer
983 vi_timer = GETDATA(curr, uint32_t);
984
985 // Program Counter
986 *r4300_cp0_last_addr(&dev->r4300.cp0) = GETDATA(curr, uint32_t);
987
988 // GPR
989 COPYARRAY(r4300_regs(&dev->r4300), curr, int64_t, 32);
990
991 // FPR
992 cp1_reg *cp1_regs = r4300_cp1_regs(&dev->r4300.cp1);
993 COPYARRAY(&cp1_regs->dword, curr, int64_t, 32);
994
995 // CP0
996 COPYARRAY(cp0_regs, curr, uint32_t, CP0_REGS_COUNT);
997
998 set_fpr_pointers(&dev->r4300.cp1, cp0_regs[CP0_STATUS_REG]);
999
1000 // Initialze the interrupts
1001 vi_timer += cp0_regs[CP0_COUNT_REG];
1002 *r4300_cp0_next_interrupt(&dev->r4300.cp0) = (cp0_regs[CP0_COMPARE_REG] < vi_timer)
1003 ? cp0_regs[CP0_COMPARE_REG]
1004 : vi_timer;
1005 dev->vi.next_vi = vi_timer;
1006 dev->vi.field = 0;
1007 *((unsigned int*)&buffer[0]) = VI_INT;
1008 *((unsigned int*)&buffer[4]) = vi_timer;
1009 *((unsigned int*)&buffer[8]) = COMPARE_INT;
1010 *((unsigned int*)&buffer[12]) = cp0_regs[CP0_COMPARE_REG];
1011 *((unsigned int*)&buffer[16]) = 0xFFFFFFFF;
1012
1013 load_eventqueue_infos(&dev->r4300.cp0, buffer);
1014
1015 // FPCR
1016 *r4300_cp1_fcr0(&dev->r4300.cp1) = GETDATA(curr, uint32_t);
1017 curr += 30 * 4; // FCR1...FCR30 not supported
1018 FCR31 = GETDATA(curr, uint32_t);
1019 *r4300_cp1_fcr31(&dev->r4300.cp1) = FCR31;
1020 update_x86_rounding_mode(&dev->r4300.cp1);
1021
1022 // hi / lo
1023 *r4300_mult_hi(&dev->r4300) = GETDATA(curr, int64_t);
1024 *r4300_mult_lo(&dev->r4300) = GETDATA(curr, int64_t);
1025
1026 // rdram register
1027 dev->rdram.regs[0][RDRAM_CONFIG_REG] = GETDATA(curr, uint32_t);
1028 dev->rdram.regs[0][RDRAM_DEVICE_ID_REG] = GETDATA(curr, uint32_t);
1029 dev->rdram.regs[0][RDRAM_DELAY_REG] = GETDATA(curr, uint32_t);
1030 dev->rdram.regs[0][RDRAM_MODE_REG] = GETDATA(curr, uint32_t);
1031 dev->rdram.regs[0][RDRAM_REF_INTERVAL_REG] = GETDATA(curr, uint32_t);
1032 dev->rdram.regs[0][RDRAM_REF_ROW_REG] = GETDATA(curr, uint32_t);
1033 dev->rdram.regs[0][RDRAM_RAS_INTERVAL_REG] = GETDATA(curr, uint32_t);
1034 dev->rdram.regs[0][RDRAM_MIN_INTERVAL_REG] = GETDATA(curr, uint32_t);
1035 dev->rdram.regs[0][RDRAM_ADDR_SELECT_REG] = GETDATA(curr, uint32_t);
1036 dev->rdram.regs[0][RDRAM_DEVICE_MANUF_REG] = GETDATA(curr, uint32_t);
1037
1038 // sp_register
1039 dev->sp.regs[SP_MEM_ADDR_REG] = GETDATA(curr, uint32_t);
1040 dev->sp.regs[SP_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
1041 dev->sp.regs[SP_RD_LEN_REG] = GETDATA(curr, uint32_t);
1042 dev->sp.regs[SP_WR_LEN_REG] = GETDATA(curr, uint32_t);
1043 dev->sp.regs[SP_STATUS_REG] = GETDATA(curr, uint32_t);
1044 dev->sp.regs[SP_DMA_FULL_REG] = GETDATA(curr, uint32_t);
1045 dev->sp.regs[SP_DMA_BUSY_REG] = GETDATA(curr, uint32_t);
1046 dev->sp.regs[SP_SEMAPHORE_REG] = GETDATA(curr, uint32_t);
1047 dev->sp.regs2[SP_PC_REG] = GETDATA(curr, uint32_t);
1048 dev->sp.regs2[SP_IBIST_REG] = GETDATA(curr, uint32_t);
1049
1050 // dpc_register
1051 dev->dp.dpc_regs[DPC_START_REG] = GETDATA(curr, uint32_t);
1052 dev->dp.dpc_regs[DPC_END_REG] = GETDATA(curr, uint32_t);
1053 dev->dp.dpc_regs[DPC_CURRENT_REG] = GETDATA(curr, uint32_t);
1054 dev->dp.dpc_regs[DPC_STATUS_REG] = GETDATA(curr, uint32_t);
1055 dev->dp.dpc_regs[DPC_CLOCK_REG] = GETDATA(curr, uint32_t);
1056 dev->dp.dpc_regs[DPC_BUFBUSY_REG] = GETDATA(curr, uint32_t);
1057 dev->dp.dpc_regs[DPC_PIPEBUSY_REG] = GETDATA(curr, uint32_t);
1058 dev->dp.dpc_regs[DPC_TMEM_REG] = GETDATA(curr, uint32_t);
1059 (void)GETDATA(curr, uint32_t); // Dummy read
1060 (void)GETDATA(curr, uint32_t); // Dummy read
1061
1062 // mi_register
1063 dev->mi.regs[MI_INIT_MODE_REG] = GETDATA(curr, uint32_t);
1064 dev->mi.regs[MI_VERSION_REG] = GETDATA(curr, uint32_t);
1065 dev->mi.regs[MI_INTR_REG] = GETDATA(curr, uint32_t);
1066 dev->mi.regs[MI_INTR_MASK_REG] = GETDATA(curr, uint32_t);
1067
1068 // vi_register
1069 dev->vi.regs[VI_STATUS_REG] = GETDATA(curr, uint32_t);
1070 dev->vi.regs[VI_ORIGIN_REG] = GETDATA(curr, uint32_t);
1071 dev->vi.regs[VI_WIDTH_REG] = GETDATA(curr, uint32_t);
1072 dev->vi.regs[VI_V_INTR_REG] = GETDATA(curr, uint32_t);
1073 dev->vi.regs[VI_CURRENT_REG] = GETDATA(curr, uint32_t);
1074 dev->vi.regs[VI_BURST_REG] = GETDATA(curr, uint32_t);
1075 dev->vi.regs[VI_V_SYNC_REG] = GETDATA(curr, uint32_t);
1076 dev->vi.regs[VI_H_SYNC_REG] = GETDATA(curr, uint32_t);
1077 dev->vi.regs[VI_LEAP_REG] = GETDATA(curr, uint32_t);
1078 dev->vi.regs[VI_H_START_REG] = GETDATA(curr, uint32_t);
1079 dev->vi.regs[VI_V_START_REG] = GETDATA(curr, uint32_t);
1080 dev->vi.regs[VI_V_BURST_REG] = GETDATA(curr, uint32_t);
1081 dev->vi.regs[VI_X_SCALE_REG] = GETDATA(curr, uint32_t);
1082 dev->vi.regs[VI_Y_SCALE_REG] = GETDATA(curr, uint32_t);
1083 // TODO vi delay?
1084 gfx.viStatusChanged();
1085 gfx.viWidthChanged();
1086
1087 dev->vi.count_per_scanline = (dev->vi.regs[VI_V_SYNC_REG] == 0)
1088 ? 1500
1089 : ((dev->vi.clock / dev->vi.expected_refresh_rate) / (dev->vi.regs[VI_V_SYNC_REG] + 1));
1090
1091 /* extra si state */
1092 dev->si.dma_dir = SI_NO_DMA;
1093
1094 /* extra dp state */
1095 dev->dp.do_on_unfreeze = 0;
1096
1097 // ai_register
1098 dev->ai.regs[AI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
1099 dev->ai.regs[AI_LEN_REG] = GETDATA(curr, uint32_t);
1100 dev->ai.regs[AI_CONTROL_REG] = GETDATA(curr, uint32_t);
1101 dev->ai.regs[AI_STATUS_REG] = GETDATA(curr, uint32_t);
1102 dev->ai.regs[AI_DACRATE_REG] = GETDATA(curr, uint32_t);
1103 dev->ai.regs[AI_BITRATE_REG] = GETDATA(curr, uint32_t);
1104 dev->ai.samples_format_changed = 1;
1105
1106 /* extra ai state */
1107 dev->ai.last_read = 0;
1108 dev->ai.delayed_carry = 0;
1109
1110 // pi_register
1111 dev->pi.regs[PI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
1112 dev->pi.regs[PI_CART_ADDR_REG] = GETDATA(curr, uint32_t);
1113 dev->pi.regs[PI_RD_LEN_REG] = GETDATA(curr, uint32_t);
1114 dev->pi.regs[PI_WR_LEN_REG] = GETDATA(curr, uint32_t);
1115 dev->pi.regs[PI_STATUS_REG] = GETDATA(curr, uint32_t);
1116 dev->pi.regs[PI_BSD_DOM1_LAT_REG] = GETDATA(curr, uint32_t);
1117 dev->pi.regs[PI_BSD_DOM1_PWD_REG] = GETDATA(curr, uint32_t);
1118 dev->pi.regs[PI_BSD_DOM1_PGS_REG] = GETDATA(curr, uint32_t);
1119 dev->pi.regs[PI_BSD_DOM1_RLS_REG] = GETDATA(curr, uint32_t);
1120 dev->pi.regs[PI_BSD_DOM2_LAT_REG] = GETDATA(curr, uint32_t);
1121 dev->pi.regs[PI_BSD_DOM2_PWD_REG] = GETDATA(curr, uint32_t);
1122 dev->pi.regs[PI_BSD_DOM2_PGS_REG] = GETDATA(curr, uint32_t);
1123 dev->pi.regs[PI_BSD_DOM2_RLS_REG] = GETDATA(curr, uint32_t);
1124 read_func(handle, dev->pi.regs, PI_REGS_COUNT*sizeof(dev->pi.regs[0]));
1125
1126 /* extra cart_rom state */
1127 dev->cart.cart_rom.last_write = 0;
1128 dev->cart.cart_rom.rom_written = 0;
1129
1130 // ri_register
1131 dev->ri.regs[RI_MODE_REG] = GETDATA(curr, uint32_t);
1132 dev->ri.regs[RI_CONFIG_REG] = GETDATA(curr, uint32_t);
1133 dev->ri.regs[RI_CURRENT_LOAD_REG] = GETDATA(curr, uint32_t);
1134 dev->ri.regs[RI_SELECT_REG] = GETDATA(curr, uint32_t);
1135 dev->ri.regs[RI_REFRESH_REG] = GETDATA(curr, uint32_t);
1136 dev->ri.regs[RI_LATENCY_REG] = GETDATA(curr, uint32_t);
1137 dev->ri.regs[RI_ERROR_REG] = GETDATA(curr, uint32_t);
1138 dev->ri.regs[RI_WERROR_REG] = GETDATA(curr, uint32_t);
1139
1140 // si_register
1141 dev->si.regs[SI_DRAM_ADDR_REG] = GETDATA(curr, uint32_t);
1142 dev->si.regs[SI_PIF_ADDR_RD64B_REG] = GETDATA(curr, uint32_t);
1143 dev->si.regs[SI_PIF_ADDR_WR64B_REG] = GETDATA(curr, uint32_t);
1144 dev->si.regs[SI_STATUS_REG] = GETDATA(curr, uint32_t);
1145
1146 // tlb
1147 memset(dev->r4300.cp0.tlb.LUT_r, 0, 0x400000);
1148 memset(dev->r4300.cp0.tlb.LUT_w, 0, 0x400000);
1149 for (i=0; i < 32; i++)
1150 {
1151 unsigned int MyPageMask, MyEntryHi, MyEntryLo0, MyEntryLo1;
1152
1153 (void)GETDATA(curr, uint32_t); // Dummy read - EntryDefined
1154 MyPageMask = GETDATA(curr, uint32_t);
1155 MyEntryHi = GETDATA(curr, uint32_t);
1156 MyEntryLo0 = GETDATA(curr, uint32_t);
1157 MyEntryLo1 = GETDATA(curr, uint32_t);
1158
1159 // This is copied from TLBWI instruction
1160 dev->r4300.cp0.tlb.entries[i].g = (MyEntryLo0 & MyEntryLo1 & 1);
1161 dev->r4300.cp0.tlb.entries[i].pfn_even = (MyEntryLo0 & 0x3FFFFFC0) >> 6;
1162 dev->r4300.cp0.tlb.entries[i].pfn_odd = (MyEntryLo1 & 0x3FFFFFC0) >> 6;
1163 dev->r4300.cp0.tlb.entries[i].c_even = (MyEntryLo0 & 0x38) >> 3;
1164 dev->r4300.cp0.tlb.entries[i].c_odd = (MyEntryLo1 & 0x38) >> 3;
1165 dev->r4300.cp0.tlb.entries[i].d_even = (MyEntryLo0 & 0x4) >> 2;
1166 dev->r4300.cp0.tlb.entries[i].d_odd = (MyEntryLo1 & 0x4) >> 2;
1167 dev->r4300.cp0.tlb.entries[i].v_even = (MyEntryLo0 & 0x2) >> 1;
1168 dev->r4300.cp0.tlb.entries[i].v_odd = (MyEntryLo1 & 0x2) >> 1;
1169 dev->r4300.cp0.tlb.entries[i].asid = (MyEntryHi & 0xFF);
1170 dev->r4300.cp0.tlb.entries[i].vpn2 = (MyEntryHi & 0xFFFFE000) >> 13;
1171 //dev->r4300.cp0.tlb.entries[i].r = (MyEntryHi & 0xC000000000000000LL) >> 62;
1172 dev->r4300.cp0.tlb.entries[i].mask = (MyPageMask & 0x1FFE000) >> 13;
1173
1174 dev->r4300.cp0.tlb.entries[i].start_even = dev->r4300.cp0.tlb.entries[i].vpn2 << 13;
1175 dev->r4300.cp0.tlb.entries[i].end_even = dev->r4300.cp0.tlb.entries[i].start_even+
1176 (dev->r4300.cp0.tlb.entries[i].mask << 12) + 0xFFF;
1177 dev->r4300.cp0.tlb.entries[i].phys_even = dev->r4300.cp0.tlb.entries[i].pfn_even << 12;
1178
1179 dev->r4300.cp0.tlb.entries[i].start_odd = dev->r4300.cp0.tlb.entries[i].end_even+1;
1180 dev->r4300.cp0.tlb.entries[i].end_odd = dev->r4300.cp0.tlb.entries[i].start_odd+
1181 (dev->r4300.cp0.tlb.entries[i].mask << 12) + 0xFFF;
1182 dev->r4300.cp0.tlb.entries[i].phys_odd = dev->r4300.cp0.tlb.entries[i].pfn_odd << 12;
1183
1184 tlb_map(&dev->r4300.cp0.tlb, i);
1185 }
1186
1187 // pif ram
1188 COPYARRAY(dev->pif.ram, curr, uint8_t, PIF_RAM_SIZE);
1189
1190 /* extra pif channels state
1191 * HACK: Assume PIF was in channel processing mode (and not in CIC challenge mode)
1192 * Try to parse pif ram to setup pif channels
1193 */
1194 setup_channels_format(&dev->pif);
1195
1196 /* Zilmar-Spec plugin expect a call with control_id = -1 when RAM processing is done */
1197 if (input.controllerCommand) {
1198 input.controllerCommand(-1, NULL);
1199 }
1200
1201 // RDRAM
1202 memset(dev->rdram.dram, 0, RDRAM_MAX_SIZE);
1203 COPYARRAY(dev->rdram.dram, curr, uint32_t, SaveRDRAMSize/4);
1204
1205 // DMEM + IMEM
1206 COPYARRAY(dev->sp.mem, curr, uint32_t, SP_MEM_SIZE/4);
1207
1208 // The following values should not matter because we don't have any AI interrupt
1209 // dev->ai.fifo[1].delay = 0; dev->ai.fifo[1].length = 0;
1210 // dev->ai.fifo[0].delay = 0; dev->ai.fifo[0].length = 0;
1211
1212 // The following is not available in PJ64 savestate. Keep the values as is.
1213 // dev->dp.dps_regs[DPS_TBIST_REG] = 0; dev->dp.dps_regs[DPS_TEST_MODE_REG] = 0;
1214 // dev->dp.dps_regs[DPS_BUFTEST_ADDR_REG] = 0; dev->dp.dps_regs[DPS_BUFTEST_DATA_REG] = 0; *r4300_llbit(&dev->r4300) = 0;
1215
1216 // No flashram info in pj64 savestate.
1217 poweron_flashram(&dev->cart.flashram);
1218
1219 dev->sp.rsp_task_locked = 0;
1220 dev->r4300.cp0.interrupt_unsafe_state = 0;
1221
1222 /* extra fb state */
1223 poweron_fb(&dev->dp.fb);
1224
1225 /* extra af-rtc state */
1226 dev->cart.af_rtc.control = 0x200;
1227 dev->cart.af_rtc.now = 0;
1228 dev->cart.af_rtc.last_update_rtc = 0;
1229
1230 /* extra controllers state */
1231 for(i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
1232 /* skip controllers handled by the input plugin */
1233 if (Controls[i].RawData)
1234 continue;
1235
1236 dev->controllers[i].flavor->reset(&dev->controllers[i]);
1237
1238 if (ROM_SETTINGS.rumble) {
1239 poweron_rumblepak(&dev->rumblepaks[i]);
1240 }
1241 if (ROM_SETTINGS.transferpak) {
1242 poweron_transferpak(&dev->transferpaks[i]);
1243 }
1244 }
1245
1246 /* extra rdram state
1247 * Best effort, copy values from RDRAM module 0 except for DEVICE_ID
1248 * which is set in accordance with the IPL3 procedure with 2M modules.
1249 */
1250 for (i = 0; i < (SaveRDRAMSize / 0x200000); ++i) {
1251 memcpy(dev->rdram.regs[i], dev->rdram.regs[0], RDRAM_REGS_COUNT*sizeof(dev->rdram.regs[0][0]));
1252 dev->rdram.regs[i][RDRAM_DEVICE_ID_REG] = ri_address_to_id_field(i * 0x200000) << 2;
1253 }
1254
1255 /* dd state */
1256 if (dev->dd.rom_size > 0 && dev->dd.idisk != NULL) {
1257 poweron_dd(&dev->dd);
1258 }
1259
1260 savestates_load_set_pc(&dev->r4300, *r4300_cp0_last_addr(&dev->r4300.cp0));
1261
1262 // assert(savestateData+savestateSize == curr)
1263
1264 free(savestateData);
1265 return 1;
1266}
1267
1268static int read_data_from_zip(void *zip, void *buffer, size_t length)
1269{
1270 int err = unzReadCurrentFile((unzFile)zip, buffer, (unsigned)length);
1271 return (err >= 0) && ((size_t)err == length);
1272}
1273
1274static int savestates_load_pj64_zip(struct device* dev, char *filepath)
1275{
1276 char szFileName[256], szExtraField[256], szComment[256];
1277 unzFile zipstatefile = NULL;
1278 unz_file_info fileinfo;
1279 int ret = 0;
1280
1281 /* Open the .zip file. */
1282 zipstatefile = unzOpen(filepath);
1283 if (zipstatefile == NULL ||
1284 unzGoToFirstFile(zipstatefile) != UNZ_OK ||
1285 unzGetCurrentFileInfo(zipstatefile, &fileinfo, szFileName, 255, szExtraField, 255, szComment, 255) != UNZ_OK ||
1286 unzOpenCurrentFile(zipstatefile) != UNZ_OK)
1287 {
1288 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Zip error. Could not open state file: %s", filepath);
1289 goto clean_and_exit;
1290 }
1291
1292 if (!savestates_load_pj64(dev, filepath, zipstatefile, read_data_from_zip))
1293 goto clean_and_exit;
1294
1295 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State loaded from: %s", namefrompath(filepath));
1296 ret = 1;
1297
1298 clean_and_exit:
1299 if (zipstatefile != NULL)
1300 unzClose(zipstatefile);
1301 return ret;
1302}
1303
1304static int read_data_from_file(void *file, void *buffer, size_t length)
1305{
1306 return fread(buffer, 1, length, file) == length;
1307}
1308
1309static int savestates_load_pj64_unc(struct device* dev, char *filepath)
1310{
1311 FILE *f;
1312
1313 /* Open the file. */
1314 f = fopen(filepath, "rb");
1315 if (f == NULL)
1316 {
1317 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not open state file: %s", filepath);
1318 return 0;
1319 }
1320
1321 if (!savestates_load_pj64(dev, filepath, f, read_data_from_file))
1322 {
1323 fclose(f);
1324 return 0;
1325 }
1326
1327 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "State loaded from: %s", namefrompath(filepath));
1328 fclose(f);
1329 return 1;
1330}
1331
1332static savestates_type savestates_detect_type(char *filepath)
1333{
1334 unsigned char magic[4];
1335 FILE *f = fopen(filepath, "rb");
1336 if (f == NULL)
1337 {
1338 DebugMessage(M64MSG_STATUS, "Could not open state file %s\n", filepath);
1339 return savestates_type_unknown;
1340 }
1341
1342 if (fread(magic, 1, 4, f) != 4)
1343 {
1344 fclose(f);
1345 DebugMessage(M64MSG_STATUS, "Could not read from state file %s\n", filepath);
1346 return savestates_type_unknown;
1347 }
1348
1349 fclose(f);
1350
1351 if (magic[0] == 0x1f && magic[1] == 0x8b) // GZIP header
1352 return savestates_type_m64p;
1353 else if (memcmp(magic, "PK\x03\x04", 4) == 0) // ZIP header
1354 return savestates_type_pj64_zip;
1355 else if (memcmp(magic, pj64_magic, 4) == 0) // PJ64 header
1356 return savestates_type_pj64_unc;
1357 else
1358 {
1359 DebugMessage(M64MSG_STATUS, "Unknown state file type %s\n", filepath);
1360 return savestates_type_unknown;
1361 }
1362}
1363
1364int savestates_load(void)
1365{
1366 FILE *fPtr = NULL;
1367 char *filepath = NULL;
1368 int ret = 0;
1369
1370 if (fname == NULL) // For slots, autodetect the savestate type
1371 {
1372 // try M64P type first
1373 type = savestates_type_m64p;
1374 filepath = savestates_generate_path(type);
1375 fPtr = fopen(filepath, "rb"); // can I open this?
1376 if (fPtr == NULL)
1377 {
1378 free(filepath);
1379 // try PJ64 zipped type second
1380 type = savestates_type_pj64_zip;
1381 filepath = savestates_generate_path(type);
1382 fPtr = fopen(filepath, "rb"); // can I open this?
1383 if (fPtr == NULL)
1384 {
1385 free(filepath);
1386 // finally, try PJ64 uncompressed
1387 type = savestates_type_pj64_unc;
1388 filepath = savestates_generate_path(type);
1389 fPtr = fopen(filepath, "rb"); // can I open this?
1390 if (fPtr == NULL)
1391 {
1392 free(filepath);
1393 filepath = NULL;
1394 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "No Mupen64Plus/PJ64 state file found for slot %i", slot);
1395 type = savestates_type_unknown;
1396 }
1397 }
1398 }
1399 }
1400 else // filename of state file to load was set explicitly in 'fname'
1401 {
1402 // detect type if unknown
1403 if (type == savestates_type_unknown)
1404 {
1405 type = savestates_detect_type(fname);
1406 }
1407 filepath = savestates_generate_path(type);
1408 if (filepath != NULL)
1409 fPtr = fopen(filepath, "rb"); // can I open this?
1410 if (fPtr == NULL)
1411 {
1412 if (filepath != NULL)
1413 free(filepath);
1414 filepath = NULL;
1415 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Failed to open savestate file %s", filepath);
1416 }
1417 }
1418 if (fPtr != NULL)
1419 fclose(fPtr);
1420
1421 if (filepath != NULL)
1422 {
1423 struct device* dev = &g_dev;
1424
1425 switch (type)
1426 {
1427 case savestates_type_m64p: ret = savestates_load_m64p(dev, filepath); break;
1428 case savestates_type_pj64_zip: ret = savestates_load_pj64_zip(dev, filepath); break;
1429 case savestates_type_pj64_unc: ret = savestates_load_pj64_unc(dev, filepath); break;
1430 default: ret = 0; break;
1431 }
1432 free(filepath);
1433 filepath = NULL;
1434 }
1435
1436 // deliver callback to indicate completion of state loading operation
1437 StateChanged(M64CORE_STATE_LOADCOMPLETE, ret);
1438
1439 savestates_clear_job();
1440
1441 return ret;
1442}
1443
1444static void savestates_save_m64p_work(struct work_struct *work)
1445{
1446 gzFile f;
1447 int gzres;
1448 struct savestate_work *save = container_of(work, struct savestate_work, work);
1449
1450 SDL_LockMutex(savestates_lock);
1451
1452 // Write the state to a GZIP file
1453 f = gzopen(save->filepath, "wb");
1454
1455 if (f==NULL)
1456 {
1457 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not open state file: %s", save->filepath);
1458 free(save->data);
1459 return;
1460 }
1461
1462 gzres = gzwrite(f, save->data, save->size);
1463 if ((gzres < 0) || ((size_t)gzres != save->size))
1464 {
1465 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not write data to state file: %s", save->filepath);
1466 gzclose(f);
1467 free(save->data);
1468 return;
1469 }
1470
1471 gzclose(f);
1472 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Saved state to: %s", namefrompath(save->filepath));
1473 free(save->data);
1474 free(save->filepath);
1475 free(save);
1476
1477 SDL_UnlockMutex(savestates_lock);
1478}
1479
1480static int savestates_save_m64p(const struct device* dev, char *filepath)
1481{
1482 unsigned char outbuf[4];
1483 int i;
1484 uint64_t flashram_status;
1485
1486 char queue[1024];
1487
1488 struct savestate_work *save;
1489 char *curr;
1490
1491 /* OK to cast away const qualifier */
1492 const uint32_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
1493
1494 save = malloc(sizeof(*save));
1495 if (!save) {
1496 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Insufficient memory to save state.");
1497 return 0;
1498 }
1499
1500 save->filepath = strdup(filepath);
1501
1502 if(autoinc_save_slot)
1503 savestates_inc_slot();
1504
1505 save_eventqueue_infos(&dev->r4300.cp0, queue);
1506
1507 // Allocate memory for the save state data
1508 save->size = 16788288 + sizeof(queue) + 4 + 4096;
1509 save->data = curr = malloc(save->size);
1510 if (save->data == NULL)
1511 {
1512 free(save->filepath);
1513 free(save);
1514 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Insufficient memory to save state.");
1515 return 0;
1516 }
1517
1518 memset(save->data, 0, save->size);
1519
1520 // Write the save state data to memory
1521 PUTARRAY(savestate_magic, curr, unsigned char, 8);
1522
1523 outbuf[0] = (savestate_latest_version >> 24) & 0xff;
1524 outbuf[1] = (savestate_latest_version >> 16) & 0xff;
1525 outbuf[2] = (savestate_latest_version >> 8) & 0xff;
1526 outbuf[3] = (savestate_latest_version >> 0) & 0xff;
1527 PUTARRAY(outbuf, curr, unsigned char, 4);
1528
1529 PUTARRAY(ROM_SETTINGS.MD5, curr, char, 32);
1530
1531 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_CONFIG_REG]);
1532 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DEVICE_ID_REG]);
1533 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DELAY_REG]);
1534 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_MODE_REG]);
1535 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_REF_INTERVAL_REG]);
1536 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_REF_ROW_REG]);
1537 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_RAS_INTERVAL_REG]);
1538 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_MIN_INTERVAL_REG]);
1539 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_ADDR_SELECT_REG]);
1540 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DEVICE_MANUF_REG]);
1541
1542 PUTDATA(curr, uint32_t, 0); // Padding from old implementation
1543 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INIT_MODE_REG]);
1544 PUTDATA(curr, uint8_t, dev->mi.regs[MI_INIT_MODE_REG] & 0x7F);
1545 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INIT_MODE_REG] & 0x80) != 0);
1546 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INIT_MODE_REG] & 0x100) != 0);
1547 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INIT_MODE_REG] & 0x200) != 0);
1548 PUTDATA(curr, uint32_t, dev->mi.regs[MI_VERSION_REG]);
1549 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INTR_REG]);
1550 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INTR_MASK_REG]);
1551 PUTDATA(curr, uint32_t, 0); //Padding from old implementation
1552 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x1) != 0);
1553 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x2) != 0);
1554 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x4) != 0);
1555 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x8) != 0);
1556 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x10) != 0);
1557 PUTDATA(curr, uint8_t, (dev->mi.regs[MI_INTR_MASK_REG] & 0x20) != 0);
1558 PUTDATA(curr, uint16_t, 0); // Padding from old implementation
1559
1560 PUTDATA(curr, uint32_t, dev->pi.regs[PI_DRAM_ADDR_REG]);
1561 PUTDATA(curr, uint32_t, dev->pi.regs[PI_CART_ADDR_REG]);
1562 PUTDATA(curr, uint32_t, dev->pi.regs[PI_RD_LEN_REG]);
1563 PUTDATA(curr, uint32_t, dev->pi.regs[PI_WR_LEN_REG]);
1564 PUTDATA(curr, uint32_t, dev->pi.regs[PI_STATUS_REG]);
1565 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_LAT_REG]);
1566 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_PWD_REG]);
1567 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_PGS_REG]);
1568 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_RLS_REG]);
1569 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_LAT_REG]);
1570 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_PWD_REG]);
1571 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_PGS_REG]);
1572 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_RLS_REG]);
1573
1574 PUTDATA(curr, uint32_t, dev->sp.regs[SP_MEM_ADDR_REG]);
1575 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DRAM_ADDR_REG]);
1576 PUTDATA(curr, uint32_t, dev->sp.regs[SP_RD_LEN_REG]);
1577 PUTDATA(curr, uint32_t, dev->sp.regs[SP_WR_LEN_REG]);
1578 PUTDATA(curr, uint32_t, 0); /* Padding from old implementation */
1579 PUTDATA(curr, uint32_t, dev->sp.regs[SP_STATUS_REG]);
1580 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x1) != 0);
1581 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x2) != 0);
1582 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x4) != 0);
1583 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x8) != 0);
1584 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x10) != 0);
1585 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x20) != 0);
1586 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x40) != 0);
1587 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x80) != 0);
1588 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x100) != 0);
1589 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x200) != 0);
1590 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x400) != 0);
1591 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x800) != 0);
1592 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x1000) != 0);
1593 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x2000) != 0);
1594 PUTDATA(curr, uint8_t, (dev->sp.regs[SP_STATUS_REG] & 0x4000) != 0);
1595 PUTDATA(curr, uint8_t, 0);
1596 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DMA_FULL_REG]);
1597 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DMA_BUSY_REG]);
1598 PUTDATA(curr, uint32_t, dev->sp.regs[SP_SEMAPHORE_REG]);
1599
1600 PUTDATA(curr, uint32_t, dev->sp.regs2[SP_PC_REG]);
1601 PUTDATA(curr, uint32_t, dev->sp.regs2[SP_IBIST_REG]);
1602
1603 PUTDATA(curr, uint32_t, dev->si.regs[SI_DRAM_ADDR_REG]);
1604 PUTDATA(curr, uint32_t, dev->si.regs[SI_PIF_ADDR_RD64B_REG]);
1605 PUTDATA(curr, uint32_t, dev->si.regs[SI_PIF_ADDR_WR64B_REG]);
1606 PUTDATA(curr, uint32_t, dev->si.regs[SI_STATUS_REG]);
1607
1608 PUTDATA(curr, uint32_t, dev->vi.regs[VI_STATUS_REG]);
1609 PUTDATA(curr, uint32_t, dev->vi.regs[VI_ORIGIN_REG]);
1610 PUTDATA(curr, uint32_t, dev->vi.regs[VI_WIDTH_REG]);
1611 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_INTR_REG]);
1612 PUTDATA(curr, uint32_t, dev->vi.regs[VI_CURRENT_REG]);
1613 PUTDATA(curr, uint32_t, dev->vi.regs[VI_BURST_REG]);
1614 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_SYNC_REG]);
1615 PUTDATA(curr, uint32_t, dev->vi.regs[VI_H_SYNC_REG]);
1616 PUTDATA(curr, uint32_t, dev->vi.regs[VI_LEAP_REG]);
1617 PUTDATA(curr, uint32_t, dev->vi.regs[VI_H_START_REG]);
1618 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_START_REG]);
1619 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_BURST_REG]);
1620 PUTDATA(curr, uint32_t, dev->vi.regs[VI_X_SCALE_REG]);
1621 PUTDATA(curr, uint32_t, dev->vi.regs[VI_Y_SCALE_REG]);
1622 PUTDATA(curr, uint32_t, dev->vi.delay);
1623
1624 PUTDATA(curr, uint32_t, dev->ri.regs[RI_MODE_REG]);
1625 PUTDATA(curr, uint32_t, dev->ri.regs[RI_CONFIG_REG]);
1626 PUTDATA(curr, uint32_t, dev->ri.regs[RI_CURRENT_LOAD_REG]);
1627 PUTDATA(curr, uint32_t, dev->ri.regs[RI_SELECT_REG]);
1628 PUTDATA(curr, uint32_t, dev->ri.regs[RI_REFRESH_REG]);
1629 PUTDATA(curr, uint32_t, dev->ri.regs[RI_LATENCY_REG]);
1630 PUTDATA(curr, uint32_t, dev->ri.regs[RI_ERROR_REG]);
1631 PUTDATA(curr, uint32_t, dev->ri.regs[RI_WERROR_REG]);
1632
1633 PUTDATA(curr, uint32_t, dev->ai.regs[AI_DRAM_ADDR_REG]);
1634 PUTDATA(curr, uint32_t, dev->ai.regs[AI_LEN_REG]);
1635 PUTDATA(curr, uint32_t, dev->ai.regs[AI_CONTROL_REG]);
1636 PUTDATA(curr, uint32_t, dev->ai.regs[AI_STATUS_REG]);
1637 PUTDATA(curr, uint32_t, dev->ai.regs[AI_DACRATE_REG]);
1638 PUTDATA(curr, uint32_t, dev->ai.regs[AI_BITRATE_REG]);
1639 PUTDATA(curr, uint32_t, dev->ai.fifo[1].duration);
1640 PUTDATA(curr, uint32_t , dev->ai.fifo[1].length);
1641 PUTDATA(curr, uint32_t, dev->ai.fifo[0].duration);
1642 PUTDATA(curr, uint32_t , dev->ai.fifo[0].length);
1643
1644 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_START_REG]);
1645 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_END_REG]);
1646 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_CURRENT_REG]);
1647 PUTDATA(curr, uint32_t, 0); /* Padding from old implementation */
1648 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_STATUS_REG]);
1649 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x1) != 0);
1650 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x2) != 0);
1651 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x4) != 0);
1652 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x8) != 0);
1653 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x10) != 0);
1654 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x20) != 0);
1655 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x40) != 0);
1656 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x80) != 0);
1657 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x100) != 0);
1658 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x200) != 0);
1659 PUTDATA(curr, uint8_t, (dev->dp.dpc_regs[DPC_STATUS_REG] & 0x400) != 0);
1660 PUTDATA(curr, uint8_t, 0);
1661 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_CLOCK_REG]);
1662 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_BUFBUSY_REG]);
1663 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_PIPEBUSY_REG]);
1664 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_TMEM_REG]);
1665
1666 PUTDATA(curr, uint32_t, dev->dp.dps_regs[DPS_TBIST_REG]);
1667 PUTDATA(curr, uint32_t, dev->dp.dps_regs[DPS_TEST_MODE_REG]);
1668 PUTDATA(curr, uint32_t, dev->dp.dps_regs[DPS_BUFTEST_ADDR_REG]);
1669 PUTDATA(curr, uint32_t, dev->dp.dps_regs[DPS_BUFTEST_DATA_REG]);
1670
1671 PUTARRAY(dev->rdram.dram, curr, uint32_t, RDRAM_MAX_SIZE/4);
1672 PUTARRAY(dev->sp.mem, curr, uint32_t, SP_MEM_SIZE/4);
1673 PUTARRAY(dev->pif.ram, curr, uint8_t, PIF_RAM_SIZE);
1674
1675 PUTDATA(curr, int32_t, dev->cart.use_flashram);
1676 PUTDATA(curr, int32_t, dev->cart.flashram.mode);
1677 flashram_status = ((uint64_t)dev->cart.flashram.status[0] << 32) | dev->cart.flashram.status[1];
1678 PUTDATA(curr, uint64_t, flashram_status);
1679 PUTDATA(curr, uint32_t, dev->cart.flashram.erase_offset);
1680 PUTDATA(curr, uint32_t, dev->cart.flashram.write_pointer);
1681
1682 PUTARRAY(dev->r4300.cp0.tlb.LUT_r, curr, uint32_t, 0x100000);
1683 PUTARRAY(dev->r4300.cp0.tlb.LUT_w, curr, uint32_t, 0x100000);
1684
1685 /* OK to cast away const qualifier */
1686 PUTDATA(curr, uint32_t, *r4300_llbit((struct r4300_core*)&dev->r4300));
1687 PUTARRAY(r4300_regs((struct r4300_core*)&dev->r4300), curr, int64_t, 32);
1688 PUTARRAY(cp0_regs, curr, uint32_t, CP0_REGS_COUNT);
1689 PUTDATA(curr, int64_t, *r4300_mult_lo((struct r4300_core*)&dev->r4300));
1690 PUTDATA(curr, int64_t, *r4300_mult_hi((struct r4300_core*)&dev->r4300));
1691
1692 const cp1_reg *cp1_regs = r4300_cp1_regs((struct cp1*)&dev->r4300.cp1);
1693 PUTARRAY(&cp1_regs->dword, curr, int64_t, 32);
1694
1695 PUTDATA(curr, uint32_t, *r4300_cp1_fcr0((struct cp1*)&dev->r4300.cp1));
1696 PUTDATA(curr, uint32_t, *r4300_cp1_fcr31((struct cp1*)&dev->r4300.cp1));
1697 for (i = 0; i < 32; i++)
1698 {
1699 PUTDATA(curr, int16_t, dev->r4300.cp0.tlb.entries[i].mask);
1700 PUTDATA(curr, int16_t, 0);
1701 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].vpn2);
1702 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].g);
1703 PUTDATA(curr, unsigned char, dev->r4300.cp0.tlb.entries[i].asid);
1704 PUTDATA(curr, int16_t, 0);
1705 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].pfn_even);
1706 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].c_even);
1707 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].d_even);
1708 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].v_even);
1709 PUTDATA(curr, char, 0);
1710 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].pfn_odd);
1711 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].c_odd);
1712 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].d_odd);
1713 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].v_odd);
1714 PUTDATA(curr, char, dev->r4300.cp0.tlb.entries[i].r);
1715
1716 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].start_even);
1717 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].end_even);
1718 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].phys_even);
1719 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].start_odd);
1720 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].end_odd);
1721 PUTDATA(curr, uint32_t, dev->r4300.cp0.tlb.entries[i].phys_odd);
1722 }
1723 PUTDATA(curr, uint32_t, *r4300_pc((struct r4300_core*)&dev->r4300));
1724
1725 PUTDATA(curr, uint32_t, *r4300_cp0_next_interrupt((struct cp0*)&dev->r4300.cp0));
1726 PUTDATA(curr, uint32_t, dev->vi.next_vi);
1727 PUTDATA(curr, uint32_t, dev->vi.field);
1728
1729 to_little_endian_buffer(queue, 4, sizeof(queue)/4);
1730 PUTARRAY(queue, curr, char, sizeof(queue));
1731
1732#ifdef NEW_DYNAREC
1733 PUTDATA(curr, uint32_t, using_tlb);
1734#else
1735 PUTDATA(curr, uint32_t, 0);
1736#endif
1737
1738 PUTDATA(curr, uint32_t, dev->ai.last_read);
1739 PUTDATA(curr, uint32_t, dev->ai.delayed_carry);
1740
1741 PUTDATA(curr, uint32_t, dev->cart.cart_rom.last_write);
1742 PUTDATA(curr, uint32_t, dev->cart.cart_rom.rom_written);
1743
1744 PUTDATA(curr, uint32_t, 0); /* here there used to be rsp_task_locked */
1745
1746 PUTDATA(curr, uint16_t, dev->cart.af_rtc.control);
1747 PUTDATA(curr, uint16_t, 0); /* padding to keep things aligned */
1748 PUTDATA(curr, int64_t, dev->cart.af_rtc.now);
1749 PUTDATA(curr, int64_t, dev->cart.af_rtc.last_update_rtc);
1750
1751 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
1752 PUTDATA(curr, uint8_t, dev->controllers[i].status);
1753 }
1754
1755 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
1756 PUTDATA(curr, uint8_t, dev->rumblepaks[i].state);
1757 }
1758
1759 for (i = 0; i < GAME_CONTROLLERS_COUNT; ++i) {
1760 PUTDATA(curr, uint32_t, dev->transferpaks[i].enabled);
1761 PUTDATA(curr, uint32_t, dev->transferpaks[i].bank);
1762 PUTDATA(curr, uint32_t, dev->transferpaks[i].access_mode);
1763 PUTDATA(curr, uint32_t, dev->transferpaks[i].access_mode_changed);
1764
1765 if (dev->transferpaks[i].gb_cart == NULL) {
1766 uint8_t gb_fingerprint[GB_CART_FINGERPRINT_SIZE];
1767 memset(gb_fingerprint, 0, GB_CART_FINGERPRINT_SIZE);
1768 PUTARRAY(gb_fingerprint, curr, uint8_t, GB_CART_FINGERPRINT_SIZE);
1769 }
1770 else {
1771 uint8_t* rom = dev->transferpaks[i].gb_cart->irom_storage->data(dev->transferpaks[i].gb_cart->rom_storage);
1772 PUTARRAY(rom + GB_CART_FINGERPRINT_OFFSET, curr, uint8_t, GB_CART_FINGERPRINT_SIZE);
1773
1774 PUTDATA(curr, uint32_t, dev->transferpaks[i].gb_cart->rom_bank);
1775 PUTDATA(curr, uint32_t, dev->transferpaks[i].gb_cart->ram_bank);
1776 PUTDATA(curr, uint32_t, dev->transferpaks[i].gb_cart->ram_enable);
1777 PUTDATA(curr, uint32_t, dev->transferpaks[i].gb_cart->mbc1_mode);
1778 PUTDATA(curr, uint32_t, dev->transferpaks[i].gb_cart->rtc.latch);
1779 PUTDATA(curr, int64_t, dev->transferpaks[i].gb_cart->rtc.last_time);
1780
1781 PUTARRAY(dev->transferpaks[i].gb_cart->rtc.regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
1782 PUTARRAY(dev->transferpaks[i].gb_cart->rtc.latched_regs, curr, uint8_t, MBC3_RTC_REGS_COUNT);
1783
1784 PUTARRAY(dev->transferpaks[i].gb_cart->cam.regs, curr, uint8_t, POCKET_CAM_REGS_COUNT);
1785 }
1786 }
1787
1788 for (i = 0; i < PIF_CHANNELS_COUNT; ++i) {
1789 PUTDATA(curr, int8_t, (dev->pif.channels[i].tx == NULL)
1790 ? (int8_t)-1
1791 : (int8_t)(dev->pif.channels[i].tx - dev->pif.ram));
1792 }
1793
1794 PUTDATA(curr, uint8_t, dev->si.dma_dir);
1795
1796 PUTDATA(curr, uint8_t, dev->dp.do_on_unfreeze);
1797
1798 PUTDATA(curr, uint32_t, dev->vi.count_per_scanline);
1799
1800 for (i = 1; i < RDRAM_MAX_MODULES_COUNT; ++i) {
1801 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_CONFIG_REG]);
1802 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_DEVICE_ID_REG]);
1803 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_DELAY_REG]);
1804 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_MODE_REG]);
1805 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_REF_INTERVAL_REG]);
1806 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_REF_ROW_REG]);
1807 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_RAS_INTERVAL_REG]);
1808 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_MIN_INTERVAL_REG]);
1809 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_ADDR_SELECT_REG]);
1810 PUTDATA(curr, uint32_t, dev->rdram.regs[i][RDRAM_DEVICE_MANUF_REG]);
1811 }
1812
1813 uint32_t* disk_id = ((dev->dd.rom_size > 0) && dev->dd.idisk != NULL)
1814 ? (uint32_t*)(dev->dd.idisk->data(dev->dd.disk) + DD_DISK_ID_OFFSET)
1815 : NULL;
1816
1817 if (disk_id == NULL) {
1818 PUTDATA(curr, uint32_t, 0);
1819 curr += (3+DD_ASIC_REGS_COUNT)*sizeof(uint32_t) + 0x100 + 0x40 + 2*sizeof(int64_t) + 2*sizeof(uint32_t);
1820 }
1821 else {
1822 PUTDATA(curr, uint32_t, *disk_id);
1823
1824 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_DATA]);
1825 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_MISC_REG]);
1826 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_CMD_STATUS]);
1827 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_CUR_TK]);
1828 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_BM_STATUS_CTL]);
1829 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_ERR_SECTOR]);
1830 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_SEQ_STATUS_CTL]);
1831 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_CUR_SECTOR]);
1832 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_HARD_RESET]);
1833 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_C1_S0]);
1834 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_HOST_SECBYTE]);
1835 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_C1_S2]);
1836 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_SEC_BYTE]);
1837 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_C1_S4]);
1838 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_C1_S6]);
1839 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_CUR_ADDR]);
1840 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_ID_REG]);
1841 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_TEST_REG]);
1842 PUTDATA(curr, uint32_t, dev->dd.regs[DD_ASIC_TEST_PIN_SEL]);
1843
1844 PUTARRAY(dev->dd.ds_buf, curr, uint8_t, 0x100);
1845 PUTARRAY(dev->dd.ms_ram, curr, uint8_t, 0x40);
1846
1847 PUTDATA(curr, int64_t, (int64_t)dev->dd.rtc.now);
1848 PUTDATA(curr, int64_t, (int64_t)dev->dd.rtc.last_update_rtc);
1849 PUTDATA(curr, uint32_t, dev->dd.bm_write);
1850 PUTDATA(curr, uint32_t, dev->dd.bm_reset_held);
1851 PUTDATA(curr, uint32_t, dev->dd.bm_block);
1852 PUTDATA(curr, uint32_t, dev->dd.bm_zone);
1853 PUTDATA(curr, uint32_t, dev->dd.bm_track_offset);
1854 }
1855
1856#ifdef NEW_DYNAREC
1857 PUTDATA(curr, uint32_t, stop_after_jal);
1858#else
1859 PUTDATA(curr, uint32_t, 0);
1860#endif
1861
1862 init_work(&save->work, savestates_save_m64p_work);
1863 queue_work(&save->work);
1864
1865 return 1;
1866}
1867
1868static int savestates_save_pj64(const struct device* dev,
1869 char *filepath, void *handle,
1870 int (*write_func)(void *, const void *, size_t))
1871{
1872 unsigned int i;
1873 unsigned int SaveRDRAMSize = RDRAM_MAX_SIZE;
1874
1875 size_t savestateSize;
1876 unsigned char *savestateData, *curr;
1877
1878 const uint32_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
1879
1880 // Allocate memory for the save state data
1881 savestateSize = 8 + SaveRDRAMSize + 0x2754;
1882 savestateData = curr = (unsigned char *)malloc(savestateSize);
1883 if (savestateData == NULL)
1884 {
1885 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Insufficient memory to save state.");
1886 return 0;
1887 }
1888
1889 // Write the save state data in memory
1890 PUTARRAY(pj64_magic, curr, unsigned char, 4);
1891 PUTDATA(curr, unsigned int, SaveRDRAMSize);
1892 PUTARRAY(dev->cart.cart_rom.rom, curr, unsigned int, 0x40/4);
1893 PUTDATA(curr, uint32_t, get_event(&dev->r4300.cp0.q, VI_INT) - cp0_regs[CP0_COUNT_REG]); // vi_timer
1894 PUTDATA(curr, uint32_t, *r4300_pc((struct r4300_core*)&dev->r4300));
1895 PUTARRAY(r4300_regs((struct r4300_core*)&dev->r4300), curr, int64_t, 32);
1896 const cp1_reg* cp1_regs = r4300_cp1_regs((struct cp1*)&dev->r4300.cp1);
1897 PUTARRAY(&cp1_regs->dword, curr, int64_t, 32);
1898 PUTARRAY(cp0_regs, curr, uint32_t, CP0_REGS_COUNT);
1899 PUTDATA(curr, uint32_t, *r4300_cp1_fcr0((struct cp1*)&dev->r4300.cp1));
1900 for (i = 0; i < 30; i++)
1901 PUTDATA(curr, int, 0); // FCR1-30 not implemented
1902 PUTDATA(curr, uint32_t, *r4300_cp1_fcr31((struct cp1*)&dev->r4300.cp1));
1903 PUTDATA(curr, int64_t, *r4300_mult_hi((struct r4300_core*)&dev->r4300));
1904 PUTDATA(curr, int64_t, *r4300_mult_lo((struct r4300_core*)&dev->r4300));
1905
1906 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_CONFIG_REG]);
1907 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DEVICE_ID_REG]);
1908 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DELAY_REG]);
1909 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_MODE_REG]);
1910 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_REF_INTERVAL_REG]);
1911 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_REF_ROW_REG]);
1912 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_RAS_INTERVAL_REG]);
1913 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_MIN_INTERVAL_REG]);
1914 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_ADDR_SELECT_REG]);
1915 PUTDATA(curr, uint32_t, dev->rdram.regs[0][RDRAM_DEVICE_MANUF_REG]);
1916
1917 PUTDATA(curr, uint32_t, dev->sp.regs[SP_MEM_ADDR_REG]);
1918 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DRAM_ADDR_REG]);
1919 PUTDATA(curr, uint32_t, dev->sp.regs[SP_RD_LEN_REG]);
1920 PUTDATA(curr, uint32_t, dev->sp.regs[SP_WR_LEN_REG]);
1921 PUTDATA(curr, uint32_t, dev->sp.regs[SP_STATUS_REG]);
1922 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DMA_FULL_REG]);
1923 PUTDATA(curr, uint32_t, dev->sp.regs[SP_DMA_BUSY_REG]);
1924 PUTDATA(curr, uint32_t, dev->sp.regs[SP_SEMAPHORE_REG]);
1925
1926 PUTDATA(curr, uint32_t, dev->sp.regs2[SP_PC_REG]);
1927 PUTDATA(curr, uint32_t, dev->sp.regs2[SP_IBIST_REG]);
1928
1929 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_START_REG]);
1930 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_END_REG]);
1931 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_CURRENT_REG]);
1932 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_STATUS_REG]);
1933 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_CLOCK_REG]);
1934 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_BUFBUSY_REG]);
1935 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_PIPEBUSY_REG]);
1936 PUTDATA(curr, uint32_t, dev->dp.dpc_regs[DPC_TMEM_REG]);
1937 PUTDATA(curr, uint32_t, 0); // ?
1938 PUTDATA(curr, uint32_t, 0); // ?
1939
1940 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INIT_MODE_REG]); //TODO Secial handling in pj64
1941 PUTDATA(curr, uint32_t, dev->mi.regs[MI_VERSION_REG]);
1942 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INTR_REG]);
1943 PUTDATA(curr, uint32_t, dev->mi.regs[MI_INTR_MASK_REG]);
1944
1945 PUTDATA(curr, uint32_t, dev->vi.regs[VI_STATUS_REG]);
1946 PUTDATA(curr, uint32_t, dev->vi.regs[VI_ORIGIN_REG]);
1947 PUTDATA(curr, uint32_t, dev->vi.regs[VI_WIDTH_REG]);
1948 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_INTR_REG]);
1949 PUTDATA(curr, uint32_t, dev->vi.regs[VI_CURRENT_REG]);
1950 PUTDATA(curr, uint32_t, dev->vi.regs[VI_BURST_REG]);
1951 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_SYNC_REG]);
1952 PUTDATA(curr, uint32_t, dev->vi.regs[VI_H_SYNC_REG]);
1953 PUTDATA(curr, uint32_t, dev->vi.regs[VI_LEAP_REG]);
1954 PUTDATA(curr, uint32_t, dev->vi.regs[VI_H_START_REG]);
1955 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_START_REG]);
1956 PUTDATA(curr, uint32_t, dev->vi.regs[VI_V_BURST_REG]);
1957 PUTDATA(curr, uint32_t, dev->vi.regs[VI_X_SCALE_REG]);
1958 PUTDATA(curr, uint32_t, dev->vi.regs[VI_Y_SCALE_REG]);
1959
1960 PUTDATA(curr, uint32_t, dev->ai.regs[AI_DRAM_ADDR_REG]);
1961 PUTDATA(curr, uint32_t, dev->ai.regs[AI_LEN_REG]);
1962 PUTDATA(curr, uint32_t, dev->ai.regs[AI_CONTROL_REG]);
1963 PUTDATA(curr, uint32_t, dev->ai.regs[AI_STATUS_REG]);
1964 PUTDATA(curr, uint32_t, dev->ai.regs[AI_DACRATE_REG]);
1965 PUTDATA(curr, uint32_t, dev->ai.regs[AI_BITRATE_REG]);
1966
1967 PUTDATA(curr, uint32_t, dev->pi.regs[PI_DRAM_ADDR_REG]);
1968 PUTDATA(curr, uint32_t, dev->pi.regs[PI_CART_ADDR_REG]);
1969 PUTDATA(curr, uint32_t, dev->pi.regs[PI_RD_LEN_REG]);
1970 PUTDATA(curr, uint32_t, dev->pi.regs[PI_WR_LEN_REG]);
1971 PUTDATA(curr, uint32_t, dev->pi.regs[PI_STATUS_REG]);
1972 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_LAT_REG]);
1973 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_PWD_REG]);
1974 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_PGS_REG]);
1975 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM1_RLS_REG]);
1976 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_LAT_REG]);
1977 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_PWD_REG]);
1978 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_PGS_REG]);
1979 PUTDATA(curr, uint32_t, dev->pi.regs[PI_BSD_DOM2_RLS_REG]);
1980
1981 PUTDATA(curr, uint32_t, dev->ri.regs[RI_MODE_REG]);
1982 PUTDATA(curr, uint32_t, dev->ri.regs[RI_CONFIG_REG]);
1983 PUTDATA(curr, uint32_t, dev->ri.regs[RI_CURRENT_LOAD_REG]);
1984 PUTDATA(curr, uint32_t, dev->ri.regs[RI_SELECT_REG]);
1985 PUTDATA(curr, uint32_t, dev->ri.regs[RI_REFRESH_REG]);
1986 PUTDATA(curr, uint32_t, dev->ri.regs[RI_LATENCY_REG]);
1987 PUTDATA(curr, uint32_t, dev->ri.regs[RI_ERROR_REG]);
1988 PUTDATA(curr, uint32_t, dev->ri.regs[RI_WERROR_REG]);
1989
1990 PUTDATA(curr, uint32_t, dev->si.regs[SI_DRAM_ADDR_REG]);
1991 PUTDATA(curr, uint32_t, dev->si.regs[SI_PIF_ADDR_RD64B_REG]);
1992 PUTDATA(curr, uint32_t, dev->si.regs[SI_PIF_ADDR_WR64B_REG]);
1993 PUTDATA(curr, uint32_t, dev->si.regs[SI_STATUS_REG]);
1994
1995 for (i=0; i < 32;i++)
1996 {
1997 // From TLBR
1998 unsigned int EntryDefined, MyPageMask, MyEntryHi, MyEntryLo0, MyEntryLo1;
1999 EntryDefined = dev->r4300.cp0.tlb.entries[i].v_even || dev->r4300.cp0.tlb.entries[i].v_odd;
2000 MyPageMask = dev->r4300.cp0.tlb.entries[i].mask << 13;
2001 MyEntryHi = ((dev->r4300.cp0.tlb.entries[i].vpn2 << 13) | dev->r4300.cp0.tlb.entries[i].asid);
2002 MyEntryLo0 = (dev->r4300.cp0.tlb.entries[i].pfn_even << 6) | (dev->r4300.cp0.tlb.entries[i].c_even << 3)
2003 | (dev->r4300.cp0.tlb.entries[i].d_even << 2) | (dev->r4300.cp0.tlb.entries[i].v_even << 1)
2004 | dev->r4300.cp0.tlb.entries[i].g;
2005 MyEntryLo1 = (dev->r4300.cp0.tlb.entries[i].pfn_odd << 6) | (dev->r4300.cp0.tlb.entries[i].c_odd << 3)
2006 | (dev->r4300.cp0.tlb.entries[i].d_odd << 2) | (dev->r4300.cp0.tlb.entries[i].v_odd << 1)
2007 | dev->r4300.cp0.tlb.entries[i].g;
2008
2009 PUTDATA(curr, uint32_t, EntryDefined);
2010 PUTDATA(curr, uint32_t, MyPageMask);
2011 PUTDATA(curr, uint32_t, MyEntryHi);
2012 PUTDATA(curr, uint32_t, MyEntryLo0);
2013 PUTDATA(curr, uint32_t, MyEntryLo1);
2014 }
2015
2016 PUTARRAY(dev->pif.ram, curr, uint8_t, PIF_RAM_SIZE);
2017
2018 PUTARRAY(dev->rdram.dram, curr, uint32_t, SaveRDRAMSize/4);
2019 PUTARRAY(dev->sp.mem, curr, uint32_t, SP_MEM_SIZE/4);
2020
2021 // Write the save state data to the output
2022 if (!write_func(handle, savestateData, savestateSize))
2023 {
2024 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Couldn't write data to Project64 state file %s.", filepath);
2025 free(savestateData);
2026 return 0;
2027 }
2028
2029 // assert(savestateData+savestateSize == curr)
2030 free(savestateData);
2031 return 1;
2032}
2033
2034static int write_data_to_zip(void *zip, const void *buffer, size_t length)
2035{
2036 return zipWriteInFileInZip((zipFile)zip, buffer, (unsigned)length) == ZIP_OK;
2037}
2038
2039static int savestates_save_pj64_zip(const struct device* dev, char *filepath)
2040{
2041 int retval;
2042 zipFile zipfile = NULL;
2043
2044 zipfile = zipOpen(filepath, APPEND_STATUS_CREATE);
2045 if(zipfile == NULL)
2046 {
2047 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not create PJ64 state file: %s", filepath);
2048 goto clean_and_exit;
2049 }
2050
2051 retval = zipOpenNewFileInZip(zipfile, namefrompath(filepath), NULL, NULL, 0, NULL, 0, NULL, Z_DEFLATED, Z_DEFAULT_COMPRESSION);
2052 if(retval != ZIP_OK)
2053 {
2054 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Zip error. Could not create state file: %s", filepath);
2055 goto clean_and_exit;
2056 }
2057
2058 if (!savestates_save_pj64(dev, filepath, zipfile, write_data_to_zip))
2059 goto clean_and_exit;
2060
2061 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Saved state to: %s", namefrompath(filepath));
2062
2063 clean_and_exit:
2064 if (zipfile != NULL)
2065 {
2066 zipCloseFileInZip(zipfile); // This may fail, but we don't care
2067 zipClose(zipfile, "");
2068 }
2069 return 1;
2070}
2071
2072static int write_data_to_file(void *file, const void *buffer, size_t length)
2073{
2074 return fwrite(buffer, 1, length, (FILE *)file) == length;
2075}
2076
2077static int savestates_save_pj64_unc(const struct device* dev, char *filepath)
2078{
2079 FILE *f;
2080
2081 f = fopen(filepath, "wb");
2082 if (f == NULL)
2083 {
2084 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Could not create PJ64 state file: %s", filepath);
2085 return 0;
2086 }
2087
2088 if (!savestates_save_pj64(dev, filepath, f, write_data_to_file))
2089 {
2090 fclose(f);
2091 return 0;
2092 }
2093
2094 main_message(M64MSG_STATUS, OSD_BOTTOM_LEFT, "Saved state to: %s", namefrompath(filepath));
2095 fclose(f);
2096 return 1;
2097}
2098
2099int savestates_save(void)
2100{
2101 char *filepath;
2102 int ret = 0;
2103 const struct device* dev = &g_dev;
2104
2105 /* Can only save PJ64 savestates on VI / COMPARE interrupt.
2106 Otherwise try again in a little while. */
2107 if ((type == savestates_type_pj64_zip ||
2108 type == savestates_type_pj64_unc) &&
2109 get_next_event_type(&dev->r4300.cp0.q) > COMPARE_INT)
2110 return 0;
2111
2112 if (fname != NULL && type == savestates_type_unknown)
2113 type = savestates_type_m64p;
2114 else if (fname == NULL) // Always save slots in M64P format
2115 type = savestates_type_m64p;
2116
2117 filepath = savestates_generate_path(type);
2118 if (filepath != NULL)
2119 {
2120 switch (type)
2121 {
2122 case savestates_type_m64p: ret = savestates_save_m64p(dev, filepath); break;
2123 case savestates_type_pj64_zip: ret = savestates_save_pj64_zip(dev, filepath); break;
2124 case savestates_type_pj64_unc: ret = savestates_save_pj64_unc(dev, filepath); break;
2125 default: ret = 0; break;
2126 }
2127 free(filepath);
2128 }
2129
2130 // deliver callback to indicate completion of state saving operation
2131 StateChanged(M64CORE_STATE_SAVECOMPLETE, ret);
2132
2133 savestates_clear_job();
2134 return ret;
2135}
2136
2137void savestates_init(void)
2138{
2139 savestates_lock = SDL_CreateMutex();
2140 if (!savestates_lock) {
2141 DebugMessage(M64MSG_ERROR, "Could not create savestates list lock");
2142 return;
2143 }
2144}
2145
2146void savestates_deinit(void)
2147{
2148 SDL_DestroyMutex(savestates_lock);
2149 savestates_clear_job();
2150}
2151