1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom E SDK |
3 | * |
4 | * Copyright (c) 2017 SiFive, Inc. |
5 | * |
6 | * Provides a board compatible with the SiFive Freedom E SDK: |
7 | * |
8 | * 0) UART |
9 | * 1) CLINT (Core Level Interruptor) |
10 | * 2) PLIC (Platform Level Interrupt Controller) |
11 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
12 | * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM |
13 | * 5) Flash memory emulated as RAM |
14 | * |
15 | * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. |
16 | * The OTP ROM and Flash boot code will be emulated in a future version. |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify it |
19 | * under the terms and conditions of the GNU General Public License, |
20 | * version 2 or later, as published by the Free Software Foundation. |
21 | * |
22 | * This program is distributed in the hope it will be useful, but WITHOUT |
23 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
24 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
25 | * more details. |
26 | * |
27 | * You should have received a copy of the GNU General Public License along with |
28 | * this program. If not, see <http://www.gnu.org/licenses/>. |
29 | */ |
30 | |
31 | #include "qemu/osdep.h" |
32 | #include "qemu/log.h" |
33 | #include "qemu/error-report.h" |
34 | #include "qapi/error.h" |
35 | #include "hw/boards.h" |
36 | #include "hw/loader.h" |
37 | #include "hw/sysbus.h" |
38 | #include "hw/char/serial.h" |
39 | #include "target/riscv/cpu.h" |
40 | #include "hw/riscv/riscv_hart.h" |
41 | #include "hw/riscv/sifive_plic.h" |
42 | #include "hw/riscv/sifive_clint.h" |
43 | #include "hw/riscv/sifive_prci.h" |
44 | #include "hw/riscv/sifive_uart.h" |
45 | #include "hw/riscv/sifive_e.h" |
46 | #include "hw/riscv/boot.h" |
47 | #include "chardev/char.h" |
48 | #include "sysemu/arch_init.h" |
49 | #include "sysemu/sysemu.h" |
50 | #include "exec/address-spaces.h" |
51 | |
52 | static const struct MemmapEntry { |
53 | hwaddr base; |
54 | hwaddr size; |
55 | } sifive_e_memmap[] = { |
56 | [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, |
57 | [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, |
58 | [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, |
59 | [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, |
60 | [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, |
61 | [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, |
62 | [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, |
63 | [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, |
64 | [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, |
65 | [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, |
66 | [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, |
67 | [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, |
68 | [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, |
69 | [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, |
70 | [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, |
71 | [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, |
72 | [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, |
73 | [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, |
74 | [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } |
75 | }; |
76 | |
77 | static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, |
78 | uintptr_t offset, uintptr_t length) |
79 | { |
80 | MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); |
81 | memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); |
82 | memory_region_add_subregion(parent, offset, mock_mmio); |
83 | } |
84 | |
85 | static void riscv_sifive_e_init(MachineState *machine) |
86 | { |
87 | const struct MemmapEntry *memmap = sifive_e_memmap; |
88 | |
89 | SiFiveEState *s = g_new0(SiFiveEState, 1); |
90 | MemoryRegion *sys_mem = get_system_memory(); |
91 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
92 | int i; |
93 | |
94 | /* Initialize SoC */ |
95 | object_initialize_child(OBJECT(machine), "soc" , &s->soc, |
96 | sizeof(s->soc), TYPE_RISCV_E_SOC, |
97 | &error_abort, NULL); |
98 | object_property_set_bool(OBJECT(&s->soc), true, "realized" , |
99 | &error_abort); |
100 | |
101 | /* Data Tightly Integrated Memory */ |
102 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram" , |
103 | memmap[SIFIVE_E_DTIM].size, &error_fatal); |
104 | memory_region_add_subregion(sys_mem, |
105 | memmap[SIFIVE_E_DTIM].base, main_mem); |
106 | |
107 | /* Mask ROM reset vector */ |
108 | uint32_t reset_vec[2] = { |
109 | 0x204002b7, /* 0x1000: lui t0,0x20400 */ |
110 | 0x00028067, /* 0x1004: jr t0 */ |
111 | }; |
112 | |
113 | /* copy in the reset vector in little_endian byte order */ |
114 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { |
115 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
116 | } |
117 | rom_add_blob_fixed_as("mrom.reset" , reset_vec, sizeof(reset_vec), |
118 | memmap[SIFIVE_E_MROM].base, &address_space_memory); |
119 | |
120 | if (machine->kernel_filename) { |
121 | riscv_load_kernel(machine->kernel_filename); |
122 | } |
123 | } |
124 | |
125 | static void riscv_sifive_e_soc_init(Object *obj) |
126 | { |
127 | MachineState *ms = MACHINE(qdev_get_machine()); |
128 | SiFiveESoCState *s = RISCV_E_SOC(obj); |
129 | |
130 | object_initialize_child(obj, "cpus" , &s->cpus, |
131 | sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, |
132 | &error_abort, NULL); |
133 | object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type" , |
134 | &error_abort); |
135 | object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts" , |
136 | &error_abort); |
137 | sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0" , |
138 | &s->gpio, sizeof(s->gpio), |
139 | TYPE_SIFIVE_GPIO); |
140 | } |
141 | |
142 | static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) |
143 | { |
144 | MachineState *ms = MACHINE(qdev_get_machine()); |
145 | const struct MemmapEntry *memmap = sifive_e_memmap; |
146 | Error *err = NULL; |
147 | |
148 | SiFiveESoCState *s = RISCV_E_SOC(dev); |
149 | MemoryRegion *sys_mem = get_system_memory(); |
150 | |
151 | object_property_set_bool(OBJECT(&s->cpus), true, "realized" , |
152 | &error_abort); |
153 | |
154 | /* Mask ROM */ |
155 | memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom" , |
156 | memmap[SIFIVE_E_MROM].size, &error_fatal); |
157 | memory_region_add_subregion(sys_mem, |
158 | memmap[SIFIVE_E_MROM].base, &s->mask_rom); |
159 | |
160 | /* MMIO */ |
161 | s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, |
162 | (char *)SIFIVE_E_PLIC_HART_CONFIG, |
163 | SIFIVE_E_PLIC_NUM_SOURCES, |
164 | SIFIVE_E_PLIC_NUM_PRIORITIES, |
165 | SIFIVE_E_PLIC_PRIORITY_BASE, |
166 | SIFIVE_E_PLIC_PENDING_BASE, |
167 | SIFIVE_E_PLIC_ENABLE_BASE, |
168 | SIFIVE_E_PLIC_ENABLE_STRIDE, |
169 | SIFIVE_E_PLIC_CONTEXT_BASE, |
170 | SIFIVE_E_PLIC_CONTEXT_STRIDE, |
171 | memmap[SIFIVE_E_PLIC].size); |
172 | sifive_clint_create(memmap[SIFIVE_E_CLINT].base, |
173 | memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, |
174 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); |
175 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon" , |
176 | memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); |
177 | sifive_prci_create(memmap[SIFIVE_E_PRCI].base); |
178 | |
179 | /* GPIO */ |
180 | |
181 | object_property_set_bool(OBJECT(&s->gpio), true, "realized" , &err); |
182 | if (err) { |
183 | error_propagate(errp, err); |
184 | return; |
185 | } |
186 | |
187 | /* Map GPIO registers */ |
188 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); |
189 | |
190 | /* Pass all GPIOs to the SOC layer so they are available to the board */ |
191 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); |
192 | |
193 | /* Connect GPIO interrupts to the PLIC */ |
194 | for (int i = 0; i < 32; i++) { |
195 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, |
196 | qdev_get_gpio_in(DEVICE(s->plic), |
197 | SIFIVE_E_GPIO0_IRQ0 + i)); |
198 | } |
199 | |
200 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, |
201 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); |
202 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0" , |
203 | memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); |
204 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0" , |
205 | memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); |
206 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, |
207 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); |
208 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1" , |
209 | memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); |
210 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1" , |
211 | memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); |
212 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2" , |
213 | memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); |
214 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2" , |
215 | memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); |
216 | |
217 | /* Flash memory */ |
218 | memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip" , |
219 | memmap[SIFIVE_E_XIP].size, &error_fatal); |
220 | memory_region_set_readonly(&s->xip_mem, true); |
221 | memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, |
222 | &s->xip_mem); |
223 | } |
224 | |
225 | static void riscv_sifive_e_machine_init(MachineClass *mc) |
226 | { |
227 | mc->desc = "RISC-V Board compatible with SiFive E SDK" ; |
228 | mc->init = riscv_sifive_e_init; |
229 | mc->max_cpus = 1; |
230 | } |
231 | |
232 | DEFINE_MACHINE("sifive_e" , riscv_sifive_e_machine_init) |
233 | |
234 | static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) |
235 | { |
236 | DeviceClass *dc = DEVICE_CLASS(oc); |
237 | |
238 | dc->realize = riscv_sifive_e_soc_realize; |
239 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
240 | dc->user_creatable = false; |
241 | } |
242 | |
243 | static const TypeInfo riscv_sifive_e_soc_type_info = { |
244 | .name = TYPE_RISCV_E_SOC, |
245 | .parent = TYPE_DEVICE, |
246 | .instance_size = sizeof(SiFiveESoCState), |
247 | .instance_init = riscv_sifive_e_soc_init, |
248 | .class_init = riscv_sifive_e_soc_class_init, |
249 | }; |
250 | |
251 | static void riscv_sifive_e_soc_register_types(void) |
252 | { |
253 | type_register_static(&riscv_sifive_e_soc_type_info); |
254 | } |
255 | |
256 | type_init(riscv_sifive_e_soc_register_types) |
257 | |