1 | /* |
2 | * SD Association Host Standard Specification v2.0 controller emulation |
3 | * |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
5 | * Mitsyanko Igor <i.mitsyanko@samsung.com> |
6 | * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> |
7 | * |
8 | * Based on MMC controller for Samsung S5PC1xx-based board emulation |
9 | * by Alexey Merkulov and Vladimir Monakhov. |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it |
12 | * under the terms of the GNU General Public License as published by the |
13 | * Free Software Foundation; either version 2 of the License, or (at your |
14 | * option) any later version. |
15 | * |
16 | * This program is distributed in the hope that it will be useful, |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
19 | * See the GNU General Public License for more details. |
20 | * |
21 | * You should have received a copy of the GNU General Public License along |
22 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qemu/units.h" |
27 | #include "qemu/error-report.h" |
28 | #include "qapi/error.h" |
29 | #include "hw/irq.h" |
30 | #include "hw/qdev-properties.h" |
31 | #include "sysemu/dma.h" |
32 | #include "qemu/timer.h" |
33 | #include "qemu/bitops.h" |
34 | #include "hw/sd/sdhci.h" |
35 | #include "migration/vmstate.h" |
36 | #include "sdhci-internal.h" |
37 | #include "qemu/log.h" |
38 | #include "qemu/module.h" |
39 | #include "trace.h" |
40 | |
41 | #define TYPE_SDHCI_BUS "sdhci-bus" |
42 | #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) |
43 | |
44 | #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) |
45 | |
46 | static inline unsigned int sdhci_get_fifolen(SDHCIState *s) |
47 | { |
48 | return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); |
49 | } |
50 | |
51 | /* return true on error */ |
52 | static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, |
53 | uint8_t freq, Error **errp) |
54 | { |
55 | if (s->sd_spec_version >= 3) { |
56 | return false; |
57 | } |
58 | switch (freq) { |
59 | case 0: |
60 | case 10 ... 63: |
61 | break; |
62 | default: |
63 | error_setg(errp, "SD %s clock frequency can have value" |
64 | "in range 0-63 only" , desc); |
65 | return true; |
66 | } |
67 | return false; |
68 | } |
69 | |
70 | static void sdhci_check_capareg(SDHCIState *s, Error **errp) |
71 | { |
72 | uint64_t msk = s->capareg; |
73 | uint32_t val; |
74 | bool y; |
75 | |
76 | switch (s->sd_spec_version) { |
77 | case 4: |
78 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); |
79 | trace_sdhci_capareg("64-bit system bus (v4)" , val); |
80 | msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); |
81 | |
82 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); |
83 | trace_sdhci_capareg("UHS-II" , val); |
84 | msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); |
85 | |
86 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); |
87 | trace_sdhci_capareg("ADMA3" , val); |
88 | msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); |
89 | |
90 | /* fallthrough */ |
91 | case 3: |
92 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); |
93 | trace_sdhci_capareg("async interrupt" , val); |
94 | msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); |
95 | |
96 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); |
97 | if (val) { |
98 | error_setg(errp, "slot-type not supported" ); |
99 | return; |
100 | } |
101 | trace_sdhci_capareg("slot type" , val); |
102 | msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); |
103 | |
104 | if (val != 2) { |
105 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); |
106 | trace_sdhci_capareg("8-bit bus" , val); |
107 | } |
108 | msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); |
109 | |
110 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); |
111 | trace_sdhci_capareg("bus speed mask" , val); |
112 | msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); |
113 | |
114 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); |
115 | trace_sdhci_capareg("driver strength mask" , val); |
116 | msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); |
117 | |
118 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); |
119 | trace_sdhci_capareg("timer re-tuning" , val); |
120 | msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); |
121 | |
122 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); |
123 | trace_sdhci_capareg("use SDR50 tuning" , val); |
124 | msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); |
125 | |
126 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); |
127 | trace_sdhci_capareg("re-tuning mode" , val); |
128 | msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); |
129 | |
130 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); |
131 | trace_sdhci_capareg("clock multiplier" , val); |
132 | msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); |
133 | |
134 | /* fallthrough */ |
135 | case 2: /* default version */ |
136 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); |
137 | trace_sdhci_capareg("ADMA2" , val); |
138 | msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); |
139 | |
140 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); |
141 | trace_sdhci_capareg("ADMA1" , val); |
142 | msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); |
143 | |
144 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); |
145 | trace_sdhci_capareg("64-bit system bus (v3)" , val); |
146 | msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); |
147 | |
148 | /* fallthrough */ |
149 | case 1: |
150 | y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); |
151 | msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); |
152 | |
153 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); |
154 | trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)" , val); |
155 | if (sdhci_check_capab_freq_range(s, "timeout" , val, errp)) { |
156 | return; |
157 | } |
158 | msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); |
159 | |
160 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); |
161 | trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)" , val); |
162 | if (sdhci_check_capab_freq_range(s, "base" , val, errp)) { |
163 | return; |
164 | } |
165 | msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); |
166 | |
167 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); |
168 | if (val >= 3) { |
169 | error_setg(errp, "block size can be 512, 1024 or 2048 only" ); |
170 | return; |
171 | } |
172 | trace_sdhci_capareg("max block length" , sdhci_get_fifolen(s)); |
173 | msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); |
174 | |
175 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); |
176 | trace_sdhci_capareg("high speed" , val); |
177 | msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); |
178 | |
179 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); |
180 | trace_sdhci_capareg("SDMA" , val); |
181 | msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); |
182 | |
183 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); |
184 | trace_sdhci_capareg("suspend/resume" , val); |
185 | msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); |
186 | |
187 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); |
188 | trace_sdhci_capareg("3.3v" , val); |
189 | msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); |
190 | |
191 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); |
192 | trace_sdhci_capareg("3.0v" , val); |
193 | msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); |
194 | |
195 | val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); |
196 | trace_sdhci_capareg("1.8v" , val); |
197 | msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); |
198 | break; |
199 | |
200 | default: |
201 | error_setg(errp, "Unsupported spec version: %u" , s->sd_spec_version); |
202 | } |
203 | if (msk) { |
204 | qemu_log_mask(LOG_UNIMP, |
205 | "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n" , msk); |
206 | } |
207 | } |
208 | |
209 | static uint8_t sdhci_slotint(SDHCIState *s) |
210 | { |
211 | return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || |
212 | ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || |
213 | ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); |
214 | } |
215 | |
216 | static inline void sdhci_update_irq(SDHCIState *s) |
217 | { |
218 | qemu_set_irq(s->irq, sdhci_slotint(s)); |
219 | } |
220 | |
221 | static void sdhci_raise_insertion_irq(void *opaque) |
222 | { |
223 | SDHCIState *s = (SDHCIState *)opaque; |
224 | |
225 | if (s->norintsts & SDHC_NIS_REMOVE) { |
226 | timer_mod(s->insert_timer, |
227 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); |
228 | } else { |
229 | s->prnsts = 0x1ff0000; |
230 | if (s->norintstsen & SDHC_NISEN_INSERT) { |
231 | s->norintsts |= SDHC_NIS_INSERT; |
232 | } |
233 | sdhci_update_irq(s); |
234 | } |
235 | } |
236 | |
237 | static void sdhci_set_inserted(DeviceState *dev, bool level) |
238 | { |
239 | SDHCIState *s = (SDHCIState *)dev; |
240 | |
241 | trace_sdhci_set_inserted(level ? "insert" : "eject" ); |
242 | if ((s->norintsts & SDHC_NIS_REMOVE) && level) { |
243 | /* Give target some time to notice card ejection */ |
244 | timer_mod(s->insert_timer, |
245 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); |
246 | } else { |
247 | if (level) { |
248 | s->prnsts = 0x1ff0000; |
249 | if (s->norintstsen & SDHC_NISEN_INSERT) { |
250 | s->norintsts |= SDHC_NIS_INSERT; |
251 | } |
252 | } else { |
253 | s->prnsts = 0x1fa0000; |
254 | s->pwrcon &= ~SDHC_POWER_ON; |
255 | s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; |
256 | if (s->norintstsen & SDHC_NISEN_REMOVE) { |
257 | s->norintsts |= SDHC_NIS_REMOVE; |
258 | } |
259 | } |
260 | sdhci_update_irq(s); |
261 | } |
262 | } |
263 | |
264 | static void sdhci_set_readonly(DeviceState *dev, bool level) |
265 | { |
266 | SDHCIState *s = (SDHCIState *)dev; |
267 | |
268 | if (level) { |
269 | s->prnsts &= ~SDHC_WRITE_PROTECT; |
270 | } else { |
271 | /* Write enabled */ |
272 | s->prnsts |= SDHC_WRITE_PROTECT; |
273 | } |
274 | } |
275 | |
276 | static void sdhci_reset(SDHCIState *s) |
277 | { |
278 | DeviceState *dev = DEVICE(s); |
279 | |
280 | timer_del(s->insert_timer); |
281 | timer_del(s->transfer_timer); |
282 | |
283 | /* Set all registers to 0. Capabilities/Version registers are not cleared |
284 | * and assumed to always preserve their value, given to them during |
285 | * initialization */ |
286 | memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); |
287 | |
288 | /* Reset other state based on current card insertion/readonly status */ |
289 | sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); |
290 | sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); |
291 | |
292 | s->data_count = 0; |
293 | s->stopped_state = sdhc_not_stopped; |
294 | s->pending_insert_state = false; |
295 | } |
296 | |
297 | static void sdhci_poweron_reset(DeviceState *dev) |
298 | { |
299 | /* QOM (ie power-on) reset. This is identical to reset |
300 | * commanded via device register apart from handling of the |
301 | * 'pending insert on powerup' quirk. |
302 | */ |
303 | SDHCIState *s = (SDHCIState *)dev; |
304 | |
305 | sdhci_reset(s); |
306 | |
307 | if (s->pending_insert_quirk) { |
308 | s->pending_insert_state = true; |
309 | } |
310 | } |
311 | |
312 | static void sdhci_data_transfer(void *opaque); |
313 | |
314 | static void sdhci_send_command(SDHCIState *s) |
315 | { |
316 | SDRequest request; |
317 | uint8_t response[16]; |
318 | int rlen; |
319 | |
320 | s->errintsts = 0; |
321 | s->acmd12errsts = 0; |
322 | request.cmd = s->cmdreg >> 8; |
323 | request.arg = s->argument; |
324 | |
325 | trace_sdhci_send_command(request.cmd, request.arg); |
326 | rlen = sdbus_do_command(&s->sdbus, &request, response); |
327 | |
328 | if (s->cmdreg & SDHC_CMD_RESPONSE) { |
329 | if (rlen == 4) { |
330 | s->rspreg[0] = ldl_be_p(response); |
331 | s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; |
332 | trace_sdhci_response4(s->rspreg[0]); |
333 | } else if (rlen == 16) { |
334 | s->rspreg[0] = ldl_be_p(&response[11]); |
335 | s->rspreg[1] = ldl_be_p(&response[7]); |
336 | s->rspreg[2] = ldl_be_p(&response[3]); |
337 | s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | |
338 | response[2]; |
339 | trace_sdhci_response16(s->rspreg[3], s->rspreg[2], |
340 | s->rspreg[1], s->rspreg[0]); |
341 | } else { |
342 | trace_sdhci_error("timeout waiting for command response" ); |
343 | if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { |
344 | s->errintsts |= SDHC_EIS_CMDTIMEOUT; |
345 | s->norintsts |= SDHC_NIS_ERR; |
346 | } |
347 | } |
348 | |
349 | if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && |
350 | (s->norintstsen & SDHC_NISEN_TRSCMP) && |
351 | (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { |
352 | s->norintsts |= SDHC_NIS_TRSCMP; |
353 | } |
354 | } |
355 | |
356 | if (s->norintstsen & SDHC_NISEN_CMDCMP) { |
357 | s->norintsts |= SDHC_NIS_CMDCMP; |
358 | } |
359 | |
360 | sdhci_update_irq(s); |
361 | |
362 | if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { |
363 | s->data_count = 0; |
364 | sdhci_data_transfer(s); |
365 | } |
366 | } |
367 | |
368 | static void sdhci_end_transfer(SDHCIState *s) |
369 | { |
370 | /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ |
371 | if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { |
372 | SDRequest request; |
373 | uint8_t response[16]; |
374 | |
375 | request.cmd = 0x0C; |
376 | request.arg = 0; |
377 | trace_sdhci_end_transfer(request.cmd, request.arg); |
378 | sdbus_do_command(&s->sdbus, &request, response); |
379 | /* Auto CMD12 response goes to the upper Response register */ |
380 | s->rspreg[3] = ldl_be_p(response); |
381 | } |
382 | |
383 | s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | |
384 | SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | |
385 | SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); |
386 | |
387 | if (s->norintstsen & SDHC_NISEN_TRSCMP) { |
388 | s->norintsts |= SDHC_NIS_TRSCMP; |
389 | } |
390 | |
391 | sdhci_update_irq(s); |
392 | } |
393 | |
394 | /* |
395 | * Programmed i/o data transfer |
396 | */ |
397 | #define BLOCK_SIZE_MASK (4 * KiB - 1) |
398 | |
399 | /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ |
400 | static void sdhci_read_block_from_card(SDHCIState *s) |
401 | { |
402 | int index = 0; |
403 | uint8_t data; |
404 | const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; |
405 | |
406 | if ((s->trnmod & SDHC_TRNS_MULTI) && |
407 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { |
408 | return; |
409 | } |
410 | |
411 | for (index = 0; index < blk_size; index++) { |
412 | data = sdbus_read_data(&s->sdbus); |
413 | if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { |
414 | /* Device is not in tuning */ |
415 | s->fifo_buffer[index] = data; |
416 | } |
417 | } |
418 | |
419 | if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { |
420 | /* Device is in tuning */ |
421 | s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; |
422 | s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; |
423 | s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | |
424 | SDHC_DATA_INHIBIT); |
425 | goto read_done; |
426 | } |
427 | |
428 | /* New data now available for READ through Buffer Port Register */ |
429 | s->prnsts |= SDHC_DATA_AVAILABLE; |
430 | if (s->norintstsen & SDHC_NISEN_RBUFRDY) { |
431 | s->norintsts |= SDHC_NIS_RBUFRDY; |
432 | } |
433 | |
434 | /* Clear DAT line active status if that was the last block */ |
435 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
436 | ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { |
437 | s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; |
438 | } |
439 | |
440 | /* If stop at block gap request was set and it's not the last block of |
441 | * data - generate Block Event interrupt */ |
442 | if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && |
443 | s->blkcnt != 1) { |
444 | s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; |
445 | if (s->norintstsen & SDHC_EISEN_BLKGAP) { |
446 | s->norintsts |= SDHC_EIS_BLKGAP; |
447 | } |
448 | } |
449 | |
450 | read_done: |
451 | sdhci_update_irq(s); |
452 | } |
453 | |
454 | /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ |
455 | static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) |
456 | { |
457 | uint32_t value = 0; |
458 | int i; |
459 | |
460 | /* first check that a valid data exists in host controller input buffer */ |
461 | if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { |
462 | trace_sdhci_error("read from empty buffer" ); |
463 | return 0; |
464 | } |
465 | |
466 | for (i = 0; i < size; i++) { |
467 | value |= s->fifo_buffer[s->data_count] << i * 8; |
468 | s->data_count++; |
469 | /* check if we've read all valid data (blksize bytes) from buffer */ |
470 | if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { |
471 | trace_sdhci_read_dataport(s->data_count); |
472 | s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ |
473 | s->data_count = 0; /* next buff read must start at position [0] */ |
474 | |
475 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
476 | s->blkcnt--; |
477 | } |
478 | |
479 | /* if that was the last block of data */ |
480 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
481 | ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || |
482 | /* stop at gap request */ |
483 | (s->stopped_state == sdhc_gap_read && |
484 | !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { |
485 | sdhci_end_transfer(s); |
486 | } else { /* if there are more data, read next block from card */ |
487 | sdhci_read_block_from_card(s); |
488 | } |
489 | break; |
490 | } |
491 | } |
492 | |
493 | return value; |
494 | } |
495 | |
496 | /* Write data from host controller FIFO to card */ |
497 | static void sdhci_write_block_to_card(SDHCIState *s) |
498 | { |
499 | int index = 0; |
500 | |
501 | if (s->prnsts & SDHC_SPACE_AVAILABLE) { |
502 | if (s->norintstsen & SDHC_NISEN_WBUFRDY) { |
503 | s->norintsts |= SDHC_NIS_WBUFRDY; |
504 | } |
505 | sdhci_update_irq(s); |
506 | return; |
507 | } |
508 | |
509 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
510 | if (s->blkcnt == 0) { |
511 | return; |
512 | } else { |
513 | s->blkcnt--; |
514 | } |
515 | } |
516 | |
517 | for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { |
518 | sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); |
519 | } |
520 | |
521 | /* Next data can be written through BUFFER DATORT register */ |
522 | s->prnsts |= SDHC_SPACE_AVAILABLE; |
523 | |
524 | /* Finish transfer if that was the last block of data */ |
525 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || |
526 | ((s->trnmod & SDHC_TRNS_MULTI) && |
527 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { |
528 | sdhci_end_transfer(s); |
529 | } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { |
530 | s->norintsts |= SDHC_NIS_WBUFRDY; |
531 | } |
532 | |
533 | /* Generate Block Gap Event if requested and if not the last block */ |
534 | if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && |
535 | s->blkcnt > 0) { |
536 | s->prnsts &= ~SDHC_DOING_WRITE; |
537 | if (s->norintstsen & SDHC_EISEN_BLKGAP) { |
538 | s->norintsts |= SDHC_EIS_BLKGAP; |
539 | } |
540 | sdhci_end_transfer(s); |
541 | } |
542 | |
543 | sdhci_update_irq(s); |
544 | } |
545 | |
546 | /* Write @size bytes of @value data to host controller @s Buffer Data Port |
547 | * register */ |
548 | static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) |
549 | { |
550 | unsigned i; |
551 | |
552 | /* Check that there is free space left in a buffer */ |
553 | if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { |
554 | trace_sdhci_error("Can't write to data buffer: buffer full" ); |
555 | return; |
556 | } |
557 | |
558 | for (i = 0; i < size; i++) { |
559 | s->fifo_buffer[s->data_count] = value & 0xFF; |
560 | s->data_count++; |
561 | value >>= 8; |
562 | if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { |
563 | trace_sdhci_write_dataport(s->data_count); |
564 | s->data_count = 0; |
565 | s->prnsts &= ~SDHC_SPACE_AVAILABLE; |
566 | if (s->prnsts & SDHC_DOING_WRITE) { |
567 | sdhci_write_block_to_card(s); |
568 | } |
569 | } |
570 | } |
571 | } |
572 | |
573 | /* |
574 | * Single DMA data transfer |
575 | */ |
576 | |
577 | /* Multi block SDMA transfer */ |
578 | static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) |
579 | { |
580 | bool page_aligned = false; |
581 | unsigned int n, begin; |
582 | const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; |
583 | uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); |
584 | uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); |
585 | |
586 | if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { |
587 | qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n" ); |
588 | return; |
589 | } |
590 | |
591 | /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for |
592 | * possible stop at page boundary if initial address is not page aligned, |
593 | * allow them to work properly */ |
594 | if ((s->sdmasysad % boundary_chk) == 0) { |
595 | page_aligned = true; |
596 | } |
597 | |
598 | if (s->trnmod & SDHC_TRNS_READ) { |
599 | s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | |
600 | SDHC_DAT_LINE_ACTIVE; |
601 | while (s->blkcnt) { |
602 | if (s->data_count == 0) { |
603 | for (n = 0; n < block_size; n++) { |
604 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
605 | } |
606 | } |
607 | begin = s->data_count; |
608 | if (((boundary_count + begin) < block_size) && page_aligned) { |
609 | s->data_count = boundary_count + begin; |
610 | boundary_count = 0; |
611 | } else { |
612 | s->data_count = block_size; |
613 | boundary_count -= block_size - begin; |
614 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
615 | s->blkcnt--; |
616 | } |
617 | } |
618 | dma_memory_write(s->dma_as, s->sdmasysad, |
619 | &s->fifo_buffer[begin], s->data_count - begin); |
620 | s->sdmasysad += s->data_count - begin; |
621 | if (s->data_count == block_size) { |
622 | s->data_count = 0; |
623 | } |
624 | if (page_aligned && boundary_count == 0) { |
625 | break; |
626 | } |
627 | } |
628 | } else { |
629 | s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | |
630 | SDHC_DAT_LINE_ACTIVE; |
631 | while (s->blkcnt) { |
632 | begin = s->data_count; |
633 | if (((boundary_count + begin) < block_size) && page_aligned) { |
634 | s->data_count = boundary_count + begin; |
635 | boundary_count = 0; |
636 | } else { |
637 | s->data_count = block_size; |
638 | boundary_count -= block_size - begin; |
639 | } |
640 | dma_memory_read(s->dma_as, s->sdmasysad, |
641 | &s->fifo_buffer[begin], s->data_count - begin); |
642 | s->sdmasysad += s->data_count - begin; |
643 | if (s->data_count == block_size) { |
644 | for (n = 0; n < block_size; n++) { |
645 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
646 | } |
647 | s->data_count = 0; |
648 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
649 | s->blkcnt--; |
650 | } |
651 | } |
652 | if (page_aligned && boundary_count == 0) { |
653 | break; |
654 | } |
655 | } |
656 | } |
657 | |
658 | if (s->blkcnt == 0) { |
659 | sdhci_end_transfer(s); |
660 | } else { |
661 | if (s->norintstsen & SDHC_NISEN_DMA) { |
662 | s->norintsts |= SDHC_NIS_DMA; |
663 | } |
664 | sdhci_update_irq(s); |
665 | } |
666 | } |
667 | |
668 | /* single block SDMA transfer */ |
669 | static void sdhci_sdma_transfer_single_block(SDHCIState *s) |
670 | { |
671 | int n; |
672 | uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; |
673 | |
674 | if (s->trnmod & SDHC_TRNS_READ) { |
675 | for (n = 0; n < datacnt; n++) { |
676 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
677 | } |
678 | dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); |
679 | } else { |
680 | dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); |
681 | for (n = 0; n < datacnt; n++) { |
682 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
683 | } |
684 | } |
685 | s->blkcnt--; |
686 | |
687 | sdhci_end_transfer(s); |
688 | } |
689 | |
690 | typedef struct ADMADescr { |
691 | hwaddr addr; |
692 | uint16_t length; |
693 | uint8_t attr; |
694 | uint8_t incr; |
695 | } ADMADescr; |
696 | |
697 | static void get_adma_description(SDHCIState *s, ADMADescr *dscr) |
698 | { |
699 | uint32_t adma1 = 0; |
700 | uint64_t adma2 = 0; |
701 | hwaddr entry_addr = (hwaddr)s->admasysaddr; |
702 | switch (SDHC_DMA_TYPE(s->hostctl1)) { |
703 | case SDHC_CTRL_ADMA2_32: |
704 | dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, |
705 | sizeof(adma2)); |
706 | adma2 = le64_to_cpu(adma2); |
707 | /* The spec does not specify endianness of descriptor table. |
708 | * We currently assume that it is LE. |
709 | */ |
710 | dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; |
711 | dscr->length = (uint16_t)extract64(adma2, 16, 16); |
712 | dscr->attr = (uint8_t)extract64(adma2, 0, 7); |
713 | dscr->incr = 8; |
714 | break; |
715 | case SDHC_CTRL_ADMA1_32: |
716 | dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, |
717 | sizeof(adma1)); |
718 | adma1 = le32_to_cpu(adma1); |
719 | dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); |
720 | dscr->attr = (uint8_t)extract32(adma1, 0, 7); |
721 | dscr->incr = 4; |
722 | if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { |
723 | dscr->length = (uint16_t)extract32(adma1, 12, 16); |
724 | } else { |
725 | dscr->length = 4 * KiB; |
726 | } |
727 | break; |
728 | case SDHC_CTRL_ADMA2_64: |
729 | dma_memory_read(s->dma_as, entry_addr, |
730 | (uint8_t *)(&dscr->attr), 1); |
731 | dma_memory_read(s->dma_as, entry_addr + 2, |
732 | (uint8_t *)(&dscr->length), 2); |
733 | dscr->length = le16_to_cpu(dscr->length); |
734 | dma_memory_read(s->dma_as, entry_addr + 4, |
735 | (uint8_t *)(&dscr->addr), 8); |
736 | dscr->addr = le64_to_cpu(dscr->addr); |
737 | dscr->attr &= (uint8_t) ~0xC0; |
738 | dscr->incr = 12; |
739 | break; |
740 | } |
741 | } |
742 | |
743 | /* Advanced DMA data transfer */ |
744 | |
745 | static void sdhci_do_adma(SDHCIState *s) |
746 | { |
747 | unsigned int n, begin, length; |
748 | const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; |
749 | ADMADescr dscr = {}; |
750 | int i; |
751 | |
752 | for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { |
753 | s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; |
754 | |
755 | get_adma_description(s, &dscr); |
756 | trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); |
757 | |
758 | if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { |
759 | /* Indicate that error occurred in ST_FDS state */ |
760 | s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; |
761 | s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; |
762 | |
763 | /* Generate ADMA error interrupt */ |
764 | if (s->errintstsen & SDHC_EISEN_ADMAERR) { |
765 | s->errintsts |= SDHC_EIS_ADMAERR; |
766 | s->norintsts |= SDHC_NIS_ERR; |
767 | } |
768 | |
769 | sdhci_update_irq(s); |
770 | return; |
771 | } |
772 | |
773 | length = dscr.length ? dscr.length : 64 * KiB; |
774 | |
775 | switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { |
776 | case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ |
777 | |
778 | if (s->trnmod & SDHC_TRNS_READ) { |
779 | while (length) { |
780 | if (s->data_count == 0) { |
781 | for (n = 0; n < block_size; n++) { |
782 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
783 | } |
784 | } |
785 | begin = s->data_count; |
786 | if ((length + begin) < block_size) { |
787 | s->data_count = length + begin; |
788 | length = 0; |
789 | } else { |
790 | s->data_count = block_size; |
791 | length -= block_size - begin; |
792 | } |
793 | dma_memory_write(s->dma_as, dscr.addr, |
794 | &s->fifo_buffer[begin], |
795 | s->data_count - begin); |
796 | dscr.addr += s->data_count - begin; |
797 | if (s->data_count == block_size) { |
798 | s->data_count = 0; |
799 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
800 | s->blkcnt--; |
801 | if (s->blkcnt == 0) { |
802 | break; |
803 | } |
804 | } |
805 | } |
806 | } |
807 | } else { |
808 | while (length) { |
809 | begin = s->data_count; |
810 | if ((length + begin) < block_size) { |
811 | s->data_count = length + begin; |
812 | length = 0; |
813 | } else { |
814 | s->data_count = block_size; |
815 | length -= block_size - begin; |
816 | } |
817 | dma_memory_read(s->dma_as, dscr.addr, |
818 | &s->fifo_buffer[begin], |
819 | s->data_count - begin); |
820 | dscr.addr += s->data_count - begin; |
821 | if (s->data_count == block_size) { |
822 | for (n = 0; n < block_size; n++) { |
823 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
824 | } |
825 | s->data_count = 0; |
826 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { |
827 | s->blkcnt--; |
828 | if (s->blkcnt == 0) { |
829 | break; |
830 | } |
831 | } |
832 | } |
833 | } |
834 | } |
835 | s->admasysaddr += dscr.incr; |
836 | break; |
837 | case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ |
838 | s->admasysaddr = dscr.addr; |
839 | trace_sdhci_adma("link" , s->admasysaddr); |
840 | break; |
841 | default: |
842 | s->admasysaddr += dscr.incr; |
843 | break; |
844 | } |
845 | |
846 | if (dscr.attr & SDHC_ADMA_ATTR_INT) { |
847 | trace_sdhci_adma("interrupt" , s->admasysaddr); |
848 | if (s->norintstsen & SDHC_NISEN_DMA) { |
849 | s->norintsts |= SDHC_NIS_DMA; |
850 | } |
851 | |
852 | sdhci_update_irq(s); |
853 | } |
854 | |
855 | /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ |
856 | if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && |
857 | (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { |
858 | trace_sdhci_adma_transfer_completed(); |
859 | if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && |
860 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && |
861 | s->blkcnt != 0)) { |
862 | trace_sdhci_error("SD/MMC host ADMA length mismatch" ); |
863 | s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | |
864 | SDHC_ADMAERR_STATE_ST_TFR; |
865 | if (s->errintstsen & SDHC_EISEN_ADMAERR) { |
866 | trace_sdhci_error("Set ADMA error flag" ); |
867 | s->errintsts |= SDHC_EIS_ADMAERR; |
868 | s->norintsts |= SDHC_NIS_ERR; |
869 | } |
870 | |
871 | sdhci_update_irq(s); |
872 | } |
873 | sdhci_end_transfer(s); |
874 | return; |
875 | } |
876 | |
877 | } |
878 | |
879 | /* we have unfinished business - reschedule to continue ADMA */ |
880 | timer_mod(s->transfer_timer, |
881 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); |
882 | } |
883 | |
884 | /* Perform data transfer according to controller configuration */ |
885 | |
886 | static void sdhci_data_transfer(void *opaque) |
887 | { |
888 | SDHCIState *s = (SDHCIState *)opaque; |
889 | |
890 | if (s->trnmod & SDHC_TRNS_DMA) { |
891 | switch (SDHC_DMA_TYPE(s->hostctl1)) { |
892 | case SDHC_CTRL_SDMA: |
893 | if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { |
894 | sdhci_sdma_transfer_single_block(s); |
895 | } else { |
896 | sdhci_sdma_transfer_multi_blocks(s); |
897 | } |
898 | |
899 | break; |
900 | case SDHC_CTRL_ADMA1_32: |
901 | if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { |
902 | trace_sdhci_error("ADMA1 not supported" ); |
903 | break; |
904 | } |
905 | |
906 | sdhci_do_adma(s); |
907 | break; |
908 | case SDHC_CTRL_ADMA2_32: |
909 | if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { |
910 | trace_sdhci_error("ADMA2 not supported" ); |
911 | break; |
912 | } |
913 | |
914 | sdhci_do_adma(s); |
915 | break; |
916 | case SDHC_CTRL_ADMA2_64: |
917 | if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || |
918 | !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { |
919 | trace_sdhci_error("64 bit ADMA not supported" ); |
920 | break; |
921 | } |
922 | |
923 | sdhci_do_adma(s); |
924 | break; |
925 | default: |
926 | trace_sdhci_error("Unsupported DMA type" ); |
927 | break; |
928 | } |
929 | } else { |
930 | if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { |
931 | s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | |
932 | SDHC_DAT_LINE_ACTIVE; |
933 | sdhci_read_block_from_card(s); |
934 | } else { |
935 | s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | |
936 | SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; |
937 | sdhci_write_block_to_card(s); |
938 | } |
939 | } |
940 | } |
941 | |
942 | static bool sdhci_can_issue_command(SDHCIState *s) |
943 | { |
944 | if (!SDHC_CLOCK_IS_ON(s->clkcon) || |
945 | (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && |
946 | ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || |
947 | ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && |
948 | !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { |
949 | return false; |
950 | } |
951 | |
952 | return true; |
953 | } |
954 | |
955 | /* The Buffer Data Port register must be accessed in sequential and |
956 | * continuous manner */ |
957 | static inline bool |
958 | sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) |
959 | { |
960 | if ((s->data_count & 0x3) != byte_num) { |
961 | trace_sdhci_error("Non-sequential access to Buffer Data Port register" |
962 | "is prohibited\n" ); |
963 | return false; |
964 | } |
965 | return true; |
966 | } |
967 | |
968 | static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) |
969 | { |
970 | SDHCIState *s = (SDHCIState *)opaque; |
971 | uint32_t ret = 0; |
972 | |
973 | switch (offset & ~0x3) { |
974 | case SDHC_SYSAD: |
975 | ret = s->sdmasysad; |
976 | break; |
977 | case SDHC_BLKSIZE: |
978 | ret = s->blksize | (s->blkcnt << 16); |
979 | break; |
980 | case SDHC_ARGUMENT: |
981 | ret = s->argument; |
982 | break; |
983 | case SDHC_TRNMOD: |
984 | ret = s->trnmod | (s->cmdreg << 16); |
985 | break; |
986 | case SDHC_RSPREG0 ... SDHC_RSPREG3: |
987 | ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; |
988 | break; |
989 | case SDHC_BDATA: |
990 | if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { |
991 | ret = sdhci_read_dataport(s, size); |
992 | trace_sdhci_access("rd" , size << 3, offset, "->" , ret, ret); |
993 | return ret; |
994 | } |
995 | break; |
996 | case SDHC_PRNSTS: |
997 | ret = s->prnsts; |
998 | ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, |
999 | sdbus_get_dat_lines(&s->sdbus)); |
1000 | ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, |
1001 | sdbus_get_cmd_line(&s->sdbus)); |
1002 | break; |
1003 | case SDHC_HOSTCTL: |
1004 | ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | |
1005 | (s->wakcon << 24); |
1006 | break; |
1007 | case SDHC_CLKCON: |
1008 | ret = s->clkcon | (s->timeoutcon << 16); |
1009 | break; |
1010 | case SDHC_NORINTSTS: |
1011 | ret = s->norintsts | (s->errintsts << 16); |
1012 | break; |
1013 | case SDHC_NORINTSTSEN: |
1014 | ret = s->norintstsen | (s->errintstsen << 16); |
1015 | break; |
1016 | case SDHC_NORINTSIGEN: |
1017 | ret = s->norintsigen | (s->errintsigen << 16); |
1018 | break; |
1019 | case SDHC_ACMD12ERRSTS: |
1020 | ret = s->acmd12errsts | (s->hostctl2 << 16); |
1021 | break; |
1022 | case SDHC_CAPAB: |
1023 | ret = (uint32_t)s->capareg; |
1024 | break; |
1025 | case SDHC_CAPAB + 4: |
1026 | ret = (uint32_t)(s->capareg >> 32); |
1027 | break; |
1028 | case SDHC_MAXCURR: |
1029 | ret = (uint32_t)s->maxcurr; |
1030 | break; |
1031 | case SDHC_MAXCURR + 4: |
1032 | ret = (uint32_t)(s->maxcurr >> 32); |
1033 | break; |
1034 | case SDHC_ADMAERR: |
1035 | ret = s->admaerr; |
1036 | break; |
1037 | case SDHC_ADMASYSADDR: |
1038 | ret = (uint32_t)s->admasysaddr; |
1039 | break; |
1040 | case SDHC_ADMASYSADDR + 4: |
1041 | ret = (uint32_t)(s->admasysaddr >> 32); |
1042 | break; |
1043 | case SDHC_SLOT_INT_STATUS: |
1044 | ret = (s->version << 16) | sdhci_slotint(s); |
1045 | break; |
1046 | default: |
1047 | qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " |
1048 | "not implemented\n" , size, offset); |
1049 | break; |
1050 | } |
1051 | |
1052 | ret >>= (offset & 0x3) * 8; |
1053 | ret &= (1ULL << (size * 8)) - 1; |
1054 | trace_sdhci_access("rd" , size << 3, offset, "->" , ret, ret); |
1055 | return ret; |
1056 | } |
1057 | |
1058 | static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) |
1059 | { |
1060 | if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { |
1061 | return; |
1062 | } |
1063 | s->blkgap = value & SDHC_STOP_AT_GAP_REQ; |
1064 | |
1065 | if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && |
1066 | (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { |
1067 | if (s->stopped_state == sdhc_gap_read) { |
1068 | s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; |
1069 | sdhci_read_block_from_card(s); |
1070 | } else { |
1071 | s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; |
1072 | sdhci_write_block_to_card(s); |
1073 | } |
1074 | s->stopped_state = sdhc_not_stopped; |
1075 | } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { |
1076 | if (s->prnsts & SDHC_DOING_READ) { |
1077 | s->stopped_state = sdhc_gap_read; |
1078 | } else if (s->prnsts & SDHC_DOING_WRITE) { |
1079 | s->stopped_state = sdhc_gap_write; |
1080 | } |
1081 | } |
1082 | } |
1083 | |
1084 | static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) |
1085 | { |
1086 | switch (value) { |
1087 | case SDHC_RESET_ALL: |
1088 | sdhci_reset(s); |
1089 | break; |
1090 | case SDHC_RESET_CMD: |
1091 | s->prnsts &= ~SDHC_CMD_INHIBIT; |
1092 | s->norintsts &= ~SDHC_NIS_CMDCMP; |
1093 | break; |
1094 | case SDHC_RESET_DATA: |
1095 | s->data_count = 0; |
1096 | s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | |
1097 | SDHC_DOING_READ | SDHC_DOING_WRITE | |
1098 | SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); |
1099 | s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); |
1100 | s->stopped_state = sdhc_not_stopped; |
1101 | s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | |
1102 | SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); |
1103 | break; |
1104 | } |
1105 | } |
1106 | |
1107 | static void |
1108 | sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) |
1109 | { |
1110 | SDHCIState *s = (SDHCIState *)opaque; |
1111 | unsigned shift = 8 * (offset & 0x3); |
1112 | uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); |
1113 | uint32_t value = val; |
1114 | value <<= shift; |
1115 | |
1116 | switch (offset & ~0x3) { |
1117 | case SDHC_SYSAD: |
1118 | s->sdmasysad = (s->sdmasysad & mask) | value; |
1119 | MASKED_WRITE(s->sdmasysad, mask, value); |
1120 | /* Writing to last byte of sdmasysad might trigger transfer */ |
1121 | if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && |
1122 | s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { |
1123 | if (s->trnmod & SDHC_TRNS_MULTI) { |
1124 | sdhci_sdma_transfer_multi_blocks(s); |
1125 | } else { |
1126 | sdhci_sdma_transfer_single_block(s); |
1127 | } |
1128 | } |
1129 | break; |
1130 | case SDHC_BLKSIZE: |
1131 | if (!TRANSFERRING_DATA(s->prnsts)) { |
1132 | MASKED_WRITE(s->blksize, mask, value); |
1133 | MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); |
1134 | } |
1135 | |
1136 | /* Limit block size to the maximum buffer size */ |
1137 | if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { |
1138 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ |
1139 | "the maximum buffer 0x%x" , __func__, s->blksize, |
1140 | s->buf_maxsz); |
1141 | |
1142 | s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); |
1143 | } |
1144 | |
1145 | break; |
1146 | case SDHC_ARGUMENT: |
1147 | MASKED_WRITE(s->argument, mask, value); |
1148 | break; |
1149 | case SDHC_TRNMOD: |
1150 | /* DMA can be enabled only if it is supported as indicated by |
1151 | * capabilities register */ |
1152 | if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { |
1153 | value &= ~SDHC_TRNS_DMA; |
1154 | } |
1155 | MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); |
1156 | MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); |
1157 | |
1158 | /* Writing to the upper byte of CMDREG triggers SD command generation */ |
1159 | if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { |
1160 | break; |
1161 | } |
1162 | |
1163 | sdhci_send_command(s); |
1164 | break; |
1165 | case SDHC_BDATA: |
1166 | if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { |
1167 | sdhci_write_dataport(s, value >> shift, size); |
1168 | } |
1169 | break; |
1170 | case SDHC_HOSTCTL: |
1171 | if (!(mask & 0xFF0000)) { |
1172 | sdhci_blkgap_write(s, value >> 16); |
1173 | } |
1174 | MASKED_WRITE(s->hostctl1, mask, value); |
1175 | MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); |
1176 | MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); |
1177 | if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || |
1178 | !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { |
1179 | s->pwrcon &= ~SDHC_POWER_ON; |
1180 | } |
1181 | break; |
1182 | case SDHC_CLKCON: |
1183 | if (!(mask & 0xFF000000)) { |
1184 | sdhci_reset_write(s, value >> 24); |
1185 | } |
1186 | MASKED_WRITE(s->clkcon, mask, value); |
1187 | MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); |
1188 | if (s->clkcon & SDHC_CLOCK_INT_EN) { |
1189 | s->clkcon |= SDHC_CLOCK_INT_STABLE; |
1190 | } else { |
1191 | s->clkcon &= ~SDHC_CLOCK_INT_STABLE; |
1192 | } |
1193 | break; |
1194 | case SDHC_NORINTSTS: |
1195 | if (s->norintstsen & SDHC_NISEN_CARDINT) { |
1196 | value &= ~SDHC_NIS_CARDINT; |
1197 | } |
1198 | s->norintsts &= mask | ~value; |
1199 | s->errintsts &= (mask >> 16) | ~(value >> 16); |
1200 | if (s->errintsts) { |
1201 | s->norintsts |= SDHC_NIS_ERR; |
1202 | } else { |
1203 | s->norintsts &= ~SDHC_NIS_ERR; |
1204 | } |
1205 | sdhci_update_irq(s); |
1206 | break; |
1207 | case SDHC_NORINTSTSEN: |
1208 | MASKED_WRITE(s->norintstsen, mask, value); |
1209 | MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); |
1210 | s->norintsts &= s->norintstsen; |
1211 | s->errintsts &= s->errintstsen; |
1212 | if (s->errintsts) { |
1213 | s->norintsts |= SDHC_NIS_ERR; |
1214 | } else { |
1215 | s->norintsts &= ~SDHC_NIS_ERR; |
1216 | } |
1217 | /* Quirk for Raspberry Pi: pending card insert interrupt |
1218 | * appears when first enabled after power on */ |
1219 | if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { |
1220 | assert(s->pending_insert_quirk); |
1221 | s->norintsts |= SDHC_NIS_INSERT; |
1222 | s->pending_insert_state = false; |
1223 | } |
1224 | sdhci_update_irq(s); |
1225 | break; |
1226 | case SDHC_NORINTSIGEN: |
1227 | MASKED_WRITE(s->norintsigen, mask, value); |
1228 | MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); |
1229 | sdhci_update_irq(s); |
1230 | break; |
1231 | case SDHC_ADMAERR: |
1232 | MASKED_WRITE(s->admaerr, mask, value); |
1233 | break; |
1234 | case SDHC_ADMASYSADDR: |
1235 | s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | |
1236 | (uint64_t)mask)) | (uint64_t)value; |
1237 | break; |
1238 | case SDHC_ADMASYSADDR + 4: |
1239 | s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | |
1240 | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); |
1241 | break; |
1242 | case SDHC_FEAER: |
1243 | s->acmd12errsts |= value; |
1244 | s->errintsts |= (value >> 16) & s->errintstsen; |
1245 | if (s->acmd12errsts) { |
1246 | s->errintsts |= SDHC_EIS_CMD12ERR; |
1247 | } |
1248 | if (s->errintsts) { |
1249 | s->norintsts |= SDHC_NIS_ERR; |
1250 | } |
1251 | sdhci_update_irq(s); |
1252 | break; |
1253 | case SDHC_ACMD12ERRSTS: |
1254 | MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); |
1255 | if (s->uhs_mode >= UHS_I) { |
1256 | MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); |
1257 | |
1258 | if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { |
1259 | sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); |
1260 | } else { |
1261 | sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); |
1262 | } |
1263 | } |
1264 | break; |
1265 | |
1266 | case SDHC_CAPAB: |
1267 | case SDHC_CAPAB + 4: |
1268 | case SDHC_MAXCURR: |
1269 | case SDHC_MAXCURR + 4: |
1270 | qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx |
1271 | " <- 0x%08x read-only\n" , size, offset, value >> shift); |
1272 | break; |
1273 | |
1274 | default: |
1275 | qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " |
1276 | "not implemented\n" , size, offset, value >> shift); |
1277 | break; |
1278 | } |
1279 | trace_sdhci_access("wr" , size << 3, offset, "<-" , |
1280 | value >> shift, value >> shift); |
1281 | } |
1282 | |
1283 | static const MemoryRegionOps sdhci_mmio_ops = { |
1284 | .read = sdhci_read, |
1285 | .write = sdhci_write, |
1286 | .valid = { |
1287 | .min_access_size = 1, |
1288 | .max_access_size = 4, |
1289 | .unaligned = false |
1290 | }, |
1291 | .endianness = DEVICE_LITTLE_ENDIAN, |
1292 | }; |
1293 | |
1294 | static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) |
1295 | { |
1296 | Error *local_err = NULL; |
1297 | |
1298 | switch (s->sd_spec_version) { |
1299 | case 2 ... 3: |
1300 | break; |
1301 | default: |
1302 | error_setg(errp, "Only Spec v2/v3 are supported" ); |
1303 | return; |
1304 | } |
1305 | s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); |
1306 | |
1307 | sdhci_check_capareg(s, &local_err); |
1308 | if (local_err) { |
1309 | error_propagate(errp, local_err); |
1310 | return; |
1311 | } |
1312 | } |
1313 | |
1314 | /* --- qdev common --- */ |
1315 | |
1316 | void sdhci_initfn(SDHCIState *s) |
1317 | { |
1318 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), |
1319 | TYPE_SDHCI_BUS, DEVICE(s), "sd-bus" ); |
1320 | |
1321 | s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); |
1322 | s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); |
1323 | |
1324 | s->io_ops = &sdhci_mmio_ops; |
1325 | } |
1326 | |
1327 | void sdhci_uninitfn(SDHCIState *s) |
1328 | { |
1329 | timer_del(s->insert_timer); |
1330 | timer_free(s->insert_timer); |
1331 | timer_del(s->transfer_timer); |
1332 | timer_free(s->transfer_timer); |
1333 | |
1334 | g_free(s->fifo_buffer); |
1335 | s->fifo_buffer = NULL; |
1336 | } |
1337 | |
1338 | void sdhci_common_realize(SDHCIState *s, Error **errp) |
1339 | { |
1340 | Error *local_err = NULL; |
1341 | |
1342 | sdhci_init_readonly_registers(s, &local_err); |
1343 | if (local_err) { |
1344 | error_propagate(errp, local_err); |
1345 | return; |
1346 | } |
1347 | s->buf_maxsz = sdhci_get_fifolen(s); |
1348 | s->fifo_buffer = g_malloc0(s->buf_maxsz); |
1349 | |
1350 | memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci" , |
1351 | SDHC_REGISTERS_MAP_SIZE); |
1352 | } |
1353 | |
1354 | void sdhci_common_unrealize(SDHCIState *s, Error **errp) |
1355 | { |
1356 | /* This function is expected to be called only once for each class: |
1357 | * - SysBus: via DeviceClass->unrealize(), |
1358 | * - PCI: via PCIDeviceClass->exit(). |
1359 | * However to avoid double-free and/or use-after-free we still nullify |
1360 | * this variable (better safe than sorry!). */ |
1361 | g_free(s->fifo_buffer); |
1362 | s->fifo_buffer = NULL; |
1363 | } |
1364 | |
1365 | static bool sdhci_pending_insert_vmstate_needed(void *opaque) |
1366 | { |
1367 | SDHCIState *s = opaque; |
1368 | |
1369 | return s->pending_insert_state; |
1370 | } |
1371 | |
1372 | static const VMStateDescription sdhci_pending_insert_vmstate = { |
1373 | .name = "sdhci/pending-insert" , |
1374 | .version_id = 1, |
1375 | .minimum_version_id = 1, |
1376 | .needed = sdhci_pending_insert_vmstate_needed, |
1377 | .fields = (VMStateField[]) { |
1378 | VMSTATE_BOOL(pending_insert_state, SDHCIState), |
1379 | VMSTATE_END_OF_LIST() |
1380 | }, |
1381 | }; |
1382 | |
1383 | const VMStateDescription sdhci_vmstate = { |
1384 | .name = "sdhci" , |
1385 | .version_id = 1, |
1386 | .minimum_version_id = 1, |
1387 | .fields = (VMStateField[]) { |
1388 | VMSTATE_UINT32(sdmasysad, SDHCIState), |
1389 | VMSTATE_UINT16(blksize, SDHCIState), |
1390 | VMSTATE_UINT16(blkcnt, SDHCIState), |
1391 | VMSTATE_UINT32(argument, SDHCIState), |
1392 | VMSTATE_UINT16(trnmod, SDHCIState), |
1393 | VMSTATE_UINT16(cmdreg, SDHCIState), |
1394 | VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), |
1395 | VMSTATE_UINT32(prnsts, SDHCIState), |
1396 | VMSTATE_UINT8(hostctl1, SDHCIState), |
1397 | VMSTATE_UINT8(pwrcon, SDHCIState), |
1398 | VMSTATE_UINT8(blkgap, SDHCIState), |
1399 | VMSTATE_UINT8(wakcon, SDHCIState), |
1400 | VMSTATE_UINT16(clkcon, SDHCIState), |
1401 | VMSTATE_UINT8(timeoutcon, SDHCIState), |
1402 | VMSTATE_UINT8(admaerr, SDHCIState), |
1403 | VMSTATE_UINT16(norintsts, SDHCIState), |
1404 | VMSTATE_UINT16(errintsts, SDHCIState), |
1405 | VMSTATE_UINT16(norintstsen, SDHCIState), |
1406 | VMSTATE_UINT16(errintstsen, SDHCIState), |
1407 | VMSTATE_UINT16(norintsigen, SDHCIState), |
1408 | VMSTATE_UINT16(errintsigen, SDHCIState), |
1409 | VMSTATE_UINT16(acmd12errsts, SDHCIState), |
1410 | VMSTATE_UINT16(data_count, SDHCIState), |
1411 | VMSTATE_UINT64(admasysaddr, SDHCIState), |
1412 | VMSTATE_UINT8(stopped_state, SDHCIState), |
1413 | VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), |
1414 | VMSTATE_TIMER_PTR(insert_timer, SDHCIState), |
1415 | VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), |
1416 | VMSTATE_END_OF_LIST() |
1417 | }, |
1418 | .subsections = (const VMStateDescription*[]) { |
1419 | &sdhci_pending_insert_vmstate, |
1420 | NULL |
1421 | }, |
1422 | }; |
1423 | |
1424 | void sdhci_common_class_init(ObjectClass *klass, void *data) |
1425 | { |
1426 | DeviceClass *dc = DEVICE_CLASS(klass); |
1427 | |
1428 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
1429 | dc->vmsd = &sdhci_vmstate; |
1430 | dc->reset = sdhci_poweron_reset; |
1431 | } |
1432 | |
1433 | /* --- qdev SysBus --- */ |
1434 | |
1435 | static Property sdhci_sysbus_properties[] = { |
1436 | DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), |
1437 | DEFINE_PROP_BOOL("pending-insert-quirk" , SDHCIState, pending_insert_quirk, |
1438 | false), |
1439 | DEFINE_PROP_LINK("dma" , SDHCIState, |
1440 | dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), |
1441 | DEFINE_PROP_END_OF_LIST(), |
1442 | }; |
1443 | |
1444 | static void sdhci_sysbus_init(Object *obj) |
1445 | { |
1446 | SDHCIState *s = SYSBUS_SDHCI(obj); |
1447 | |
1448 | sdhci_initfn(s); |
1449 | } |
1450 | |
1451 | static void sdhci_sysbus_finalize(Object *obj) |
1452 | { |
1453 | SDHCIState *s = SYSBUS_SDHCI(obj); |
1454 | |
1455 | if (s->dma_mr) { |
1456 | object_unparent(OBJECT(s->dma_mr)); |
1457 | } |
1458 | |
1459 | sdhci_uninitfn(s); |
1460 | } |
1461 | |
1462 | static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) |
1463 | { |
1464 | SDHCIState *s = SYSBUS_SDHCI(dev); |
1465 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
1466 | Error *local_err = NULL; |
1467 | |
1468 | sdhci_common_realize(s, &local_err); |
1469 | if (local_err) { |
1470 | error_propagate(errp, local_err); |
1471 | return; |
1472 | } |
1473 | |
1474 | if (s->dma_mr) { |
1475 | s->dma_as = &s->sysbus_dma_as; |
1476 | address_space_init(s->dma_as, s->dma_mr, "sdhci-dma" ); |
1477 | } else { |
1478 | /* use system_memory() if property "dma" not set */ |
1479 | s->dma_as = &address_space_memory; |
1480 | } |
1481 | |
1482 | sysbus_init_irq(sbd, &s->irq); |
1483 | |
1484 | sysbus_init_mmio(sbd, &s->iomem); |
1485 | } |
1486 | |
1487 | static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) |
1488 | { |
1489 | SDHCIState *s = SYSBUS_SDHCI(dev); |
1490 | |
1491 | sdhci_common_unrealize(s, &error_abort); |
1492 | |
1493 | if (s->dma_mr) { |
1494 | address_space_destroy(s->dma_as); |
1495 | } |
1496 | } |
1497 | |
1498 | static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) |
1499 | { |
1500 | DeviceClass *dc = DEVICE_CLASS(klass); |
1501 | |
1502 | dc->props = sdhci_sysbus_properties; |
1503 | dc->realize = sdhci_sysbus_realize; |
1504 | dc->unrealize = sdhci_sysbus_unrealize; |
1505 | |
1506 | sdhci_common_class_init(klass, data); |
1507 | } |
1508 | |
1509 | static const TypeInfo sdhci_sysbus_info = { |
1510 | .name = TYPE_SYSBUS_SDHCI, |
1511 | .parent = TYPE_SYS_BUS_DEVICE, |
1512 | .instance_size = sizeof(SDHCIState), |
1513 | .instance_init = sdhci_sysbus_init, |
1514 | .instance_finalize = sdhci_sysbus_finalize, |
1515 | .class_init = sdhci_sysbus_class_init, |
1516 | }; |
1517 | |
1518 | /* --- qdev bus master --- */ |
1519 | |
1520 | static void sdhci_bus_class_init(ObjectClass *klass, void *data) |
1521 | { |
1522 | SDBusClass *sbc = SD_BUS_CLASS(klass); |
1523 | |
1524 | sbc->set_inserted = sdhci_set_inserted; |
1525 | sbc->set_readonly = sdhci_set_readonly; |
1526 | } |
1527 | |
1528 | static const TypeInfo sdhci_bus_info = { |
1529 | .name = TYPE_SDHCI_BUS, |
1530 | .parent = TYPE_SD_BUS, |
1531 | .instance_size = sizeof(SDBus), |
1532 | .class_init = sdhci_bus_class_init, |
1533 | }; |
1534 | |
1535 | static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) |
1536 | { |
1537 | SDHCIState *s = SYSBUS_SDHCI(opaque); |
1538 | uint32_t ret; |
1539 | uint16_t hostctl1; |
1540 | |
1541 | switch (offset) { |
1542 | default: |
1543 | return sdhci_read(opaque, offset, size); |
1544 | |
1545 | case SDHC_HOSTCTL: |
1546 | /* |
1547 | * For a detailed explanation on the following bit |
1548 | * manipulation code see comments in a similar part of |
1549 | * usdhc_write() |
1550 | */ |
1551 | hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); |
1552 | |
1553 | if (s->hostctl1 & SDHC_CTRL_8BITBUS) { |
1554 | hostctl1 |= ESDHC_CTRL_8BITBUS; |
1555 | } |
1556 | |
1557 | if (s->hostctl1 & SDHC_CTRL_4BITBUS) { |
1558 | hostctl1 |= ESDHC_CTRL_4BITBUS; |
1559 | } |
1560 | |
1561 | ret = hostctl1; |
1562 | ret |= (uint32_t)s->blkgap << 16; |
1563 | ret |= (uint32_t)s->wakcon << 24; |
1564 | |
1565 | break; |
1566 | |
1567 | case SDHC_PRNSTS: |
1568 | /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ |
1569 | ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; |
1570 | if (s->clkcon & SDHC_CLOCK_INT_STABLE) { |
1571 | ret |= ESDHC_PRNSTS_SDSTB; |
1572 | } |
1573 | break; |
1574 | |
1575 | case ESDHC_DLL_CTRL: |
1576 | case ESDHC_TUNE_CTRL_STATUS: |
1577 | case ESDHC_UNDOCUMENTED_REG27: |
1578 | case ESDHC_TUNING_CTRL: |
1579 | case ESDHC_VENDOR_SPEC: |
1580 | case ESDHC_MIX_CTRL: |
1581 | case ESDHC_WTMK_LVL: |
1582 | ret = 0; |
1583 | break; |
1584 | } |
1585 | |
1586 | return ret; |
1587 | } |
1588 | |
1589 | static void |
1590 | usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) |
1591 | { |
1592 | SDHCIState *s = SYSBUS_SDHCI(opaque); |
1593 | uint8_t hostctl1; |
1594 | uint32_t value = (uint32_t)val; |
1595 | |
1596 | switch (offset) { |
1597 | case ESDHC_DLL_CTRL: |
1598 | case ESDHC_TUNE_CTRL_STATUS: |
1599 | case ESDHC_UNDOCUMENTED_REG27: |
1600 | case ESDHC_TUNING_CTRL: |
1601 | case ESDHC_WTMK_LVL: |
1602 | case ESDHC_VENDOR_SPEC: |
1603 | break; |
1604 | |
1605 | case SDHC_HOSTCTL: |
1606 | /* |
1607 | * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) |
1608 | * |
1609 | * 7 6 5 4 3 2 1 0 |
1610 | * |-----------+--------+--------+-----------+----------+---------| |
1611 | * | Card | Card | Endian | DATA3 | Data | Led | |
1612 | * | Detect | Detect | Mode | as Card | Transfer | Control | |
1613 | * | Signal | Test | | Detection | Width | | |
1614 | * | Selection | Level | | Pin | | | |
1615 | * |-----------+--------+--------+-----------+----------+---------| |
1616 | * |
1617 | * and 0x29 |
1618 | * |
1619 | * 15 10 9 8 |
1620 | * |----------+------| |
1621 | * | Reserved | DMA | |
1622 | * | | Sel. | |
1623 | * | | | |
1624 | * |----------+------| |
1625 | * |
1626 | * and here's what SDCHI spec expects those offsets to be: |
1627 | * |
1628 | * 0x28 (Host Control Register) |
1629 | * |
1630 | * 7 6 5 4 3 2 1 0 |
1631 | * |--------+--------+----------+------+--------+----------+---------| |
1632 | * | Card | Card | Extended | DMA | High | Data | LED | |
1633 | * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | |
1634 | * | Signal | Test | Transfer | | Enable | Width | | |
1635 | * | Sel. | Level | Width | | | | | |
1636 | * |--------+--------+----------+------+--------+----------+---------| |
1637 | * |
1638 | * and 0x29 (Power Control Register) |
1639 | * |
1640 | * |----------------------------------| |
1641 | * | Power Control Register | |
1642 | * | | |
1643 | * | Description omitted, | |
1644 | * | since it has no analog in ESDHCI | |
1645 | * | | |
1646 | * |----------------------------------| |
1647 | * |
1648 | * Since offsets 0x2A and 0x2B should be compatible between |
1649 | * both IP specs we only need to reconcile least 16-bit of the |
1650 | * word we've been given. |
1651 | */ |
1652 | |
1653 | /* |
1654 | * First, save bits 7 6 and 0 since they are identical |
1655 | */ |
1656 | hostctl1 = value & (SDHC_CTRL_LED | |
1657 | SDHC_CTRL_CDTEST_INS | |
1658 | SDHC_CTRL_CDTEST_EN); |
1659 | /* |
1660 | * Second, split "Data Transfer Width" from bits 2 and 1 in to |
1661 | * bits 5 and 1 |
1662 | */ |
1663 | if (value & ESDHC_CTRL_8BITBUS) { |
1664 | hostctl1 |= SDHC_CTRL_8BITBUS; |
1665 | } |
1666 | |
1667 | if (value & ESDHC_CTRL_4BITBUS) { |
1668 | hostctl1 |= ESDHC_CTRL_4BITBUS; |
1669 | } |
1670 | |
1671 | /* |
1672 | * Third, move DMA select from bits 9 and 8 to bits 4 and 3 |
1673 | */ |
1674 | hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); |
1675 | |
1676 | /* |
1677 | * Now place the corrected value into low 16-bit of the value |
1678 | * we are going to give standard SDHCI write function |
1679 | * |
1680 | * NOTE: This transformation should be the inverse of what can |
1681 | * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux |
1682 | * kernel |
1683 | */ |
1684 | value &= ~UINT16_MAX; |
1685 | value |= hostctl1; |
1686 | value |= (uint16_t)s->pwrcon << 8; |
1687 | |
1688 | sdhci_write(opaque, offset, value, size); |
1689 | break; |
1690 | |
1691 | case ESDHC_MIX_CTRL: |
1692 | /* |
1693 | * So, when SD/MMC stack in Linux tries to write to "Transfer |
1694 | * Mode Register", ESDHC i.MX quirk code will translate it |
1695 | * into a write to ESDHC_MIX_CTRL, so we do the opposite in |
1696 | * order to get where we started |
1697 | * |
1698 | * Note that Auto CMD23 Enable bit is located in a wrong place |
1699 | * on i.MX, but since it is not used by QEMU we do not care. |
1700 | * |
1701 | * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) |
1702 | * here becuase it will result in a call to |
1703 | * sdhci_send_command(s) which we don't want. |
1704 | * |
1705 | */ |
1706 | s->trnmod = value & UINT16_MAX; |
1707 | break; |
1708 | case SDHC_TRNMOD: |
1709 | /* |
1710 | * Similar to above, but this time a write to "Command |
1711 | * Register" will be translated into a 4-byte write to |
1712 | * "Transfer Mode register" where lower 16-bit of value would |
1713 | * be set to zero. So what we do is fill those bits with |
1714 | * cached value from s->trnmod and let the SDHCI |
1715 | * infrastructure handle the rest |
1716 | */ |
1717 | sdhci_write(opaque, offset, val | s->trnmod, size); |
1718 | break; |
1719 | case SDHC_BLKSIZE: |
1720 | /* |
1721 | * ESDHCI does not implement "Host SDMA Buffer Boundary", and |
1722 | * Linux driver will try to zero this field out which will |
1723 | * break the rest of SDHCI emulation. |
1724 | * |
1725 | * Linux defaults to maximum possible setting (512K boundary) |
1726 | * and it seems to be the only option that i.MX IP implements, |
1727 | * so we artificially set it to that value. |
1728 | */ |
1729 | val |= 0x7 << 12; |
1730 | /* FALLTHROUGH */ |
1731 | default: |
1732 | sdhci_write(opaque, offset, val, size); |
1733 | break; |
1734 | } |
1735 | } |
1736 | |
1737 | |
1738 | static const MemoryRegionOps usdhc_mmio_ops = { |
1739 | .read = usdhc_read, |
1740 | .write = usdhc_write, |
1741 | .valid = { |
1742 | .min_access_size = 1, |
1743 | .max_access_size = 4, |
1744 | .unaligned = false |
1745 | }, |
1746 | .endianness = DEVICE_LITTLE_ENDIAN, |
1747 | }; |
1748 | |
1749 | static void imx_usdhc_init(Object *obj) |
1750 | { |
1751 | SDHCIState *s = SYSBUS_SDHCI(obj); |
1752 | |
1753 | s->io_ops = &usdhc_mmio_ops; |
1754 | s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; |
1755 | } |
1756 | |
1757 | static const TypeInfo imx_usdhc_info = { |
1758 | .name = TYPE_IMX_USDHC, |
1759 | .parent = TYPE_SYSBUS_SDHCI, |
1760 | .instance_init = imx_usdhc_init, |
1761 | }; |
1762 | |
1763 | static void sdhci_register_types(void) |
1764 | { |
1765 | type_register_static(&sdhci_sysbus_info); |
1766 | type_register_static(&sdhci_bus_info); |
1767 | type_register_static(&imx_usdhc_info); |
1768 | } |
1769 | |
1770 | type_init(sdhci_register_types) |
1771 | |