1 | /* |
2 | * QEMU Malta board support |
3 | * |
4 | * Copyright (c) 2006 Aurelien Jarno |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qemu/units.h" |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" |
29 | #include "hw/i386/pc.h" |
30 | #include "hw/isa/superio.h" |
31 | #include "hw/dma/i8257.h" |
32 | #include "hw/char/serial.h" |
33 | #include "net/net.h" |
34 | #include "hw/boards.h" |
35 | #include "hw/i2c/smbus_eeprom.h" |
36 | #include "hw/block/flash.h" |
37 | #include "hw/mips/mips.h" |
38 | #include "hw/mips/cpudevs.h" |
39 | #include "hw/pci/pci.h" |
40 | #include "sysemu/sysemu.h" |
41 | #include "sysemu/arch_init.h" |
42 | #include "qemu/log.h" |
43 | #include "hw/mips/bios.h" |
44 | #include "hw/ide.h" |
45 | #include "hw/irq.h" |
46 | #include "hw/loader.h" |
47 | #include "elf.h" |
48 | #include "hw/timer/mc146818rtc.h" |
49 | #include "hw/timer/i8254.h" |
50 | #include "exec/address-spaces.h" |
51 | #include "hw/sysbus.h" /* SysBusDevice */ |
52 | #include "qemu/host-utils.h" |
53 | #include "sysemu/qtest.h" |
54 | #include "sysemu/reset.h" |
55 | #include "sysemu/runstate.h" |
56 | #include "qapi/error.h" |
57 | #include "qemu/error-report.h" |
58 | #include "hw/empty_slot.h" |
59 | #include "sysemu/kvm.h" |
60 | #include "hw/semihosting/semihost.h" |
61 | #include "hw/mips/cps.h" |
62 | |
63 | #define ENVP_ADDR 0x80002000l |
64 | #define ENVP_NB_ENTRIES 16 |
65 | #define ENVP_ENTRY_SIZE 256 |
66 | |
67 | /* Hardware addresses */ |
68 | #define FLASH_ADDRESS 0x1e000000ULL |
69 | #define FPGA_ADDRESS 0x1f000000ULL |
70 | #define RESET_ADDRESS 0x1fc00000ULL |
71 | |
72 | #define FLASH_SIZE 0x400000 |
73 | |
74 | #define MAX_IDE_BUS 2 |
75 | |
76 | typedef struct { |
77 | MemoryRegion iomem; |
78 | MemoryRegion iomem_lo; /* 0 - 0x900 */ |
79 | MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ |
80 | uint32_t leds; |
81 | uint32_t brk; |
82 | uint32_t gpout; |
83 | uint32_t i2cin; |
84 | uint32_t i2coe; |
85 | uint32_t i2cout; |
86 | uint32_t i2csel; |
87 | CharBackend display; |
88 | char display_text[9]; |
89 | SerialState *uart; |
90 | bool display_inited; |
91 | } MaltaFPGAState; |
92 | |
93 | #define TYPE_MIPS_MALTA "mips-malta" |
94 | #define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA) |
95 | |
96 | typedef struct { |
97 | SysBusDevice parent_obj; |
98 | |
99 | MIPSCPSState cps; |
100 | qemu_irq *i8259; |
101 | } MaltaState; |
102 | |
103 | static ISADevice *pit; |
104 | |
105 | static struct _loaderparams { |
106 | int ram_size, ram_low_size; |
107 | const char *kernel_filename; |
108 | const char *kernel_cmdline; |
109 | const char *initrd_filename; |
110 | } loaderparams; |
111 | |
112 | /* Malta FPGA */ |
113 | static void malta_fpga_update_display(void *opaque) |
114 | { |
115 | char leds_text[9]; |
116 | int i; |
117 | MaltaFPGAState *s = opaque; |
118 | |
119 | for (i = 7 ; i >= 0 ; i--) { |
120 | if (s->leds & (1 << i)) { |
121 | leds_text[i] = '#'; |
122 | } else { |
123 | leds_text[i] = ' '; |
124 | } |
125 | } |
126 | leds_text[8] = '\0'; |
127 | |
128 | qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n" , |
129 | leds_text); |
130 | qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|" , |
131 | s->display_text); |
132 | } |
133 | |
134 | /* |
135 | * EEPROM 24C01 / 24C02 emulation. |
136 | * |
137 | * Emulation for serial EEPROMs: |
138 | * 24C01 - 1024 bit (128 x 8) |
139 | * 24C02 - 2048 bit (256 x 8) |
140 | * |
141 | * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. |
142 | */ |
143 | |
144 | #if defined(DEBUG) |
145 | # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) |
146 | #else |
147 | # define logout(fmt, ...) ((void)0) |
148 | #endif |
149 | |
150 | struct _eeprom24c0x_t { |
151 | uint8_t tick; |
152 | uint8_t address; |
153 | uint8_t command; |
154 | uint8_t ack; |
155 | uint8_t scl; |
156 | uint8_t sda; |
157 | uint8_t data; |
158 | /* uint16_t size; */ |
159 | uint8_t contents[256]; |
160 | }; |
161 | |
162 | typedef struct _eeprom24c0x_t eeprom24c0x_t; |
163 | |
164 | static eeprom24c0x_t spd_eeprom = { |
165 | .contents = { |
166 | /* 00000000: */ |
167 | 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, |
168 | /* 00000008: */ |
169 | 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, |
170 | /* 00000010: */ |
171 | 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, |
172 | /* 00000018: */ |
173 | 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, |
174 | /* 00000020: */ |
175 | 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, |
176 | /* 00000028: */ |
177 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
178 | /* 00000030: */ |
179 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
180 | /* 00000038: */ |
181 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, |
182 | /* 00000040: */ |
183 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
184 | /* 00000048: */ |
185 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
186 | /* 00000050: */ |
187 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
188 | /* 00000058: */ |
189 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
190 | /* 00000060: */ |
191 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
192 | /* 00000068: */ |
193 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
194 | /* 00000070: */ |
195 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
196 | /* 00000078: */ |
197 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, |
198 | }, |
199 | }; |
200 | |
201 | static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) |
202 | { |
203 | enum { SDR = 0x4, DDR2 = 0x8 } type; |
204 | uint8_t *spd = spd_eeprom.contents; |
205 | uint8_t nbanks = 0; |
206 | uint16_t density = 0; |
207 | int i; |
208 | |
209 | /* work in terms of MB */ |
210 | ram_size /= MiB; |
211 | |
212 | while ((ram_size >= 4) && (nbanks <= 2)) { |
213 | int sz_log2 = MIN(31 - clz32(ram_size), 14); |
214 | nbanks++; |
215 | density |= 1 << (sz_log2 - 2); |
216 | ram_size -= 1 << sz_log2; |
217 | } |
218 | |
219 | /* split to 2 banks if possible */ |
220 | if ((nbanks == 1) && (density > 1)) { |
221 | nbanks++; |
222 | density >>= 1; |
223 | } |
224 | |
225 | if (density & 0xff00) { |
226 | density = (density & 0xe0) | ((density >> 8) & 0x1f); |
227 | type = DDR2; |
228 | } else if (!(density & 0x1f)) { |
229 | type = DDR2; |
230 | } else { |
231 | type = SDR; |
232 | } |
233 | |
234 | if (ram_size) { |
235 | warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" |
236 | " of SDRAM" , ram_size); |
237 | } |
238 | |
239 | /* fill in SPD memory information */ |
240 | spd[2] = type; |
241 | spd[5] = nbanks; |
242 | spd[31] = density; |
243 | |
244 | /* checksum */ |
245 | spd[63] = 0; |
246 | for (i = 0; i < 63; i++) { |
247 | spd[63] += spd[i]; |
248 | } |
249 | |
250 | /* copy for SMBUS */ |
251 | memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); |
252 | } |
253 | |
254 | static void generate_eeprom_serial(uint8_t *eeprom) |
255 | { |
256 | int i, pos = 0; |
257 | uint8_t mac[6] = { 0x00 }; |
258 | uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; |
259 | |
260 | /* version */ |
261 | eeprom[pos++] = 0x01; |
262 | |
263 | /* count */ |
264 | eeprom[pos++] = 0x02; |
265 | |
266 | /* MAC address */ |
267 | eeprom[pos++] = 0x01; /* MAC */ |
268 | eeprom[pos++] = 0x06; /* length */ |
269 | memcpy(&eeprom[pos], mac, sizeof(mac)); |
270 | pos += sizeof(mac); |
271 | |
272 | /* serial number */ |
273 | eeprom[pos++] = 0x02; /* serial */ |
274 | eeprom[pos++] = 0x05; /* length */ |
275 | memcpy(&eeprom[pos], sn, sizeof(sn)); |
276 | pos += sizeof(sn); |
277 | |
278 | /* checksum */ |
279 | eeprom[pos] = 0; |
280 | for (i = 0; i < pos; i++) { |
281 | eeprom[pos] += eeprom[i]; |
282 | } |
283 | } |
284 | |
285 | static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) |
286 | { |
287 | logout("%u: scl = %u, sda = %u, data = 0x%02x\n" , |
288 | eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); |
289 | return eeprom->sda; |
290 | } |
291 | |
292 | static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) |
293 | { |
294 | if (eeprom->scl && scl && (eeprom->sda != sda)) { |
295 | logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n" , |
296 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, |
297 | sda ? "stop" : "start" ); |
298 | if (!sda) { |
299 | eeprom->tick = 1; |
300 | eeprom->command = 0; |
301 | } |
302 | } else if (eeprom->tick == 0 && !eeprom->ack) { |
303 | /* Waiting for start. */ |
304 | logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n" , |
305 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
306 | } else if (!eeprom->scl && scl) { |
307 | logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n" , |
308 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
309 | if (eeprom->ack) { |
310 | logout("\ti2c ack bit = 0\n" ); |
311 | sda = 0; |
312 | eeprom->ack = 0; |
313 | } else if (eeprom->sda == sda) { |
314 | uint8_t bit = (sda != 0); |
315 | logout("\ti2c bit = %d\n" , bit); |
316 | if (eeprom->tick < 9) { |
317 | eeprom->command <<= 1; |
318 | eeprom->command += bit; |
319 | eeprom->tick++; |
320 | if (eeprom->tick == 9) { |
321 | logout("\tcommand 0x%04x, %s\n" , eeprom->command, |
322 | bit ? "read" : "write" ); |
323 | eeprom->ack = 1; |
324 | } |
325 | } else if (eeprom->tick < 17) { |
326 | if (eeprom->command & 1) { |
327 | sda = ((eeprom->data & 0x80) != 0); |
328 | } |
329 | eeprom->address <<= 1; |
330 | eeprom->address += bit; |
331 | eeprom->tick++; |
332 | eeprom->data <<= 1; |
333 | if (eeprom->tick == 17) { |
334 | eeprom->data = eeprom->contents[eeprom->address]; |
335 | logout("\taddress 0x%04x, data 0x%02x\n" , |
336 | eeprom->address, eeprom->data); |
337 | eeprom->ack = 1; |
338 | eeprom->tick = 0; |
339 | } |
340 | } else if (eeprom->tick >= 17) { |
341 | sda = 0; |
342 | } |
343 | } else { |
344 | logout("\tsda changed with raising scl\n" ); |
345 | } |
346 | } else { |
347 | logout("%u: scl = %u->%u, sda = %u->%u\n" , eeprom->tick, eeprom->scl, |
348 | scl, eeprom->sda, sda); |
349 | } |
350 | eeprom->scl = scl; |
351 | eeprom->sda = sda; |
352 | } |
353 | |
354 | static uint64_t malta_fpga_read(void *opaque, hwaddr addr, |
355 | unsigned size) |
356 | { |
357 | MaltaFPGAState *s = opaque; |
358 | uint32_t val = 0; |
359 | uint32_t saddr; |
360 | |
361 | saddr = (addr & 0xfffff); |
362 | |
363 | switch (saddr) { |
364 | |
365 | /* SWITCH Register */ |
366 | case 0x00200: |
367 | /* ori a3, a3, low(ram_low_size) */ |
368 | val = 0x00000000; |
369 | break; |
370 | |
371 | /* STATUS Register */ |
372 | case 0x00208: |
373 | #ifdef TARGET_WORDS_BIGENDIAN |
374 | val = 0x00000012; |
375 | #else |
376 | val = 0x00000010; |
377 | #endif |
378 | break; |
379 | |
380 | /* JMPRS Register */ |
381 | case 0x00210: |
382 | val = 0x00; |
383 | break; |
384 | |
385 | /* LEDBAR Register */ |
386 | case 0x00408: |
387 | val = s->leds; |
388 | break; |
389 | |
390 | /* BRKRES Register */ |
391 | case 0x00508: |
392 | val = s->brk; |
393 | break; |
394 | |
395 | /* UART Registers are handled directly by the serial device */ |
396 | |
397 | /* GPOUT Register */ |
398 | case 0x00a00: |
399 | val = s->gpout; |
400 | break; |
401 | |
402 | /* XXX: implement a real I2C controller */ |
403 | |
404 | /* GPINP Register */ |
405 | case 0x00a08: |
406 | /* IN = OUT until a real I2C control is implemented */ |
407 | if (s->i2csel) { |
408 | val = s->i2cout; |
409 | } else { |
410 | val = 0x00; |
411 | } |
412 | break; |
413 | |
414 | /* I2CINP Register */ |
415 | case 0x00b00: |
416 | val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); |
417 | break; |
418 | |
419 | /* I2COE Register */ |
420 | case 0x00b08: |
421 | val = s->i2coe; |
422 | break; |
423 | |
424 | /* I2COUT Register */ |
425 | case 0x00b10: |
426 | val = s->i2cout; |
427 | break; |
428 | |
429 | /* I2CSEL Register */ |
430 | case 0x00b18: |
431 | val = s->i2csel; |
432 | break; |
433 | |
434 | default: |
435 | #if 0 |
436 | printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n" , |
437 | addr); |
438 | #endif |
439 | break; |
440 | } |
441 | return val; |
442 | } |
443 | |
444 | static void malta_fpga_write(void *opaque, hwaddr addr, |
445 | uint64_t val, unsigned size) |
446 | { |
447 | MaltaFPGAState *s = opaque; |
448 | uint32_t saddr; |
449 | |
450 | saddr = (addr & 0xfffff); |
451 | |
452 | switch (saddr) { |
453 | |
454 | /* SWITCH Register */ |
455 | case 0x00200: |
456 | break; |
457 | |
458 | /* JMPRS Register */ |
459 | case 0x00210: |
460 | break; |
461 | |
462 | /* LEDBAR Register */ |
463 | case 0x00408: |
464 | s->leds = val & 0xff; |
465 | malta_fpga_update_display(s); |
466 | break; |
467 | |
468 | /* ASCIIWORD Register */ |
469 | case 0x00410: |
470 | snprintf(s->display_text, 9, "%08X" , (uint32_t)val); |
471 | malta_fpga_update_display(s); |
472 | break; |
473 | |
474 | /* ASCIIPOS0 to ASCIIPOS7 Registers */ |
475 | case 0x00418: |
476 | case 0x00420: |
477 | case 0x00428: |
478 | case 0x00430: |
479 | case 0x00438: |
480 | case 0x00440: |
481 | case 0x00448: |
482 | case 0x00450: |
483 | s->display_text[(saddr - 0x00418) >> 3] = (char) val; |
484 | malta_fpga_update_display(s); |
485 | break; |
486 | |
487 | /* SOFTRES Register */ |
488 | case 0x00500: |
489 | if (val == 0x42) { |
490 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
491 | } |
492 | break; |
493 | |
494 | /* BRKRES Register */ |
495 | case 0x00508: |
496 | s->brk = val & 0xff; |
497 | break; |
498 | |
499 | /* UART Registers are handled directly by the serial device */ |
500 | |
501 | /* GPOUT Register */ |
502 | case 0x00a00: |
503 | s->gpout = val & 0xff; |
504 | break; |
505 | |
506 | /* I2COE Register */ |
507 | case 0x00b08: |
508 | s->i2coe = val & 0x03; |
509 | break; |
510 | |
511 | /* I2COUT Register */ |
512 | case 0x00b10: |
513 | eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); |
514 | s->i2cout = val; |
515 | break; |
516 | |
517 | /* I2CSEL Register */ |
518 | case 0x00b18: |
519 | s->i2csel = val & 0x01; |
520 | break; |
521 | |
522 | default: |
523 | #if 0 |
524 | printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n" , |
525 | addr); |
526 | #endif |
527 | break; |
528 | } |
529 | } |
530 | |
531 | static const MemoryRegionOps malta_fpga_ops = { |
532 | .read = malta_fpga_read, |
533 | .write = malta_fpga_write, |
534 | .endianness = DEVICE_NATIVE_ENDIAN, |
535 | }; |
536 | |
537 | static void malta_fpga_reset(void *opaque) |
538 | { |
539 | MaltaFPGAState *s = opaque; |
540 | |
541 | s->leds = 0x00; |
542 | s->brk = 0x0a; |
543 | s->gpout = 0x00; |
544 | s->i2cin = 0x3; |
545 | s->i2coe = 0x0; |
546 | s->i2cout = 0x3; |
547 | s->i2csel = 0x1; |
548 | |
549 | s->display_text[8] = '\0'; |
550 | snprintf(s->display_text, 9, " " ); |
551 | } |
552 | |
553 | static void malta_fgpa_display_event(void *opaque, int event) |
554 | { |
555 | MaltaFPGAState *s = opaque; |
556 | |
557 | if (event == CHR_EVENT_OPENED && !s->display_inited) { |
558 | qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n" ); |
559 | qemu_chr_fe_printf(&s->display, "+--------+\r\n" ); |
560 | qemu_chr_fe_printf(&s->display, "+ +\r\n" ); |
561 | qemu_chr_fe_printf(&s->display, "+--------+\r\n" ); |
562 | qemu_chr_fe_printf(&s->display, "\n" ); |
563 | qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n" ); |
564 | qemu_chr_fe_printf(&s->display, "+--------+\r\n" ); |
565 | qemu_chr_fe_printf(&s->display, "+ +\r\n" ); |
566 | qemu_chr_fe_printf(&s->display, "+--------+\r\n" ); |
567 | s->display_inited = true; |
568 | } |
569 | } |
570 | |
571 | static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, |
572 | hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) |
573 | { |
574 | MaltaFPGAState *s; |
575 | Chardev *chr; |
576 | |
577 | s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState)); |
578 | |
579 | memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, |
580 | "malta-fpga" , 0x100000); |
581 | memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga" , |
582 | &s->iomem, 0, 0x900); |
583 | memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga" , |
584 | &s->iomem, 0xa00, 0x10000 - 0xa00); |
585 | |
586 | memory_region_add_subregion(address_space, base, &s->iomem_lo); |
587 | memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); |
588 | |
589 | chr = qemu_chr_new("fpga" , "vc:320x200" , NULL); |
590 | qemu_chr_fe_init(&s->display, chr, NULL); |
591 | qemu_chr_fe_set_handlers(&s->display, NULL, NULL, |
592 | malta_fgpa_display_event, NULL, s, NULL, true); |
593 | |
594 | s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, |
595 | 230400, uart_chr, DEVICE_NATIVE_ENDIAN); |
596 | |
597 | malta_fpga_reset(s); |
598 | qemu_register_reset(malta_fpga_reset, s); |
599 | |
600 | return s; |
601 | } |
602 | |
603 | /* Network support */ |
604 | static void network_init(PCIBus *pci_bus) |
605 | { |
606 | int i; |
607 | |
608 | for (i = 0; i < nb_nics; i++) { |
609 | NICInfo *nd = &nd_table[i]; |
610 | const char *default_devaddr = NULL; |
611 | |
612 | if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet" ) == 0)) |
613 | /* The malta board has a PCNet card using PCI SLOT 11 */ |
614 | default_devaddr = "0b" ; |
615 | |
616 | pci_nic_init_nofail(nd, pci_bus, "pcnet" , default_devaddr); |
617 | } |
618 | } |
619 | |
620 | static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, |
621 | int64_t kernel_entry) |
622 | { |
623 | uint16_t *p; |
624 | |
625 | /* Small bootloader */ |
626 | p = (uint16_t *)base; |
627 | |
628 | #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) |
629 | #define NM_HI2(VAL) \ |
630 | (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) |
631 | #define NM_LO(VAL) ((VAL) & 0xfff) |
632 | |
633 | stw_p(p++, 0x2800); stw_p(p++, 0x001c); |
634 | /* bc to_here */ |
635 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
636 | /* nop */ |
637 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
638 | /* nop */ |
639 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
640 | /* nop */ |
641 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
642 | /* nop */ |
643 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
644 | /* nop */ |
645 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
646 | /* nop */ |
647 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
648 | /* nop */ |
649 | |
650 | /* to_here: */ |
651 | if (semihosting_get_argc()) { |
652 | /* Preserve a0 content as arguments have been passed */ |
653 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); |
654 | /* nop */ |
655 | } else { |
656 | stw_p(p++, 0x0080); stw_p(p++, 0x0002); |
657 | /* li a0,2 */ |
658 | } |
659 | |
660 | stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); |
661 | |
662 | stw_p(p++, NM_HI2(ENVP_ADDR - 64)); |
663 | /* lui sp,%hi(ENVP_ADDR - 64) */ |
664 | |
665 | stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); |
666 | /* ori sp,sp,%lo(ENVP_ADDR - 64) */ |
667 | |
668 | stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); |
669 | |
670 | stw_p(p++, NM_HI2(ENVP_ADDR)); |
671 | /* lui a1,%hi(ENVP_ADDR) */ |
672 | |
673 | stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); |
674 | /* ori a1,a1,%lo(ENVP_ADDR) */ |
675 | |
676 | stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); |
677 | |
678 | stw_p(p++, NM_HI2(ENVP_ADDR + 8)); |
679 | /* lui a2,%hi(ENVP_ADDR + 8) */ |
680 | |
681 | stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); |
682 | /* ori a2,a2,%lo(ENVP_ADDR + 8) */ |
683 | |
684 | stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); |
685 | |
686 | stw_p(p++, NM_HI2(loaderparams.ram_low_size)); |
687 | /* lui a3,%hi(loaderparams.ram_low_size) */ |
688 | |
689 | stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); |
690 | /* ori a3,a3,%lo(loaderparams.ram_low_size) */ |
691 | |
692 | /* |
693 | * Load BAR registers as done by YAMON: |
694 | * |
695 | * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff |
696 | * - set up PCI0 MEM0 at 0x10000000, size 0x8000000 |
697 | * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000 |
698 | * |
699 | */ |
700 | stw_p(p++, 0xe040); stw_p(p++, 0x0681); |
701 | /* lui t1, %hi(0xb4000000) */ |
702 | |
703 | #ifdef TARGET_WORDS_BIGENDIAN |
704 | |
705 | stw_p(p++, 0xe020); stw_p(p++, 0x0be1); |
706 | /* lui t0, %hi(0xdf000000) */ |
707 | |
708 | /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */ |
709 | stw_p(p++, 0x8422); stw_p(p++, 0x9068); |
710 | /* sw t0, 0x68(t1) */ |
711 | |
712 | stw_p(p++, 0xe040); stw_p(p++, 0x077d); |
713 | /* lui t1, %hi(0xbbe00000) */ |
714 | |
715 | stw_p(p++, 0xe020); stw_p(p++, 0x0801); |
716 | /* lui t0, %hi(0xc0000000) */ |
717 | |
718 | /* 0x48 corresponds to GT_PCI0IOLD */ |
719 | stw_p(p++, 0x8422); stw_p(p++, 0x9048); |
720 | /* sw t0, 0x48(t1) */ |
721 | |
722 | stw_p(p++, 0xe020); stw_p(p++, 0x0800); |
723 | /* lui t0, %hi(0x40000000) */ |
724 | |
725 | /* 0x50 corresponds to GT_PCI0IOHD */ |
726 | stw_p(p++, 0x8422); stw_p(p++, 0x9050); |
727 | /* sw t0, 0x50(t1) */ |
728 | |
729 | stw_p(p++, 0xe020); stw_p(p++, 0x0001); |
730 | /* lui t0, %hi(0x80000000) */ |
731 | |
732 | /* 0x58 corresponds to GT_PCI0M0LD */ |
733 | stw_p(p++, 0x8422); stw_p(p++, 0x9058); |
734 | /* sw t0, 0x58(t1) */ |
735 | |
736 | stw_p(p++, 0xe020); stw_p(p++, 0x07e0); |
737 | /* lui t0, %hi(0x3f000000) */ |
738 | |
739 | /* 0x60 corresponds to GT_PCI0M0HD */ |
740 | stw_p(p++, 0x8422); stw_p(p++, 0x9060); |
741 | /* sw t0, 0x60(t1) */ |
742 | |
743 | stw_p(p++, 0xe020); stw_p(p++, 0x0821); |
744 | /* lui t0, %hi(0xc1000000) */ |
745 | |
746 | /* 0x80 corresponds to GT_PCI0M1LD */ |
747 | stw_p(p++, 0x8422); stw_p(p++, 0x9080); |
748 | /* sw t0, 0x80(t1) */ |
749 | |
750 | stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); |
751 | /* lui t0, %hi(0x5e000000) */ |
752 | |
753 | #else |
754 | |
755 | stw_p(p++, 0x0020); stw_p(p++, 0x00df); |
756 | /* addiu[32] t0, $0, 0xdf */ |
757 | |
758 | /* 0x68 corresponds to GT_ISD */ |
759 | stw_p(p++, 0x8422); stw_p(p++, 0x9068); |
760 | /* sw t0, 0x68(t1) */ |
761 | |
762 | /* Use kseg2 remapped address 0x1be00000 */ |
763 | stw_p(p++, 0xe040); stw_p(p++, 0x077d); |
764 | /* lui t1, %hi(0xbbe00000) */ |
765 | |
766 | stw_p(p++, 0x0020); stw_p(p++, 0x00c0); |
767 | /* addiu[32] t0, $0, 0xc0 */ |
768 | |
769 | /* 0x48 corresponds to GT_PCI0IOLD */ |
770 | stw_p(p++, 0x8422); stw_p(p++, 0x9048); |
771 | /* sw t0, 0x48(t1) */ |
772 | |
773 | stw_p(p++, 0x0020); stw_p(p++, 0x0040); |
774 | /* addiu[32] t0, $0, 0x40 */ |
775 | |
776 | /* 0x50 corresponds to GT_PCI0IOHD */ |
777 | stw_p(p++, 0x8422); stw_p(p++, 0x9050); |
778 | /* sw t0, 0x50(t1) */ |
779 | |
780 | stw_p(p++, 0x0020); stw_p(p++, 0x0080); |
781 | /* addiu[32] t0, $0, 0x80 */ |
782 | |
783 | /* 0x58 corresponds to GT_PCI0M0LD */ |
784 | stw_p(p++, 0x8422); stw_p(p++, 0x9058); |
785 | /* sw t0, 0x58(t1) */ |
786 | |
787 | stw_p(p++, 0x0020); stw_p(p++, 0x003f); |
788 | /* addiu[32] t0, $0, 0x3f */ |
789 | |
790 | /* 0x60 corresponds to GT_PCI0M0HD */ |
791 | stw_p(p++, 0x8422); stw_p(p++, 0x9060); |
792 | /* sw t0, 0x60(t1) */ |
793 | |
794 | stw_p(p++, 0x0020); stw_p(p++, 0x00c1); |
795 | /* addiu[32] t0, $0, 0xc1 */ |
796 | |
797 | /* 0x80 corresponds to GT_PCI0M1LD */ |
798 | stw_p(p++, 0x8422); stw_p(p++, 0x9080); |
799 | /* sw t0, 0x80(t1) */ |
800 | |
801 | stw_p(p++, 0x0020); stw_p(p++, 0x005e); |
802 | /* addiu[32] t0, $0, 0x5e */ |
803 | |
804 | #endif |
805 | |
806 | /* 0x88 corresponds to GT_PCI0M1HD */ |
807 | stw_p(p++, 0x8422); stw_p(p++, 0x9088); |
808 | /* sw t0, 0x88(t1) */ |
809 | |
810 | stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); |
811 | |
812 | stw_p(p++, NM_HI2(kernel_entry)); |
813 | /* lui t9,%hi(kernel_entry) */ |
814 | |
815 | stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); |
816 | /* ori t9,t9,%lo(kernel_entry) */ |
817 | |
818 | stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); |
819 | /* jalrc t8 */ |
820 | } |
821 | |
822 | /* |
823 | * ROM and pseudo bootloader |
824 | * |
825 | * The following code implements a very very simple bootloader. It first |
826 | * loads the registers a0 to a3 to the values expected by the OS, and |
827 | * then jump at the kernel address. |
828 | * |
829 | * The bootloader should pass the locations of the kernel arguments and |
830 | * environment variables tables. Those tables contain the 32-bit address |
831 | * of NULL terminated strings. The environment variables table should be |
832 | * terminated by a NULL address. |
833 | * |
834 | * For a simpler implementation, the number of kernel arguments is fixed |
835 | * to two (the name of the kernel and the command line), and the two |
836 | * tables are actually the same one. |
837 | * |
838 | * The registers a0 to a3 should contain the following values: |
839 | * a0 - number of kernel arguments |
840 | * a1 - 32-bit address of the kernel arguments table |
841 | * a2 - 32-bit address of the environment variables table |
842 | * a3 - RAM size in bytes |
843 | */ |
844 | static void write_bootloader(uint8_t *base, int64_t run_addr, |
845 | int64_t kernel_entry) |
846 | { |
847 | uint32_t *p; |
848 | |
849 | /* Small bootloader */ |
850 | p = (uint32_t *)base; |
851 | |
852 | stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ |
853 | ((run_addr + 0x580) & 0x0fffffff) >> 2); |
854 | stl_p(p++, 0x00000000); /* nop */ |
855 | |
856 | /* YAMON service vector */ |
857 | stl_p(base + 0x500, run_addr + 0x0580); /* start: */ |
858 | stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ |
859 | stl_p(base + 0x520, run_addr + 0x0580); /* start: */ |
860 | stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ |
861 | stl_p(base + 0x534, run_addr + 0x0808); /* print: */ |
862 | stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ |
863 | stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ |
864 | stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ |
865 | stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ |
866 | stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ |
867 | stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ |
868 | stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ |
869 | stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ |
870 | |
871 | |
872 | /* Second part of the bootloader */ |
873 | p = (uint32_t *) (base + 0x580); |
874 | |
875 | if (semihosting_get_argc()) { |
876 | /* Preserve a0 content as arguments have been passed */ |
877 | stl_p(p++, 0x00000000); /* nop */ |
878 | } else { |
879 | stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ |
880 | } |
881 | |
882 | /* lui sp, high(ENVP_ADDR) */ |
883 | stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); |
884 | /* ori sp, sp, low(ENVP_ADDR) */ |
885 | stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); |
886 | /* lui a1, high(ENVP_ADDR) */ |
887 | stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); |
888 | /* ori a1, a1, low(ENVP_ADDR) */ |
889 | stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); |
890 | /* lui a2, high(ENVP_ADDR + 8) */ |
891 | stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); |
892 | /* ori a2, a2, low(ENVP_ADDR + 8) */ |
893 | stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); |
894 | /* lui a3, high(ram_low_size) */ |
895 | stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); |
896 | /* ori a3, a3, low(ram_low_size) */ |
897 | stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); |
898 | |
899 | /* Load BAR registers as done by YAMON */ |
900 | stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ |
901 | |
902 | #ifdef TARGET_WORDS_BIGENDIAN |
903 | stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ |
904 | #else |
905 | stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ |
906 | #endif |
907 | stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ |
908 | |
909 | stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ |
910 | |
911 | #ifdef TARGET_WORDS_BIGENDIAN |
912 | stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ |
913 | #else |
914 | stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ |
915 | #endif |
916 | stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ |
917 | #ifdef TARGET_WORDS_BIGENDIAN |
918 | stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ |
919 | #else |
920 | stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ |
921 | #endif |
922 | stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ |
923 | |
924 | #ifdef TARGET_WORDS_BIGENDIAN |
925 | stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ |
926 | #else |
927 | stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ |
928 | #endif |
929 | stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ |
930 | #ifdef TARGET_WORDS_BIGENDIAN |
931 | stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ |
932 | #else |
933 | stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ |
934 | #endif |
935 | stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ |
936 | |
937 | #ifdef TARGET_WORDS_BIGENDIAN |
938 | stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ |
939 | #else |
940 | stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ |
941 | #endif |
942 | stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ |
943 | #ifdef TARGET_WORDS_BIGENDIAN |
944 | stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ |
945 | #else |
946 | stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ |
947 | #endif |
948 | stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ |
949 | |
950 | /* Jump to kernel code */ |
951 | stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ |
952 | stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ |
953 | stl_p(p++, 0x03e00009); /* jalr ra */ |
954 | stl_p(p++, 0x00000000); /* nop */ |
955 | |
956 | /* YAMON subroutines */ |
957 | p = (uint32_t *) (base + 0x800); |
958 | stl_p(p++, 0x03e00009); /* jalr ra */ |
959 | stl_p(p++, 0x24020000); /* li v0,0 */ |
960 | /* 808 YAMON print */ |
961 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
962 | stl_p(p++, 0x00805821); /* move t3,a0 */ |
963 | stl_p(p++, 0x00a05021); /* move t2,a1 */ |
964 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ |
965 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ |
966 | stl_p(p++, 0x10800005); /* beqz a0,834 */ |
967 | stl_p(p++, 0x00000000); /* nop */ |
968 | stl_p(p++, 0x0ff0021c); /* jal 870 */ |
969 | stl_p(p++, 0x00000000); /* nop */ |
970 | stl_p(p++, 0x1000fff9); /* b 814 */ |
971 | stl_p(p++, 0x00000000); /* nop */ |
972 | stl_p(p++, 0x01a00009); /* jalr t5 */ |
973 | stl_p(p++, 0x01602021); /* move a0,t3 */ |
974 | /* 0x83c YAMON print_count */ |
975 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
976 | stl_p(p++, 0x00805821); /* move t3,a0 */ |
977 | stl_p(p++, 0x00a05021); /* move t2,a1 */ |
978 | stl_p(p++, 0x00c06021); /* move t4,a2 */ |
979 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ |
980 | stl_p(p++, 0x0ff0021c); /* jal 870 */ |
981 | stl_p(p++, 0x00000000); /* nop */ |
982 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ |
983 | stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ |
984 | stl_p(p++, 0x1580fffa); /* bnez t4,84c */ |
985 | stl_p(p++, 0x00000000); /* nop */ |
986 | stl_p(p++, 0x01a00009); /* jalr t5 */ |
987 | stl_p(p++, 0x01602021); /* move a0,t3 */ |
988 | /* 0x870 */ |
989 | stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ |
990 | stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ |
991 | stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ |
992 | stl_p(p++, 0x00000000); /* nop */ |
993 | stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ |
994 | stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ |
995 | stl_p(p++, 0x00000000); /* nop */ |
996 | stl_p(p++, 0x03e00009); /* jalr ra */ |
997 | stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ |
998 | |
999 | } |
1000 | |
1001 | static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, |
1002 | const char *string, ...) |
1003 | { |
1004 | va_list ap; |
1005 | int32_t table_addr; |
1006 | |
1007 | if (index >= ENVP_NB_ENTRIES) { |
1008 | return; |
1009 | } |
1010 | |
1011 | if (string == NULL) { |
1012 | prom_buf[index] = 0; |
1013 | return; |
1014 | } |
1015 | |
1016 | table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; |
1017 | prom_buf[index] = tswap32(ENVP_ADDR + table_addr); |
1018 | |
1019 | va_start(ap, string); |
1020 | vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); |
1021 | va_end(ap); |
1022 | } |
1023 | |
1024 | /* Kernel */ |
1025 | static int64_t load_kernel(void) |
1026 | { |
1027 | int64_t kernel_entry, kernel_high, initrd_size; |
1028 | long kernel_size; |
1029 | ram_addr_t initrd_offset; |
1030 | int big_endian; |
1031 | uint32_t *prom_buf; |
1032 | long prom_size; |
1033 | int prom_index = 0; |
1034 | uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); |
1035 | |
1036 | #ifdef TARGET_WORDS_BIGENDIAN |
1037 | big_endian = 1; |
1038 | #else |
1039 | big_endian = 0; |
1040 | #endif |
1041 | |
1042 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, |
1043 | cpu_mips_kseg0_to_phys, NULL, |
1044 | (uint64_t *)&kernel_entry, NULL, |
1045 | (uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0); |
1046 | if (kernel_size < 0) { |
1047 | error_report("could not load kernel '%s': %s" , |
1048 | loaderparams.kernel_filename, |
1049 | load_elf_strerror(kernel_size)); |
1050 | exit(1); |
1051 | } |
1052 | |
1053 | /* Check where the kernel has been linked */ |
1054 | if (kernel_entry & 0x80000000ll) { |
1055 | if (kvm_enabled()) { |
1056 | error_report("KVM guest kernels must be linked in useg. " |
1057 | "Did you forget to enable CONFIG_KVM_GUEST?" ); |
1058 | exit(1); |
1059 | } |
1060 | |
1061 | xlate_to_kseg0 = cpu_mips_phys_to_kseg0; |
1062 | } else { |
1063 | /* if kernel entry is in useg it is probably a KVM T&E kernel */ |
1064 | mips_um_ksegs_enable(); |
1065 | |
1066 | xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; |
1067 | } |
1068 | |
1069 | /* load initrd */ |
1070 | initrd_size = 0; |
1071 | initrd_offset = 0; |
1072 | if (loaderparams.initrd_filename) { |
1073 | initrd_size = get_image_size(loaderparams.initrd_filename); |
1074 | if (initrd_size > 0) { |
1075 | /* |
1076 | * The kernel allocates the bootmap memory in the low memory after |
1077 | * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB |
1078 | * pages. |
1079 | */ |
1080 | initrd_offset = (loaderparams.ram_low_size - initrd_size |
1081 | - (128 * KiB) |
1082 | - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; |
1083 | if (kernel_high >= initrd_offset) { |
1084 | error_report("memory too small for initial ram disk '%s'" , |
1085 | loaderparams.initrd_filename); |
1086 | exit(1); |
1087 | } |
1088 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
1089 | initrd_offset, |
1090 | ram_size - initrd_offset); |
1091 | } |
1092 | if (initrd_size == (target_ulong) -1) { |
1093 | error_report("could not load initial ram disk '%s'" , |
1094 | loaderparams.initrd_filename); |
1095 | exit(1); |
1096 | } |
1097 | } |
1098 | |
1099 | /* Setup prom parameters. */ |
1100 | prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); |
1101 | prom_buf = g_malloc(prom_size); |
1102 | |
1103 | prom_set(prom_buf, prom_index++, "%s" , loaderparams.kernel_filename); |
1104 | if (initrd_size > 0) { |
1105 | prom_set(prom_buf, prom_index++, |
1106 | "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s" , |
1107 | xlate_to_kseg0(NULL, initrd_offset), |
1108 | initrd_size, loaderparams.kernel_cmdline); |
1109 | } else { |
1110 | prom_set(prom_buf, prom_index++, "%s" , loaderparams.kernel_cmdline); |
1111 | } |
1112 | |
1113 | prom_set(prom_buf, prom_index++, "memsize" ); |
1114 | prom_set(prom_buf, prom_index++, "%u" , loaderparams.ram_low_size); |
1115 | |
1116 | prom_set(prom_buf, prom_index++, "ememsize" ); |
1117 | prom_set(prom_buf, prom_index++, "%u" , loaderparams.ram_size); |
1118 | |
1119 | prom_set(prom_buf, prom_index++, "modetty0" ); |
1120 | prom_set(prom_buf, prom_index++, "38400n8r" ); |
1121 | prom_set(prom_buf, prom_index++, NULL); |
1122 | |
1123 | rom_add_blob_fixed("prom" , prom_buf, prom_size, |
1124 | cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); |
1125 | |
1126 | g_free(prom_buf); |
1127 | return kernel_entry; |
1128 | } |
1129 | |
1130 | static void malta_mips_config(MIPSCPU *cpu) |
1131 | { |
1132 | MachineState *ms = MACHINE(qdev_get_machine()); |
1133 | unsigned int smp_cpus = ms->smp.cpus; |
1134 | CPUMIPSState *env = &cpu->env; |
1135 | CPUState *cs = CPU(cpu); |
1136 | |
1137 | env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | |
1138 | ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); |
1139 | } |
1140 | |
1141 | static void main_cpu_reset(void *opaque) |
1142 | { |
1143 | MIPSCPU *cpu = opaque; |
1144 | CPUMIPSState *env = &cpu->env; |
1145 | |
1146 | cpu_reset(CPU(cpu)); |
1147 | |
1148 | /* |
1149 | * The bootloader does not need to be rewritten as it is located in a |
1150 | * read only location. The kernel location and the arguments table |
1151 | * location does not change. |
1152 | */ |
1153 | if (loaderparams.kernel_filename) { |
1154 | env->CP0_Status &= ~(1 << CP0St_ERL); |
1155 | } |
1156 | |
1157 | malta_mips_config(cpu); |
1158 | |
1159 | if (kvm_enabled()) { |
1160 | /* Start running from the bootloader we wrote to end of RAM */ |
1161 | env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; |
1162 | } |
1163 | } |
1164 | |
1165 | static void create_cpu_without_cps(MachineState *ms, |
1166 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
1167 | { |
1168 | CPUMIPSState *env; |
1169 | MIPSCPU *cpu; |
1170 | int i; |
1171 | |
1172 | for (i = 0; i < ms->smp.cpus; i++) { |
1173 | cpu = MIPS_CPU(cpu_create(ms->cpu_type)); |
1174 | |
1175 | /* Init internal devices */ |
1176 | cpu_mips_irq_init_cpu(cpu); |
1177 | cpu_mips_clock_init(cpu); |
1178 | qemu_register_reset(main_cpu_reset, cpu); |
1179 | } |
1180 | |
1181 | cpu = MIPS_CPU(first_cpu); |
1182 | env = &cpu->env; |
1183 | *i8259_irq = env->irq[2]; |
1184 | *cbus_irq = env->irq[4]; |
1185 | } |
1186 | |
1187 | static void create_cps(MachineState *ms, MaltaState *s, |
1188 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
1189 | { |
1190 | Error *err = NULL; |
1191 | |
1192 | sysbus_init_child_obj(OBJECT(s), "cps" , OBJECT(&s->cps), sizeof(s->cps), |
1193 | TYPE_MIPS_CPS); |
1194 | object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type" , &err); |
1195 | object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp" , &err); |
1196 | object_property_set_bool(OBJECT(&s->cps), true, "realized" , &err); |
1197 | if (err != NULL) { |
1198 | error_report("%s" , error_get_pretty(err)); |
1199 | exit(1); |
1200 | } |
1201 | |
1202 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
1203 | |
1204 | *i8259_irq = get_cps_irq(&s->cps, 3); |
1205 | *cbus_irq = NULL; |
1206 | } |
1207 | |
1208 | static void mips_create_cpu(MachineState *ms, MaltaState *s, |
1209 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
1210 | { |
1211 | if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { |
1212 | create_cps(ms, s, cbus_irq, i8259_irq); |
1213 | } else { |
1214 | create_cpu_without_cps(ms, cbus_irq, i8259_irq); |
1215 | } |
1216 | } |
1217 | |
1218 | static |
1219 | void mips_malta_init(MachineState *machine) |
1220 | { |
1221 | ram_addr_t ram_size = machine->ram_size; |
1222 | ram_addr_t ram_low_size; |
1223 | const char *kernel_filename = machine->kernel_filename; |
1224 | const char *kernel_cmdline = machine->kernel_cmdline; |
1225 | const char *initrd_filename = machine->initrd_filename; |
1226 | char *filename; |
1227 | PFlashCFI01 *fl; |
1228 | MemoryRegion *system_memory = get_system_memory(); |
1229 | MemoryRegion *ram_high = g_new(MemoryRegion, 1); |
1230 | MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); |
1231 | MemoryRegion *ram_low_postio; |
1232 | MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); |
1233 | const size_t smbus_eeprom_size = 8 * 256; |
1234 | uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); |
1235 | int64_t kernel_entry, bootloader_run_addr; |
1236 | PCIBus *pci_bus; |
1237 | ISABus *isa_bus; |
1238 | qemu_irq *isa_irq; |
1239 | qemu_irq cbus_irq, i8259_irq; |
1240 | int piix4_devfn; |
1241 | I2CBus *smbus; |
1242 | DriveInfo *dinfo; |
1243 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
1244 | int fl_idx = 0; |
1245 | int be; |
1246 | |
1247 | DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); |
1248 | MaltaState *s = MIPS_MALTA(dev); |
1249 | |
1250 | /* |
1251 | * The whole address space decoded by the GT-64120A doesn't generate |
1252 | * exception when accessing invalid memory. Create an empty slot to |
1253 | * emulate this feature.\ |
1254 | */ |
1255 | empty_slot_init(0, 0x20000000); |
1256 | |
1257 | qdev_init_nofail(dev); |
1258 | |
1259 | /* create CPU */ |
1260 | mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); |
1261 | |
1262 | /* allocate RAM */ |
1263 | if (ram_size > 2 * GiB) { |
1264 | error_report("Too much memory for this machine: %" PRId64 "MB," |
1265 | " maximum 2048MB" , ram_size / MiB); |
1266 | exit(1); |
1267 | } |
1268 | |
1269 | /* register RAM at high address where it is undisturbed by IO */ |
1270 | memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram" , |
1271 | ram_size); |
1272 | memory_region_add_subregion(system_memory, 0x80000000, ram_high); |
1273 | |
1274 | /* alias for pre IO hole access */ |
1275 | memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram" , |
1276 | ram_high, 0, MIN(ram_size, 256 * MiB)); |
1277 | memory_region_add_subregion(system_memory, 0, ram_low_preio); |
1278 | |
1279 | /* alias for post IO hole access, if there is enough RAM */ |
1280 | if (ram_size > 512 * MiB) { |
1281 | ram_low_postio = g_new(MemoryRegion, 1); |
1282 | memory_region_init_alias(ram_low_postio, NULL, |
1283 | "mips_malta_low_postio.ram" , |
1284 | ram_high, 512 * MiB, |
1285 | ram_size - 512 * MiB); |
1286 | memory_region_add_subregion(system_memory, 512 * MiB, |
1287 | ram_low_postio); |
1288 | } |
1289 | |
1290 | #ifdef TARGET_WORDS_BIGENDIAN |
1291 | be = 1; |
1292 | #else |
1293 | be = 0; |
1294 | #endif |
1295 | |
1296 | /* FPGA */ |
1297 | |
1298 | /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ |
1299 | malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); |
1300 | |
1301 | /* Load firmware in flash / BIOS. */ |
1302 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
1303 | fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios" , |
1304 | FLASH_SIZE, |
1305 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
1306 | 65536, |
1307 | 4, 0x0000, 0x0000, 0x0000, 0x0000, be); |
1308 | bios = pflash_cfi01_get_memory(fl); |
1309 | fl_idx++; |
1310 | if (kernel_filename) { |
1311 | ram_low_size = MIN(ram_size, 256 * MiB); |
1312 | /* For KVM we reserve 1MB of RAM for running bootloader */ |
1313 | if (kvm_enabled()) { |
1314 | ram_low_size -= 0x100000; |
1315 | bootloader_run_addr = 0x40000000 + ram_low_size; |
1316 | } else { |
1317 | bootloader_run_addr = 0xbfc00000; |
1318 | } |
1319 | |
1320 | /* Write a small bootloader to the flash location. */ |
1321 | loaderparams.ram_size = ram_size; |
1322 | loaderparams.ram_low_size = ram_low_size; |
1323 | loaderparams.kernel_filename = kernel_filename; |
1324 | loaderparams.kernel_cmdline = kernel_cmdline; |
1325 | loaderparams.initrd_filename = initrd_filename; |
1326 | kernel_entry = load_kernel(); |
1327 | |
1328 | if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { |
1329 | write_bootloader(memory_region_get_ram_ptr(bios), |
1330 | bootloader_run_addr, kernel_entry); |
1331 | } else { |
1332 | write_bootloader_nanomips(memory_region_get_ram_ptr(bios), |
1333 | bootloader_run_addr, kernel_entry); |
1334 | } |
1335 | if (kvm_enabled()) { |
1336 | /* Write the bootloader code @ the end of RAM, 1MB reserved */ |
1337 | write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + |
1338 | ram_low_size, |
1339 | bootloader_run_addr, kernel_entry); |
1340 | } |
1341 | } else { |
1342 | target_long bios_size = FLASH_SIZE; |
1343 | /* The flash region isn't executable from a KVM guest */ |
1344 | if (kvm_enabled()) { |
1345 | error_report("KVM enabled but no -kernel argument was specified. " |
1346 | "Booting from flash is not supported with KVM." ); |
1347 | exit(1); |
1348 | } |
1349 | /* Load firmware from flash. */ |
1350 | if (!dinfo) { |
1351 | /* Load a BIOS image. */ |
1352 | if (bios_name == NULL) { |
1353 | bios_name = BIOS_FILENAME; |
1354 | } |
1355 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1356 | if (filename) { |
1357 | bios_size = load_image_targphys(filename, FLASH_ADDRESS, |
1358 | BIOS_SIZE); |
1359 | g_free(filename); |
1360 | } else { |
1361 | bios_size = -1; |
1362 | } |
1363 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && |
1364 | !kernel_filename && !qtest_enabled()) { |
1365 | error_report("Could not load MIPS bios '%s', and no " |
1366 | "-kernel argument was specified" , bios_name); |
1367 | exit(1); |
1368 | } |
1369 | } |
1370 | /* |
1371 | * In little endian mode the 32bit words in the bios are swapped, |
1372 | * a neat trick which allows bi-endian firmware. |
1373 | */ |
1374 | #ifndef TARGET_WORDS_BIGENDIAN |
1375 | { |
1376 | uint32_t *end, *addr; |
1377 | const size_t swapsize = MIN(bios_size, 0x3e0000); |
1378 | addr = rom_ptr(FLASH_ADDRESS, swapsize); |
1379 | if (!addr) { |
1380 | addr = memory_region_get_ram_ptr(bios); |
1381 | } |
1382 | end = (void *)addr + swapsize; |
1383 | while (addr < end) { |
1384 | bswap32s(addr); |
1385 | addr++; |
1386 | } |
1387 | } |
1388 | #endif |
1389 | } |
1390 | |
1391 | /* |
1392 | * Map the BIOS at a 2nd physical location, as on the real board. |
1393 | * Copy it so that we can patch in the MIPS revision, which cannot be |
1394 | * handled by an overlapping region as the resulting ROM code subpage |
1395 | * regions are not executable. |
1396 | */ |
1397 | memory_region_init_ram(bios_copy, NULL, "bios.1fc" , BIOS_SIZE, |
1398 | &error_fatal); |
1399 | if (!rom_copy(memory_region_get_ram_ptr(bios_copy), |
1400 | FLASH_ADDRESS, BIOS_SIZE)) { |
1401 | memcpy(memory_region_get_ram_ptr(bios_copy), |
1402 | memory_region_get_ram_ptr(bios), BIOS_SIZE); |
1403 | } |
1404 | memory_region_set_readonly(bios_copy, true); |
1405 | memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); |
1406 | |
1407 | /* Board ID = 0x420 (Malta Board with CoreLV) */ |
1408 | stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); |
1409 | |
1410 | /* |
1411 | * We have a circular dependency problem: pci_bus depends on isa_irq, |
1412 | * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends |
1413 | * on piix4, and piix4 depends on pci_bus. To stop the cycle we have |
1414 | * qemu_irq_proxy() adds an extra bit of indirection, allowing us |
1415 | * to resolve the isa_irq -> i8259 dependency after i8259 is initialized. |
1416 | */ |
1417 | isa_irq = qemu_irq_proxy(&s->i8259, 16); |
1418 | |
1419 | /* Northbridge */ |
1420 | pci_bus = gt64120_register(isa_irq); |
1421 | |
1422 | /* Southbridge */ |
1423 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
1424 | |
1425 | piix4_devfn = piix4_init(pci_bus, &isa_bus, 80); |
1426 | |
1427 | /* |
1428 | * Interrupt controller |
1429 | * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 |
1430 | */ |
1431 | s->i8259 = i8259_init(isa_bus, i8259_irq); |
1432 | |
1433 | isa_bus_irqs(isa_bus, s->i8259); |
1434 | pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); |
1435 | pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci" ); |
1436 | smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, |
1437 | isa_get_irq(NULL, 9), NULL, 0, NULL); |
1438 | pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); |
1439 | i8257_dma_init(isa_bus, 0); |
1440 | mc146818_rtc_init(isa_bus, 2000, NULL); |
1441 | |
1442 | /* generate SPD EEPROM data */ |
1443 | generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); |
1444 | generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); |
1445 | smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); |
1446 | g_free(smbus_eeprom_buf); |
1447 | |
1448 | /* Super I/O: SMS FDC37M817 */ |
1449 | isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); |
1450 | |
1451 | /* Network card */ |
1452 | network_init(pci_bus); |
1453 | |
1454 | /* Optional PCI video card */ |
1455 | pci_vga_init(pci_bus); |
1456 | } |
1457 | |
1458 | static const TypeInfo mips_malta_device = { |
1459 | .name = TYPE_MIPS_MALTA, |
1460 | .parent = TYPE_SYS_BUS_DEVICE, |
1461 | .instance_size = sizeof(MaltaState), |
1462 | }; |
1463 | |
1464 | static void mips_malta_machine_init(MachineClass *mc) |
1465 | { |
1466 | mc->desc = "MIPS Malta Core LV" ; |
1467 | mc->init = mips_malta_init; |
1468 | mc->block_default_type = IF_IDE; |
1469 | mc->max_cpus = 16; |
1470 | mc->is_default = 1; |
1471 | #ifdef TARGET_MIPS64 |
1472 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc" ); |
1473 | #else |
1474 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf" ); |
1475 | #endif |
1476 | } |
1477 | |
1478 | DEFINE_MACHINE("malta" , mips_malta_machine_init) |
1479 | |
1480 | static void mips_malta_register_types(void) |
1481 | { |
1482 | type_register_static(&mips_malta_device); |
1483 | } |
1484 | |
1485 | type_init(mips_malta_register_types) |
1486 | |