1 | /* |
2 | * QEMU PowerPC 440 Bamboo board emulation |
3 | * |
4 | * Copyright 2007 IBM Corporation. |
5 | * Authors: |
6 | * Jerone Young <jyoung5@us.ibm.com> |
7 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> |
8 | * Hollis Blanchard <hollisb@us.ibm.com> |
9 | * |
10 | * This work is licensed under the GNU GPL license version 2 or later. |
11 | * |
12 | */ |
13 | |
14 | #include "qemu/osdep.h" |
15 | #include "qemu/units.h" |
16 | #include "qemu/error-report.h" |
17 | #include "qemu-common.h" |
18 | #include "qemu/error-report.h" |
19 | #include "net/net.h" |
20 | #include "hw/pci/pci.h" |
21 | #include "hw/boards.h" |
22 | #include "sysemu/kvm.h" |
23 | #include "kvm_ppc.h" |
24 | #include "sysemu/device_tree.h" |
25 | #include "hw/loader.h" |
26 | #include "elf.h" |
27 | #include "exec/address-spaces.h" |
28 | #include "hw/char/serial.h" |
29 | #include "hw/ppc/ppc.h" |
30 | #include "ppc405.h" |
31 | #include "sysemu/sysemu.h" |
32 | #include "sysemu/qtest.h" |
33 | #include "sysemu/reset.h" |
34 | #include "hw/sysbus.h" |
35 | |
36 | #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" |
37 | |
38 | /* from u-boot */ |
39 | #define KERNEL_ADDR 0x1000000 |
40 | #define FDT_ADDR 0x1800000 |
41 | #define RAMDISK_ADDR 0x1900000 |
42 | |
43 | #define PPC440EP_PCI_CONFIG 0xeec00000 |
44 | #define PPC440EP_PCI_INTACK 0xeed00000 |
45 | #define PPC440EP_PCI_SPECIAL 0xeed00000 |
46 | #define PPC440EP_PCI_REGS 0xef400000 |
47 | #define PPC440EP_PCI_IO 0xe8000000 |
48 | #define PPC440EP_PCI_IOLEN 0x00010000 |
49 | |
50 | #define PPC440EP_SDRAM_NR_BANKS 4 |
51 | |
52 | static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { |
53 | 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 |
54 | }; |
55 | |
56 | static hwaddr entry; |
57 | |
58 | static int bamboo_load_device_tree(hwaddr addr, |
59 | uint32_t ramsize, |
60 | hwaddr initrd_base, |
61 | hwaddr initrd_size, |
62 | const char *kernel_cmdline) |
63 | { |
64 | int ret = -1; |
65 | uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; |
66 | char *filename; |
67 | int fdt_size; |
68 | void *fdt; |
69 | uint32_t tb_freq = 400000000; |
70 | uint32_t clock_freq = 400000000; |
71 | |
72 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
73 | if (!filename) { |
74 | goto out; |
75 | } |
76 | fdt = load_device_tree(filename, &fdt_size); |
77 | g_free(filename); |
78 | if (fdt == NULL) { |
79 | goto out; |
80 | } |
81 | |
82 | /* Manipulate device tree in memory. */ |
83 | |
84 | ret = qemu_fdt_setprop(fdt, "/memory" , "reg" , mem_reg_property, |
85 | sizeof(mem_reg_property)); |
86 | if (ret < 0) |
87 | fprintf(stderr, "couldn't set /memory/reg\n" ); |
88 | |
89 | ret = qemu_fdt_setprop_cell(fdt, "/chosen" , "linux,initrd-start" , |
90 | initrd_base); |
91 | if (ret < 0) |
92 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n" ); |
93 | |
94 | ret = qemu_fdt_setprop_cell(fdt, "/chosen" , "linux,initrd-end" , |
95 | (initrd_base + initrd_size)); |
96 | if (ret < 0) |
97 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n" ); |
98 | |
99 | ret = qemu_fdt_setprop_string(fdt, "/chosen" , "bootargs" , |
100 | kernel_cmdline); |
101 | if (ret < 0) |
102 | fprintf(stderr, "couldn't set /chosen/bootargs\n" ); |
103 | |
104 | /* Copy data from the host device tree into the guest. Since the guest can |
105 | * directly access the timebase without host involvement, we must expose |
106 | * the correct frequencies. */ |
107 | if (kvm_enabled()) { |
108 | tb_freq = kvmppc_get_tbfreq(); |
109 | clock_freq = kvmppc_get_clockfreq(); |
110 | } |
111 | |
112 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0" , "clock-frequency" , |
113 | clock_freq); |
114 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0" , "timebase-frequency" , |
115 | tb_freq); |
116 | |
117 | rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
118 | g_free(fdt); |
119 | return 0; |
120 | |
121 | out: |
122 | |
123 | return ret; |
124 | } |
125 | |
126 | /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ |
127 | static void mmubooke_create_initial_mapping(CPUPPCState *env, |
128 | target_ulong va, |
129 | hwaddr pa) |
130 | { |
131 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; |
132 | |
133 | tlb->attr = 0; |
134 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); |
135 | tlb->size = 1U << 31; /* up to 0x80000000 */ |
136 | tlb->EPN = va & TARGET_PAGE_MASK; |
137 | tlb->RPN = pa & TARGET_PAGE_MASK; |
138 | tlb->PID = 0; |
139 | |
140 | tlb = &env->tlb.tlbe[1]; |
141 | tlb->attr = 0; |
142 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); |
143 | tlb->size = 1U << 31; /* up to 0xffffffff */ |
144 | tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; |
145 | tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; |
146 | tlb->PID = 0; |
147 | } |
148 | |
149 | static void main_cpu_reset(void *opaque) |
150 | { |
151 | PowerPCCPU *cpu = opaque; |
152 | CPUPPCState *env = &cpu->env; |
153 | |
154 | cpu_reset(CPU(cpu)); |
155 | env->gpr[1] = (16 * MiB) - 8; |
156 | env->gpr[3] = FDT_ADDR; |
157 | env->nip = entry; |
158 | |
159 | /* Create a mapping for the kernel. */ |
160 | mmubooke_create_initial_mapping(env, 0, 0); |
161 | } |
162 | |
163 | static void bamboo_init(MachineState *machine) |
164 | { |
165 | ram_addr_t ram_size = machine->ram_size; |
166 | const char *kernel_filename = machine->kernel_filename; |
167 | const char *kernel_cmdline = machine->kernel_cmdline; |
168 | const char *initrd_filename = machine->initrd_filename; |
169 | unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; |
170 | MemoryRegion *address_space_mem = get_system_memory(); |
171 | MemoryRegion *isa = g_new(MemoryRegion, 1); |
172 | MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); |
173 | hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
174 | hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; |
175 | qemu_irq *pic; |
176 | qemu_irq *irqs; |
177 | PCIBus *pcibus; |
178 | PowerPCCPU *cpu; |
179 | CPUPPCState *env; |
180 | uint64_t elf_entry; |
181 | uint64_t elf_lowaddr; |
182 | hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
183 | target_long initrd_size = 0; |
184 | DeviceState *dev; |
185 | int success; |
186 | int i; |
187 | |
188 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
189 | env = &cpu->env; |
190 | |
191 | if (env->mmu_model != POWERPC_MMU_BOOKE) { |
192 | error_report("MMU model %i not supported by this machine" , |
193 | env->mmu_model); |
194 | exit(1); |
195 | } |
196 | |
197 | qemu_register_reset(main_cpu_reset, cpu); |
198 | ppc_booke_timers_init(cpu, 400000000, 0); |
199 | ppc_dcr_init(env, NULL, NULL); |
200 | |
201 | /* interrupt controller */ |
202 | irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); |
203 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
204 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
205 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
206 | |
207 | /* SDRAM controller */ |
208 | memset(ram_bases, 0, sizeof(ram_bases)); |
209 | memset(ram_sizes, 0, sizeof(ram_sizes)); |
210 | ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, |
211 | ram_memories, |
212 | ram_bases, ram_sizes, |
213 | ppc440ep_sdram_bank_sizes); |
214 | /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ |
215 | ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, |
216 | ram_bases, ram_sizes, 1); |
217 | |
218 | /* PCI */ |
219 | dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, |
220 | PPC440EP_PCI_CONFIG, |
221 | pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], |
222 | pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], |
223 | NULL); |
224 | pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0" ); |
225 | if (!pcibus) { |
226 | error_report("couldn't create PCI controller" ); |
227 | exit(1); |
228 | } |
229 | |
230 | memory_region_init_alias(isa, NULL, "isa_mmio" , |
231 | get_system_io(), 0, PPC440EP_PCI_IOLEN); |
232 | memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); |
233 | |
234 | if (serial_hd(0) != NULL) { |
235 | serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], |
236 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
237 | DEVICE_BIG_ENDIAN); |
238 | } |
239 | if (serial_hd(1) != NULL) { |
240 | serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], |
241 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
242 | DEVICE_BIG_ENDIAN); |
243 | } |
244 | |
245 | if (pcibus) { |
246 | /* Register network interfaces. */ |
247 | for (i = 0; i < nb_nics; i++) { |
248 | /* There are no PCI NICs on the Bamboo board, but there are |
249 | * PCI slots, so we can pick whatever default model we want. */ |
250 | pci_nic_init_nofail(&nd_table[i], pcibus, "e1000" , NULL); |
251 | } |
252 | } |
253 | |
254 | /* Load kernel. */ |
255 | if (kernel_filename) { |
256 | success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, |
257 | NULL, NULL); |
258 | if (success < 0) { |
259 | success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, |
260 | &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, |
261 | 0, 0); |
262 | entry = elf_entry; |
263 | loadaddr = elf_lowaddr; |
264 | } |
265 | /* XXX try again as binary */ |
266 | if (success < 0) { |
267 | error_report("could not load kernel '%s'" , kernel_filename); |
268 | exit(1); |
269 | } |
270 | } |
271 | |
272 | /* Load initrd. */ |
273 | if (initrd_filename) { |
274 | initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, |
275 | ram_size - RAMDISK_ADDR); |
276 | |
277 | if (initrd_size < 0) { |
278 | error_report("could not load ram disk '%s' at %x" , |
279 | initrd_filename, RAMDISK_ADDR); |
280 | exit(1); |
281 | } |
282 | } |
283 | |
284 | /* If we're loading a kernel directly, we must load the device tree too. */ |
285 | if (kernel_filename) { |
286 | if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, |
287 | initrd_size, kernel_cmdline) < 0) { |
288 | error_report("couldn't load device tree" ); |
289 | exit(1); |
290 | } |
291 | } |
292 | } |
293 | |
294 | static void bamboo_machine_init(MachineClass *mc) |
295 | { |
296 | mc->desc = "bamboo" ; |
297 | mc->init = bamboo_init; |
298 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb" ); |
299 | } |
300 | |
301 | DEFINE_MACHINE("bamboo" , bamboo_machine_init) |
302 | |