1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator |
3 | * |
4 | * Copyright (c) 2004-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
9 | * of this software and associated documentation files (the "Software"), to deal |
10 | * in the Software without restriction, including without limitation the rights |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
12 | * copies of the Software, and to permit persons to whom the Software is |
13 | * furnished to do so, subject to the following conditions: |
14 | * |
15 | * The above copyright notice and this permission notice shall be included in |
16 | * all copies or substantial portions of the Software. |
17 | * |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
24 | * THE SOFTWARE. |
25 | */ |
26 | |
27 | #include "qemu/osdep.h" |
28 | #include "qemu-common.h" |
29 | #include "qapi/error.h" |
30 | #include "qapi/visitor.h" |
31 | #include "sysemu/sysemu.h" |
32 | #include "sysemu/hostmem.h" |
33 | #include "sysemu/numa.h" |
34 | #include "sysemu/qtest.h" |
35 | #include "sysemu/reset.h" |
36 | #include "sysemu/runstate.h" |
37 | #include "qemu/log.h" |
38 | #include "hw/fw-path-provider.h" |
39 | #include "elf.h" |
40 | #include "net/net.h" |
41 | #include "sysemu/device_tree.h" |
42 | #include "sysemu/cpus.h" |
43 | #include "sysemu/hw_accel.h" |
44 | #include "kvm_ppc.h" |
45 | #include "migration/misc.h" |
46 | #include "migration/qemu-file-types.h" |
47 | #include "migration/global_state.h" |
48 | #include "migration/register.h" |
49 | #include "mmu-hash64.h" |
50 | #include "mmu-book3s-v3.h" |
51 | #include "cpu-models.h" |
52 | #include "hw/core/cpu.h" |
53 | |
54 | #include "hw/boards.h" |
55 | #include "hw/ppc/ppc.h" |
56 | #include "hw/loader.h" |
57 | |
58 | #include "hw/ppc/fdt.h" |
59 | #include "hw/ppc/spapr.h" |
60 | #include "hw/ppc/spapr_vio.h" |
61 | #include "hw/qdev-properties.h" |
62 | #include "hw/pci-host/spapr.h" |
63 | #include "hw/pci/msi.h" |
64 | |
65 | #include "hw/pci/pci.h" |
66 | #include "hw/scsi/scsi.h" |
67 | #include "hw/virtio/virtio-scsi.h" |
68 | #include "hw/virtio/vhost-scsi-common.h" |
69 | |
70 | #include "exec/address-spaces.h" |
71 | #include "exec/ram_addr.h" |
72 | #include "hw/usb.h" |
73 | #include "qemu/config-file.h" |
74 | #include "qemu/error-report.h" |
75 | #include "trace.h" |
76 | #include "hw/nmi.h" |
77 | #include "hw/intc/intc.h" |
78 | |
79 | #include "qemu/cutils.h" |
80 | #include "hw/ppc/spapr_cpu_core.h" |
81 | #include "hw/mem/memory-device.h" |
82 | #include "hw/ppc/spapr_tpm_proxy.h" |
83 | |
84 | #include <libfdt.h> |
85 | |
86 | /* SLOF memory layout: |
87 | * |
88 | * SLOF raw image loaded at 0, copies its romfs right below the flat |
89 | * device-tree, then position SLOF itself 31M below that |
90 | * |
91 | * So we set FW_OVERHEAD to 40MB which should account for all of that |
92 | * and more |
93 | * |
94 | * We load our kernel at 4M, leaving space for SLOF initial image |
95 | */ |
96 | #define FDT_MAX_SIZE 0x100000 |
97 | #define RTAS_MAX_SIZE 0x10000 |
98 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
99 | #define FW_MAX_SIZE 0x400000 |
100 | #define FW_FILE_NAME "slof.bin" |
101 | #define FW_OVERHEAD 0x2800000 |
102 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE |
103 | |
104 | #define MIN_RMA_SLOF 128UL |
105 | |
106 | #define PHANDLE_INTC 0x00001111 |
107 | |
108 | /* These two functions implement the VCPU id numbering: one to compute them |
109 | * all and one to identify thread 0 of a VCORE. Any change to the first one |
110 | * is likely to have an impact on the second one, so let's keep them close. |
111 | */ |
112 | static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) |
113 | { |
114 | MachineState *ms = MACHINE(spapr); |
115 | unsigned int smp_threads = ms->smp.threads; |
116 | |
117 | assert(spapr->vsmt); |
118 | return |
119 | (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; |
120 | } |
121 | static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, |
122 | PowerPCCPU *cpu) |
123 | { |
124 | assert(spapr->vsmt); |
125 | return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; |
126 | } |
127 | |
128 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
129 | { |
130 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, |
131 | * and newer QEMUs don't even have them. In both cases, we don't want |
132 | * to send anything on the wire. |
133 | */ |
134 | return false; |
135 | } |
136 | |
137 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { |
138 | .name = "icp/server" , |
139 | .version_id = 1, |
140 | .minimum_version_id = 1, |
141 | .needed = pre_2_10_vmstate_dummy_icp_needed, |
142 | .fields = (VMStateField[]) { |
143 | VMSTATE_UNUSED(4), /* uint32_t xirr */ |
144 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ |
145 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ |
146 | VMSTATE_END_OF_LIST() |
147 | }, |
148 | }; |
149 | |
150 | static void pre_2_10_vmstate_register_dummy_icp(int i) |
151 | { |
152 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, |
153 | (void *)(uintptr_t) i); |
154 | } |
155 | |
156 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) |
157 | { |
158 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, |
159 | (void *)(uintptr_t) i); |
160 | } |
161 | |
162 | int spapr_max_server_number(SpaprMachineState *spapr) |
163 | { |
164 | MachineState *ms = MACHINE(spapr); |
165 | |
166 | assert(spapr->vsmt); |
167 | return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); |
168 | } |
169 | |
170 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
171 | int smt_threads) |
172 | { |
173 | int i, ret = 0; |
174 | uint32_t servers_prop[smt_threads]; |
175 | uint32_t gservers_prop[smt_threads * 2]; |
176 | int index = spapr_get_vcpu_id(cpu); |
177 | |
178 | if (cpu->compat_pvr) { |
179 | ret = fdt_setprop_cell(fdt, offset, "cpu-version" , cpu->compat_pvr); |
180 | if (ret < 0) { |
181 | return ret; |
182 | } |
183 | } |
184 | |
185 | /* Build interrupt servers and gservers properties */ |
186 | for (i = 0; i < smt_threads; i++) { |
187 | servers_prop[i] = cpu_to_be32(index + i); |
188 | /* Hack, direct the group queues back to cpu 0 */ |
189 | gservers_prop[i*2] = cpu_to_be32(index + i); |
190 | gservers_prop[i*2 + 1] = 0; |
191 | } |
192 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s" , |
193 | servers_prop, sizeof(servers_prop)); |
194 | if (ret < 0) { |
195 | return ret; |
196 | } |
197 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s" , |
198 | gservers_prop, sizeof(gservers_prop)); |
199 | |
200 | return ret; |
201 | } |
202 | |
203 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
204 | { |
205 | int index = spapr_get_vcpu_id(cpu); |
206 | uint32_t associativity[] = {cpu_to_be32(0x5), |
207 | cpu_to_be32(0x0), |
208 | cpu_to_be32(0x0), |
209 | cpu_to_be32(0x0), |
210 | cpu_to_be32(cpu->node_id), |
211 | cpu_to_be32(index)}; |
212 | |
213 | /* Advertise NUMA via ibm,associativity */ |
214 | return fdt_setprop(fdt, offset, "ibm,associativity" , associativity, |
215 | sizeof(associativity)); |
216 | } |
217 | |
218 | /* Populate the "ibm,pa-features" property */ |
219 | static void spapr_populate_pa_features(SpaprMachineState *spapr, |
220 | PowerPCCPU *cpu, |
221 | void *fdt, int offset, |
222 | bool legacy_guest) |
223 | { |
224 | uint8_t pa_features_206[] = { 6, 0, |
225 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; |
226 | uint8_t pa_features_207[] = { 24, 0, |
227 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, |
228 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, |
229 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, |
230 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; |
231 | uint8_t pa_features_300[] = { 66, 0, |
232 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ |
233 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ |
234 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ |
235 | /* 6: DS207 */ |
236 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ |
237 | /* 16: Vector */ |
238 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
239 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
240 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
241 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
242 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ |
243 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ |
244 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ |
245 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ |
246 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ |
247 | /* 42: PM, 44: PC RA, 46: SC vec'd */ |
248 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ |
249 | /* 48: SIMD, 50: QP BFP, 52: String */ |
250 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ |
251 | /* 54: DecFP, 56: DecI, 58: SHA */ |
252 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ |
253 | /* 60: NM atomic, 62: RNG */ |
254 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ |
255 | }; |
256 | uint8_t *pa_features = NULL; |
257 | size_t pa_size; |
258 | |
259 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
260 | pa_features = pa_features_206; |
261 | pa_size = sizeof(pa_features_206); |
262 | } |
263 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { |
264 | pa_features = pa_features_207; |
265 | pa_size = sizeof(pa_features_207); |
266 | } |
267 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { |
268 | pa_features = pa_features_300; |
269 | pa_size = sizeof(pa_features_300); |
270 | } |
271 | if (!pa_features) { |
272 | return; |
273 | } |
274 | |
275 | if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { |
276 | /* |
277 | * Note: we keep CI large pages off by default because a 64K capable |
278 | * guest provisioned with large pages might otherwise try to map a qemu |
279 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages |
280 | * even if that qemu runs on a 4k host. |
281 | * We dd this bit back here if we are confident this is not an issue |
282 | */ |
283 | pa_features[3] |= 0x20; |
284 | } |
285 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
286 | pa_features[24] |= 0x80; /* Transactional memory support */ |
287 | } |
288 | if (legacy_guest && pa_size > 40) { |
289 | /* Workaround for broken kernels that attempt (guest) radix |
290 | * mode when they can't handle it, if they see the radix bit set |
291 | * in pa-features. So hide it from them. */ |
292 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ |
293 | } |
294 | |
295 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features" , pa_features, pa_size))); |
296 | } |
297 | |
298 | static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr) |
299 | { |
300 | MachineState *ms = MACHINE(spapr); |
301 | int ret = 0, offset, cpus_offset; |
302 | CPUState *cs; |
303 | char cpu_model[32]; |
304 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
305 | |
306 | CPU_FOREACH(cs) { |
307 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
308 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
309 | int index = spapr_get_vcpu_id(cpu); |
310 | int compat_smt = MIN(ms->smp.threads, ppc_compat_max_vthreads(cpu)); |
311 | |
312 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
313 | continue; |
314 | } |
315 | |
316 | snprintf(cpu_model, 32, "%s@%x" , dc->fw_name, index); |
317 | |
318 | cpus_offset = fdt_path_offset(fdt, "/cpus" ); |
319 | if (cpus_offset < 0) { |
320 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus" ); |
321 | if (cpus_offset < 0) { |
322 | return cpus_offset; |
323 | } |
324 | } |
325 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); |
326 | if (offset < 0) { |
327 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
328 | if (offset < 0) { |
329 | return offset; |
330 | } |
331 | } |
332 | |
333 | ret = fdt_setprop(fdt, offset, "ibm,pft-size" , |
334 | pft_size_prop, sizeof(pft_size_prop)); |
335 | if (ret < 0) { |
336 | return ret; |
337 | } |
338 | |
339 | if (ms->numa_state->num_nodes > 1) { |
340 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); |
341 | if (ret < 0) { |
342 | return ret; |
343 | } |
344 | } |
345 | |
346 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
347 | if (ret < 0) { |
348 | return ret; |
349 | } |
350 | |
351 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
352 | spapr->cas_legacy_guest_workaround); |
353 | } |
354 | return ret; |
355 | } |
356 | |
357 | static hwaddr spapr_node0_size(MachineState *machine) |
358 | { |
359 | if (machine->numa_state->num_nodes) { |
360 | int i; |
361 | for (i = 0; i < machine->numa_state->num_nodes; ++i) { |
362 | if (machine->numa_state->nodes[i].node_mem) { |
363 | return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), |
364 | machine->ram_size); |
365 | } |
366 | } |
367 | } |
368 | return machine->ram_size; |
369 | } |
370 | |
371 | static void add_str(GString *s, const gchar *s1) |
372 | { |
373 | g_string_append_len(s, s1, strlen(s1) + 1); |
374 | } |
375 | |
376 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
377 | hwaddr size) |
378 | { |
379 | uint32_t associativity[] = { |
380 | cpu_to_be32(0x4), /* length */ |
381 | cpu_to_be32(0x0), cpu_to_be32(0x0), |
382 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
383 | }; |
384 | char mem_name[32]; |
385 | uint64_t mem_reg_property[2]; |
386 | int off; |
387 | |
388 | mem_reg_property[0] = cpu_to_be64(start); |
389 | mem_reg_property[1] = cpu_to_be64(size); |
390 | |
391 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); |
392 | off = fdt_add_subnode(fdt, 0, mem_name); |
393 | _FDT(off); |
394 | _FDT((fdt_setprop_string(fdt, off, "device_type" , "memory" ))); |
395 | _FDT((fdt_setprop(fdt, off, "reg" , mem_reg_property, |
396 | sizeof(mem_reg_property)))); |
397 | _FDT((fdt_setprop(fdt, off, "ibm,associativity" , associativity, |
398 | sizeof(associativity)))); |
399 | return off; |
400 | } |
401 | |
402 | static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) |
403 | { |
404 | MachineState *machine = MACHINE(spapr); |
405 | hwaddr mem_start, node_size; |
406 | int i, nb_nodes = machine->numa_state->num_nodes; |
407 | NodeInfo *nodes = machine->numa_state->nodes; |
408 | NodeInfo ramnode; |
409 | |
410 | /* No NUMA nodes, assume there is just one node with whole RAM */ |
411 | if (!nb_nodes) { |
412 | nb_nodes = 1; |
413 | ramnode.node_mem = machine->ram_size; |
414 | nodes = &ramnode; |
415 | } |
416 | |
417 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
418 | if (!nodes[i].node_mem) { |
419 | continue; |
420 | } |
421 | if (mem_start >= machine->ram_size) { |
422 | node_size = 0; |
423 | } else { |
424 | node_size = nodes[i].node_mem; |
425 | if (node_size > machine->ram_size - mem_start) { |
426 | node_size = machine->ram_size - mem_start; |
427 | } |
428 | } |
429 | if (!mem_start) { |
430 | /* spapr_machine_init() checks for rma_size <= node0_size |
431 | * already */ |
432 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
433 | mem_start += spapr->rma_size; |
434 | node_size -= spapr->rma_size; |
435 | } |
436 | for ( ; node_size; ) { |
437 | hwaddr sizetmp = pow2floor(node_size); |
438 | |
439 | /* mem_start != 0 here */ |
440 | if (ctzl(mem_start) < ctzl(sizetmp)) { |
441 | sizetmp = 1ULL << ctzl(mem_start); |
442 | } |
443 | |
444 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); |
445 | node_size -= sizetmp; |
446 | mem_start += sizetmp; |
447 | } |
448 | } |
449 | |
450 | return 0; |
451 | } |
452 | |
453 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
454 | SpaprMachineState *spapr) |
455 | { |
456 | MachineState *ms = MACHINE(spapr); |
457 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
458 | CPUPPCState *env = &cpu->env; |
459 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); |
460 | int index = spapr_get_vcpu_id(cpu); |
461 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
462 | 0xffffffff, 0xffffffff}; |
463 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
464 | : SPAPR_TIMEBASE_FREQ; |
465 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
466 | uint32_t page_sizes_prop[64]; |
467 | size_t page_sizes_prop_size; |
468 | unsigned int smp_threads = ms->smp.threads; |
469 | uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; |
470 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
471 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
472 | SpaprDrc *drc; |
473 | int drc_index; |
474 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
475 | int i; |
476 | |
477 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
478 | if (drc) { |
479 | drc_index = spapr_drc_index(drc); |
480 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index" , drc_index))); |
481 | } |
482 | |
483 | _FDT((fdt_setprop_cell(fdt, offset, "reg" , index))); |
484 | _FDT((fdt_setprop_string(fdt, offset, "device_type" , "cpu" ))); |
485 | |
486 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version" , env->spr[SPR_PVR]))); |
487 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size" , |
488 | env->dcache_line_size))); |
489 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size" , |
490 | env->dcache_line_size))); |
491 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size" , |
492 | env->icache_line_size))); |
493 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size" , |
494 | env->icache_line_size))); |
495 | |
496 | if (pcc->l1_dcache_size) { |
497 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size" , |
498 | pcc->l1_dcache_size))); |
499 | } else { |
500 | warn_report("Unknown L1 dcache size for cpu" ); |
501 | } |
502 | if (pcc->l1_icache_size) { |
503 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size" , |
504 | pcc->l1_icache_size))); |
505 | } else { |
506 | warn_report("Unknown L1 icache size for cpu" ); |
507 | } |
508 | |
509 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency" , tbfreq))); |
510 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency" , cpufreq))); |
511 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size" , cpu->hash64_opts->slb_size))); |
512 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size" , cpu->hash64_opts->slb_size))); |
513 | _FDT((fdt_setprop_string(fdt, offset, "status" , "okay" ))); |
514 | _FDT((fdt_setprop(fdt, offset, "64-bit" , NULL, 0))); |
515 | |
516 | if (env->spr_cb[SPR_PURR].oea_read) { |
517 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr" , 1))); |
518 | } |
519 | if (env->spr_cb[SPR_SPURR].oea_read) { |
520 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr" , 1))); |
521 | } |
522 | |
523 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
524 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes" , |
525 | segs, sizeof(segs)))); |
526 | } |
527 | |
528 | /* Advertise VSX (vector extensions) if available |
529 | * 1 == VMX / Altivec available |
530 | * 2 == VSX available |
531 | * |
532 | * Only CPUs for which we create core types in spapr_cpu_core.c |
533 | * are possible, and all of those have VMX */ |
534 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { |
535 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx" , 2))); |
536 | } else { |
537 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx" , 1))); |
538 | } |
539 | |
540 | /* Advertise DFP (Decimal Floating Point) if available |
541 | * 0 / no property == no DFP |
542 | * 1 == DFP available */ |
543 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { |
544 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp" , 1))); |
545 | } |
546 | |
547 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
548 | sizeof(page_sizes_prop)); |
549 | if (page_sizes_prop_size) { |
550 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes" , |
551 | page_sizes_prop, page_sizes_prop_size))); |
552 | } |
553 | |
554 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
555 | |
556 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id" , |
557 | cs->cpu_index / vcpus_per_socket))); |
558 | |
559 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size" , |
560 | pft_size_prop, sizeof(pft_size_prop)))); |
561 | |
562 | if (ms->numa_state->num_nodes > 1) { |
563 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); |
564 | } |
565 | |
566 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
567 | |
568 | if (pcc->radix_page_info) { |
569 | for (i = 0; i < pcc->radix_page_info->count; i++) { |
570 | radix_AP_encodings[i] = |
571 | cpu_to_be32(pcc->radix_page_info->entries[i]); |
572 | } |
573 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings" , |
574 | radix_AP_encodings, |
575 | pcc->radix_page_info->count * |
576 | sizeof(radix_AP_encodings[0])))); |
577 | } |
578 | |
579 | /* |
580 | * We set this property to let the guest know that it can use the large |
581 | * decrementer and its width in bits. |
582 | */ |
583 | if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) |
584 | _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits" , |
585 | pcc->lrg_decr_bits))); |
586 | } |
587 | |
588 | static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) |
589 | { |
590 | CPUState **rev; |
591 | CPUState *cs; |
592 | int n_cpus; |
593 | int cpus_offset; |
594 | char *nodename; |
595 | int i; |
596 | |
597 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus" ); |
598 | _FDT(cpus_offset); |
599 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells" , 0x1))); |
600 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells" , 0x0))); |
601 | |
602 | /* |
603 | * We walk the CPUs in reverse order to ensure that CPU DT nodes |
604 | * created by fdt_add_subnode() end up in the right order in FDT |
605 | * for the guest kernel the enumerate the CPUs correctly. |
606 | * |
607 | * The CPU list cannot be traversed in reverse order, so we need |
608 | * to do extra work. |
609 | */ |
610 | n_cpus = 0; |
611 | rev = NULL; |
612 | CPU_FOREACH(cs) { |
613 | rev = g_renew(CPUState *, rev, n_cpus + 1); |
614 | rev[n_cpus++] = cs; |
615 | } |
616 | |
617 | for (i = n_cpus - 1; i >= 0; i--) { |
618 | CPUState *cs = rev[i]; |
619 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
620 | int index = spapr_get_vcpu_id(cpu); |
621 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
622 | int offset; |
623 | |
624 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
625 | continue; |
626 | } |
627 | |
628 | nodename = g_strdup_printf("%s@%x" , dc->fw_name, index); |
629 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); |
630 | g_free(nodename); |
631 | _FDT(offset); |
632 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); |
633 | } |
634 | |
635 | g_free(rev); |
636 | } |
637 | |
638 | static int spapr_rng_populate_dt(void *fdt) |
639 | { |
640 | int node; |
641 | int ret; |
642 | |
643 | node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities" ); |
644 | if (node <= 0) { |
645 | return -1; |
646 | } |
647 | ret = fdt_setprop_string(fdt, node, "device_type" , |
648 | "ibm,platform-facilities" ); |
649 | ret |= fdt_setprop_cell(fdt, node, "#address-cells" , 0x1); |
650 | ret |= fdt_setprop_cell(fdt, node, "#size-cells" , 0x0); |
651 | |
652 | node = fdt_add_subnode(fdt, node, "ibm,random-v1" ); |
653 | if (node <= 0) { |
654 | return -1; |
655 | } |
656 | ret |= fdt_setprop_string(fdt, node, "compatible" , "ibm,random" ); |
657 | |
658 | return ret ? -1 : 0; |
659 | } |
660 | |
661 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
662 | { |
663 | MemoryDeviceInfoList *info; |
664 | |
665 | for (info = list; info; info = info->next) { |
666 | MemoryDeviceInfo *value = info->value; |
667 | |
668 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { |
669 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; |
670 | |
671 | if (addr >= pcdimm_info->addr && |
672 | addr < (pcdimm_info->addr + pcdimm_info->size)) { |
673 | return pcdimm_info->node; |
674 | } |
675 | } |
676 | } |
677 | |
678 | return -1; |
679 | } |
680 | |
681 | struct sPAPRDrconfCellV2 { |
682 | uint32_t seq_lmbs; |
683 | uint64_t base_addr; |
684 | uint32_t drc_index; |
685 | uint32_t aa_index; |
686 | uint32_t flags; |
687 | } QEMU_PACKED; |
688 | |
689 | typedef struct DrconfCellQueue { |
690 | struct sPAPRDrconfCellV2 cell; |
691 | QSIMPLEQ_ENTRY(DrconfCellQueue) entry; |
692 | } DrconfCellQueue; |
693 | |
694 | static DrconfCellQueue * |
695 | spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, |
696 | uint32_t drc_index, uint32_t aa_index, |
697 | uint32_t flags) |
698 | { |
699 | DrconfCellQueue *elem; |
700 | |
701 | elem = g_malloc0(sizeof(*elem)); |
702 | elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); |
703 | elem->cell.base_addr = cpu_to_be64(base_addr); |
704 | elem->cell.drc_index = cpu_to_be32(drc_index); |
705 | elem->cell.aa_index = cpu_to_be32(aa_index); |
706 | elem->cell.flags = cpu_to_be32(flags); |
707 | |
708 | return elem; |
709 | } |
710 | |
711 | /* ibm,dynamic-memory-v2 */ |
712 | static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, |
713 | int offset, MemoryDeviceInfoList *dimms) |
714 | { |
715 | MachineState *machine = MACHINE(spapr); |
716 | uint8_t *int_buf, *cur_index; |
717 | int ret; |
718 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
719 | uint64_t addr, cur_addr, size; |
720 | uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); |
721 | uint64_t mem_end = machine->device_memory->base + |
722 | memory_region_size(&machine->device_memory->mr); |
723 | uint32_t node, buf_len, nr_entries = 0; |
724 | SpaprDrc *drc; |
725 | DrconfCellQueue *elem, *next; |
726 | MemoryDeviceInfoList *info; |
727 | QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue |
728 | = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); |
729 | |
730 | /* Entry to cover RAM and the gap area */ |
731 | elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, |
732 | SPAPR_LMB_FLAGS_RESERVED | |
733 | SPAPR_LMB_FLAGS_DRC_INVALID); |
734 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); |
735 | nr_entries++; |
736 | |
737 | cur_addr = machine->device_memory->base; |
738 | for (info = dimms; info; info = info->next) { |
739 | PCDIMMDeviceInfo *di = info->value->u.dimm.data; |
740 | |
741 | addr = di->addr; |
742 | size = di->size; |
743 | node = di->node; |
744 | |
745 | /* Entry for hot-pluggable area */ |
746 | if (cur_addr < addr) { |
747 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); |
748 | g_assert(drc); |
749 | elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, |
750 | cur_addr, spapr_drc_index(drc), -1, 0); |
751 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); |
752 | nr_entries++; |
753 | } |
754 | |
755 | /* Entry for DIMM */ |
756 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); |
757 | g_assert(drc); |
758 | elem = spapr_get_drconf_cell(size / lmb_size, addr, |
759 | spapr_drc_index(drc), node, |
760 | SPAPR_LMB_FLAGS_ASSIGNED); |
761 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); |
762 | nr_entries++; |
763 | cur_addr = addr + size; |
764 | } |
765 | |
766 | /* Entry for remaining hotpluggable area */ |
767 | if (cur_addr < mem_end) { |
768 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); |
769 | g_assert(drc); |
770 | elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, |
771 | cur_addr, spapr_drc_index(drc), -1, 0); |
772 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); |
773 | nr_entries++; |
774 | } |
775 | |
776 | buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); |
777 | int_buf = cur_index = g_malloc0(buf_len); |
778 | *(uint32_t *)int_buf = cpu_to_be32(nr_entries); |
779 | cur_index += sizeof(nr_entries); |
780 | |
781 | QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { |
782 | memcpy(cur_index, &elem->cell, sizeof(elem->cell)); |
783 | cur_index += sizeof(elem->cell); |
784 | QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); |
785 | g_free(elem); |
786 | } |
787 | |
788 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2" , int_buf, buf_len); |
789 | g_free(int_buf); |
790 | if (ret < 0) { |
791 | return -1; |
792 | } |
793 | return 0; |
794 | } |
795 | |
796 | /* ibm,dynamic-memory */ |
797 | static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, |
798 | int offset, MemoryDeviceInfoList *dimms) |
799 | { |
800 | MachineState *machine = MACHINE(spapr); |
801 | int i, ret; |
802 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
803 | uint32_t device_lmb_start = machine->device_memory->base / lmb_size; |
804 | uint32_t nr_lmbs = (machine->device_memory->base + |
805 | memory_region_size(&machine->device_memory->mr)) / |
806 | lmb_size; |
807 | uint32_t *int_buf, *cur_index, buf_len; |
808 | |
809 | /* |
810 | * Allocate enough buffer size to fit in ibm,dynamic-memory |
811 | */ |
812 | buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); |
813 | cur_index = int_buf = g_malloc0(buf_len); |
814 | int_buf[0] = cpu_to_be32(nr_lmbs); |
815 | cur_index++; |
816 | for (i = 0; i < nr_lmbs; i++) { |
817 | uint64_t addr = i * lmb_size; |
818 | uint32_t *dynamic_memory = cur_index; |
819 | |
820 | if (i >= device_lmb_start) { |
821 | SpaprDrc *drc; |
822 | |
823 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
824 | g_assert(drc); |
825 | |
826 | dynamic_memory[0] = cpu_to_be32(addr >> 32); |
827 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); |
828 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
829 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
830 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
831 | if (memory_region_present(get_system_memory(), addr)) { |
832 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); |
833 | } else { |
834 | dynamic_memory[5] = cpu_to_be32(0); |
835 | } |
836 | } else { |
837 | /* |
838 | * LMB information for RMA, boot time RAM and gap b/n RAM and |
839 | * device memory region -- all these are marked as reserved |
840 | * and as having no valid DRC. |
841 | */ |
842 | dynamic_memory[0] = cpu_to_be32(addr >> 32); |
843 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); |
844 | dynamic_memory[2] = cpu_to_be32(0); |
845 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
846 | dynamic_memory[4] = cpu_to_be32(-1); |
847 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | |
848 | SPAPR_LMB_FLAGS_DRC_INVALID); |
849 | } |
850 | |
851 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; |
852 | } |
853 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory" , int_buf, buf_len); |
854 | g_free(int_buf); |
855 | if (ret < 0) { |
856 | return -1; |
857 | } |
858 | return 0; |
859 | } |
860 | |
861 | /* |
862 | * Adds ibm,dynamic-reconfiguration-memory node. |
863 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation |
864 | * of this device tree node. |
865 | */ |
866 | static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) |
867 | { |
868 | MachineState *machine = MACHINE(spapr); |
869 | int nb_numa_nodes = machine->numa_state->num_nodes; |
870 | int ret, i, offset; |
871 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
872 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; |
873 | uint32_t *int_buf, *cur_index, buf_len; |
874 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
875 | MemoryDeviceInfoList *dimms = NULL; |
876 | |
877 | /* |
878 | * Don't create the node if there is no device memory |
879 | */ |
880 | if (machine->ram_size == machine->maxram_size) { |
881 | return 0; |
882 | } |
883 | |
884 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory" ); |
885 | |
886 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size" , prop_lmb_size, |
887 | sizeof(prop_lmb_size)); |
888 | if (ret < 0) { |
889 | return ret; |
890 | } |
891 | |
892 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask" , 0xff); |
893 | if (ret < 0) { |
894 | return ret; |
895 | } |
896 | |
897 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time" , 0x0); |
898 | if (ret < 0) { |
899 | return ret; |
900 | } |
901 | |
902 | /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ |
903 | dimms = qmp_memory_device_list(); |
904 | if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { |
905 | ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); |
906 | } else { |
907 | ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); |
908 | } |
909 | qapi_free_MemoryDeviceInfoList(dimms); |
910 | |
911 | if (ret < 0) { |
912 | return ret; |
913 | } |
914 | |
915 | /* ibm,associativity-lookup-arrays */ |
916 | buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); |
917 | cur_index = int_buf = g_malloc0(buf_len); |
918 | int_buf[0] = cpu_to_be32(nr_nodes); |
919 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
920 | cur_index += 2; |
921 | for (i = 0; i < nr_nodes; i++) { |
922 | uint32_t associativity[] = { |
923 | cpu_to_be32(0x0), |
924 | cpu_to_be32(0x0), |
925 | cpu_to_be32(0x0), |
926 | cpu_to_be32(i) |
927 | }; |
928 | memcpy(cur_index, associativity, sizeof(associativity)); |
929 | cur_index += 4; |
930 | } |
931 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays" , int_buf, |
932 | (cur_index - int_buf) * sizeof(uint32_t)); |
933 | g_free(int_buf); |
934 | |
935 | return ret; |
936 | } |
937 | |
938 | static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, |
939 | SpaprOptionVector *ov5_updates) |
940 | { |
941 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
942 | int ret = 0, offset; |
943 | |
944 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ |
945 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { |
946 | g_assert(smc->dr_lmb_enabled); |
947 | ret = spapr_populate_drconf_memory(spapr, fdt); |
948 | if (ret) { |
949 | goto out; |
950 | } |
951 | } |
952 | |
953 | offset = fdt_path_offset(fdt, "/chosen" ); |
954 | if (offset < 0) { |
955 | offset = fdt_add_subnode(fdt, 0, "chosen" ); |
956 | if (offset < 0) { |
957 | return offset; |
958 | } |
959 | } |
960 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, |
961 | "ibm,architecture-vec-5" ); |
962 | |
963 | out: |
964 | return ret; |
965 | } |
966 | |
967 | static bool spapr_hotplugged_dev_before_cas(void) |
968 | { |
969 | Object *drc_container, *obj; |
970 | ObjectProperty *prop; |
971 | ObjectPropertyIterator iter; |
972 | |
973 | drc_container = container_get(object_get_root(), "/dr-connector" ); |
974 | object_property_iter_init(&iter, drc_container); |
975 | while ((prop = object_property_iter_next(&iter))) { |
976 | if (!strstart(prop->type, "link<" , NULL)) { |
977 | continue; |
978 | } |
979 | obj = object_property_get_link(drc_container, prop->name, NULL); |
980 | if (spapr_drc_needed(obj)) { |
981 | return true; |
982 | } |
983 | } |
984 | return false; |
985 | } |
986 | |
987 | int spapr_h_cas_compose_response(SpaprMachineState *spapr, |
988 | target_ulong addr, target_ulong size, |
989 | SpaprOptionVector *ov5_updates) |
990 | { |
991 | void *fdt, *fdt_skel; |
992 | SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; |
993 | |
994 | if (spapr_hotplugged_dev_before_cas()) { |
995 | return 1; |
996 | } |
997 | |
998 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
999 | error_report("SLOF provided an unexpected CAS buffer size " |
1000 | TARGET_FMT_lu " (min: %zu, max: %u)" , |
1001 | size, sizeof(hdr), FW_MAX_SIZE); |
1002 | exit(EXIT_FAILURE); |
1003 | } |
1004 | |
1005 | size -= sizeof(hdr); |
1006 | |
1007 | /* Create skeleton */ |
1008 | fdt_skel = g_malloc0(size); |
1009 | _FDT((fdt_create(fdt_skel, size))); |
1010 | _FDT((fdt_finish_reservemap(fdt_skel))); |
1011 | _FDT((fdt_begin_node(fdt_skel, "" ))); |
1012 | _FDT((fdt_end_node(fdt_skel))); |
1013 | _FDT((fdt_finish(fdt_skel))); |
1014 | fdt = g_malloc0(size); |
1015 | _FDT((fdt_open_into(fdt_skel, fdt, size))); |
1016 | g_free(fdt_skel); |
1017 | |
1018 | /* Fixup cpu nodes */ |
1019 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
1020 | |
1021 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
1022 | return -1; |
1023 | } |
1024 | |
1025 | /* Pack resulting tree */ |
1026 | _FDT((fdt_pack(fdt))); |
1027 | |
1028 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { |
1029 | trace_spapr_cas_failed(size); |
1030 | return -1; |
1031 | } |
1032 | |
1033 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); |
1034 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); |
1035 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); |
1036 | g_free(fdt); |
1037 | |
1038 | return 0; |
1039 | } |
1040 | |
1041 | static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) |
1042 | { |
1043 | MachineState *ms = MACHINE(spapr); |
1044 | int rtas; |
1045 | GString *hypertas = g_string_sized_new(256); |
1046 | GString *qemu_hypertas = g_string_sized_new(256); |
1047 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; |
1048 | uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + |
1049 | memory_region_size(&MACHINE(spapr)->device_memory->mr); |
1050 | uint32_t lrdr_capacity[] = { |
1051 | cpu_to_be32(max_device_addr >> 32), |
1052 | cpu_to_be32(max_device_addr & 0xffffffff), |
1053 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), |
1054 | cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), |
1055 | }; |
1056 | uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); |
1057 | uint32_t maxdomains[] = { |
1058 | cpu_to_be32(4), |
1059 | maxdomain, |
1060 | maxdomain, |
1061 | maxdomain, |
1062 | cpu_to_be32(spapr->gpu_numa_id), |
1063 | }; |
1064 | |
1065 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas" )); |
1066 | |
1067 | /* hypertas */ |
1068 | add_str(hypertas, "hcall-pft" ); |
1069 | add_str(hypertas, "hcall-term" ); |
1070 | add_str(hypertas, "hcall-dabr" ); |
1071 | add_str(hypertas, "hcall-interrupt" ); |
1072 | add_str(hypertas, "hcall-tce" ); |
1073 | add_str(hypertas, "hcall-vio" ); |
1074 | add_str(hypertas, "hcall-splpar" ); |
1075 | add_str(hypertas, "hcall-join" ); |
1076 | add_str(hypertas, "hcall-bulk" ); |
1077 | add_str(hypertas, "hcall-set-mode" ); |
1078 | add_str(hypertas, "hcall-sprg0" ); |
1079 | add_str(hypertas, "hcall-copy" ); |
1080 | add_str(hypertas, "hcall-debug" ); |
1081 | add_str(hypertas, "hcall-vphn" ); |
1082 | add_str(qemu_hypertas, "hcall-memop1" ); |
1083 | |
1084 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { |
1085 | add_str(hypertas, "hcall-multi-tce" ); |
1086 | } |
1087 | |
1088 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { |
1089 | add_str(hypertas, "hcall-hpt-resize" ); |
1090 | } |
1091 | |
1092 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions" , |
1093 | hypertas->str, hypertas->len)); |
1094 | g_string_free(hypertas, TRUE); |
1095 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions" , |
1096 | qemu_hypertas->str, qemu_hypertas->len)); |
1097 | g_string_free(qemu_hypertas, TRUE); |
1098 | |
1099 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points" , |
1100 | refpoints, sizeof(refpoints))); |
1101 | |
1102 | _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains" , |
1103 | maxdomains, sizeof(maxdomains))); |
1104 | |
1105 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max" , |
1106 | RTAS_ERROR_LOG_MAX)); |
1107 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate" , |
1108 | RTAS_EVENT_SCAN_RATE)); |
1109 | |
1110 | g_assert(msi_nonbroken); |
1111 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable" , NULL, 0)); |
1112 | |
1113 | /* |
1114 | * According to PAPR, rtas ibm,os-term does not guarantee a return |
1115 | * back to the guest cpu. |
1116 | * |
1117 | * While an additional ibm,extended-os-term property indicates |
1118 | * that rtas call return will always occur. Set this property. |
1119 | */ |
1120 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term" , NULL, 0)); |
1121 | |
1122 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity" , |
1123 | lrdr_capacity, sizeof(lrdr_capacity))); |
1124 | |
1125 | spapr_dt_rtas_tokens(fdt, rtas); |
1126 | } |
1127 | |
1128 | /* |
1129 | * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU |
1130 | * and the XIVE features that the guest may request and thus the valid |
1131 | * values for bytes 23..26 of option vector 5: |
1132 | */ |
1133 | static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, |
1134 | int chosen) |
1135 | { |
1136 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
1137 | |
1138 | char val[2 * 4] = { |
1139 | 23, spapr->irq->ov5, /* Xive mode. */ |
1140 | 24, 0x00, /* Hash/Radix, filled in below. */ |
1141 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ |
1142 | 26, 0x40, /* Radix options: GTSE == yes. */ |
1143 | }; |
1144 | |
1145 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
1146 | first_ppc_cpu->compat_pvr)) { |
1147 | /* |
1148 | * If we're in a pre POWER9 compat mode then the guest should |
1149 | * do hash and use the legacy interrupt mode |
1150 | */ |
1151 | val[1] = 0x00; /* XICS */ |
1152 | val[3] = 0x00; /* Hash */ |
1153 | } else if (kvm_enabled()) { |
1154 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
1155 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
1156 | } else if (kvmppc_has_cap_mmu_radix()) { |
1157 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
1158 | } else { |
1159 | val[3] = 0x00; /* Hash */ |
1160 | } |
1161 | } else { |
1162 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
1163 | val[3] = 0xC0; |
1164 | } |
1165 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support" , |
1166 | val, sizeof(val))); |
1167 | } |
1168 | |
1169 | static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) |
1170 | { |
1171 | MachineState *machine = MACHINE(spapr); |
1172 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
1173 | int chosen; |
1174 | const char *boot_device = machine->boot_order; |
1175 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); |
1176 | size_t cb = 0; |
1177 | char *bootlist = get_boot_devices_list(&cb); |
1178 | |
1179 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen" )); |
1180 | |
1181 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs" , machine->kernel_cmdline)); |
1182 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start" , |
1183 | spapr->initrd_base)); |
1184 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end" , |
1185 | spapr->initrd_base + spapr->initrd_size)); |
1186 | |
1187 | if (spapr->kernel_size) { |
1188 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), |
1189 | cpu_to_be64(spapr->kernel_size) }; |
1190 | |
1191 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel" , |
1192 | &kprop, sizeof(kprop))); |
1193 | if (spapr->kernel_le) { |
1194 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le" , NULL, 0)); |
1195 | } |
1196 | } |
1197 | if (boot_menu) { |
1198 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu" , boot_menu))); |
1199 | } |
1200 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width" , graphic_width)); |
1201 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height" , graphic_height)); |
1202 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth" , graphic_depth)); |
1203 | |
1204 | if (cb && bootlist) { |
1205 | int i; |
1206 | |
1207 | for (i = 0; i < cb; i++) { |
1208 | if (bootlist[i] == '\n') { |
1209 | bootlist[i] = ' '; |
1210 | } |
1211 | } |
1212 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list" , bootlist)); |
1213 | } |
1214 | |
1215 | if (boot_device && strlen(boot_device)) { |
1216 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device" , boot_device)); |
1217 | } |
1218 | |
1219 | if (!spapr->has_graphics && stdout_path) { |
1220 | /* |
1221 | * "linux,stdout-path" and "stdout" properties are deprecated by linux |
1222 | * kernel. New platforms should only use the "stdout-path" property. Set |
1223 | * the new property and continue using older property to remain |
1224 | * compatible with the existing firmware. |
1225 | */ |
1226 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path" , stdout_path)); |
1227 | _FDT(fdt_setprop_string(fdt, chosen, "stdout-path" , stdout_path)); |
1228 | } |
1229 | |
1230 | /* We can deal with BAR reallocation just fine, advertise it to the guest */ |
1231 | if (smc->linux_pci_probe) { |
1232 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only" , 0)); |
1233 | } |
1234 | |
1235 | spapr_dt_ov5_platform_support(spapr, fdt, chosen); |
1236 | |
1237 | g_free(stdout_path); |
1238 | g_free(bootlist); |
1239 | } |
1240 | |
1241 | static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) |
1242 | { |
1243 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR |
1244 | * KVM to work under pHyp with some guest co-operation */ |
1245 | int hypervisor; |
1246 | uint8_t hypercall[16]; |
1247 | |
1248 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor" )); |
1249 | /* indicate KVM hypercall interface */ |
1250 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible" , "linux,kvm" )); |
1251 | if (kvmppc_has_cap_fixup_hcalls()) { |
1252 | /* |
1253 | * Older KVM versions with older guest kernels were broken |
1254 | * with the magic page, don't allow the guest to map it. |
1255 | */ |
1256 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, |
1257 | sizeof(hypercall))) { |
1258 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions" , |
1259 | hypercall, sizeof(hypercall))); |
1260 | } |
1261 | } |
1262 | } |
1263 | |
1264 | static void *spapr_build_fdt(SpaprMachineState *spapr) |
1265 | { |
1266 | MachineState *machine = MACHINE(spapr); |
1267 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1268 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
1269 | int ret; |
1270 | void *fdt; |
1271 | SpaprPhbState *phb; |
1272 | char *buf; |
1273 | |
1274 | fdt = g_malloc0(FDT_MAX_SIZE); |
1275 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); |
1276 | |
1277 | /* Root node */ |
1278 | _FDT(fdt_setprop_string(fdt, 0, "device_type" , "chrp" )); |
1279 | _FDT(fdt_setprop_string(fdt, 0, "model" , "IBM pSeries (emulated by qemu)" )); |
1280 | _FDT(fdt_setprop_string(fdt, 0, "compatible" , "qemu,pseries" )); |
1281 | |
1282 | /* Guest UUID & Name*/ |
1283 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); |
1284 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid" , buf)); |
1285 | if (qemu_uuid_set) { |
1286 | _FDT(fdt_setprop_string(fdt, 0, "system-id" , buf)); |
1287 | } |
1288 | g_free(buf); |
1289 | |
1290 | if (qemu_get_vm_name()) { |
1291 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name" , |
1292 | qemu_get_vm_name())); |
1293 | } |
1294 | |
1295 | /* Host Model & Serial Number */ |
1296 | if (spapr->host_model) { |
1297 | _FDT(fdt_setprop_string(fdt, 0, "host-model" , spapr->host_model)); |
1298 | } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { |
1299 | _FDT(fdt_setprop_string(fdt, 0, "host-model" , buf)); |
1300 | g_free(buf); |
1301 | } |
1302 | |
1303 | if (spapr->host_serial) { |
1304 | _FDT(fdt_setprop_string(fdt, 0, "host-serial" , spapr->host_serial)); |
1305 | } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { |
1306 | _FDT(fdt_setprop_string(fdt, 0, "host-serial" , buf)); |
1307 | g_free(buf); |
1308 | } |
1309 | |
1310 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells" , 2)); |
1311 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells" , 2)); |
1312 | |
1313 | /* /interrupt controller */ |
1314 | spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, |
1315 | PHANDLE_INTC); |
1316 | |
1317 | ret = spapr_populate_memory(spapr, fdt); |
1318 | if (ret < 0) { |
1319 | error_report("couldn't setup memory nodes in fdt" ); |
1320 | exit(1); |
1321 | } |
1322 | |
1323 | /* /vdevice */ |
1324 | spapr_dt_vdevice(spapr->vio_bus, fdt); |
1325 | |
1326 | if (object_resolve_path_type("" , TYPE_SPAPR_RNG, NULL)) { |
1327 | ret = spapr_rng_populate_dt(fdt); |
1328 | if (ret < 0) { |
1329 | error_report("could not set up rng device in the fdt" ); |
1330 | exit(1); |
1331 | } |
1332 | } |
1333 | |
1334 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
1335 | ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL); |
1336 | if (ret < 0) { |
1337 | error_report("couldn't setup PCI devices in fdt" ); |
1338 | exit(1); |
1339 | } |
1340 | } |
1341 | |
1342 | /* cpus */ |
1343 | spapr_populate_cpus_dt_node(fdt, spapr); |
1344 | |
1345 | if (smc->dr_lmb_enabled) { |
1346 | _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); |
1347 | } |
1348 | |
1349 | if (mc->has_hotpluggable_cpus) { |
1350 | int offset = fdt_path_offset(fdt, "/cpus" ); |
1351 | ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); |
1352 | if (ret < 0) { |
1353 | error_report("Couldn't set up CPU DR device tree properties" ); |
1354 | exit(1); |
1355 | } |
1356 | } |
1357 | |
1358 | /* /event-sources */ |
1359 | spapr_dt_events(spapr, fdt); |
1360 | |
1361 | /* /rtas */ |
1362 | spapr_dt_rtas(spapr, fdt); |
1363 | |
1364 | /* /chosen */ |
1365 | spapr_dt_chosen(spapr, fdt); |
1366 | |
1367 | /* /hypervisor */ |
1368 | if (kvm_enabled()) { |
1369 | spapr_dt_hypervisor(spapr, fdt); |
1370 | } |
1371 | |
1372 | /* Build memory reserve map */ |
1373 | if (spapr->kernel_size) { |
1374 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); |
1375 | } |
1376 | if (spapr->initrd_size) { |
1377 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); |
1378 | } |
1379 | |
1380 | /* ibm,client-architecture-support updates */ |
1381 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); |
1382 | if (ret < 0) { |
1383 | error_report("couldn't setup CAS properties fdt" ); |
1384 | exit(1); |
1385 | } |
1386 | |
1387 | if (smc->dr_phb_enabled) { |
1388 | ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); |
1389 | if (ret < 0) { |
1390 | error_report("Couldn't set up PHB DR device tree properties" ); |
1391 | exit(1); |
1392 | } |
1393 | } |
1394 | |
1395 | return fdt; |
1396 | } |
1397 | |
1398 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
1399 | { |
1400 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
1401 | } |
1402 | |
1403 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1404 | PowerPCCPU *cpu) |
1405 | { |
1406 | CPUPPCState *env = &cpu->env; |
1407 | |
1408 | /* The TCG path should also be holding the BQL at this point */ |
1409 | g_assert(qemu_mutex_iothread_locked()); |
1410 | |
1411 | if (msr_pr) { |
1412 | hcall_dprintf("Hypercall made with MSR[PR]=1\n" ); |
1413 | env->gpr[3] = H_PRIVILEGE; |
1414 | } else { |
1415 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
1416 | } |
1417 | } |
1418 | |
1419 | struct LPCRSyncState { |
1420 | target_ulong value; |
1421 | target_ulong mask; |
1422 | }; |
1423 | |
1424 | static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) |
1425 | { |
1426 | struct LPCRSyncState *s = arg.host_ptr; |
1427 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1428 | CPUPPCState *env = &cpu->env; |
1429 | target_ulong lpcr; |
1430 | |
1431 | cpu_synchronize_state(cs); |
1432 | lpcr = env->spr[SPR_LPCR]; |
1433 | lpcr &= ~s->mask; |
1434 | lpcr |= s->value; |
1435 | ppc_store_lpcr(cpu, lpcr); |
1436 | } |
1437 | |
1438 | void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) |
1439 | { |
1440 | CPUState *cs; |
1441 | struct LPCRSyncState s = { |
1442 | .value = value, |
1443 | .mask = mask |
1444 | }; |
1445 | CPU_FOREACH(cs) { |
1446 | run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); |
1447 | } |
1448 | } |
1449 | |
1450 | static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) |
1451 | { |
1452 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1453 | |
1454 | /* Copy PATE1:GR into PATE0:HR */ |
1455 | entry->dw0 = spapr->patb_entry & PATE0_HR; |
1456 | entry->dw1 = spapr->patb_entry; |
1457 | } |
1458 | |
1459 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1460 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) |
1461 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) |
1462 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) |
1463 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) |
1464 | |
1465 | /* |
1466 | * Get the fd to access the kernel htab, re-opening it if necessary |
1467 | */ |
1468 | static int get_htab_fd(SpaprMachineState *spapr) |
1469 | { |
1470 | Error *local_err = NULL; |
1471 | |
1472 | if (spapr->htab_fd >= 0) { |
1473 | return spapr->htab_fd; |
1474 | } |
1475 | |
1476 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
1477 | if (spapr->htab_fd < 0) { |
1478 | error_report_err(local_err); |
1479 | } |
1480 | |
1481 | return spapr->htab_fd; |
1482 | } |
1483 | |
1484 | void close_htab_fd(SpaprMachineState *spapr) |
1485 | { |
1486 | if (spapr->htab_fd >= 0) { |
1487 | close(spapr->htab_fd); |
1488 | } |
1489 | spapr->htab_fd = -1; |
1490 | } |
1491 | |
1492 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1493 | { |
1494 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1495 | |
1496 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; |
1497 | } |
1498 | |
1499 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1500 | { |
1501 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1502 | |
1503 | assert(kvm_enabled()); |
1504 | |
1505 | if (!spapr->htab) { |
1506 | return 0; |
1507 | } |
1508 | |
1509 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); |
1510 | } |
1511 | |
1512 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1513 | hwaddr ptex, int n) |
1514 | { |
1515 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1516 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
1517 | |
1518 | if (!spapr->htab) { |
1519 | /* |
1520 | * HTAB is controlled by KVM. Fetch into temporary buffer |
1521 | */ |
1522 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); |
1523 | kvmppc_read_hptes(hptes, ptex, n); |
1524 | return hptes; |
1525 | } |
1526 | |
1527 | /* |
1528 | * HTAB is controlled by QEMU. Just point to the internally |
1529 | * accessible PTEG. |
1530 | */ |
1531 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); |
1532 | } |
1533 | |
1534 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, |
1535 | const ppc_hash_pte64_t *hptes, |
1536 | hwaddr ptex, int n) |
1537 | { |
1538 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1539 | |
1540 | if (!spapr->htab) { |
1541 | g_free((void *)hptes); |
1542 | } |
1543 | |
1544 | /* Nothing to do for qemu managed HPT */ |
1545 | } |
1546 | |
1547 | void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, |
1548 | uint64_t pte0, uint64_t pte1) |
1549 | { |
1550 | SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); |
1551 | hwaddr offset = ptex * HASH_PTE_SIZE_64; |
1552 | |
1553 | if (!spapr->htab) { |
1554 | kvmppc_write_hpte(ptex, pte0, pte1); |
1555 | } else { |
1556 | if (pte0 & HPTE64_V_VALID) { |
1557 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); |
1558 | /* |
1559 | * When setting valid, we write PTE1 first. This ensures |
1560 | * proper synchronization with the reading code in |
1561 | * ppc_hash64_pteg_search() |
1562 | */ |
1563 | smp_wmb(); |
1564 | stq_p(spapr->htab + offset, pte0); |
1565 | } else { |
1566 | stq_p(spapr->htab + offset, pte0); |
1567 | /* |
1568 | * When clearing it we set PTE0 first. This ensures proper |
1569 | * synchronization with the reading code in |
1570 | * ppc_hash64_pteg_search() |
1571 | */ |
1572 | smp_wmb(); |
1573 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); |
1574 | } |
1575 | } |
1576 | } |
1577 | |
1578 | static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, |
1579 | uint64_t pte1) |
1580 | { |
1581 | hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; |
1582 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1583 | |
1584 | if (!spapr->htab) { |
1585 | /* There should always be a hash table when this is called */ |
1586 | error_report("spapr_hpte_set_c called with no hash table !" ); |
1587 | return; |
1588 | } |
1589 | |
1590 | /* The HW performs a non-atomic byte update */ |
1591 | stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); |
1592 | } |
1593 | |
1594 | static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, |
1595 | uint64_t pte1) |
1596 | { |
1597 | hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; |
1598 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1599 | |
1600 | if (!spapr->htab) { |
1601 | /* There should always be a hash table when this is called */ |
1602 | error_report("spapr_hpte_set_r called with no hash table !" ); |
1603 | return; |
1604 | } |
1605 | |
1606 | /* The HW performs a non-atomic byte update */ |
1607 | stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); |
1608 | } |
1609 | |
1610 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1611 | { |
1612 | int shift; |
1613 | |
1614 | /* We aim for a hash table of size 1/128 the size of RAM (rounded |
1615 | * up). The PAPR recommendation is actually 1/64 of RAM size, but |
1616 | * that's much more than is needed for Linux guests */ |
1617 | shift = ctz64(pow2ceil(ramsize)) - 7; |
1618 | shift = MAX(shift, 18); /* Minimum architected size */ |
1619 | shift = MIN(shift, 46); /* Maximum architected size */ |
1620 | return shift; |
1621 | } |
1622 | |
1623 | void spapr_free_hpt(SpaprMachineState *spapr) |
1624 | { |
1625 | g_free(spapr->htab); |
1626 | spapr->htab = NULL; |
1627 | spapr->htab_shift = 0; |
1628 | close_htab_fd(spapr); |
1629 | } |
1630 | |
1631 | void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, |
1632 | Error **errp) |
1633 | { |
1634 | long rc; |
1635 | |
1636 | /* Clean up any HPT info from a previous boot */ |
1637 | spapr_free_hpt(spapr); |
1638 | |
1639 | rc = kvmppc_reset_htab(shift); |
1640 | if (rc < 0) { |
1641 | /* kernel-side HPT needed, but couldn't allocate one */ |
1642 | error_setg_errno(errp, errno, |
1643 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)" , |
1644 | shift); |
1645 | /* This is almost certainly fatal, but if the caller really |
1646 | * wants to carry on with shift == 0, it's welcome to try */ |
1647 | } else if (rc > 0) { |
1648 | /* kernel-side HPT allocated */ |
1649 | if (rc != shift) { |
1650 | error_setg(errp, |
1651 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)" , |
1652 | shift, rc); |
1653 | } |
1654 | |
1655 | spapr->htab_shift = shift; |
1656 | spapr->htab = NULL; |
1657 | } else { |
1658 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1659 | size_t size = 1ULL << shift; |
1660 | int i; |
1661 | |
1662 | spapr->htab = qemu_memalign(size, size); |
1663 | if (!spapr->htab) { |
1664 | error_setg_errno(errp, errno, |
1665 | "Could not allocate HPT of order %d" , shift); |
1666 | return; |
1667 | } |
1668 | |
1669 | memset(spapr->htab, 0, size); |
1670 | spapr->htab_shift = shift; |
1671 | |
1672 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1673 | DIRTY_HPTE(HPTE(spapr->htab, i)); |
1674 | } |
1675 | } |
1676 | /* We're setting up a hash table, so that means we're not radix */ |
1677 | spapr->patb_entry = 0; |
1678 | spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); |
1679 | } |
1680 | |
1681 | void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) |
1682 | { |
1683 | int hpt_shift; |
1684 | |
1685 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) |
1686 | || (spapr->cas_reboot |
1687 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { |
1688 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); |
1689 | } else { |
1690 | uint64_t current_ram_size; |
1691 | |
1692 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); |
1693 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); |
1694 | } |
1695 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); |
1696 | |
1697 | if (spapr->vrma_adjust) { |
1698 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
1699 | spapr->htab_shift); |
1700 | } |
1701 | } |
1702 | |
1703 | static int spapr_reset_drcs(Object *child, void *opaque) |
1704 | { |
1705 | SpaprDrc *drc = |
1706 | (SpaprDrc *) object_dynamic_cast(child, |
1707 | TYPE_SPAPR_DR_CONNECTOR); |
1708 | |
1709 | if (drc) { |
1710 | spapr_drc_reset(drc); |
1711 | } |
1712 | |
1713 | return 0; |
1714 | } |
1715 | |
1716 | static void spapr_machine_reset(MachineState *machine) |
1717 | { |
1718 | SpaprMachineState *spapr = SPAPR_MACHINE(machine); |
1719 | PowerPCCPU *first_ppc_cpu; |
1720 | uint32_t rtas_limit; |
1721 | hwaddr rtas_addr, fdt_addr; |
1722 | void *fdt; |
1723 | int rc; |
1724 | |
1725 | spapr_caps_apply(spapr); |
1726 | |
1727 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1728 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && |
1729 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
1730 | spapr->max_compat_pvr)) { |
1731 | /* |
1732 | * If using KVM with radix mode available, VCPUs can be started |
1733 | * without a HPT because KVM will start them in radix mode. |
1734 | * Set the GR bit in PATE so that we know there is no HPT. |
1735 | */ |
1736 | spapr->patb_entry = PATE1_GR; |
1737 | spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); |
1738 | } else { |
1739 | spapr_setup_hpt_and_vrma(spapr); |
1740 | } |
1741 | |
1742 | /* |
1743 | * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. |
1744 | * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is |
1745 | * called from vPHB reset handler so we initialize the counter here. |
1746 | * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM |
1747 | * must be equally distant from any other node. |
1748 | * The final value of spapr->gpu_numa_id is going to be written to |
1749 | * max-associativity-domains in spapr_build_fdt(). |
1750 | */ |
1751 | spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); |
1752 | qemu_devices_reset(); |
1753 | |
1754 | /* |
1755 | * If this reset wasn't generated by CAS, we should reset our |
1756 | * negotiated options and start from scratch |
1757 | */ |
1758 | if (!spapr->cas_reboot) { |
1759 | spapr_ovec_cleanup(spapr->ov5_cas); |
1760 | spapr->ov5_cas = spapr_ovec_new(); |
1761 | |
1762 | ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); |
1763 | } |
1764 | |
1765 | /* |
1766 | * This is fixing some of the default configuration of the XIVE |
1767 | * devices. To be called after the reset of the machine devices. |
1768 | */ |
1769 | spapr_irq_reset(spapr, &error_fatal); |
1770 | |
1771 | /* |
1772 | * There is no CAS under qtest. Simulate one to please the code that |
1773 | * depends on spapr->ov5_cas. This is especially needed to test device |
1774 | * unplug, so we do that before resetting the DRCs. |
1775 | */ |
1776 | if (qtest_enabled()) { |
1777 | spapr_ovec_cleanup(spapr->ov5_cas); |
1778 | spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); |
1779 | } |
1780 | |
1781 | /* DRC reset may cause a device to be unplugged. This will cause troubles |
1782 | * if this device is used by another device (eg, a running vhost backend |
1783 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such |
1784 | * situations, we reset DRCs after all devices have been reset. |
1785 | */ |
1786 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); |
1787 | |
1788 | spapr_clear_pending_events(spapr); |
1789 | |
1790 | /* |
1791 | * We place the device tree and RTAS just below either the top of the RMA, |
1792 | * or just below 2GB, whichever is lower, so that it can be |
1793 | * processed with 32-bit real mode code if necessary |
1794 | */ |
1795 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); |
1796 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1797 | fdt_addr = rtas_addr - FDT_MAX_SIZE; |
1798 | |
1799 | fdt = spapr_build_fdt(spapr); |
1800 | |
1801 | spapr_load_rtas(spapr, fdt, rtas_addr); |
1802 | |
1803 | rc = fdt_pack(fdt); |
1804 | |
1805 | /* Should only fail if we've built a corrupted tree */ |
1806 | assert(rc == 0); |
1807 | |
1808 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
1809 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)" , |
1810 | fdt_totalsize(fdt), FDT_MAX_SIZE); |
1811 | exit(1); |
1812 | } |
1813 | |
1814 | /* Load the fdt */ |
1815 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); |
1816 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
1817 | g_free(spapr->fdt_blob); |
1818 | spapr->fdt_size = fdt_totalsize(fdt); |
1819 | spapr->fdt_initial_size = spapr->fdt_size; |
1820 | spapr->fdt_blob = fdt; |
1821 | |
1822 | /* Set up the entry state */ |
1823 | spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); |
1824 | first_ppc_cpu->env.gpr[5] = 0; |
1825 | |
1826 | spapr->cas_reboot = false; |
1827 | } |
1828 | |
1829 | static void spapr_create_nvram(SpaprMachineState *spapr) |
1830 | { |
1831 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram" ); |
1832 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
1833 | |
1834 | if (dinfo) { |
1835 | qdev_prop_set_drive(dev, "drive" , blk_by_legacy_dinfo(dinfo), |
1836 | &error_fatal); |
1837 | } |
1838 | |
1839 | qdev_init_nofail(dev); |
1840 | |
1841 | spapr->nvram = (struct SpaprNvram *)dev; |
1842 | } |
1843 | |
1844 | static void spapr_rtc_create(SpaprMachineState *spapr) |
1845 | { |
1846 | object_initialize_child(OBJECT(spapr), "rtc" , |
1847 | &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, |
1848 | &error_fatal, NULL); |
1849 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized" , |
1850 | &error_fatal); |
1851 | object_property_add_alias(OBJECT(spapr), "rtc-time" , OBJECT(&spapr->rtc), |
1852 | "date" , &error_fatal); |
1853 | } |
1854 | |
1855 | /* Returns whether we want to use VGA or not */ |
1856 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
1857 | { |
1858 | switch (vga_interface_type) { |
1859 | case VGA_NONE: |
1860 | return false; |
1861 | case VGA_DEVICE: |
1862 | return true; |
1863 | case VGA_STD: |
1864 | case VGA_VIRTIO: |
1865 | case VGA_CIRRUS: |
1866 | return pci_vga_init(pci_bus) != NULL; |
1867 | default: |
1868 | error_setg(errp, |
1869 | "Unsupported VGA mode, only -vga std or -vga virtio is supported" ); |
1870 | return false; |
1871 | } |
1872 | } |
1873 | |
1874 | static int spapr_pre_load(void *opaque) |
1875 | { |
1876 | int rc; |
1877 | |
1878 | rc = spapr_caps_pre_load(opaque); |
1879 | if (rc) { |
1880 | return rc; |
1881 | } |
1882 | |
1883 | return 0; |
1884 | } |
1885 | |
1886 | static int spapr_post_load(void *opaque, int version_id) |
1887 | { |
1888 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
1889 | int err = 0; |
1890 | |
1891 | err = spapr_caps_post_migration(spapr); |
1892 | if (err) { |
1893 | return err; |
1894 | } |
1895 | |
1896 | /* |
1897 | * In earlier versions, there was no separate qdev for the PAPR |
1898 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1899 | * So when migrating from those versions, poke the incoming offset |
1900 | * value into the RTC device |
1901 | */ |
1902 | if (version_id < 3) { |
1903 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
1904 | if (err) { |
1905 | return err; |
1906 | } |
1907 | } |
1908 | |
1909 | if (kvm_enabled() && spapr->patb_entry) { |
1910 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1911 | bool radix = !!(spapr->patb_entry & PATE1_GR); |
1912 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); |
1913 | |
1914 | /* |
1915 | * Update LPCR:HR and UPRT as they may not be set properly in |
1916 | * the stream |
1917 | */ |
1918 | spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, |
1919 | LPCR_HR | LPCR_UPRT); |
1920 | |
1921 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); |
1922 | if (err) { |
1923 | error_report("Process table config unsupported by the host" ); |
1924 | return -EINVAL; |
1925 | } |
1926 | } |
1927 | |
1928 | err = spapr_irq_post_load(spapr, version_id); |
1929 | if (err) { |
1930 | return err; |
1931 | } |
1932 | |
1933 | return err; |
1934 | } |
1935 | |
1936 | static int spapr_pre_save(void *opaque) |
1937 | { |
1938 | int rc; |
1939 | |
1940 | rc = spapr_caps_pre_save(opaque); |
1941 | if (rc) { |
1942 | return rc; |
1943 | } |
1944 | |
1945 | return 0; |
1946 | } |
1947 | |
1948 | static bool version_before_3(void *opaque, int version_id) |
1949 | { |
1950 | return version_id < 3; |
1951 | } |
1952 | |
1953 | static bool spapr_pending_events_needed(void *opaque) |
1954 | { |
1955 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
1956 | return !QTAILQ_EMPTY(&spapr->pending_events); |
1957 | } |
1958 | |
1959 | static const VMStateDescription vmstate_spapr_event_entry = { |
1960 | .name = "spapr_event_log_entry" , |
1961 | .version_id = 1, |
1962 | .minimum_version_id = 1, |
1963 | .fields = (VMStateField[]) { |
1964 | VMSTATE_UINT32(summary, SpaprEventLogEntry), |
1965 | VMSTATE_UINT32(extended_length, SpaprEventLogEntry), |
1966 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, |
1967 | NULL, extended_length), |
1968 | VMSTATE_END_OF_LIST() |
1969 | }, |
1970 | }; |
1971 | |
1972 | static const VMStateDescription vmstate_spapr_pending_events = { |
1973 | .name = "spapr_pending_events" , |
1974 | .version_id = 1, |
1975 | .minimum_version_id = 1, |
1976 | .needed = spapr_pending_events_needed, |
1977 | .fields = (VMStateField[]) { |
1978 | VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, |
1979 | vmstate_spapr_event_entry, SpaprEventLogEntry, next), |
1980 | VMSTATE_END_OF_LIST() |
1981 | }, |
1982 | }; |
1983 | |
1984 | static bool spapr_ov5_cas_needed(void *opaque) |
1985 | { |
1986 | SpaprMachineState *spapr = opaque; |
1987 | SpaprOptionVector *ov5_mask = spapr_ovec_new(); |
1988 | SpaprOptionVector *ov5_legacy = spapr_ovec_new(); |
1989 | SpaprOptionVector *ov5_removed = spapr_ovec_new(); |
1990 | bool cas_needed; |
1991 | |
1992 | /* Prior to the introduction of SpaprOptionVector, we had two option |
1993 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. |
1994 | * Both of these options encode machine topology into the device-tree |
1995 | * in such a way that the now-booted OS should still be able to interact |
1996 | * appropriately with QEMU regardless of what options were actually |
1997 | * negotiatied on the source side. |
1998 | * |
1999 | * As such, we can avoid migrating the CAS-negotiated options if these |
2000 | * are the only options available on the current machine/platform. |
2001 | * Since these are the only options available for pseries-2.7 and |
2002 | * earlier, this allows us to maintain old->new/new->old migration |
2003 | * compatibility. |
2004 | * |
2005 | * For QEMU 2.8+, there are additional CAS-negotiatable options available |
2006 | * via default pseries-2.8 machines and explicit command-line parameters. |
2007 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware |
2008 | * of the actual CAS-negotiated values to continue working properly. For |
2009 | * example, availability of memory unplug depends on knowing whether |
2010 | * OV5_HP_EVT was negotiated via CAS. |
2011 | * |
2012 | * Thus, for any cases where the set of available CAS-negotiatable |
2013 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we |
2014 | * include the CAS-negotiated options in the migration stream, unless |
2015 | * if they affect boot time behaviour only. |
2016 | */ |
2017 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); |
2018 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); |
2019 | spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); |
2020 | |
2021 | /* spapr_ovec_diff returns true if bits were removed. we avoid using |
2022 | * the mask itself since in the future it's possible "legacy" bits may be |
2023 | * removed via machine options, which could generate a false positive |
2024 | * that breaks migration. |
2025 | */ |
2026 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); |
2027 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); |
2028 | |
2029 | spapr_ovec_cleanup(ov5_mask); |
2030 | spapr_ovec_cleanup(ov5_legacy); |
2031 | spapr_ovec_cleanup(ov5_removed); |
2032 | |
2033 | return cas_needed; |
2034 | } |
2035 | |
2036 | static const VMStateDescription vmstate_spapr_ov5_cas = { |
2037 | .name = "spapr_option_vector_ov5_cas" , |
2038 | .version_id = 1, |
2039 | .minimum_version_id = 1, |
2040 | .needed = spapr_ov5_cas_needed, |
2041 | .fields = (VMStateField[]) { |
2042 | VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, |
2043 | vmstate_spapr_ovec, SpaprOptionVector), |
2044 | VMSTATE_END_OF_LIST() |
2045 | }, |
2046 | }; |
2047 | |
2048 | static bool spapr_patb_entry_needed(void *opaque) |
2049 | { |
2050 | SpaprMachineState *spapr = opaque; |
2051 | |
2052 | return !!spapr->patb_entry; |
2053 | } |
2054 | |
2055 | static const VMStateDescription vmstate_spapr_patb_entry = { |
2056 | .name = "spapr_patb_entry" , |
2057 | .version_id = 1, |
2058 | .minimum_version_id = 1, |
2059 | .needed = spapr_patb_entry_needed, |
2060 | .fields = (VMStateField[]) { |
2061 | VMSTATE_UINT64(patb_entry, SpaprMachineState), |
2062 | VMSTATE_END_OF_LIST() |
2063 | }, |
2064 | }; |
2065 | |
2066 | static bool spapr_irq_map_needed(void *opaque) |
2067 | { |
2068 | SpaprMachineState *spapr = opaque; |
2069 | |
2070 | return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); |
2071 | } |
2072 | |
2073 | static const VMStateDescription vmstate_spapr_irq_map = { |
2074 | .name = "spapr_irq_map" , |
2075 | .version_id = 1, |
2076 | .minimum_version_id = 1, |
2077 | .needed = spapr_irq_map_needed, |
2078 | .fields = (VMStateField[]) { |
2079 | VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), |
2080 | VMSTATE_END_OF_LIST() |
2081 | }, |
2082 | }; |
2083 | |
2084 | static bool spapr_dtb_needed(void *opaque) |
2085 | { |
2086 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); |
2087 | |
2088 | return smc->update_dt_enabled; |
2089 | } |
2090 | |
2091 | static int spapr_dtb_pre_load(void *opaque) |
2092 | { |
2093 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
2094 | |
2095 | g_free(spapr->fdt_blob); |
2096 | spapr->fdt_blob = NULL; |
2097 | spapr->fdt_size = 0; |
2098 | |
2099 | return 0; |
2100 | } |
2101 | |
2102 | static const VMStateDescription vmstate_spapr_dtb = { |
2103 | .name = "spapr_dtb" , |
2104 | .version_id = 1, |
2105 | .minimum_version_id = 1, |
2106 | .needed = spapr_dtb_needed, |
2107 | .pre_load = spapr_dtb_pre_load, |
2108 | .fields = (VMStateField[]) { |
2109 | VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), |
2110 | VMSTATE_UINT32(fdt_size, SpaprMachineState), |
2111 | VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, |
2112 | fdt_size), |
2113 | VMSTATE_END_OF_LIST() |
2114 | }, |
2115 | }; |
2116 | |
2117 | static const VMStateDescription vmstate_spapr = { |
2118 | .name = "spapr" , |
2119 | .version_id = 3, |
2120 | .minimum_version_id = 1, |
2121 | .pre_load = spapr_pre_load, |
2122 | .post_load = spapr_post_load, |
2123 | .pre_save = spapr_pre_save, |
2124 | .fields = (VMStateField[]) { |
2125 | /* used to be @next_irq */ |
2126 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), |
2127 | |
2128 | /* RTC offset */ |
2129 | VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), |
2130 | |
2131 | VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), |
2132 | VMSTATE_END_OF_LIST() |
2133 | }, |
2134 | .subsections = (const VMStateDescription*[]) { |
2135 | &vmstate_spapr_ov5_cas, |
2136 | &vmstate_spapr_patb_entry, |
2137 | &vmstate_spapr_pending_events, |
2138 | &vmstate_spapr_cap_htm, |
2139 | &vmstate_spapr_cap_vsx, |
2140 | &vmstate_spapr_cap_dfp, |
2141 | &vmstate_spapr_cap_cfpc, |
2142 | &vmstate_spapr_cap_sbbc, |
2143 | &vmstate_spapr_cap_ibs, |
2144 | &vmstate_spapr_cap_hpt_maxpagesize, |
2145 | &vmstate_spapr_irq_map, |
2146 | &vmstate_spapr_cap_nested_kvm_hv, |
2147 | &vmstate_spapr_dtb, |
2148 | &vmstate_spapr_cap_large_decr, |
2149 | &vmstate_spapr_cap_ccf_assist, |
2150 | NULL |
2151 | } |
2152 | }; |
2153 | |
2154 | static int htab_save_setup(QEMUFile *f, void *opaque) |
2155 | { |
2156 | SpaprMachineState *spapr = opaque; |
2157 | |
2158 | /* "Iteration" header */ |
2159 | if (!spapr->htab_shift) { |
2160 | qemu_put_be32(f, -1); |
2161 | } else { |
2162 | qemu_put_be32(f, spapr->htab_shift); |
2163 | } |
2164 | |
2165 | if (spapr->htab) { |
2166 | spapr->htab_save_index = 0; |
2167 | spapr->htab_first_pass = true; |
2168 | } else { |
2169 | if (spapr->htab_shift) { |
2170 | assert(kvm_enabled()); |
2171 | } |
2172 | } |
2173 | |
2174 | |
2175 | return 0; |
2176 | } |
2177 | |
2178 | static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, |
2179 | int chunkstart, int n_valid, int n_invalid) |
2180 | { |
2181 | qemu_put_be32(f, chunkstart); |
2182 | qemu_put_be16(f, n_valid); |
2183 | qemu_put_be16(f, n_invalid); |
2184 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), |
2185 | HASH_PTE_SIZE_64 * n_valid); |
2186 | } |
2187 | |
2188 | static void htab_save_end_marker(QEMUFile *f) |
2189 | { |
2190 | qemu_put_be32(f, 0); |
2191 | qemu_put_be16(f, 0); |
2192 | qemu_put_be16(f, 0); |
2193 | } |
2194 | |
2195 | static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, |
2196 | int64_t max_ns) |
2197 | { |
2198 | bool has_timeout = max_ns != -1; |
2199 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
2200 | int index = spapr->htab_save_index; |
2201 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
2202 | |
2203 | assert(spapr->htab_first_pass); |
2204 | |
2205 | do { |
2206 | int chunkstart; |
2207 | |
2208 | /* Consume invalid HPTEs */ |
2209 | while ((index < htabslots) |
2210 | && !HPTE_VALID(HPTE(spapr->htab, index))) { |
2211 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
2212 | index++; |
2213 | } |
2214 | |
2215 | /* Consume valid HPTEs */ |
2216 | chunkstart = index; |
2217 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
2218 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
2219 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
2220 | index++; |
2221 | } |
2222 | |
2223 | if (index > chunkstart) { |
2224 | int n_valid = index - chunkstart; |
2225 | |
2226 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
2227 | |
2228 | if (has_timeout && |
2229 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
2230 | break; |
2231 | } |
2232 | } |
2233 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); |
2234 | |
2235 | if (index >= htabslots) { |
2236 | assert(index == htabslots); |
2237 | index = 0; |
2238 | spapr->htab_first_pass = false; |
2239 | } |
2240 | spapr->htab_save_index = index; |
2241 | } |
2242 | |
2243 | static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, |
2244 | int64_t max_ns) |
2245 | { |
2246 | bool final = max_ns < 0; |
2247 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
2248 | int examined = 0, sent = 0; |
2249 | int index = spapr->htab_save_index; |
2250 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
2251 | |
2252 | assert(!spapr->htab_first_pass); |
2253 | |
2254 | do { |
2255 | int chunkstart, invalidstart; |
2256 | |
2257 | /* Consume non-dirty HPTEs */ |
2258 | while ((index < htabslots) |
2259 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { |
2260 | index++; |
2261 | examined++; |
2262 | } |
2263 | |
2264 | chunkstart = index; |
2265 | /* Consume valid dirty HPTEs */ |
2266 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
2267 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2268 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
2269 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
2270 | index++; |
2271 | examined++; |
2272 | } |
2273 | |
2274 | invalidstart = index; |
2275 | /* Consume invalid dirty HPTEs */ |
2276 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
2277 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2278 | && !HPTE_VALID(HPTE(spapr->htab, index))) { |
2279 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
2280 | index++; |
2281 | examined++; |
2282 | } |
2283 | |
2284 | if (index > chunkstart) { |
2285 | int n_valid = invalidstart - chunkstart; |
2286 | int n_invalid = index - invalidstart; |
2287 | |
2288 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
2289 | sent += index - chunkstart; |
2290 | |
2291 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
2292 | break; |
2293 | } |
2294 | } |
2295 | |
2296 | if (examined >= htabslots) { |
2297 | break; |
2298 | } |
2299 | |
2300 | if (index >= htabslots) { |
2301 | assert(index == htabslots); |
2302 | index = 0; |
2303 | } |
2304 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); |
2305 | |
2306 | if (index >= htabslots) { |
2307 | assert(index == htabslots); |
2308 | index = 0; |
2309 | } |
2310 | |
2311 | spapr->htab_save_index = index; |
2312 | |
2313 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
2314 | } |
2315 | |
2316 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
2317 | #define MAX_KVM_BUF_SIZE 2048 |
2318 | |
2319 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
2320 | { |
2321 | SpaprMachineState *spapr = opaque; |
2322 | int fd; |
2323 | int rc = 0; |
2324 | |
2325 | /* Iteration header */ |
2326 | if (!spapr->htab_shift) { |
2327 | qemu_put_be32(f, -1); |
2328 | return 1; |
2329 | } else { |
2330 | qemu_put_be32(f, 0); |
2331 | } |
2332 | |
2333 | if (!spapr->htab) { |
2334 | assert(kvm_enabled()); |
2335 | |
2336 | fd = get_htab_fd(spapr); |
2337 | if (fd < 0) { |
2338 | return fd; |
2339 | } |
2340 | |
2341 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
2342 | if (rc < 0) { |
2343 | return rc; |
2344 | } |
2345 | } else if (spapr->htab_first_pass) { |
2346 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
2347 | } else { |
2348 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
2349 | } |
2350 | |
2351 | htab_save_end_marker(f); |
2352 | |
2353 | return rc; |
2354 | } |
2355 | |
2356 | static int htab_save_complete(QEMUFile *f, void *opaque) |
2357 | { |
2358 | SpaprMachineState *spapr = opaque; |
2359 | int fd; |
2360 | |
2361 | /* Iteration header */ |
2362 | if (!spapr->htab_shift) { |
2363 | qemu_put_be32(f, -1); |
2364 | return 0; |
2365 | } else { |
2366 | qemu_put_be32(f, 0); |
2367 | } |
2368 | |
2369 | if (!spapr->htab) { |
2370 | int rc; |
2371 | |
2372 | assert(kvm_enabled()); |
2373 | |
2374 | fd = get_htab_fd(spapr); |
2375 | if (fd < 0) { |
2376 | return fd; |
2377 | } |
2378 | |
2379 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
2380 | if (rc < 0) { |
2381 | return rc; |
2382 | } |
2383 | } else { |
2384 | if (spapr->htab_first_pass) { |
2385 | htab_save_first_pass(f, spapr, -1); |
2386 | } |
2387 | htab_save_later_pass(f, spapr, -1); |
2388 | } |
2389 | |
2390 | /* End marker */ |
2391 | htab_save_end_marker(f); |
2392 | |
2393 | return 0; |
2394 | } |
2395 | |
2396 | static int htab_load(QEMUFile *f, void *opaque, int version_id) |
2397 | { |
2398 | SpaprMachineState *spapr = opaque; |
2399 | uint32_t section_hdr; |
2400 | int fd = -1; |
2401 | Error *local_err = NULL; |
2402 | |
2403 | if (version_id < 1 || version_id > 1) { |
2404 | error_report("htab_load() bad version" ); |
2405 | return -EINVAL; |
2406 | } |
2407 | |
2408 | section_hdr = qemu_get_be32(f); |
2409 | |
2410 | if (section_hdr == -1) { |
2411 | spapr_free_hpt(spapr); |
2412 | return 0; |
2413 | } |
2414 | |
2415 | if (section_hdr) { |
2416 | /* First section gives the htab size */ |
2417 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); |
2418 | if (local_err) { |
2419 | error_report_err(local_err); |
2420 | return -EINVAL; |
2421 | } |
2422 | return 0; |
2423 | } |
2424 | |
2425 | if (!spapr->htab) { |
2426 | assert(kvm_enabled()); |
2427 | |
2428 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
2429 | if (fd < 0) { |
2430 | error_report_err(local_err); |
2431 | return fd; |
2432 | } |
2433 | } |
2434 | |
2435 | while (true) { |
2436 | uint32_t index; |
2437 | uint16_t n_valid, n_invalid; |
2438 | |
2439 | index = qemu_get_be32(f); |
2440 | n_valid = qemu_get_be16(f); |
2441 | n_invalid = qemu_get_be16(f); |
2442 | |
2443 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { |
2444 | /* End of Stream */ |
2445 | break; |
2446 | } |
2447 | |
2448 | if ((index + n_valid + n_invalid) > |
2449 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2450 | /* Bad index in stream */ |
2451 | error_report( |
2452 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)" , |
2453 | index, n_valid, n_invalid, spapr->htab_shift); |
2454 | return -EINVAL; |
2455 | } |
2456 | |
2457 | if (spapr->htab) { |
2458 | if (n_valid) { |
2459 | qemu_get_buffer(f, HPTE(spapr->htab, index), |
2460 | HASH_PTE_SIZE_64 * n_valid); |
2461 | } |
2462 | if (n_invalid) { |
2463 | memset(HPTE(spapr->htab, index + n_valid), 0, |
2464 | HASH_PTE_SIZE_64 * n_invalid); |
2465 | } |
2466 | } else { |
2467 | int rc; |
2468 | |
2469 | assert(fd >= 0); |
2470 | |
2471 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); |
2472 | if (rc < 0) { |
2473 | return rc; |
2474 | } |
2475 | } |
2476 | } |
2477 | |
2478 | if (!spapr->htab) { |
2479 | assert(fd >= 0); |
2480 | close(fd); |
2481 | } |
2482 | |
2483 | return 0; |
2484 | } |
2485 | |
2486 | static void htab_save_cleanup(void *opaque) |
2487 | { |
2488 | SpaprMachineState *spapr = opaque; |
2489 | |
2490 | close_htab_fd(spapr); |
2491 | } |
2492 | |
2493 | static SaveVMHandlers savevm_htab_handlers = { |
2494 | .save_setup = htab_save_setup, |
2495 | .save_live_iterate = htab_save_iterate, |
2496 | .save_live_complete_precopy = htab_save_complete, |
2497 | .save_cleanup = htab_save_cleanup, |
2498 | .load_state = htab_load, |
2499 | }; |
2500 | |
2501 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2502 | Error **errp) |
2503 | { |
2504 | MachineState *machine = MACHINE(opaque); |
2505 | machine->boot_order = g_strdup(boot_device); |
2506 | } |
2507 | |
2508 | static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) |
2509 | { |
2510 | MachineState *machine = MACHINE(spapr); |
2511 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
2512 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
2513 | int i; |
2514 | |
2515 | for (i = 0; i < nr_lmbs; i++) { |
2516 | uint64_t addr; |
2517 | |
2518 | addr = i * lmb_size + machine->device_memory->base; |
2519 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2520 | addr / lmb_size); |
2521 | } |
2522 | } |
2523 | |
2524 | /* |
2525 | * If RAM size, maxmem size and individual node mem sizes aren't aligned |
2526 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest |
2527 | * since we can't support such unaligned sizes with DRCONF_MEMORY. |
2528 | */ |
2529 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
2530 | { |
2531 | int i; |
2532 | |
2533 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2534 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT |
2535 | " is not aligned to %" PRIu64 " MiB" , |
2536 | machine->ram_size, |
2537 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
2538 | return; |
2539 | } |
2540 | |
2541 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2542 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT |
2543 | " is not aligned to %" PRIu64 " MiB" , |
2544 | machine->ram_size, |
2545 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
2546 | return; |
2547 | } |
2548 | |
2549 | for (i = 0; i < machine->numa_state->num_nodes; i++) { |
2550 | if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { |
2551 | error_setg(errp, |
2552 | "Node %d memory size 0x%" PRIx64 |
2553 | " is not aligned to %" PRIu64 " MiB" , |
2554 | i, machine->numa_state->nodes[i].node_mem, |
2555 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
2556 | return; |
2557 | } |
2558 | } |
2559 | } |
2560 | |
2561 | /* find cpu slot in machine->possible_cpus by core_id */ |
2562 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
2563 | { |
2564 | int index = id / ms->smp.threads; |
2565 | |
2566 | if (index >= ms->possible_cpus->len) { |
2567 | return NULL; |
2568 | } |
2569 | if (idx) { |
2570 | *idx = index; |
2571 | } |
2572 | return &ms->possible_cpus->cpus[index]; |
2573 | } |
2574 | |
2575 | static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) |
2576 | { |
2577 | MachineState *ms = MACHINE(spapr); |
2578 | Error *local_err = NULL; |
2579 | bool vsmt_user = !!spapr->vsmt; |
2580 | int kvm_smt = kvmppc_smt_threads(); |
2581 | int ret; |
2582 | unsigned int smp_threads = ms->smp.threads; |
2583 | |
2584 | if (!kvm_enabled() && (smp_threads > 1)) { |
2585 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " |
2586 | "on a pseries machine" ); |
2587 | goto out; |
2588 | } |
2589 | if (!is_power_of_2(smp_threads)) { |
2590 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " |
2591 | "machine because it must be a power of 2" , smp_threads); |
2592 | goto out; |
2593 | } |
2594 | |
2595 | /* Detemine the VSMT mode to use: */ |
2596 | if (vsmt_user) { |
2597 | if (spapr->vsmt < smp_threads) { |
2598 | error_setg(&local_err, "Cannot support VSMT mode %d" |
2599 | " because it must be >= threads/core (%d)" , |
2600 | spapr->vsmt, smp_threads); |
2601 | goto out; |
2602 | } |
2603 | /* In this case, spapr->vsmt has been set by the command line */ |
2604 | } else { |
2605 | /* |
2606 | * Default VSMT value is tricky, because we need it to be as |
2607 | * consistent as possible (for migration), but this requires |
2608 | * changing it for at least some existing cases. We pick 8 as |
2609 | * the value that we'd get with KVM on POWER8, the |
2610 | * overwhelmingly common case in production systems. |
2611 | */ |
2612 | spapr->vsmt = MAX(8, smp_threads); |
2613 | } |
2614 | |
2615 | /* KVM: If necessary, set the SMT mode: */ |
2616 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { |
2617 | ret = kvmppc_set_smt_threads(spapr->vsmt); |
2618 | if (ret) { |
2619 | /* Looks like KVM isn't able to change VSMT mode */ |
2620 | error_setg(&local_err, |
2621 | "Failed to set KVM's VSMT mode to %d (errno %d)" , |
2622 | spapr->vsmt, ret); |
2623 | /* We can live with that if the default one is big enough |
2624 | * for the number of threads, and a submultiple of the one |
2625 | * we want. In this case we'll waste some vcpu ids, but |
2626 | * behaviour will be correct */ |
2627 | if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { |
2628 | warn_report_err(local_err); |
2629 | local_err = NULL; |
2630 | goto out; |
2631 | } else { |
2632 | if (!vsmt_user) { |
2633 | error_append_hint(&local_err, |
2634 | "On PPC, a VM with %d threads/core" |
2635 | " on a host with %d threads/core" |
2636 | " requires the use of VSMT mode %d.\n" , |
2637 | smp_threads, kvm_smt, spapr->vsmt); |
2638 | } |
2639 | kvmppc_hint_smt_possible(&local_err); |
2640 | goto out; |
2641 | } |
2642 | } |
2643 | } |
2644 | /* else TCG: nothing to do currently */ |
2645 | out: |
2646 | error_propagate(errp, local_err); |
2647 | } |
2648 | |
2649 | static void spapr_init_cpus(SpaprMachineState *spapr) |
2650 | { |
2651 | MachineState *machine = MACHINE(spapr); |
2652 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
2653 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
2654 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); |
2655 | const CPUArchIdList *possible_cpus; |
2656 | unsigned int smp_cpus = machine->smp.cpus; |
2657 | unsigned int smp_threads = machine->smp.threads; |
2658 | unsigned int max_cpus = machine->smp.max_cpus; |
2659 | int boot_cores_nr = smp_cpus / smp_threads; |
2660 | int i; |
2661 | |
2662 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
2663 | if (mc->has_hotpluggable_cpus) { |
2664 | if (smp_cpus % smp_threads) { |
2665 | error_report("smp_cpus (%u) must be multiple of threads (%u)" , |
2666 | smp_cpus, smp_threads); |
2667 | exit(1); |
2668 | } |
2669 | if (max_cpus % smp_threads) { |
2670 | error_report("max_cpus (%u) must be multiple of threads (%u)" , |
2671 | max_cpus, smp_threads); |
2672 | exit(1); |
2673 | } |
2674 | } else { |
2675 | if (max_cpus != smp_cpus) { |
2676 | error_report("This machine version does not support CPU hotplug" ); |
2677 | exit(1); |
2678 | } |
2679 | boot_cores_nr = possible_cpus->len; |
2680 | } |
2681 | |
2682 | if (smc->pre_2_10_has_unused_icps) { |
2683 | int i; |
2684 | |
2685 | for (i = 0; i < spapr_max_server_number(spapr); i++) { |
2686 | /* Dummy entries get deregistered when real ICPState objects |
2687 | * are registered during CPU core hotplug. |
2688 | */ |
2689 | pre_2_10_vmstate_register_dummy_icp(i); |
2690 | } |
2691 | } |
2692 | |
2693 | for (i = 0; i < possible_cpus->len; i++) { |
2694 | int core_id = i * smp_threads; |
2695 | |
2696 | if (mc->has_hotpluggable_cpus) { |
2697 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, |
2698 | spapr_vcpu_id(spapr, core_id)); |
2699 | } |
2700 | |
2701 | if (i < boot_cores_nr) { |
2702 | Object *core = object_new(type); |
2703 | int nr_threads = smp_threads; |
2704 | |
2705 | /* Handle the partially filled core for older machine types */ |
2706 | if ((i + 1) * smp_threads >= smp_cpus) { |
2707 | nr_threads = smp_cpus - i * smp_threads; |
2708 | } |
2709 | |
2710 | object_property_set_int(core, nr_threads, "nr-threads" , |
2711 | &error_fatal); |
2712 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, |
2713 | &error_fatal); |
2714 | object_property_set_bool(core, true, "realized" , &error_fatal); |
2715 | |
2716 | object_unref(core); |
2717 | } |
2718 | } |
2719 | } |
2720 | |
2721 | static PCIHostState *spapr_create_default_phb(void) |
2722 | { |
2723 | DeviceState *dev; |
2724 | |
2725 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); |
2726 | qdev_prop_set_uint32(dev, "index" , 0); |
2727 | qdev_init_nofail(dev); |
2728 | |
2729 | return PCI_HOST_BRIDGE(dev); |
2730 | } |
2731 | |
2732 | /* pSeries LPAR / sPAPR hardware init */ |
2733 | static void spapr_machine_init(MachineState *machine) |
2734 | { |
2735 | SpaprMachineState *spapr = SPAPR_MACHINE(machine); |
2736 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
2737 | const char *kernel_filename = machine->kernel_filename; |
2738 | const char *initrd_filename = machine->initrd_filename; |
2739 | PCIHostState *phb; |
2740 | int i; |
2741 | MemoryRegion *sysmem = get_system_memory(); |
2742 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
2743 | hwaddr node0_size = spapr_node0_size(machine); |
2744 | long load_limit, fw_size; |
2745 | char *filename; |
2746 | Error *resize_hpt_err = NULL; |
2747 | |
2748 | msi_nonbroken = true; |
2749 | |
2750 | QLIST_INIT(&spapr->phbs); |
2751 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
2752 | |
2753 | /* Determine capabilities to run with */ |
2754 | spapr_caps_init(spapr); |
2755 | |
2756 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); |
2757 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { |
2758 | /* |
2759 | * If the user explicitly requested a mode we should either |
2760 | * supply it, or fail completely (which we do below). But if |
2761 | * it's not set explicitly, we reset our mode to something |
2762 | * that works |
2763 | */ |
2764 | if (resize_hpt_err) { |
2765 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; |
2766 | error_free(resize_hpt_err); |
2767 | resize_hpt_err = NULL; |
2768 | } else { |
2769 | spapr->resize_hpt = smc->resize_hpt_default; |
2770 | } |
2771 | } |
2772 | |
2773 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); |
2774 | |
2775 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { |
2776 | /* |
2777 | * User requested HPT resize, but this host can't supply it. Bail out |
2778 | */ |
2779 | error_report_err(resize_hpt_err); |
2780 | exit(1); |
2781 | } |
2782 | |
2783 | spapr->rma_size = node0_size; |
2784 | |
2785 | /* With KVM, we don't actually know whether KVM supports an |
2786 | * unbounded RMA (PR KVM) or is limited by the hash table size |
2787 | * (HV KVM using VRMA), so we always assume the latter |
2788 | * |
2789 | * In that case, we also limit the initial allocations for RTAS |
2790 | * etc... to 256M since we have no way to know what the VRMA size |
2791 | * is going to be as it depends on the size of the hash table |
2792 | * which isn't determined yet. |
2793 | */ |
2794 | if (kvm_enabled()) { |
2795 | spapr->vrma_adjust = 1; |
2796 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); |
2797 | } |
2798 | |
2799 | /* Actually we don't support unbounded RMA anymore since we added |
2800 | * proper emulation of HV mode. The max we can get is 16G which |
2801 | * also happens to be what we configure for PAPR mode so make sure |
2802 | * we don't do anything bigger than that |
2803 | */ |
2804 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); |
2805 | |
2806 | if (spapr->rma_size > node0_size) { |
2807 | error_report("Numa node 0 has to span the RMA (%#08" HWADDR_PRIx")" , |
2808 | spapr->rma_size); |
2809 | exit(1); |
2810 | } |
2811 | |
2812 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2813 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; |
2814 | |
2815 | /* |
2816 | * VSMT must be set in order to be able to compute VCPU ids, ie to |
2817 | * call spapr_max_server_number() or spapr_vcpu_id(). |
2818 | */ |
2819 | spapr_set_vsmt_mode(spapr, &error_fatal); |
2820 | |
2821 | /* Set up Interrupt Controller before we create the VCPUs */ |
2822 | spapr_irq_init(spapr, &error_fatal); |
2823 | |
2824 | /* Set up containers for ibm,client-architecture-support negotiated options |
2825 | */ |
2826 | spapr->ov5 = spapr_ovec_new(); |
2827 | spapr->ov5_cas = spapr_ovec_new(); |
2828 | |
2829 | if (smc->dr_lmb_enabled) { |
2830 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
2831 | spapr_validate_node_memory(machine, &error_fatal); |
2832 | } |
2833 | |
2834 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
2835 | |
2836 | /* advertise support for dedicated HP event source to guests */ |
2837 | if (spapr->use_hotplug_event_source) { |
2838 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); |
2839 | } |
2840 | |
2841 | /* advertise support for HPT resizing */ |
2842 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { |
2843 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); |
2844 | } |
2845 | |
2846 | /* advertise support for ibm,dyamic-memory-v2 */ |
2847 | spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); |
2848 | |
2849 | /* advertise XIVE on POWER9 machines */ |
2850 | if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { |
2851 | spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); |
2852 | } |
2853 | |
2854 | /* init CPUs */ |
2855 | spapr_init_cpus(spapr); |
2856 | |
2857 | if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && |
2858 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
2859 | spapr->max_compat_pvr)) { |
2860 | /* KVM and TCG always allow GTSE with radix... */ |
2861 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2862 | } |
2863 | /* ... but not with hash (currently). */ |
2864 | |
2865 | if (kvm_enabled()) { |
2866 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ |
2867 | kvmppc_enable_logical_ci_hcalls(); |
2868 | kvmppc_enable_set_mode_hcall(); |
2869 | |
2870 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ |
2871 | kvmppc_enable_clear_ref_mod_hcalls(); |
2872 | |
2873 | /* Enable H_PAGE_INIT */ |
2874 | kvmppc_enable_h_page_init(); |
2875 | } |
2876 | |
2877 | /* allocate RAM */ |
2878 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram" , |
2879 | machine->ram_size); |
2880 | memory_region_add_subregion(sysmem, 0, ram); |
2881 | |
2882 | /* always allocate the device memory information */ |
2883 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); |
2884 | |
2885 | /* initialize hotplug memory address space */ |
2886 | if (machine->ram_size < machine->maxram_size) { |
2887 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
2888 | /* |
2889 | * Limit the number of hotpluggable memory slots to half the number |
2890 | * slots that KVM supports, leaving the other half for PCI and other |
2891 | * devices. However ensure that number of slots doesn't drop below 32. |
2892 | */ |
2893 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : |
2894 | SPAPR_MAX_RAM_SLOTS; |
2895 | |
2896 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2897 | max_memslots = SPAPR_MAX_RAM_SLOTS; |
2898 | } |
2899 | if (machine->ram_slots > max_memslots) { |
2900 | error_report("Specified number of memory slots %" |
2901 | PRIu64" exceeds max supported %d" , |
2902 | machine->ram_slots, max_memslots); |
2903 | exit(1); |
2904 | } |
2905 | |
2906 | machine->device_memory->base = ROUND_UP(machine->ram_size, |
2907 | SPAPR_DEVICE_MEM_ALIGN); |
2908 | memory_region_init(&machine->device_memory->mr, OBJECT(spapr), |
2909 | "device-memory" , device_mem_size); |
2910 | memory_region_add_subregion(sysmem, machine->device_memory->base, |
2911 | &machine->device_memory->mr); |
2912 | } |
2913 | |
2914 | if (smc->dr_lmb_enabled) { |
2915 | spapr_create_lmb_dr_connectors(spapr); |
2916 | } |
2917 | |
2918 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin" ); |
2919 | if (!filename) { |
2920 | error_report("Could not find LPAR rtas '%s'" , "spapr-rtas.bin" ); |
2921 | exit(1); |
2922 | } |
2923 | spapr->rtas_size = get_image_size(filename); |
2924 | if (spapr->rtas_size < 0) { |
2925 | error_report("Could not get size of LPAR rtas '%s'" , filename); |
2926 | exit(1); |
2927 | } |
2928 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2929 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { |
2930 | error_report("Could not load LPAR rtas '%s'" , filename); |
2931 | exit(1); |
2932 | } |
2933 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
2934 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)" , |
2935 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); |
2936 | exit(1); |
2937 | } |
2938 | g_free(filename); |
2939 | |
2940 | /* Set up RTAS event infrastructure */ |
2941 | spapr_events_init(spapr); |
2942 | |
2943 | /* Set up the RTC RTAS interfaces */ |
2944 | spapr_rtc_create(spapr); |
2945 | |
2946 | /* Set up VIO bus */ |
2947 | spapr->vio_bus = spapr_vio_bus_init(); |
2948 | |
2949 | for (i = 0; i < serial_max_hds(); i++) { |
2950 | if (serial_hd(i)) { |
2951 | spapr_vty_create(spapr->vio_bus, serial_hd(i)); |
2952 | } |
2953 | } |
2954 | |
2955 | /* We always have at least the nvram device on VIO */ |
2956 | spapr_create_nvram(spapr); |
2957 | |
2958 | /* |
2959 | * Setup hotplug / dynamic-reconfiguration connectors. top-level |
2960 | * connectors (described in root DT node's "ibm,drc-types" property) |
2961 | * are pre-initialized here. additional child connectors (such as |
2962 | * connectors for a PHBs PCI slots) are added as needed during their |
2963 | * parent's realization. |
2964 | */ |
2965 | if (smc->dr_phb_enabled) { |
2966 | for (i = 0; i < SPAPR_MAX_PHBS; i++) { |
2967 | spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); |
2968 | } |
2969 | } |
2970 | |
2971 | /* Set up PCI */ |
2972 | spapr_pci_rtas_init(); |
2973 | |
2974 | phb = spapr_create_default_phb(); |
2975 | |
2976 | for (i = 0; i < nb_nics; i++) { |
2977 | NICInfo *nd = &nd_table[i]; |
2978 | |
2979 | if (!nd->model) { |
2980 | nd->model = g_strdup("spapr-vlan" ); |
2981 | } |
2982 | |
2983 | if (g_str_equal(nd->model, "spapr-vlan" ) || |
2984 | g_str_equal(nd->model, "ibmveth" )) { |
2985 | spapr_vlan_create(spapr->vio_bus, nd); |
2986 | } else { |
2987 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
2988 | } |
2989 | } |
2990 | |
2991 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
2992 | spapr_vscsi_create(spapr->vio_bus); |
2993 | } |
2994 | |
2995 | /* Graphics */ |
2996 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
2997 | spapr->has_graphics = true; |
2998 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
2999 | } |
3000 | |
3001 | if (machine->usb) { |
3002 | if (smc->use_ohci_by_default) { |
3003 | pci_create_simple(phb->bus, -1, "pci-ohci" ); |
3004 | } else { |
3005 | pci_create_simple(phb->bus, -1, "nec-usb-xhci" ); |
3006 | } |
3007 | |
3008 | if (spapr->has_graphics) { |
3009 | USBBus *usb_bus = usb_bus_find(-1); |
3010 | |
3011 | usb_create_simple(usb_bus, "usb-kbd" ); |
3012 | usb_create_simple(usb_bus, "usb-mouse" ); |
3013 | } |
3014 | } |
3015 | |
3016 | if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { |
3017 | error_report( |
3018 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)" , |
3019 | MIN_RMA_SLOF); |
3020 | exit(1); |
3021 | } |
3022 | |
3023 | if (kernel_filename) { |
3024 | uint64_t lowaddr = 0; |
3025 | |
3026 | spapr->kernel_size = load_elf(kernel_filename, NULL, |
3027 | translate_kernel_address, NULL, |
3028 | NULL, &lowaddr, NULL, 1, |
3029 | PPC_ELF_MACHINE, 0, 0); |
3030 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { |
3031 | spapr->kernel_size = load_elf(kernel_filename, NULL, |
3032 | translate_kernel_address, NULL, NULL, |
3033 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, |
3034 | 0, 0); |
3035 | spapr->kernel_le = spapr->kernel_size > 0; |
3036 | } |
3037 | if (spapr->kernel_size < 0) { |
3038 | error_report("error loading %s: %s" , kernel_filename, |
3039 | load_elf_strerror(spapr->kernel_size)); |
3040 | exit(1); |
3041 | } |
3042 | |
3043 | /* load initrd */ |
3044 | if (initrd_filename) { |
3045 | /* Try to locate the initrd in the gap between the kernel |
3046 | * and the firmware. Add a bit of space just in case |
3047 | */ |
3048 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
3049 | + 0x1ffff) & ~0xffff; |
3050 | spapr->initrd_size = load_image_targphys(initrd_filename, |
3051 | spapr->initrd_base, |
3052 | load_limit |
3053 | - spapr->initrd_base); |
3054 | if (spapr->initrd_size < 0) { |
3055 | error_report("could not load initial ram disk '%s'" , |
3056 | initrd_filename); |
3057 | exit(1); |
3058 | } |
3059 | } |
3060 | } |
3061 | |
3062 | if (bios_name == NULL) { |
3063 | bios_name = FW_FILE_NAME; |
3064 | } |
3065 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
3066 | if (!filename) { |
3067 | error_report("Could not find LPAR firmware '%s'" , bios_name); |
3068 | exit(1); |
3069 | } |
3070 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
3071 | if (fw_size <= 0) { |
3072 | error_report("Could not load LPAR firmware '%s'" , filename); |
3073 | exit(1); |
3074 | } |
3075 | g_free(filename); |
3076 | |
3077 | /* FIXME: Should register things through the MachineState's qdev |
3078 | * interface, this is a legacy from the sPAPREnvironment structure |
3079 | * which predated MachineState but had a similar function */ |
3080 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
3081 | register_savevm_live(NULL, "spapr/htab" , -1, 1, |
3082 | &savevm_htab_handlers, spapr); |
3083 | |
3084 | qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), |
3085 | &error_fatal); |
3086 | |
3087 | qemu_register_boot_set(spapr_boot_set, spapr); |
3088 | |
3089 | /* |
3090 | * Nothing needs to be done to resume a suspended guest because |
3091 | * suspending does not change the machine state, so no need for |
3092 | * a ->wakeup method. |
3093 | */ |
3094 | qemu_register_wakeup_support(); |
3095 | |
3096 | if (kvm_enabled()) { |
3097 | /* to stop and start vmclock */ |
3098 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
3099 | &spapr->tb); |
3100 | |
3101 | kvmppc_spapr_enable_inkernel_multitce(); |
3102 | } |
3103 | } |
3104 | |
3105 | static int spapr_kvm_type(MachineState *machine, const char *vm_type) |
3106 | { |
3107 | if (!vm_type) { |
3108 | return 0; |
3109 | } |
3110 | |
3111 | if (!strcmp(vm_type, "HV" )) { |
3112 | return 1; |
3113 | } |
3114 | |
3115 | if (!strcmp(vm_type, "PR" )) { |
3116 | return 2; |
3117 | } |
3118 | |
3119 | error_report("Unknown kvm-type specified '%s'" , vm_type); |
3120 | exit(1); |
3121 | } |
3122 | |
3123 | /* |
3124 | * Implementation of an interface to adjust firmware path |
3125 | * for the bootindex property handling. |
3126 | */ |
3127 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, |
3128 | DeviceState *dev) |
3129 | { |
3130 | #define CAST(type, obj, name) \ |
3131 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) |
3132 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); |
3133 | SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); |
3134 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
3135 | |
3136 | if (d) { |
3137 | void *spapr = CAST(void, bus->parent, "spapr-vscsi" ); |
3138 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); |
3139 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); |
3140 | |
3141 | if (spapr) { |
3142 | /* |
3143 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": |
3144 | * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form |
3145 | * 0x8000 | (target << 8) | (bus << 5) | lun |
3146 | * (see the "Logical unit addressing format" table in SAM5) |
3147 | */ |
3148 | unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; |
3149 | return g_strdup_printf("%s@%" PRIX64, qdev_fw_name(dev), |
3150 | (uint64_t)id << 48); |
3151 | } else if (virtio) { |
3152 | /* |
3153 | * We use SRP luns of the form 01000000 | (target << 8) | lun |
3154 | * in the top 32 bits of the 64-bit LUN |
3155 | * Note: the quote above is from SLOF and it is wrong, |
3156 | * the actual binding is: |
3157 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) |
3158 | */ |
3159 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; |
3160 | if (d->lun >= 256) { |
3161 | /* Use the LUN "flat space addressing method" */ |
3162 | id |= 0x4000; |
3163 | } |
3164 | return g_strdup_printf("%s@%" PRIX64, qdev_fw_name(dev), |
3165 | (uint64_t)id << 32); |
3166 | } else if (usb) { |
3167 | /* |
3168 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun |
3169 | * in the top 32 bits of the 64-bit LUN |
3170 | */ |
3171 | unsigned usb_port = atoi(usb->port->path); |
3172 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; |
3173 | return g_strdup_printf("%s@%" PRIX64, qdev_fw_name(dev), |
3174 | (uint64_t)id << 32); |
3175 | } |
3176 | } |
3177 | |
3178 | /* |
3179 | * SLOF probes the USB devices, and if it recognizes that the device is a |
3180 | * storage device, it changes its name to "storage" instead of "usb-host", |
3181 | * and additionally adds a child node for the SCSI LUN, so the correct |
3182 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. |
3183 | */ |
3184 | if (strcmp("usb-host" , qdev_fw_name(dev)) == 0) { |
3185 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); |
3186 | if (usb_host_dev_is_scsi_storage(usbdev)) { |
3187 | return g_strdup_printf("storage@%s/disk" , usbdev->port->path); |
3188 | } |
3189 | } |
3190 | |
3191 | if (phb) { |
3192 | /* Replace "pci" with "pci@800000020000000" */ |
3193 | return g_strdup_printf("pci@%" PRIX64, phb->buid); |
3194 | } |
3195 | |
3196 | if (vsc) { |
3197 | /* Same logic as virtio above */ |
3198 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; |
3199 | return g_strdup_printf("disk@%" PRIX64, (uint64_t)id << 32); |
3200 | } |
3201 | |
3202 | if (g_str_equal("pci-bridge" , qdev_fw_name(dev))) { |
3203 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ |
3204 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); |
3205 | return g_strdup_printf("pci@%x" , PCI_SLOT(pcidev->devfn)); |
3206 | } |
3207 | |
3208 | return NULL; |
3209 | } |
3210 | |
3211 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
3212 | { |
3213 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3214 | |
3215 | return g_strdup(spapr->kvm_type); |
3216 | } |
3217 | |
3218 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) |
3219 | { |
3220 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3221 | |
3222 | g_free(spapr->kvm_type); |
3223 | spapr->kvm_type = g_strdup(value); |
3224 | } |
3225 | |
3226 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
3227 | { |
3228 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3229 | |
3230 | return spapr->use_hotplug_event_source; |
3231 | } |
3232 | |
3233 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, |
3234 | Error **errp) |
3235 | { |
3236 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3237 | |
3238 | spapr->use_hotplug_event_source = value; |
3239 | } |
3240 | |
3241 | static bool spapr_get_msix_emulation(Object *obj, Error **errp) |
3242 | { |
3243 | return true; |
3244 | } |
3245 | |
3246 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
3247 | { |
3248 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3249 | |
3250 | switch (spapr->resize_hpt) { |
3251 | case SPAPR_RESIZE_HPT_DEFAULT: |
3252 | return g_strdup("default" ); |
3253 | case SPAPR_RESIZE_HPT_DISABLED: |
3254 | return g_strdup("disabled" ); |
3255 | case SPAPR_RESIZE_HPT_ENABLED: |
3256 | return g_strdup("enabled" ); |
3257 | case SPAPR_RESIZE_HPT_REQUIRED: |
3258 | return g_strdup("required" ); |
3259 | } |
3260 | g_assert_not_reached(); |
3261 | } |
3262 | |
3263 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) |
3264 | { |
3265 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3266 | |
3267 | if (strcmp(value, "default" ) == 0) { |
3268 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; |
3269 | } else if (strcmp(value, "disabled" ) == 0) { |
3270 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; |
3271 | } else if (strcmp(value, "enabled" ) == 0) { |
3272 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; |
3273 | } else if (strcmp(value, "required" ) == 0) { |
3274 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; |
3275 | } else { |
3276 | error_setg(errp, "Bad value for \"resize-hpt\" property" ); |
3277 | } |
3278 | } |
3279 | |
3280 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
3281 | void *opaque, Error **errp) |
3282 | { |
3283 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); |
3284 | } |
3285 | |
3286 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, |
3287 | void *opaque, Error **errp) |
3288 | { |
3289 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); |
3290 | } |
3291 | |
3292 | static char *spapr_get_ic_mode(Object *obj, Error **errp) |
3293 | { |
3294 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3295 | |
3296 | if (spapr->irq == &spapr_irq_xics_legacy) { |
3297 | return g_strdup("legacy" ); |
3298 | } else if (spapr->irq == &spapr_irq_xics) { |
3299 | return g_strdup("xics" ); |
3300 | } else if (spapr->irq == &spapr_irq_xive) { |
3301 | return g_strdup("xive" ); |
3302 | } else if (spapr->irq == &spapr_irq_dual) { |
3303 | return g_strdup("dual" ); |
3304 | } |
3305 | g_assert_not_reached(); |
3306 | } |
3307 | |
3308 | static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) |
3309 | { |
3310 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3311 | |
3312 | if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
3313 | error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode" ); |
3314 | return; |
3315 | } |
3316 | |
3317 | /* The legacy IRQ backend can not be set */ |
3318 | if (strcmp(value, "xics" ) == 0) { |
3319 | spapr->irq = &spapr_irq_xics; |
3320 | } else if (strcmp(value, "xive" ) == 0) { |
3321 | spapr->irq = &spapr_irq_xive; |
3322 | } else if (strcmp(value, "dual" ) == 0) { |
3323 | spapr->irq = &spapr_irq_dual; |
3324 | } else { |
3325 | error_setg(errp, "Bad value for \"ic-mode\" property" ); |
3326 | } |
3327 | } |
3328 | |
3329 | static char *spapr_get_host_model(Object *obj, Error **errp) |
3330 | { |
3331 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3332 | |
3333 | return g_strdup(spapr->host_model); |
3334 | } |
3335 | |
3336 | static void spapr_set_host_model(Object *obj, const char *value, Error **errp) |
3337 | { |
3338 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3339 | |
3340 | g_free(spapr->host_model); |
3341 | spapr->host_model = g_strdup(value); |
3342 | } |
3343 | |
3344 | static char *spapr_get_host_serial(Object *obj, Error **errp) |
3345 | { |
3346 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3347 | |
3348 | return g_strdup(spapr->host_serial); |
3349 | } |
3350 | |
3351 | static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) |
3352 | { |
3353 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3354 | |
3355 | g_free(spapr->host_serial); |
3356 | spapr->host_serial = g_strdup(value); |
3357 | } |
3358 | |
3359 | static void spapr_instance_init(Object *obj) |
3360 | { |
3361 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3362 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
3363 | |
3364 | spapr->htab_fd = -1; |
3365 | spapr->use_hotplug_event_source = true; |
3366 | object_property_add_str(obj, "kvm-type" , |
3367 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); |
3368 | object_property_set_description(obj, "kvm-type" , |
3369 | "Specifies the KVM virtualization mode (HV, PR)" , |
3370 | NULL); |
3371 | object_property_add_bool(obj, "modern-hotplug-events" , |
3372 | spapr_get_modern_hotplug_events, |
3373 | spapr_set_modern_hotplug_events, |
3374 | NULL); |
3375 | object_property_set_description(obj, "modern-hotplug-events" , |
3376 | "Use dedicated hotplug event mechanism in" |
3377 | " place of standard EPOW events when possible" |
3378 | " (required for memory hot-unplug support)" , |
3379 | NULL); |
3380 | ppc_compat_add_property(obj, "max-cpu-compat" , &spapr->max_compat_pvr, |
3381 | "Maximum permitted CPU compatibility mode" , |
3382 | &error_fatal); |
3383 | |
3384 | object_property_add_str(obj, "resize-hpt" , |
3385 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); |
3386 | object_property_set_description(obj, "resize-hpt" , |
3387 | "Resizing of the Hash Page Table (enabled, disabled, required)" , |
3388 | NULL); |
3389 | object_property_add(obj, "vsmt" , "uint32" , spapr_get_vsmt, |
3390 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); |
3391 | object_property_set_description(obj, "vsmt" , |
3392 | "Virtual SMT: KVM behaves as if this were" |
3393 | " the host's SMT mode" , &error_abort); |
3394 | object_property_add_bool(obj, "vfio-no-msix-emulation" , |
3395 | spapr_get_msix_emulation, NULL, NULL); |
3396 | |
3397 | /* The machine class defines the default interrupt controller mode */ |
3398 | spapr->irq = smc->irq; |
3399 | object_property_add_str(obj, "ic-mode" , spapr_get_ic_mode, |
3400 | spapr_set_ic_mode, NULL); |
3401 | object_property_set_description(obj, "ic-mode" , |
3402 | "Specifies the interrupt controller mode (xics, xive, dual)" , |
3403 | NULL); |
3404 | |
3405 | object_property_add_str(obj, "host-model" , |
3406 | spapr_get_host_model, spapr_set_host_model, |
3407 | &error_abort); |
3408 | object_property_set_description(obj, "host-model" , |
3409 | "Host model to advertise in guest device tree" , &error_abort); |
3410 | object_property_add_str(obj, "host-serial" , |
3411 | spapr_get_host_serial, spapr_set_host_serial, |
3412 | &error_abort); |
3413 | object_property_set_description(obj, "host-serial" , |
3414 | "Host serial number to advertise in guest device tree" , &error_abort); |
3415 | } |
3416 | |
3417 | static void spapr_machine_finalizefn(Object *obj) |
3418 | { |
3419 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3420 | |
3421 | g_free(spapr->kvm_type); |
3422 | } |
3423 | |
3424 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
3425 | { |
3426 | cpu_synchronize_state(cs); |
3427 | ppc_cpu_do_system_reset(cs); |
3428 | } |
3429 | |
3430 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) |
3431 | { |
3432 | CPUState *cs; |
3433 | |
3434 | CPU_FOREACH(cs) { |
3435 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
3436 | } |
3437 | } |
3438 | |
3439 | int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
3440 | void *fdt, int *fdt_start_offset, Error **errp) |
3441 | { |
3442 | uint64_t addr; |
3443 | uint32_t node; |
3444 | |
3445 | addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; |
3446 | node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, |
3447 | &error_abort); |
3448 | *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, |
3449 | SPAPR_MEMORY_BLOCK_SIZE); |
3450 | return 0; |
3451 | } |
3452 | |
3453 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
3454 | bool dedicated_hp_event_source, Error **errp) |
3455 | { |
3456 | SpaprDrc *drc; |
3457 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
3458 | int i; |
3459 | uint64_t addr = addr_start; |
3460 | bool hotplugged = spapr_drc_hotplugged(dev); |
3461 | Error *local_err = NULL; |
3462 | |
3463 | for (i = 0; i < nr_lmbs; i++) { |
3464 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3465 | addr / SPAPR_MEMORY_BLOCK_SIZE); |
3466 | g_assert(drc); |
3467 | |
3468 | spapr_drc_attach(drc, dev, &local_err); |
3469 | if (local_err) { |
3470 | while (addr > addr_start) { |
3471 | addr -= SPAPR_MEMORY_BLOCK_SIZE; |
3472 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3473 | addr / SPAPR_MEMORY_BLOCK_SIZE); |
3474 | spapr_drc_detach(drc); |
3475 | } |
3476 | error_propagate(errp, local_err); |
3477 | return; |
3478 | } |
3479 | if (!hotplugged) { |
3480 | spapr_drc_reset(drc); |
3481 | } |
3482 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3483 | } |
3484 | /* send hotplug notification to the |
3485 | * guest only in case of hotplugged memory |
3486 | */ |
3487 | if (hotplugged) { |
3488 | if (dedicated_hp_event_source) { |
3489 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3490 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); |
3491 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3492 | nr_lmbs, |
3493 | spapr_drc_index(drc)); |
3494 | } else { |
3495 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3496 | nr_lmbs); |
3497 | } |
3498 | } |
3499 | } |
3500 | |
3501 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3502 | Error **errp) |
3503 | { |
3504 | Error *local_err = NULL; |
3505 | SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); |
3506 | PCDIMMDevice *dimm = PC_DIMM(dev); |
3507 | uint64_t size, addr; |
3508 | |
3509 | size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); |
3510 | |
3511 | pc_dimm_plug(dimm, MACHINE(ms), &local_err); |
3512 | if (local_err) { |
3513 | goto out; |
3514 | } |
3515 | |
3516 | addr = object_property_get_uint(OBJECT(dimm), |
3517 | PC_DIMM_ADDR_PROP, &local_err); |
3518 | if (local_err) { |
3519 | goto out_unplug; |
3520 | } |
3521 | |
3522 | spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), |
3523 | &local_err); |
3524 | if (local_err) { |
3525 | goto out_unplug; |
3526 | } |
3527 | |
3528 | return; |
3529 | |
3530 | out_unplug: |
3531 | pc_dimm_unplug(dimm, MACHINE(ms)); |
3532 | out: |
3533 | error_propagate(errp, local_err); |
3534 | } |
3535 | |
3536 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3537 | Error **errp) |
3538 | { |
3539 | const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); |
3540 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
3541 | PCDIMMDevice *dimm = PC_DIMM(dev); |
3542 | Error *local_err = NULL; |
3543 | uint64_t size; |
3544 | Object *memdev; |
3545 | hwaddr pagesize; |
3546 | |
3547 | if (!smc->dr_lmb_enabled) { |
3548 | error_setg(errp, "Memory hotplug not supported for this machine" ); |
3549 | return; |
3550 | } |
3551 | |
3552 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); |
3553 | if (local_err) { |
3554 | error_propagate(errp, local_err); |
3555 | return; |
3556 | } |
3557 | |
3558 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3559 | error_setg(errp, "Hotplugged memory size must be a multiple of " |
3560 | "%" PRIu64 " MB" , SPAPR_MEMORY_BLOCK_SIZE / MiB); |
3561 | return; |
3562 | } |
3563 | |
3564 | memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, |
3565 | &error_abort); |
3566 | pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); |
3567 | spapr_check_pagesize(spapr, pagesize, &local_err); |
3568 | if (local_err) { |
3569 | error_propagate(errp, local_err); |
3570 | return; |
3571 | } |
3572 | |
3573 | pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); |
3574 | } |
3575 | |
3576 | struct SpaprDimmState { |
3577 | PCDIMMDevice *dimm; |
3578 | uint32_t nr_lmbs; |
3579 | QTAILQ_ENTRY(SpaprDimmState) next; |
3580 | }; |
3581 | |
3582 | static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, |
3583 | PCDIMMDevice *dimm) |
3584 | { |
3585 | SpaprDimmState *dimm_state = NULL; |
3586 | |
3587 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { |
3588 | if (dimm_state->dimm == dimm) { |
3589 | break; |
3590 | } |
3591 | } |
3592 | return dimm_state; |
3593 | } |
3594 | |
3595 | static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, |
3596 | uint32_t nr_lmbs, |
3597 | PCDIMMDevice *dimm) |
3598 | { |
3599 | SpaprDimmState *ds = NULL; |
3600 | |
3601 | /* |
3602 | * If this request is for a DIMM whose removal had failed earlier |
3603 | * (due to guest's refusal to remove the LMBs), we would have this |
3604 | * dimm already in the pending_dimm_unplugs list. In that |
3605 | * case don't add again. |
3606 | */ |
3607 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); |
3608 | if (!ds) { |
3609 | ds = g_malloc0(sizeof(SpaprDimmState)); |
3610 | ds->nr_lmbs = nr_lmbs; |
3611 | ds->dimm = dimm; |
3612 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); |
3613 | } |
3614 | return ds; |
3615 | } |
3616 | |
3617 | static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, |
3618 | SpaprDimmState *dimm_state) |
3619 | { |
3620 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); |
3621 | g_free(dimm_state); |
3622 | } |
3623 | |
3624 | static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, |
3625 | PCDIMMDevice *dimm) |
3626 | { |
3627 | SpaprDrc *drc; |
3628 | uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), |
3629 | &error_abort); |
3630 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3631 | uint32_t avail_lmbs = 0; |
3632 | uint64_t addr_start, addr; |
3633 | int i; |
3634 | |
3635 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
3636 | &error_abort); |
3637 | |
3638 | addr = addr_start; |
3639 | for (i = 0; i < nr_lmbs; i++) { |
3640 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3641 | addr / SPAPR_MEMORY_BLOCK_SIZE); |
3642 | g_assert(drc); |
3643 | if (drc->dev) { |
3644 | avail_lmbs++; |
3645 | } |
3646 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3647 | } |
3648 | |
3649 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
3650 | } |
3651 | |
3652 | /* Callback to be called during DRC release. */ |
3653 | void spapr_lmb_release(DeviceState *dev) |
3654 | { |
3655 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3656 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); |
3657 | SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
3658 | |
3659 | /* This information will get lost if a migration occurs |
3660 | * during the unplug process. In this case recover it. */ |
3661 | if (ds == NULL) { |
3662 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); |
3663 | g_assert(ds); |
3664 | /* The DRC being examined by the caller at least must be counted */ |
3665 | g_assert(ds->nr_lmbs); |
3666 | } |
3667 | |
3668 | if (--ds->nr_lmbs) { |
3669 | return; |
3670 | } |
3671 | |
3672 | /* |
3673 | * Now that all the LMBs have been removed by the guest, call the |
3674 | * unplug handler chain. This can never fail. |
3675 | */ |
3676 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
3677 | object_unparent(OBJECT(dev)); |
3678 | } |
3679 | |
3680 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) |
3681 | { |
3682 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
3683 | SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
3684 | |
3685 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); |
3686 | object_property_set_bool(OBJECT(dev), false, "realized" , NULL); |
3687 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
3688 | } |
3689 | |
3690 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, |
3691 | DeviceState *dev, Error **errp) |
3692 | { |
3693 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
3694 | Error *local_err = NULL; |
3695 | PCDIMMDevice *dimm = PC_DIMM(dev); |
3696 | uint32_t nr_lmbs; |
3697 | uint64_t size, addr_start, addr; |
3698 | int i; |
3699 | SpaprDrc *drc; |
3700 | |
3701 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); |
3702 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3703 | |
3704 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
3705 | &local_err); |
3706 | if (local_err) { |
3707 | goto out; |
3708 | } |
3709 | |
3710 | /* |
3711 | * An existing pending dimm state for this DIMM means that there is an |
3712 | * unplug operation in progress, waiting for the spapr_lmb_release |
3713 | * callback to complete the job (BQL can't cover that far). In this case, |
3714 | * bail out to avoid detaching DRCs that were already released. |
3715 | */ |
3716 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { |
3717 | error_setg(&local_err, |
3718 | "Memory unplug already in progress for device %s" , |
3719 | dev->id); |
3720 | goto out; |
3721 | } |
3722 | |
3723 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
3724 | |
3725 | addr = addr_start; |
3726 | for (i = 0; i < nr_lmbs; i++) { |
3727 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3728 | addr / SPAPR_MEMORY_BLOCK_SIZE); |
3729 | g_assert(drc); |
3730 | |
3731 | spapr_drc_detach(drc); |
3732 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3733 | } |
3734 | |
3735 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3736 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); |
3737 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3738 | nr_lmbs, spapr_drc_index(drc)); |
3739 | out: |
3740 | error_propagate(errp, local_err); |
3741 | } |
3742 | |
3743 | /* Callback to be called during DRC release. */ |
3744 | void spapr_core_release(DeviceState *dev) |
3745 | { |
3746 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3747 | |
3748 | /* Call the unplug handler chain. This can never fail. */ |
3749 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
3750 | object_unparent(OBJECT(dev)); |
3751 | } |
3752 | |
3753 | static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) |
3754 | { |
3755 | MachineState *ms = MACHINE(hotplug_dev); |
3756 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
3757 | CPUCore *cc = CPU_CORE(dev); |
3758 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
3759 | |
3760 | if (smc->pre_2_10_has_unused_icps) { |
3761 | SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); |
3762 | int i; |
3763 | |
3764 | for (i = 0; i < cc->nr_threads; i++) { |
3765 | CPUState *cs = CPU(sc->threads[i]); |
3766 | |
3767 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); |
3768 | } |
3769 | } |
3770 | |
3771 | assert(core_slot); |
3772 | core_slot->cpu = NULL; |
3773 | object_property_set_bool(OBJECT(dev), false, "realized" , NULL); |
3774 | } |
3775 | |
3776 | static |
3777 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, |
3778 | Error **errp) |
3779 | { |
3780 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3781 | int index; |
3782 | SpaprDrc *drc; |
3783 | CPUCore *cc = CPU_CORE(dev); |
3784 | |
3785 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3786 | error_setg(errp, "Unable to find CPU core with core-id: %d" , |
3787 | cc->core_id); |
3788 | return; |
3789 | } |
3790 | if (index == 0) { |
3791 | error_setg(errp, "Boot CPU core may not be unplugged" ); |
3792 | return; |
3793 | } |
3794 | |
3795 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3796 | spapr_vcpu_id(spapr, cc->core_id)); |
3797 | g_assert(drc); |
3798 | |
3799 | spapr_drc_detach(drc); |
3800 | |
3801 | spapr_hotplug_req_remove_by_index(drc); |
3802 | } |
3803 | |
3804 | int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
3805 | void *fdt, int *fdt_start_offset, Error **errp) |
3806 | { |
3807 | SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); |
3808 | CPUState *cs = CPU(core->threads[0]); |
3809 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
3810 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
3811 | int id = spapr_get_vcpu_id(cpu); |
3812 | char *nodename; |
3813 | int offset; |
3814 | |
3815 | nodename = g_strdup_printf("%s@%x" , dc->fw_name, id); |
3816 | offset = fdt_add_subnode(fdt, 0, nodename); |
3817 | g_free(nodename); |
3818 | |
3819 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); |
3820 | |
3821 | *fdt_start_offset = offset; |
3822 | return 0; |
3823 | } |
3824 | |
3825 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3826 | Error **errp) |
3827 | { |
3828 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3829 | MachineClass *mc = MACHINE_GET_CLASS(spapr); |
3830 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3831 | SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3832 | CPUCore *cc = CPU_CORE(dev); |
3833 | CPUState *cs; |
3834 | SpaprDrc *drc; |
3835 | Error *local_err = NULL; |
3836 | CPUArchId *core_slot; |
3837 | int index; |
3838 | bool hotplugged = spapr_drc_hotplugged(dev); |
3839 | int i; |
3840 | |
3841 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3842 | if (!core_slot) { |
3843 | error_setg(errp, "Unable to find CPU core with core-id: %d" , |
3844 | cc->core_id); |
3845 | return; |
3846 | } |
3847 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3848 | spapr_vcpu_id(spapr, cc->core_id)); |
3849 | |
3850 | g_assert(drc || !mc->has_hotpluggable_cpus); |
3851 | |
3852 | if (drc) { |
3853 | spapr_drc_attach(drc, dev, &local_err); |
3854 | if (local_err) { |
3855 | error_propagate(errp, local_err); |
3856 | return; |
3857 | } |
3858 | |
3859 | if (hotplugged) { |
3860 | /* |
3861 | * Send hotplug notification interrupt to the guest only |
3862 | * in case of hotplugged CPUs. |
3863 | */ |
3864 | spapr_hotplug_req_add_by_index(drc); |
3865 | } else { |
3866 | spapr_drc_reset(drc); |
3867 | } |
3868 | } |
3869 | |
3870 | core_slot->cpu = OBJECT(dev); |
3871 | |
3872 | if (smc->pre_2_10_has_unused_icps) { |
3873 | for (i = 0; i < cc->nr_threads; i++) { |
3874 | cs = CPU(core->threads[i]); |
3875 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3876 | } |
3877 | } |
3878 | |
3879 | /* |
3880 | * Set compatibility mode to match the boot CPU, which was either set |
3881 | * by the machine reset code or by CAS. |
3882 | */ |
3883 | if (hotplugged) { |
3884 | for (i = 0; i < cc->nr_threads; i++) { |
3885 | ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, |
3886 | &local_err); |
3887 | if (local_err) { |
3888 | error_propagate(errp, local_err); |
3889 | return; |
3890 | } |
3891 | } |
3892 | } |
3893 | } |
3894 | |
3895 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3896 | Error **errp) |
3897 | { |
3898 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); |
3899 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); |
3900 | Error *local_err = NULL; |
3901 | CPUCore *cc = CPU_CORE(dev); |
3902 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
3903 | const char *type = object_get_typename(OBJECT(dev)); |
3904 | CPUArchId *core_slot; |
3905 | int index; |
3906 | unsigned int smp_threads = machine->smp.threads; |
3907 | |
3908 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
3909 | error_setg(&local_err, "CPU hotplug not supported for this machine" ); |
3910 | goto out; |
3911 | } |
3912 | |
3913 | if (strcmp(base_core_type, type)) { |
3914 | error_setg(&local_err, "CPU core type should be %s" , base_core_type); |
3915 | goto out; |
3916 | } |
3917 | |
3918 | if (cc->core_id % smp_threads) { |
3919 | error_setg(&local_err, "invalid core id %d" , cc->core_id); |
3920 | goto out; |
3921 | } |
3922 | |
3923 | /* |
3924 | * In general we should have homogeneous threads-per-core, but old |
3925 | * (pre hotplug support) machine types allow the last core to have |
3926 | * reduced threads as a compatibility hack for when we allowed |
3927 | * total vcpus not a multiple of threads-per-core. |
3928 | */ |
3929 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { |
3930 | error_setg(&local_err, "invalid nr-threads %d, must be %d" , |
3931 | cc->nr_threads, smp_threads); |
3932 | goto out; |
3933 | } |
3934 | |
3935 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3936 | if (!core_slot) { |
3937 | error_setg(&local_err, "core id %d out of range" , cc->core_id); |
3938 | goto out; |
3939 | } |
3940 | |
3941 | if (core_slot->cpu) { |
3942 | error_setg(&local_err, "core %d already populated" , cc->core_id); |
3943 | goto out; |
3944 | } |
3945 | |
3946 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
3947 | |
3948 | out: |
3949 | error_propagate(errp, local_err); |
3950 | } |
3951 | |
3952 | int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
3953 | void *fdt, int *fdt_start_offset, Error **errp) |
3954 | { |
3955 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); |
3956 | int intc_phandle; |
3957 | |
3958 | intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); |
3959 | if (intc_phandle <= 0) { |
3960 | return -1; |
3961 | } |
3962 | |
3963 | if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis, |
3964 | fdt_start_offset)) { |
3965 | error_setg(errp, "unable to create FDT node for PHB %d" , sphb->index); |
3966 | return -1; |
3967 | } |
3968 | |
3969 | /* generally SLOF creates these, for hotplug it's up to QEMU */ |
3970 | _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name" , "pci" )); |
3971 | |
3972 | return 0; |
3973 | } |
3974 | |
3975 | static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3976 | Error **errp) |
3977 | { |
3978 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3979 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); |
3980 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
3981 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); |
3982 | |
3983 | if (dev->hotplugged && !smc->dr_phb_enabled) { |
3984 | error_setg(errp, "PHB hotplug not supported for this machine" ); |
3985 | return; |
3986 | } |
3987 | |
3988 | if (sphb->index == (uint32_t)-1) { |
3989 | error_setg(errp, "\"index\" for PAPR PHB is mandatory" ); |
3990 | return; |
3991 | } |
3992 | |
3993 | /* |
3994 | * This will check that sphb->index doesn't exceed the maximum number of |
3995 | * PHBs for the current machine type. |
3996 | */ |
3997 | smc->phb_placement(spapr, sphb->index, |
3998 | &sphb->buid, &sphb->io_win_addr, |
3999 | &sphb->mem_win_addr, &sphb->mem64_win_addr, |
4000 | windows_supported, sphb->dma_liobn, |
4001 | &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, |
4002 | errp); |
4003 | } |
4004 | |
4005 | static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
4006 | Error **errp) |
4007 | { |
4008 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
4009 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
4010 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); |
4011 | SpaprDrc *drc; |
4012 | bool hotplugged = spapr_drc_hotplugged(dev); |
4013 | Error *local_err = NULL; |
4014 | |
4015 | if (!smc->dr_phb_enabled) { |
4016 | return; |
4017 | } |
4018 | |
4019 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); |
4020 | /* hotplug hooks should check it's enabled before getting this far */ |
4021 | assert(drc); |
4022 | |
4023 | spapr_drc_attach(drc, DEVICE(dev), &local_err); |
4024 | if (local_err) { |
4025 | error_propagate(errp, local_err); |
4026 | return; |
4027 | } |
4028 | |
4029 | if (hotplugged) { |
4030 | spapr_hotplug_req_add_by_index(drc); |
4031 | } else { |
4032 | spapr_drc_reset(drc); |
4033 | } |
4034 | } |
4035 | |
4036 | void spapr_phb_release(DeviceState *dev) |
4037 | { |
4038 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
4039 | |
4040 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
4041 | object_unparent(OBJECT(dev)); |
4042 | } |
4043 | |
4044 | static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) |
4045 | { |
4046 | object_property_set_bool(OBJECT(dev), false, "realized" , NULL); |
4047 | } |
4048 | |
4049 | static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, |
4050 | DeviceState *dev, Error **errp) |
4051 | { |
4052 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); |
4053 | SpaprDrc *drc; |
4054 | |
4055 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); |
4056 | assert(drc); |
4057 | |
4058 | if (!spapr_drc_unplug_requested(drc)) { |
4059 | spapr_drc_detach(drc); |
4060 | spapr_hotplug_req_remove_by_index(drc); |
4061 | } |
4062 | } |
4063 | |
4064 | static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
4065 | Error **errp) |
4066 | { |
4067 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
4068 | SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); |
4069 | |
4070 | if (spapr->tpm_proxy != NULL) { |
4071 | error_setg(errp, "Only one TPM proxy can be specified for this machine" ); |
4072 | return; |
4073 | } |
4074 | |
4075 | spapr->tpm_proxy = tpm_proxy; |
4076 | } |
4077 | |
4078 | static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) |
4079 | { |
4080 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
4081 | |
4082 | object_property_set_bool(OBJECT(dev), false, "realized" , NULL); |
4083 | object_unparent(OBJECT(dev)); |
4084 | spapr->tpm_proxy = NULL; |
4085 | } |
4086 | |
4087 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
4088 | DeviceState *dev, Error **errp) |
4089 | { |
4090 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4091 | spapr_memory_plug(hotplug_dev, dev, errp); |
4092 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4093 | spapr_core_plug(hotplug_dev, dev, errp); |
4094 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4095 | spapr_phb_plug(hotplug_dev, dev, errp); |
4096 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4097 | spapr_tpm_proxy_plug(hotplug_dev, dev, errp); |
4098 | } |
4099 | } |
4100 | |
4101 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, |
4102 | DeviceState *dev, Error **errp) |
4103 | { |
4104 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4105 | spapr_memory_unplug(hotplug_dev, dev); |
4106 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4107 | spapr_core_unplug(hotplug_dev, dev); |
4108 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4109 | spapr_phb_unplug(hotplug_dev, dev); |
4110 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4111 | spapr_tpm_proxy_unplug(hotplug_dev, dev); |
4112 | } |
4113 | } |
4114 | |
4115 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
4116 | DeviceState *dev, Error **errp) |
4117 | { |
4118 | SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
4119 | MachineClass *mc = MACHINE_GET_CLASS(sms); |
4120 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4121 | |
4122 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4123 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { |
4124 | spapr_memory_unplug_request(hotplug_dev, dev, errp); |
4125 | } else { |
4126 | /* NOTE: this means there is a window after guest reset, prior to |
4127 | * CAS negotiation, where unplug requests will fail due to the |
4128 | * capability not being detected yet. This is a bit different than |
4129 | * the case with PCI unplug, where the events will be queued and |
4130 | * eventually handled by the guest after boot |
4131 | */ |
4132 | error_setg(errp, "Memory hot unplug not supported for this guest" ); |
4133 | } |
4134 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4135 | if (!mc->has_hotpluggable_cpus) { |
4136 | error_setg(errp, "CPU hot unplug not supported on this machine" ); |
4137 | return; |
4138 | } |
4139 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
4140 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4141 | if (!smc->dr_phb_enabled) { |
4142 | error_setg(errp, "PHB hot unplug not supported on this machine" ); |
4143 | return; |
4144 | } |
4145 | spapr_phb_unplug_request(hotplug_dev, dev, errp); |
4146 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4147 | spapr_tpm_proxy_unplug(hotplug_dev, dev); |
4148 | } |
4149 | } |
4150 | |
4151 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
4152 | DeviceState *dev, Error **errp) |
4153 | { |
4154 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4155 | spapr_memory_pre_plug(hotplug_dev, dev, errp); |
4156 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4157 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
4158 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4159 | spapr_phb_pre_plug(hotplug_dev, dev, errp); |
4160 | } |
4161 | } |
4162 | |
4163 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
4164 | DeviceState *dev) |
4165 | { |
4166 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
4167 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || |
4168 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || |
4169 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4170 | return HOTPLUG_HANDLER(machine); |
4171 | } |
4172 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
4173 | PCIDevice *pcidev = PCI_DEVICE(dev); |
4174 | PCIBus *root = pci_device_root_bus(pcidev); |
4175 | SpaprPhbState *phb = |
4176 | (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), |
4177 | TYPE_SPAPR_PCI_HOST_BRIDGE); |
4178 | |
4179 | if (phb) { |
4180 | return HOTPLUG_HANDLER(phb); |
4181 | } |
4182 | } |
4183 | return NULL; |
4184 | } |
4185 | |
4186 | static CpuInstanceProperties |
4187 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) |
4188 | { |
4189 | CPUArchId *core_slot; |
4190 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
4191 | |
4192 | /* make sure possible_cpu are intialized */ |
4193 | mc->possible_cpu_arch_ids(machine); |
4194 | /* get CPU core slot containing thread that matches cpu_index */ |
4195 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); |
4196 | assert(core_slot); |
4197 | return core_slot->props; |
4198 | } |
4199 | |
4200 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
4201 | { |
4202 | return idx / ms->smp.cores % ms->numa_state->num_nodes; |
4203 | } |
4204 | |
4205 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
4206 | { |
4207 | int i; |
4208 | unsigned int smp_threads = machine->smp.threads; |
4209 | unsigned int smp_cpus = machine->smp.cpus; |
4210 | const char *core_type; |
4211 | int spapr_max_cores = machine->smp.max_cpus / smp_threads; |
4212 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
4213 | |
4214 | if (!mc->has_hotpluggable_cpus) { |
4215 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
4216 | } |
4217 | if (machine->possible_cpus) { |
4218 | assert(machine->possible_cpus->len == spapr_max_cores); |
4219 | return machine->possible_cpus; |
4220 | } |
4221 | |
4222 | core_type = spapr_get_cpu_core_type(machine->cpu_type); |
4223 | if (!core_type) { |
4224 | error_report("Unable to find sPAPR CPU Core definition" ); |
4225 | exit(1); |
4226 | } |
4227 | |
4228 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
4229 | sizeof(CPUArchId) * spapr_max_cores); |
4230 | machine->possible_cpus->len = spapr_max_cores; |
4231 | for (i = 0; i < machine->possible_cpus->len; i++) { |
4232 | int core_id = i * smp_threads; |
4233 | |
4234 | machine->possible_cpus->cpus[i].type = core_type; |
4235 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
4236 | machine->possible_cpus->cpus[i].arch_id = core_id; |
4237 | machine->possible_cpus->cpus[i].props.has_core_id = true; |
4238 | machine->possible_cpus->cpus[i].props.core_id = core_id; |
4239 | } |
4240 | return machine->possible_cpus; |
4241 | } |
4242 | |
4243 | static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, |
4244 | uint64_t *buid, hwaddr *pio, |
4245 | hwaddr *mmio32, hwaddr *mmio64, |
4246 | unsigned n_dma, uint32_t *liobns, |
4247 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) |
4248 | { |
4249 | /* |
4250 | * New-style PHB window placement. |
4251 | * |
4252 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window |
4253 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO |
4254 | * windows. |
4255 | * |
4256 | * Some guest kernels can't work with MMIO windows above 1<<46 |
4257 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB |
4258 | * |
4259 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each |
4260 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the |
4261 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the |
4262 | * 1TiB 64-bit MMIO windows for each PHB. |
4263 | */ |
4264 | const uint64_t base_buid = 0x800000020000000ULL; |
4265 | int i; |
4266 | |
4267 | /* Sanity check natural alignments */ |
4268 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); |
4269 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); |
4270 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); |
4271 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); |
4272 | /* Sanity check bounds */ |
4273 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
4274 | SPAPR_PCI_MEM32_WIN_SIZE); |
4275 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > |
4276 | SPAPR_PCI_MEM64_WIN_SIZE); |
4277 | |
4278 | if (index >= SPAPR_MAX_PHBS) { |
4279 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)" , |
4280 | SPAPR_MAX_PHBS - 1); |
4281 | return; |
4282 | } |
4283 | |
4284 | *buid = base_buid + index; |
4285 | for (i = 0; i < n_dma; ++i) { |
4286 | liobns[i] = SPAPR_PCI_LIOBN(index, i); |
4287 | } |
4288 | |
4289 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
4290 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; |
4291 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; |
4292 | |
4293 | *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; |
4294 | *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; |
4295 | } |
4296 | |
4297 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
4298 | { |
4299 | SpaprMachineState *spapr = SPAPR_MACHINE(dev); |
4300 | |
4301 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; |
4302 | } |
4303 | |
4304 | static void spapr_ics_resend(XICSFabric *dev) |
4305 | { |
4306 | SpaprMachineState *spapr = SPAPR_MACHINE(dev); |
4307 | |
4308 | ics_resend(spapr->ics); |
4309 | } |
4310 | |
4311 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
4312 | { |
4313 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
4314 | |
4315 | return cpu ? spapr_cpu_state(cpu)->icp : NULL; |
4316 | } |
4317 | |
4318 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
4319 | Monitor *mon) |
4320 | { |
4321 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
4322 | |
4323 | spapr->irq->print_info(spapr, mon); |
4324 | } |
4325 | |
4326 | int spapr_get_vcpu_id(PowerPCCPU *cpu) |
4327 | { |
4328 | return cpu->vcpu_id; |
4329 | } |
4330 | |
4331 | void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) |
4332 | { |
4333 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
4334 | MachineState *ms = MACHINE(spapr); |
4335 | int vcpu_id; |
4336 | |
4337 | vcpu_id = spapr_vcpu_id(spapr, cpu_index); |
4338 | |
4339 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { |
4340 | error_setg(errp, "Can't create CPU with id %d in KVM" , vcpu_id); |
4341 | error_append_hint(errp, "Adjust the number of cpus to %d " |
4342 | "or try to raise the number of threads per core\n" , |
4343 | vcpu_id * ms->smp.threads / spapr->vsmt); |
4344 | return; |
4345 | } |
4346 | |
4347 | cpu->vcpu_id = vcpu_id; |
4348 | } |
4349 | |
4350 | PowerPCCPU *spapr_find_cpu(int vcpu_id) |
4351 | { |
4352 | CPUState *cs; |
4353 | |
4354 | CPU_FOREACH(cs) { |
4355 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
4356 | |
4357 | if (spapr_get_vcpu_id(cpu) == vcpu_id) { |
4358 | return cpu; |
4359 | } |
4360 | } |
4361 | |
4362 | return NULL; |
4363 | } |
4364 | |
4365 | static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) |
4366 | { |
4367 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
4368 | |
4369 | /* These are only called by TCG, KVM maintains dispatch state */ |
4370 | |
4371 | spapr_cpu->prod = false; |
4372 | if (spapr_cpu->vpa_addr) { |
4373 | CPUState *cs = CPU(cpu); |
4374 | uint32_t dispatch; |
4375 | |
4376 | dispatch = ldl_be_phys(cs->as, |
4377 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); |
4378 | dispatch++; |
4379 | if ((dispatch & 1) != 0) { |
4380 | qemu_log_mask(LOG_GUEST_ERROR, |
4381 | "VPA: incorrect dispatch counter value for " |
4382 | "dispatched partition %u, correcting.\n" , dispatch); |
4383 | dispatch++; |
4384 | } |
4385 | stl_be_phys(cs->as, |
4386 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); |
4387 | } |
4388 | } |
4389 | |
4390 | static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) |
4391 | { |
4392 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
4393 | |
4394 | if (spapr_cpu->vpa_addr) { |
4395 | CPUState *cs = CPU(cpu); |
4396 | uint32_t dispatch; |
4397 | |
4398 | dispatch = ldl_be_phys(cs->as, |
4399 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); |
4400 | dispatch++; |
4401 | if ((dispatch & 1) != 1) { |
4402 | qemu_log_mask(LOG_GUEST_ERROR, |
4403 | "VPA: incorrect dispatch counter value for " |
4404 | "preempted partition %u, correcting.\n" , dispatch); |
4405 | dispatch++; |
4406 | } |
4407 | stl_be_phys(cs->as, |
4408 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); |
4409 | } |
4410 | } |
4411 | |
4412 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
4413 | { |
4414 | MachineClass *mc = MACHINE_CLASS(oc); |
4415 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
4416 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
4417 | NMIClass *nc = NMI_CLASS(oc); |
4418 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
4419 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
4420 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
4421 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
4422 | |
4423 | mc->desc = "pSeries Logical Partition (PAPR compliant)" ; |
4424 | mc->ignore_boot_device_suffixes = true; |
4425 | |
4426 | /* |
4427 | * We set up the default / latest behaviour here. The class_init |
4428 | * functions for the specific versioned machine types can override |
4429 | * these details for backwards compatibility |
4430 | */ |
4431 | mc->init = spapr_machine_init; |
4432 | mc->reset = spapr_machine_reset; |
4433 | mc->block_default_type = IF_SCSI; |
4434 | mc->max_cpus = 1024; |
4435 | mc->no_parallel = 1; |
4436 | mc->default_boot_order = "" ; |
4437 | mc->default_ram_size = 512 * MiB; |
4438 | mc->default_display = "std" ; |
4439 | mc->kvm_type = spapr_kvm_type; |
4440 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); |
4441 | mc->pci_allow_0_address = true; |
4442 | assert(!mc->get_hotplug_handler); |
4443 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
4444 | hc->pre_plug = spapr_machine_device_pre_plug; |
4445 | hc->plug = spapr_machine_device_plug; |
4446 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
4447 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
4448 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
4449 | hc->unplug_request = spapr_machine_device_unplug_request; |
4450 | hc->unplug = spapr_machine_device_unplug; |
4451 | |
4452 | smc->dr_lmb_enabled = true; |
4453 | smc->update_dt_enabled = true; |
4454 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0" ); |
4455 | mc->has_hotpluggable_cpus = true; |
4456 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
4457 | fwc->get_dev_path = spapr_get_fw_dev_path; |
4458 | nc->nmi_monitor_handler = spapr_nmi; |
4459 | smc->phb_placement = spapr_phb_placement; |
4460 | vhc->hypercall = emulate_spapr_hypercall; |
4461 | vhc->hpt_mask = spapr_hpt_mask; |
4462 | vhc->map_hptes = spapr_map_hptes; |
4463 | vhc->unmap_hptes = spapr_unmap_hptes; |
4464 | vhc->hpte_set_c = spapr_hpte_set_c; |
4465 | vhc->hpte_set_r = spapr_hpte_set_r; |
4466 | vhc->get_pate = spapr_get_pate; |
4467 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
4468 | vhc->cpu_exec_enter = spapr_cpu_exec_enter; |
4469 | vhc->cpu_exec_exit = spapr_cpu_exec_exit; |
4470 | xic->ics_get = spapr_ics_get; |
4471 | xic->ics_resend = spapr_ics_resend; |
4472 | xic->icp_get = spapr_icp_get; |
4473 | ispc->print_info = spapr_pic_print_info; |
4474 | /* Force NUMA node memory size to be a multiple of |
4475 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity |
4476 | * in which LMBs are represented and hot-added |
4477 | */ |
4478 | mc->numa_mem_align_shift = 28; |
4479 | mc->numa_mem_supported = true; |
4480 | |
4481 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
4482 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; |
4483 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; |
4484 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; |
4485 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; |
4486 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; |
4487 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ |
4488 | smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; |
4489 | smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; |
4490 | smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; |
4491 | spapr_caps_add_properties(smc, &error_abort); |
4492 | smc->irq = &spapr_irq_dual; |
4493 | smc->dr_phb_enabled = true; |
4494 | smc->linux_pci_probe = true; |
4495 | } |
4496 | |
4497 | static const TypeInfo spapr_machine_info = { |
4498 | .name = TYPE_SPAPR_MACHINE, |
4499 | .parent = TYPE_MACHINE, |
4500 | .abstract = true, |
4501 | .instance_size = sizeof(SpaprMachineState), |
4502 | .instance_init = spapr_instance_init, |
4503 | .instance_finalize = spapr_machine_finalizefn, |
4504 | .class_size = sizeof(SpaprMachineClass), |
4505 | .class_init = spapr_machine_class_init, |
4506 | .interfaces = (InterfaceInfo[]) { |
4507 | { TYPE_FW_PATH_PROVIDER }, |
4508 | { TYPE_NMI }, |
4509 | { TYPE_HOTPLUG_HANDLER }, |
4510 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
4511 | { TYPE_XICS_FABRIC }, |
4512 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
4513 | { } |
4514 | }, |
4515 | }; |
4516 | |
4517 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
4518 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
4519 | void *data) \ |
4520 | { \ |
4521 | MachineClass *mc = MACHINE_CLASS(oc); \ |
4522 | spapr_machine_##suffix##_class_options(mc); \ |
4523 | if (latest) { \ |
4524 | mc->alias = "pseries"; \ |
4525 | mc->is_default = 1; \ |
4526 | } \ |
4527 | } \ |
4528 | static const TypeInfo spapr_machine_##suffix##_info = { \ |
4529 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ |
4530 | .parent = TYPE_SPAPR_MACHINE, \ |
4531 | .class_init = spapr_machine_##suffix##_class_init, \ |
4532 | }; \ |
4533 | static void spapr_machine_register_##suffix(void) \ |
4534 | { \ |
4535 | type_register(&spapr_machine_##suffix##_info); \ |
4536 | } \ |
4537 | type_init(spapr_machine_register_##suffix) |
4538 | |
4539 | /* |
4540 | * pseries-4.2 |
4541 | */ |
4542 | static void spapr_machine_4_2_class_options(MachineClass *mc) |
4543 | { |
4544 | /* Defaults for the latest behaviour inherited from the base class */ |
4545 | } |
4546 | |
4547 | DEFINE_SPAPR_MACHINE(4_2, "4.2" , true); |
4548 | |
4549 | /* |
4550 | * pseries-4.1 |
4551 | */ |
4552 | static void spapr_machine_4_1_class_options(MachineClass *mc) |
4553 | { |
4554 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4555 | static GlobalProperty compat[] = { |
4556 | /* Only allow 4kiB and 64kiB IOMMU pagesizes */ |
4557 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz" , "0x11000" }, |
4558 | }; |
4559 | |
4560 | spapr_machine_4_2_class_options(mc); |
4561 | smc->linux_pci_probe = false; |
4562 | compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); |
4563 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4564 | } |
4565 | |
4566 | DEFINE_SPAPR_MACHINE(4_1, "4.1" , false); |
4567 | |
4568 | /* |
4569 | * pseries-4.0 |
4570 | */ |
4571 | static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, |
4572 | uint64_t *buid, hwaddr *pio, |
4573 | hwaddr *mmio32, hwaddr *mmio64, |
4574 | unsigned n_dma, uint32_t *liobns, |
4575 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) |
4576 | { |
4577 | spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, |
4578 | nv2gpa, nv2atsd, errp); |
4579 | *nv2gpa = 0; |
4580 | *nv2atsd = 0; |
4581 | } |
4582 | |
4583 | static void spapr_machine_4_0_class_options(MachineClass *mc) |
4584 | { |
4585 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4586 | |
4587 | spapr_machine_4_1_class_options(mc); |
4588 | compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); |
4589 | smc->phb_placement = phb_placement_4_0; |
4590 | smc->irq = &spapr_irq_xics; |
4591 | smc->pre_4_1_migration = true; |
4592 | } |
4593 | |
4594 | DEFINE_SPAPR_MACHINE(4_0, "4.0" , false); |
4595 | |
4596 | /* |
4597 | * pseries-3.1 |
4598 | */ |
4599 | static void spapr_machine_3_1_class_options(MachineClass *mc) |
4600 | { |
4601 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4602 | |
4603 | spapr_machine_4_0_class_options(mc); |
4604 | compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); |
4605 | |
4606 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0" ); |
4607 | smc->update_dt_enabled = false; |
4608 | smc->dr_phb_enabled = false; |
4609 | smc->broken_host_serial_model = true; |
4610 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
4611 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; |
4612 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; |
4613 | smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; |
4614 | } |
4615 | |
4616 | DEFINE_SPAPR_MACHINE(3_1, "3.1" , false); |
4617 | |
4618 | /* |
4619 | * pseries-3.0 |
4620 | */ |
4621 | |
4622 | static void spapr_machine_3_0_class_options(MachineClass *mc) |
4623 | { |
4624 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4625 | |
4626 | spapr_machine_3_1_class_options(mc); |
4627 | compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); |
4628 | |
4629 | smc->legacy_irq_allocation = true; |
4630 | smc->irq = &spapr_irq_xics_legacy; |
4631 | } |
4632 | |
4633 | DEFINE_SPAPR_MACHINE(3_0, "3.0" , false); |
4634 | |
4635 | /* |
4636 | * pseries-2.12 |
4637 | */ |
4638 | static void spapr_machine_2_12_class_options(MachineClass *mc) |
4639 | { |
4640 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4641 | static GlobalProperty compat[] = { |
4642 | { TYPE_POWERPC_CPU, "pre-3.0-migration" , "on" }, |
4643 | { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration" , "on" }, |
4644 | }; |
4645 | |
4646 | spapr_machine_3_0_class_options(mc); |
4647 | compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); |
4648 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4649 | |
4650 | /* We depend on kvm_enabled() to choose a default value for the |
4651 | * hpt-max-page-size capability. Of course we can't do it here |
4652 | * because this is too early and the HW accelerator isn't initialzed |
4653 | * yet. Postpone this to machine init (see default_caps_with_cpu()). |
4654 | */ |
4655 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; |
4656 | } |
4657 | |
4658 | DEFINE_SPAPR_MACHINE(2_12, "2.12" , false); |
4659 | |
4660 | static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) |
4661 | { |
4662 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4663 | |
4664 | spapr_machine_2_12_class_options(mc); |
4665 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; |
4666 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; |
4667 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; |
4668 | } |
4669 | |
4670 | DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm" , false); |
4671 | |
4672 | /* |
4673 | * pseries-2.11 |
4674 | */ |
4675 | |
4676 | static void spapr_machine_2_11_class_options(MachineClass *mc) |
4677 | { |
4678 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4679 | |
4680 | spapr_machine_2_12_class_options(mc); |
4681 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
4682 | compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); |
4683 | } |
4684 | |
4685 | DEFINE_SPAPR_MACHINE(2_11, "2.11" , false); |
4686 | |
4687 | /* |
4688 | * pseries-2.10 |
4689 | */ |
4690 | |
4691 | static void spapr_machine_2_10_class_options(MachineClass *mc) |
4692 | { |
4693 | spapr_machine_2_11_class_options(mc); |
4694 | compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); |
4695 | } |
4696 | |
4697 | DEFINE_SPAPR_MACHINE(2_10, "2.10" , false); |
4698 | |
4699 | /* |
4700 | * pseries-2.9 |
4701 | */ |
4702 | |
4703 | static void spapr_machine_2_9_class_options(MachineClass *mc) |
4704 | { |
4705 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4706 | static GlobalProperty compat[] = { |
4707 | { TYPE_POWERPC_CPU, "pre-2.10-migration" , "on" }, |
4708 | }; |
4709 | |
4710 | spapr_machine_2_10_class_options(mc); |
4711 | compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); |
4712 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4713 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
4714 | smc->pre_2_10_has_unused_icps = true; |
4715 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
4716 | } |
4717 | |
4718 | DEFINE_SPAPR_MACHINE(2_9, "2.9" , false); |
4719 | |
4720 | /* |
4721 | * pseries-2.8 |
4722 | */ |
4723 | |
4724 | static void spapr_machine_2_8_class_options(MachineClass *mc) |
4725 | { |
4726 | static GlobalProperty compat[] = { |
4727 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space" , "off" }, |
4728 | }; |
4729 | |
4730 | spapr_machine_2_9_class_options(mc); |
4731 | compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); |
4732 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4733 | mc->numa_mem_align_shift = 23; |
4734 | } |
4735 | |
4736 | DEFINE_SPAPR_MACHINE(2_8, "2.8" , false); |
4737 | |
4738 | /* |
4739 | * pseries-2.7 |
4740 | */ |
4741 | |
4742 | static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, |
4743 | uint64_t *buid, hwaddr *pio, |
4744 | hwaddr *mmio32, hwaddr *mmio64, |
4745 | unsigned n_dma, uint32_t *liobns, |
4746 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) |
4747 | { |
4748 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ |
4749 | const uint64_t base_buid = 0x800000020000000ULL; |
4750 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ |
4751 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ |
4752 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ |
4753 | const uint32_t max_index = 255; |
4754 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ |
4755 | |
4756 | uint64_t ram_top = MACHINE(spapr)->ram_size; |
4757 | hwaddr phb0_base, phb_base; |
4758 | int i; |
4759 | |
4760 | /* Do we have device memory? */ |
4761 | if (MACHINE(spapr)->maxram_size > ram_top) { |
4762 | /* Can't just use maxram_size, because there may be an |
4763 | * alignment gap between normal and device memory regions |
4764 | */ |
4765 | ram_top = MACHINE(spapr)->device_memory->base + |
4766 | memory_region_size(&MACHINE(spapr)->device_memory->mr); |
4767 | } |
4768 | |
4769 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); |
4770 | |
4771 | if (index > max_index) { |
4772 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)" , |
4773 | max_index); |
4774 | return; |
4775 | } |
4776 | |
4777 | *buid = base_buid + index; |
4778 | for (i = 0; i < n_dma; ++i) { |
4779 | liobns[i] = SPAPR_PCI_LIOBN(index, i); |
4780 | } |
4781 | |
4782 | phb_base = phb0_base + index * phb_spacing; |
4783 | *pio = phb_base + pio_offset; |
4784 | *mmio32 = phb_base + mmio_offset; |
4785 | /* |
4786 | * We don't set the 64-bit MMIO window, relying on the PHB's |
4787 | * fallback behaviour of automatically splitting a large "32-bit" |
4788 | * window into contiguous 32-bit and 64-bit windows |
4789 | */ |
4790 | |
4791 | *nv2gpa = 0; |
4792 | *nv2atsd = 0; |
4793 | } |
4794 | |
4795 | static void spapr_machine_2_7_class_options(MachineClass *mc) |
4796 | { |
4797 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4798 | static GlobalProperty compat[] = { |
4799 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size" , "0xf80000000" , }, |
4800 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size" , "0" , }, |
4801 | { TYPE_POWERPC_CPU, "pre-2.8-migration" , "on" , }, |
4802 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration" , "on" , }, |
4803 | }; |
4804 | |
4805 | spapr_machine_2_8_class_options(mc); |
4806 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3" ); |
4807 | mc->default_machine_opts = "modern-hotplug-events=off" ; |
4808 | compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); |
4809 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4810 | smc->phb_placement = phb_placement_2_7; |
4811 | } |
4812 | |
4813 | DEFINE_SPAPR_MACHINE(2_7, "2.7" , false); |
4814 | |
4815 | /* |
4816 | * pseries-2.6 |
4817 | */ |
4818 | |
4819 | static void spapr_machine_2_6_class_options(MachineClass *mc) |
4820 | { |
4821 | static GlobalProperty compat[] = { |
4822 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw" , "off" }, |
4823 | }; |
4824 | |
4825 | spapr_machine_2_7_class_options(mc); |
4826 | mc->has_hotpluggable_cpus = false; |
4827 | compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); |
4828 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4829 | } |
4830 | |
4831 | DEFINE_SPAPR_MACHINE(2_6, "2.6" , false); |
4832 | |
4833 | /* |
4834 | * pseries-2.5 |
4835 | */ |
4836 | |
4837 | static void spapr_machine_2_5_class_options(MachineClass *mc) |
4838 | { |
4839 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4840 | static GlobalProperty compat[] = { |
4841 | { "spapr-vlan" , "use-rx-buffer-pools" , "off" }, |
4842 | }; |
4843 | |
4844 | spapr_machine_2_6_class_options(mc); |
4845 | smc->use_ohci_by_default = true; |
4846 | compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); |
4847 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4848 | } |
4849 | |
4850 | DEFINE_SPAPR_MACHINE(2_5, "2.5" , false); |
4851 | |
4852 | /* |
4853 | * pseries-2.4 |
4854 | */ |
4855 | |
4856 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4857 | { |
4858 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4859 | |
4860 | spapr_machine_2_5_class_options(mc); |
4861 | smc->dr_lmb_enabled = false; |
4862 | compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); |
4863 | } |
4864 | |
4865 | DEFINE_SPAPR_MACHINE(2_4, "2.4" , false); |
4866 | |
4867 | /* |
4868 | * pseries-2.3 |
4869 | */ |
4870 | |
4871 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
4872 | { |
4873 | static GlobalProperty compat[] = { |
4874 | { "spapr-pci-host-bridge" , "dynamic-reconfiguration" , "off" }, |
4875 | }; |
4876 | spapr_machine_2_4_class_options(mc); |
4877 | compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); |
4878 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4879 | } |
4880 | DEFINE_SPAPR_MACHINE(2_3, "2.3" , false); |
4881 | |
4882 | /* |
4883 | * pseries-2.2 |
4884 | */ |
4885 | |
4886 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4887 | { |
4888 | static GlobalProperty compat[] = { |
4889 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size" , "0x20000000" }, |
4890 | }; |
4891 | |
4892 | spapr_machine_2_3_class_options(mc); |
4893 | compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); |
4894 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4895 | mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on" ; |
4896 | } |
4897 | DEFINE_SPAPR_MACHINE(2_2, "2.2" , false); |
4898 | |
4899 | /* |
4900 | * pseries-2.1 |
4901 | */ |
4902 | |
4903 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
4904 | { |
4905 | spapr_machine_2_2_class_options(mc); |
4906 | compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); |
4907 | } |
4908 | DEFINE_SPAPR_MACHINE(2_1, "2.1" , false); |
4909 | |
4910 | static void spapr_machine_register_types(void) |
4911 | { |
4912 | type_register_static(&spapr_machine_info); |
4913 | } |
4914 | |
4915 | type_init(spapr_machine_register_types) |
4916 | |