1/*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25#include "precompiled.hpp"
26#include "gc/shared/collectedHeap.hpp"
27#include "memory/universe.hpp"
28#include "oops/compressedOops.hpp"
29#include "opto/machnode.hpp"
30#include "opto/regalloc.hpp"
31#include "utilities/vmError.hpp"
32
33//=============================================================================
34// Return the value requested
35// result register lookup, corresponding to int_format
36int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
37 return (int)ra_->get_encode(node);
38}
39// input register lookup, corresponding to ext_format
40int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
41 return (int)(ra_->get_encode(node->in(idx)));
42}
43intptr_t MachOper::constant() const { return 0x00; }
44relocInfo::relocType MachOper::constant_reloc() const { return relocInfo::none; }
45jdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; }
46jfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; }
47jlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; }
48TypeOopPtr *MachOper::oop() const { return NULL; }
49int MachOper::ccode() const { return 0x00; }
50// A zero, default, indicates this value is not needed.
51// May need to lookup the base register, as done in int_ and ext_format
52int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
53int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
54int MachOper::scale() const { return 0x00; }
55int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
56int MachOper::constant_disp() const { return 0; }
57int MachOper::base_position() const { return -1; } // no base input
58int MachOper::index_position() const { return -1; } // no index input
59// Check for PC-Relative displacement
60relocInfo::relocType MachOper::disp_reloc() const { return relocInfo::none; }
61// Return the label
62Label* MachOper::label() const { ShouldNotReachHere(); return 0; }
63intptr_t MachOper::method() const { ShouldNotReachHere(); return 0; }
64
65
66//------------------------------negate-----------------------------------------
67// Negate conditional branches. Error for non-branch operands
68void MachOper::negate() {
69 ShouldNotCallThis();
70}
71
72//-----------------------------type--------------------------------------------
73const Type *MachOper::type() const {
74 return Type::BOTTOM;
75}
76
77//------------------------------in_RegMask-------------------------------------
78const RegMask *MachOper::in_RegMask(int index) const {
79 ShouldNotReachHere();
80 return NULL;
81}
82
83//------------------------------dump_spec--------------------------------------
84// Print any per-operand special info
85#ifndef PRODUCT
86void MachOper::dump_spec(outputStream *st) const { }
87#endif
88
89//------------------------------hash-------------------------------------------
90// Print any per-operand special info
91uint MachOper::hash() const {
92 ShouldNotCallThis();
93 return 5;
94}
95
96//------------------------------cmp--------------------------------------------
97// Print any per-operand special info
98bool MachOper::cmp( const MachOper &oper ) const {
99 ShouldNotCallThis();
100 return opcode() == oper.opcode();
101}
102
103//------------------------------hash-------------------------------------------
104// Print any per-operand special info
105uint labelOper::hash() const {
106 return _block_num;
107}
108
109//------------------------------cmp--------------------------------------------
110// Print any per-operand special info
111bool labelOper::cmp( const MachOper &oper ) const {
112 return (opcode() == oper.opcode()) && (_label == oper.label());
113}
114
115//------------------------------hash-------------------------------------------
116// Print any per-operand special info
117uint methodOper::hash() const {
118 return (uint)_method;
119}
120
121//------------------------------cmp--------------------------------------------
122// Print any per-operand special info
123bool methodOper::cmp( const MachOper &oper ) const {
124 return (opcode() == oper.opcode()) && (_method == oper.method());
125}
126
127
128//=============================================================================
129//------------------------------MachNode---------------------------------------
130
131//------------------------------emit-------------------------------------------
132void MachNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
133 #ifdef ASSERT
134 tty->print("missing MachNode emit function: ");
135 dump();
136 #endif
137 ShouldNotCallThis();
138}
139
140//---------------------------postalloc_expand----------------------------------
141// Expand node after register allocation.
142void MachNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {}
143
144//------------------------------size-------------------------------------------
145// Size of instruction in bytes
146uint MachNode::size(PhaseRegAlloc *ra_) const {
147 // If a virtual was not defined for this specific instruction,
148 // Call the helper which finds the size by emitting the bits.
149 return MachNode::emit_size(ra_);
150}
151
152//------------------------------size-------------------------------------------
153// Helper function that computes size by emitting code
154uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
155 // Emit into a trash buffer and count bytes emitted.
156 assert(ra_ == ra_->C->regalloc(), "sanity");
157 return ra_->C->scratch_emit_size(this);
158}
159
160
161
162//------------------------------hash-------------------------------------------
163uint MachNode::hash() const {
164 uint no = num_opnds();
165 uint sum = rule();
166 for( uint i=0; i<no; i++ )
167 sum += _opnds[i]->hash();
168 return sum+Node::hash();
169}
170
171//-----------------------------cmp---------------------------------------------
172bool MachNode::cmp( const Node &node ) const {
173 MachNode& n = *((Node&)node).as_Mach();
174 uint no = num_opnds();
175 if( no != n.num_opnds() ) return false;
176 if( rule() != n.rule() ) return false;
177 for( uint i=0; i<no; i++ ) // All operands must match
178 if( !_opnds[i]->cmp( *n._opnds[i] ) )
179 return false; // mis-matched operands
180 return true; // match
181}
182
183// Return an equivalent instruction using memory for cisc_operand position
184MachNode *MachNode::cisc_version(int offset) {
185 ShouldNotCallThis();
186 return NULL;
187}
188
189void MachNode::use_cisc_RegMask() {
190 ShouldNotReachHere();
191}
192
193
194//-----------------------------in_RegMask--------------------------------------
195const RegMask &MachNode::in_RegMask( uint idx ) const {
196 uint numopnds = num_opnds(); // Virtual call for number of operands
197 uint skipped = oper_input_base(); // Sum of leaves skipped so far
198 if( idx < skipped ) {
199 assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
200 assert( idx == 1, "expected base ptr here" );
201 // debug info can be anywhere
202 return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
203 }
204 uint opcnt = 1; // First operand
205 uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
206 while( idx >= skipped+num_edges ) {
207 skipped += num_edges;
208 opcnt++; // Bump operand count
209 assert( opcnt < numopnds, "Accessing non-existent operand" );
210 num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
211 }
212
213 const RegMask *rm = cisc_RegMask();
214 if( rm == NULL || (int)opcnt != cisc_operand() ) {
215 rm = _opnds[opcnt]->in_RegMask(idx-skipped);
216 }
217 return *rm;
218}
219
220//-----------------------------memory_inputs--------------------------------
221const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
222 const MachOper* oper = memory_operand();
223
224 if (oper == (MachOper*)-1) {
225 base = NodeSentinel;
226 index = NodeSentinel;
227 } else {
228 base = NULL;
229 index = NULL;
230 if (oper != NULL) {
231 // It has a unique memory operand. Find its index.
232 int oper_idx = num_opnds();
233 while (--oper_idx >= 0) {
234 if (_opnds[oper_idx] == oper) break;
235 }
236 int oper_pos = operand_index(oper_idx);
237 int base_pos = oper->base_position();
238 if (base_pos >= 0) {
239 base = _in[oper_pos+base_pos];
240 }
241 int index_pos = oper->index_position();
242 if (index_pos >= 0) {
243 index = _in[oper_pos+index_pos];
244 }
245 }
246 }
247
248 return oper;
249}
250
251//-----------------------------get_base_and_disp----------------------------
252const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
253
254 // Find the memory inputs using our helper function
255 Node* base;
256 Node* index;
257 const MachOper* oper = memory_inputs(base, index);
258
259 if (oper == NULL) {
260 // Base has been set to NULL
261 offset = 0;
262 } else if (oper == (MachOper*)-1) {
263 // Base has been set to NodeSentinel
264 // There is not a unique memory use here. We will fall to AliasIdxBot.
265 offset = Type::OffsetBot;
266 } else {
267 // Base may be NULL, even if offset turns out to be != 0
268
269 intptr_t disp = oper->constant_disp();
270 int scale = oper->scale();
271 // Now we have collected every part of the ADLC MEMORY_INTER.
272 // See if it adds up to a base + offset.
273 if (index != NULL) {
274 const Type* t_index = index->bottom_type();
275 if (t_index->isa_narrowoop() || t_index->isa_narrowklass()) { // EncodeN, LoadN, LoadConN, LoadNKlass,
276 // EncodeNKlass, LoadConNklass.
277 // Memory references through narrow oops have a
278 // funny base so grab the type from the index:
279 // [R12 + narrow_oop_reg<<3 + offset]
280 assert(base == NULL, "Memory references through narrow oops have no base");
281 offset = disp;
282 adr_type = t_index->make_ptr()->add_offset(offset);
283 return NULL;
284 } else if (!index->is_Con()) {
285 disp = Type::OffsetBot;
286 } else if (disp != Type::OffsetBot) {
287 const TypeX* ti = t_index->isa_intptr_t();
288 if (ti == NULL) {
289 disp = Type::OffsetBot; // a random constant??
290 } else {
291 disp += ti->get_con() << scale;
292 }
293 }
294 }
295 offset = disp;
296
297 // In i486.ad, indOffset32X uses base==RegI and disp==RegP,
298 // this will prevent alias analysis without the following support:
299 // Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
300 // Add the offset determined by the "base", or use Type::OffsetBot.
301 if( adr_type == TYPE_PTR_SENTINAL ) {
302 const TypePtr *t_disp = oper->disp_as_type(); // only !NULL for indOffset32X
303 if (t_disp != NULL) {
304 offset = Type::OffsetBot;
305 const Type* t_base = base->bottom_type();
306 if (t_base->isa_intptr_t()) {
307 const TypeX *t_offset = t_base->is_intptr_t();
308 if( t_offset->is_con() ) {
309 offset = t_offset->get_con();
310 }
311 }
312 adr_type = t_disp->add_offset(offset);
313 } else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) {
314 // Use ideal type if it is oop ptr.
315 const TypePtr *tp = oper->type()->isa_ptr();
316 if( tp != NULL) {
317 adr_type = tp;
318 }
319 }
320 }
321
322 }
323 return base;
324}
325
326
327//---------------------------------adr_type---------------------------------
328const class TypePtr *MachNode::adr_type() const {
329 intptr_t offset = 0;
330 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
331 const Node *base = get_base_and_disp(offset, adr_type);
332 if( adr_type != TYPE_PTR_SENTINAL ) {
333 return adr_type; // get_base_and_disp has the answer
334 }
335
336 // Direct addressing modes have no base node, simply an indirect
337 // offset, which is always to raw memory.
338 // %%%%% Someday we'd like to allow constant oop offsets which
339 // would let Intel load from static globals in 1 instruction.
340 // Currently Intel requires 2 instructions and a register temp.
341 if (base == NULL) {
342 // NULL base, zero offset means no memory at all (a null pointer!)
343 if (offset == 0) {
344 return NULL;
345 }
346 // NULL base, any offset means any pointer whatever
347 if (offset == Type::OffsetBot) {
348 return TypePtr::BOTTOM;
349 }
350 // %%% make offset be intptr_t
351 assert(!Universe::heap()->is_in_reserved(cast_to_oop(offset)), "must be a raw ptr");
352 return TypeRawPtr::BOTTOM;
353 }
354
355 // base of -1 with no particular offset means all of memory
356 if (base == NodeSentinel) return TypePtr::BOTTOM;
357
358 const Type* t = base->bottom_type();
359 if (t->isa_narrowoop() && CompressedOops::shift() == 0) {
360 // 32-bit unscaled narrow oop can be the base of any address expression
361 t = t->make_ptr();
362 }
363 if (t->isa_narrowklass() && CompressedKlassPointers::shift() == 0) {
364 // 32-bit unscaled narrow oop can be the base of any address expression
365 t = t->make_ptr();
366 }
367 if (t->isa_intptr_t() && offset != 0 && offset != Type::OffsetBot) {
368 // We cannot assert that the offset does not look oop-ish here.
369 // Depending on the heap layout the cardmark base could land
370 // inside some oopish region. It definitely does for Win2K.
371 // The sum of cardmark-base plus shift-by-9-oop lands outside
372 // the oop-ish area but we can't assert for that statically.
373 return TypeRawPtr::BOTTOM;
374 }
375
376 const TypePtr *tp = t->isa_ptr();
377
378 // be conservative if we do not recognize the type
379 if (tp == NULL) {
380 assert(false, "this path may produce not optimal code");
381 return TypePtr::BOTTOM;
382 }
383 assert(tp->base() != Type::AnyPtr, "not a bare pointer");
384
385 return tp->add_offset(offset);
386}
387
388
389//-----------------------------operand_index---------------------------------
390int MachNode::operand_index( uint operand ) const {
391 if( operand < 1 ) return -1;
392 assert(operand < num_opnds(), "oob");
393 if( _opnds[operand]->num_edges() == 0 ) return -1;
394
395 uint skipped = oper_input_base(); // Sum of leaves skipped so far
396 for (uint opcnt = 1; opcnt < operand; opcnt++) {
397 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
398 skipped += num_edges;
399 }
400 return skipped;
401}
402
403int MachNode::operand_index(const MachOper *oper) const {
404 uint skipped = oper_input_base(); // Sum of leaves skipped so far
405 uint opcnt;
406 for (opcnt = 1; opcnt < num_opnds(); opcnt++) {
407 if (_opnds[opcnt] == oper) break;
408 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
409 skipped += num_edges;
410 }
411 if (_opnds[opcnt] != oper) return -1;
412 return skipped;
413}
414
415//------------------------------peephole---------------------------------------
416// Apply peephole rule(s) to this instruction
417MachNode *MachNode::peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted) {
418 return NULL;
419}
420
421//------------------------------add_case_label---------------------------------
422// Adds the label for the case
423void MachNode::add_case_label( int index_num, Label* blockLabel) {
424 ShouldNotCallThis();
425}
426
427//------------------------------method_set-------------------------------------
428// Set the absolute address of a method
429void MachNode::method_set( intptr_t addr ) {
430 ShouldNotCallThis();
431}
432
433//------------------------------rematerialize----------------------------------
434bool MachNode::rematerialize() const {
435 // Temps are always rematerializable
436 if (is_MachTemp()) return true;
437
438 uint r = rule(); // Match rule
439 if (r < Matcher::_begin_rematerialize ||
440 r >= Matcher::_end_rematerialize) {
441 return false;
442 }
443
444 // For 2-address instructions, the input live range is also the output
445 // live range. Remateralizing does not make progress on the that live range.
446 if (two_adr()) return false;
447
448 // Check for rematerializing float constants, or not
449 if (!Matcher::rematerialize_float_constants) {
450 int op = ideal_Opcode();
451 if (op == Op_ConF || op == Op_ConD) {
452 return false;
453 }
454 }
455
456 // Defining flags - can't spill these! Must remateralize.
457 if (ideal_reg() == Op_RegFlags) {
458 return true;
459 }
460
461 // Stretching lots of inputs - don't do it.
462 if (req() > 2) {
463 return false;
464 }
465
466 if (req() == 2 && in(1) && in(1)->ideal_reg() == Op_RegFlags) {
467 // In(1) will be rematerialized, too.
468 // Stretching lots of inputs - don't do it.
469 if (in(1)->req() > 2) {
470 return false;
471 }
472 }
473
474 // Don't remateralize somebody with bound inputs - it stretches a
475 // fixed register lifetime.
476 uint idx = oper_input_base();
477 if (req() > idx) {
478 const RegMask &rm = in_RegMask(idx);
479 if (rm.is_bound(ideal_reg())) {
480 return false;
481 }
482 }
483
484 return true;
485}
486
487#ifndef PRODUCT
488//------------------------------dump_spec--------------------------------------
489// Print any per-operand special info
490void MachNode::dump_spec(outputStream *st) const {
491 uint cnt = num_opnds();
492 for( uint i=0; i<cnt; i++ ) {
493 if (_opnds[i] != NULL) {
494 _opnds[i]->dump_spec(st);
495 } else {
496 st->print(" _");
497 }
498 }
499 const TypePtr *t = adr_type();
500 if( t ) {
501 Compile* C = Compile::current();
502 if( C->alias_type(t)->is_volatile() )
503 st->print(" Volatile!");
504 }
505}
506
507//------------------------------dump_format------------------------------------
508// access to virtual
509void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
510 format(ra, st); // access to virtual
511}
512#endif
513
514//=============================================================================
515#ifndef PRODUCT
516void MachTypeNode::dump_spec(outputStream *st) const {
517 if (_bottom_type != NULL) {
518 _bottom_type->dump_on(st);
519 } else {
520 st->print(" NULL");
521 }
522}
523#endif
524
525
526//=============================================================================
527int MachConstantNode::constant_offset() {
528 // Bind the offset lazily.
529 if (_constant.offset() == -1) {
530 Compile::ConstantTable& constant_table = Compile::current()->constant_table();
531 int offset = constant_table.find_offset(_constant);
532 // If called from Compile::scratch_emit_size return the
533 // pre-calculated offset.
534 // NOTE: If the AD file does some table base offset optimizations
535 // later the AD file needs to take care of this fact.
536 if (Compile::current()->in_scratch_emit_size()) {
537 return constant_table.calculate_table_base_offset() + offset;
538 }
539 _constant.set_offset(constant_table.table_base_offset() + offset);
540 }
541 return _constant.offset();
542}
543
544int MachConstantNode::constant_offset_unchecked() const {
545 return _constant.offset();
546}
547
548//=============================================================================
549#ifndef PRODUCT
550void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
551 int reg = ra_->get_reg_first(in(1)->in(_vidx));
552 st->print("%s %s", Name(), Matcher::regName[reg]);
553}
554#endif
555
556void MachNullCheckNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
557 // only emits entries in the null-pointer exception handler table
558}
559void MachNullCheckNode::label_set(Label* label, uint block_num) {
560 // Nothing to emit
561}
562void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
563 // Nothing to emit
564}
565
566const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
567 if( idx == 0 ) return RegMask::Empty;
568 else return in(1)->as_Mach()->out_RegMask();
569}
570
571//=============================================================================
572const Type *MachProjNode::bottom_type() const {
573 if( _ideal_reg == fat_proj ) return Type::BOTTOM;
574 // Try the normal mechanism first
575 const Type *t = in(0)->bottom_type();
576 if( t->base() == Type::Tuple ) {
577 const TypeTuple *tt = t->is_tuple();
578 if (_con < tt->cnt())
579 return tt->field_at(_con);
580 }
581 // Else use generic type from ideal register set
582 assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
583 return Type::mreg2type[_ideal_reg];
584}
585
586const TypePtr *MachProjNode::adr_type() const {
587 if (bottom_type() == Type::MEMORY) {
588 // in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
589 Node* ctrl = in(0);
590 if (ctrl == NULL) return NULL; // node is dead
591 const TypePtr* adr_type = ctrl->adr_type();
592 #ifdef ASSERT
593 if (!VMError::is_error_reported() && !Node::in_dump())
594 assert(adr_type != NULL, "source must have adr_type");
595 #endif
596 return adr_type;
597 }
598 assert(bottom_type()->base() != Type::Memory, "no other memories?");
599 return NULL;
600}
601
602#ifndef PRODUCT
603void MachProjNode::dump_spec(outputStream *st) const {
604 ProjNode::dump_spec(st);
605 switch (_ideal_reg) {
606 case unmatched_proj: st->print("/unmatched"); break;
607 case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(st); break;
608 }
609}
610#endif
611
612//=============================================================================
613#ifndef PRODUCT
614void MachIfNode::dump_spec(outputStream *st) const {
615 st->print("P=%f, C=%f",_prob, _fcnt);
616}
617#endif
618
619//=============================================================================
620uint MachReturnNode::size_of() const { return sizeof(*this); }
621
622//------------------------------Registers--------------------------------------
623const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
624 return _in_rms[idx];
625}
626
627const TypePtr *MachReturnNode::adr_type() const {
628 // most returns and calls are assumed to consume & modify all of memory
629 // the matcher will copy non-wide adr_types from ideal originals
630 return _adr_type;
631}
632
633//=============================================================================
634const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
635
636//------------------------------Registers--------------------------------------
637const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
638 // Values in the domain use the users calling convention, embodied in the
639 // _in_rms array of RegMasks.
640 if( idx < TypeFunc::Parms ) return _in_rms[idx];
641
642 if (SafePointNode::needs_polling_address_input() &&
643 idx == TypeFunc::Parms &&
644 ideal_Opcode() == Op_SafePoint) {
645 return MachNode::in_RegMask(idx);
646 }
647
648 // Values outside the domain represent debug info
649 assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
650 return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
651}
652
653
654//=============================================================================
655
656bool MachCallNode::cmp( const Node &n ) const
657{ return _tf == ((MachCallNode&)n)._tf; }
658const Type *MachCallNode::bottom_type() const { return tf()->range(); }
659const Type* MachCallNode::Value(PhaseGVN* phase) const { return tf()->range(); }
660
661#ifndef PRODUCT
662void MachCallNode::dump_spec(outputStream *st) const {
663 st->print("# ");
664 if (tf() != NULL) tf()->dump_on(st);
665 if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
666 if (jvms() != NULL) jvms()->dump_spec(st);
667}
668#endif
669
670bool MachCallNode::return_value_is_used() const {
671 if (tf()->range()->cnt() == TypeFunc::Parms) {
672 // void return
673 return false;
674 }
675
676 // find the projection corresponding to the return value
677 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
678 Node *use = fast_out(i);
679 if (!use->is_Proj()) continue;
680 if (use->as_Proj()->_con == TypeFunc::Parms) {
681 return true;
682 }
683 }
684 return false;
685}
686
687// Similar to cousin class CallNode::returns_pointer
688// Because this is used in deoptimization, we want the type info, not the data
689// flow info; the interpreter will "use" things that are dead to the optimizer.
690bool MachCallNode::returns_pointer() const {
691 const TypeTuple *r = tf()->range();
692 return (r->cnt() > TypeFunc::Parms &&
693 r->field_at(TypeFunc::Parms)->isa_ptr());
694}
695
696//------------------------------Registers--------------------------------------
697const RegMask &MachCallNode::in_RegMask(uint idx) const {
698 // Values in the domain use the users calling convention, embodied in the
699 // _in_rms array of RegMasks.
700 if (idx < tf()->domain()->cnt()) {
701 return _in_rms[idx];
702 }
703 if (idx == mach_constant_base_node_input()) {
704 return MachConstantBaseNode::static_out_RegMask();
705 }
706 // Values outside the domain represent debug info
707 return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
708}
709
710//=============================================================================
711uint MachCallJavaNode::size_of() const { return sizeof(*this); }
712bool MachCallJavaNode::cmp( const Node &n ) const {
713 MachCallJavaNode &call = (MachCallJavaNode&)n;
714 return MachCallNode::cmp(call) && _method->equals(call._method) &&
715 _override_symbolic_info == call._override_symbolic_info;
716}
717#ifndef PRODUCT
718void MachCallJavaNode::dump_spec(outputStream *st) const {
719 if (_method_handle_invoke)
720 st->print("MethodHandle ");
721 if (_method) {
722 _method->print_short_name(st);
723 st->print(" ");
724 }
725 MachCallNode::dump_spec(st);
726}
727#endif
728
729//------------------------------Registers--------------------------------------
730const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
731 // Values in the domain use the users calling convention, embodied in the
732 // _in_rms array of RegMasks.
733 if (idx < tf()->domain()->cnt()) {
734 return _in_rms[idx];
735 }
736 if (idx == mach_constant_base_node_input()) {
737 return MachConstantBaseNode::static_out_RegMask();
738 }
739 // Values outside the domain represent debug info
740 Matcher* m = Compile::current()->matcher();
741 // If this call is a MethodHandle invoke we have to use a different
742 // debugmask which does not include the register we use to save the
743 // SP over MH invokes.
744 RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
745 return *debugmask[in(idx)->ideal_reg()];
746}
747
748//=============================================================================
749uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
750bool MachCallStaticJavaNode::cmp( const Node &n ) const {
751 MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
752 return MachCallJavaNode::cmp(call) && _name == call._name;
753}
754
755//----------------------------uncommon_trap_request----------------------------
756// If this is an uncommon trap, return the request code, else zero.
757int MachCallStaticJavaNode::uncommon_trap_request() const {
758 if (_name != NULL && !strcmp(_name, "uncommon_trap")) {
759 return CallStaticJavaNode::extract_uncommon_trap_request(this);
760 }
761 return 0;
762}
763
764#ifndef PRODUCT
765// Helper for summarizing uncommon_trap arguments.
766void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
767 int trap_req = uncommon_trap_request();
768 if (trap_req != 0) {
769 char buf[100];
770 st->print("(%s)",
771 Deoptimization::format_trap_request(buf, sizeof(buf),
772 trap_req));
773 }
774}
775
776void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
777 st->print("Static ");
778 if (_name != NULL) {
779 st->print("wrapper for: %s", _name );
780 dump_trap_args(st);
781 st->print(" ");
782 }
783 MachCallJavaNode::dump_spec(st);
784}
785#endif
786
787//=============================================================================
788#ifndef PRODUCT
789void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
790 st->print("Dynamic ");
791 MachCallJavaNode::dump_spec(st);
792}
793#endif
794//=============================================================================
795uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
796bool MachCallRuntimeNode::cmp( const Node &n ) const {
797 MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
798 return MachCallNode::cmp(call) && !strcmp(_name,call._name);
799}
800#ifndef PRODUCT
801void MachCallRuntimeNode::dump_spec(outputStream *st) const {
802 st->print("%s ",_name);
803 MachCallNode::dump_spec(st);
804}
805#endif
806//=============================================================================
807// A shared JVMState for all HaltNodes. Indicates the start of debug info
808// is at TypeFunc::Parms. Only required for SOE register spill handling -
809// to indicate where the stack-slot-only debug info inputs begin.
810// There is no other JVM state needed here.
811JVMState jvms_for_throw(0);
812JVMState *MachHaltNode::jvms() const {
813 return &jvms_for_throw;
814}
815
816uint MachMemBarNode::size_of() const { return sizeof(*this); }
817
818const TypePtr *MachMemBarNode::adr_type() const {
819 return _adr_type;
820}
821
822
823//=============================================================================
824#ifndef PRODUCT
825void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
826 st->print("B%d", _block_num);
827}
828#endif // PRODUCT
829
830//=============================================================================
831#ifndef PRODUCT
832void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
833 st->print(INTPTR_FORMAT, _method);
834}
835#endif // PRODUCT
836