1#line 1 "ad_x86.cpp"
2//
3// Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5//
6// This code is free software; you can redistribute it and/or modify it
7// under the terms of the GNU General Public License version 2 only, as
8// published by the Free Software Foundation.
9//
10// This code is distributed in the hope that it will be useful, but WITHOUT
11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13// version 2 for more details (a copy is included in the LICENSE file that
14// accompanied this code).
15//
16// You should have received a copy of the GNU General Public License version
17// 2 along with this work; if not, write to the Free Software Foundation,
18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19//
20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21// or visit www.oracle.com if you need additional information or have any
22// questions.
23//
24//
25
26// Machine Generated File. Do Not Edit!
27
28#include "precompiled.hpp"
29#include "adfiles/adGlobals_x86.hpp"
30#include "adfiles/ad_x86.hpp"
31#include "memory/allocation.inline.hpp"
32#include "asm/macroAssembler.inline.hpp"
33#include "code/compiledIC.hpp"
34#include "code/nativeInst.hpp"
35#include "code/vmreg.inline.hpp"
36#include "gc/shared/collectedHeap.inline.hpp"
37#include "oops/compiledICHolder.hpp"
38#include "oops/compressedOops.hpp"
39#include "oops/markOop.hpp"
40#include "oops/method.hpp"
41#include "oops/oop.inline.hpp"
42#include "opto/cfgnode.hpp"
43#include "opto/intrinsicnode.hpp"
44#include "opto/locknode.hpp"
45#include "opto/opcodes.hpp"
46#include "opto/regalloc.hpp"
47#include "opto/regmask.hpp"
48#include "opto/runtime.hpp"
49#include "runtime/biasedLocking.hpp"
50#include "runtime/safepointMechanism.hpp"
51#include "runtime/sharedRuntime.hpp"
52#include "runtime/stubRoutines.hpp"
53#include "utilities/growableArray.hpp"
54
55//SourceForm
56
57#line 335 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
58
59#define RELOC_IMM64 Assembler::imm_operand
60#define RELOC_DISP32 Assembler::disp32_operand
61
62#define __ _masm.
63
64RegMask _ANY_REG_mask;
65RegMask _PTR_REG_mask;
66RegMask _PTR_REG_NO_RBP_mask;
67RegMask _PTR_NO_RAX_REG_mask;
68RegMask _PTR_NO_RAX_RBX_REG_mask;
69RegMask _LONG_REG_mask;
70RegMask _LONG_NO_RAX_RDX_REG_mask;
71RegMask _LONG_NO_RCX_REG_mask;
72RegMask _INT_REG_mask;
73RegMask _INT_NO_RAX_RDX_REG_mask;
74RegMask _INT_NO_RCX_REG_mask;
75RegMask _STACK_OR_PTR_REG_mask;
76RegMask _STACK_OR_LONG_REG_mask;
77RegMask _STACK_OR_INT_REG_mask;
78
79static bool need_r12_heapbase() {
80 return UseCompressedOops || UseCompressedClassPointers;
81}
82
83void reg_mask_init() {
84 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
85 // We derive a number of subsets from it.
86 _ANY_REG_mask = _ALL_REG_mask;
87
88 if (PreserveFramePointer) {
89 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
90 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
91 }
92 if (need_r12_heapbase()) {
93 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
94 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
95 }
96
97 _PTR_REG_mask = _ANY_REG_mask;
98 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
99 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
100 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
101 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
102
103 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
104 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
105
106 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
107 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
108 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
109
110 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
111 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
112 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
113
114 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
115 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
116 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
117
118 _LONG_REG_mask = _PTR_REG_mask;
119 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
120 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
121
122 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
123 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
124 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
125 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
126 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
127
128 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
129 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
130 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
131
132 _INT_REG_mask = _ALL_INT_REG_mask;
133 if (PreserveFramePointer) {
134 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
135 }
136 if (need_r12_heapbase()) {
137 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
138 }
139
140 _STACK_OR_INT_REG_mask = _INT_REG_mask;
141 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
142
143 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
144 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
145 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
146
147 _INT_NO_RCX_REG_mask = _INT_REG_mask;
148 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
149}
150
151static bool generate_vzeroupper(Compile* C) {
152 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
153}
154
155static int clear_avx_size() {
156 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
157}
158
159// !!!!! Special hack to get all types of calls to specify the byte offset
160// from the start of the call to the point where the return address
161// will point.
162int MachCallStaticJavaNode::ret_addr_offset()
163{
164 int offset = 5; // 5 bytes from start of call to where return address points
165 offset += clear_avx_size();
166 return offset;
167}
168
169int MachCallDynamicJavaNode::ret_addr_offset()
170{
171 int offset = 15; // 15 bytes from start of call to where return address points
172 offset += clear_avx_size();
173 return offset;
174}
175
176int MachCallRuntimeNode::ret_addr_offset() {
177 int offset = 13; // movq r10,#addr; callq (r10)
178 offset += clear_avx_size();
179 return offset;
180}
181
182// Indicate if the safepoint node needs the polling page as an input,
183// it does if the polling page is more than disp32 away.
184bool SafePointNode::needs_polling_address_input()
185{
186 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
187}
188
189//
190// Compute padding required for nodes which need alignment
191//
192
193// The address of the call instruction needs to be 4-byte aligned to
194// ensure that it does not span a cache line so that it can be patched.
195int CallStaticJavaDirectNode::compute_padding(int current_offset) const
196{
197 current_offset += clear_avx_size(); // skip vzeroupper
198 current_offset += 1; // skip call opcode byte
199 return align_up(current_offset, alignment_required()) - current_offset;
200}
201
202// The address of the call instruction needs to be 4-byte aligned to
203// ensure that it does not span a cache line so that it can be patched.
204int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
205{
206 current_offset += clear_avx_size(); // skip vzeroupper
207 current_offset += 11; // skip movq instruction + call opcode byte
208 return align_up(current_offset, alignment_required()) - current_offset;
209}
210
211// EMIT_RM()
212void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
213 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
214 cbuf.insts()->emit_int8(c);
215}
216
217// EMIT_CC()
218void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
219 unsigned char c = (unsigned char) (f1 | f2);
220 cbuf.insts()->emit_int8(c);
221}
222
223// EMIT_OPCODE()
224void emit_opcode(CodeBuffer &cbuf, int code) {
225 cbuf.insts()->emit_int8((unsigned char) code);
226}
227
228// EMIT_OPCODE() w/ relocation information
229void emit_opcode(CodeBuffer &cbuf,
230 int code, relocInfo::relocType reloc, int offset, int format)
231{
232 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
233 emit_opcode(cbuf, code);
234}
235
236// EMIT_D8()
237void emit_d8(CodeBuffer &cbuf, int d8) {
238 cbuf.insts()->emit_int8((unsigned char) d8);
239}
240
241// EMIT_D16()
242void emit_d16(CodeBuffer &cbuf, int d16) {
243 cbuf.insts()->emit_int16(d16);
244}
245
246// EMIT_D32()
247void emit_d32(CodeBuffer &cbuf, int d32) {
248 cbuf.insts()->emit_int32(d32);
249}
250
251// EMIT_D64()
252void emit_d64(CodeBuffer &cbuf, int64_t d64) {
253 cbuf.insts()->emit_int64(d64);
254}
255
256// emit 32 bit value and construct relocation entry from relocInfo::relocType
257void emit_d32_reloc(CodeBuffer& cbuf,
258 int d32,
259 relocInfo::relocType reloc,
260 int format)
261{
262 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
263 cbuf.relocate(cbuf.insts_mark(), reloc, format);
264 cbuf.insts()->emit_int32(d32);
265}
266
267// emit 32 bit value and construct relocation entry from RelocationHolder
268void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
269#ifdef ASSERT
270 if (rspec.reloc()->type() == relocInfo::oop_type &&
271 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
272 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
273 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
274 }
275#endif
276 cbuf.relocate(cbuf.insts_mark(), rspec, format);
277 cbuf.insts()->emit_int32(d32);
278}
279
280void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
281 address next_ip = cbuf.insts_end() + 4;
282 emit_d32_reloc(cbuf, (int) (addr - next_ip),
283 external_word_Relocation::spec(addr),
284 RELOC_DISP32);
285}
286
287
288// emit 64 bit value and construct relocation entry from relocInfo::relocType
289void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
290 cbuf.relocate(cbuf.insts_mark(), reloc, format);
291 cbuf.insts()->emit_int64(d64);
292}
293
294// emit 64 bit value and construct relocation entry from RelocationHolder
295void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
296#ifdef ASSERT
297 if (rspec.reloc()->type() == relocInfo::oop_type &&
298 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
299 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
300 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
301 }
302#endif
303 cbuf.relocate(cbuf.insts_mark(), rspec, format);
304 cbuf.insts()->emit_int64(d64);
305}
306
307// Access stack slot for load or store
308void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
309{
310 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
311 if (-0x80 <= disp && disp < 0x80) {
312 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
313 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
314 emit_d8(cbuf, disp); // Displacement // R/M byte
315 } else {
316 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
317 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
318 emit_d32(cbuf, disp); // Displacement // R/M byte
319 }
320}
321
322 // rRegI ereg, memory mem) %{ // emit_reg_mem
323void encode_RegMem(CodeBuffer &cbuf,
324 int reg,
325 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
326{
327 assert(disp_reloc == relocInfo::none, "cannot have disp");
328 int regenc = reg & 7;
329 int baseenc = base & 7;
330 int indexenc = index & 7;
331
332 // There is no index & no scale, use form without SIB byte
333 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
334 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
335 if (disp == 0 && base != RBP_enc && base != R13_enc) {
336 emit_rm(cbuf, 0x0, regenc, baseenc); // *
337 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
338 // If 8-bit displacement, mode 0x1
339 emit_rm(cbuf, 0x1, regenc, baseenc); // *
340 emit_d8(cbuf, disp);
341 } else {
342 // If 32-bit displacement
343 if (base == -1) { // Special flag for absolute address
344 emit_rm(cbuf, 0x0, regenc, 0x5); // *
345 if (disp_reloc != relocInfo::none) {
346 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
347 } else {
348 emit_d32(cbuf, disp);
349 }
350 } else {
351 // Normal base + offset
352 emit_rm(cbuf, 0x2, regenc, baseenc); // *
353 if (disp_reloc != relocInfo::none) {
354 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
355 } else {
356 emit_d32(cbuf, disp);
357 }
358 }
359 }
360 } else {
361 // Else, encode with the SIB byte
362 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
363 if (disp == 0 && base != RBP_enc && base != R13_enc) {
364 // If no displacement
365 emit_rm(cbuf, 0x0, regenc, 0x4); // *
366 emit_rm(cbuf, scale, indexenc, baseenc);
367 } else {
368 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
369 // If 8-bit displacement, mode 0x1
370 emit_rm(cbuf, 0x1, regenc, 0x4); // *
371 emit_rm(cbuf, scale, indexenc, baseenc);
372 emit_d8(cbuf, disp);
373 } else {
374 // If 32-bit displacement
375 if (base == 0x04 ) {
376 emit_rm(cbuf, 0x2, regenc, 0x4);
377 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
378 } else {
379 emit_rm(cbuf, 0x2, regenc, 0x4);
380 emit_rm(cbuf, scale, indexenc, baseenc); // *
381 }
382 if (disp_reloc != relocInfo::none) {
383 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
384 } else {
385 emit_d32(cbuf, disp);
386 }
387 }
388 }
389 }
390}
391
392// This could be in MacroAssembler but it's fairly C2 specific
393void emit_cmpfp_fixup(MacroAssembler& _masm) {
394 Label exit;
395 __ jccb(Assembler::noParity, exit);
396 __ pushf();
397 //
398 // comiss/ucomiss instructions set ZF,PF,CF flags and
399 // zero OF,AF,SF for NaN values.
400 // Fixup flags by zeroing ZF,PF so that compare of NaN
401 // values returns 'less than' result (CF is set).
402 // Leave the rest of flags unchanged.
403 //
404 // 7 6 5 4 3 2 1 0
405 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
406 // 0 0 1 0 1 0 1 1 (0x2B)
407 //
408 __ andq(Address(rsp, 0), 0xffffff2b);
409 __ popf();
410 __ bind(exit);
411}
412
413void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
414 Label done;
415 __ movl(dst, -1);
416 __ jcc(Assembler::parity, done);
417 __ jcc(Assembler::below, done);
418 __ setb(Assembler::notEqual, dst);
419 __ movzbl(dst, dst);
420 __ bind(done);
421}
422
423// Math.min() # Math.max()
424// --------------------------
425// ucomis[s/d] #
426// ja -> b # a
427// jp -> NaN # NaN
428// jb -> a # b
429// je #
430// |-jz -> a | b # a & b
431// | -> a #
432void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
433 XMMRegister a, XMMRegister b,
434 XMMRegister xmmt, Register rt,
435 bool min, bool single) {
436
437 Label nan, zero, below, above, done;
438
439 if (single)
440 __ ucomiss(a, b);
441 else
442 __ ucomisd(a, b);
443
444 if (dst->encoding() != (min ? b : a)->encoding())
445 __ jccb(Assembler::above, above); // CF=0 & ZF=0
446 else
447 __ jccb(Assembler::above, done);
448
449 __ jccb(Assembler::parity, nan); // PF=1
450 __ jccb(Assembler::below, below); // CF=1
451
452 // equal
453 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
454 if (single) {
455 __ ucomiss(a, xmmt);
456 __ jccb(Assembler::equal, zero);
457
458 __ movflt(dst, a);
459 __ jmp(done);
460 }
461 else {
462 __ ucomisd(a, xmmt);
463 __ jccb(Assembler::equal, zero);
464
465 __ movdbl(dst, a);
466 __ jmp(done);
467 }
468
469 __ bind(zero);
470 if (min)
471 __ vpor(dst, a, b, Assembler::AVX_128bit);
472 else
473 __ vpand(dst, a, b, Assembler::AVX_128bit);
474
475 __ jmp(done);
476
477 __ bind(above);
478 if (single)
479 __ movflt(dst, min ? b : a);
480 else
481 __ movdbl(dst, min ? b : a);
482
483 __ jmp(done);
484
485 __ bind(nan);
486 if (single) {
487 __ movl(rt, 0x7fc00000); // Float.NaN
488 __ movdl(dst, rt);
489 }
490 else {
491 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
492 __ movdq(dst, rt);
493 }
494 __ jmp(done);
495
496 __ bind(below);
497 if (single)
498 __ movflt(dst, min ? a : b);
499 else
500 __ movdbl(dst, min ? a : b);
501
502 __ bind(done);
503}
504
505//=============================================================================
506const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
507
508int Compile::ConstantTable::calculate_table_base_offset() const {
509 return 0; // absolute addressing, no offset
510}
511
512bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
513void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
514 ShouldNotReachHere();
515}
516
517void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
518 // Empty encoding
519}
520
521uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
522 return 0;
523}
524
525#ifndef PRODUCT
526void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
527 st->print("# MachConstantBaseNode (empty encoding)");
528}
529#endif
530
531
532//=============================================================================
533#ifndef PRODUCT
534void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
535 Compile* C = ra_->C;
536
537 int framesize = C->frame_size_in_bytes();
538 int bangsize = C->bang_size_in_bytes();
539 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
540 // Remove wordSize for return addr which is already pushed.
541 framesize -= wordSize;
542
543 if (C->need_stack_bang(bangsize)) {
544 framesize -= wordSize;
545 st->print("# stack bang (%d bytes)", bangsize);
546 st->print("\n\t");
547 st->print("pushq rbp\t# Save rbp");
548 if (PreserveFramePointer) {
549 st->print("\n\t");
550 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
551 }
552 if (framesize) {
553 st->print("\n\t");
554 st->print("subq rsp, #%d\t# Create frame",framesize);
555 }
556 } else {
557 st->print("subq rsp, #%d\t# Create frame",framesize);
558 st->print("\n\t");
559 framesize -= wordSize;
560 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
561 if (PreserveFramePointer) {
562 st->print("\n\t");
563 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
564 if (framesize > 0) {
565 st->print("\n\t");
566 st->print("addq rbp, #%d", framesize);
567 }
568 }
569 }
570
571 if (VerifyStackAtCalls) {
572 st->print("\n\t");
573 framesize -= wordSize;
574 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
575#ifdef ASSERT
576 st->print("\n\t");
577 st->print("# stack alignment check");
578#endif
579 }
580 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
581 st->print("\n\t");
582 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
583 st->print("\n\t");
584 st->print("je fast_entry\t");
585 st->print("\n\t");
586 st->print("call #nmethod_entry_barrier_stub\t");
587 st->print("\n\tfast_entry:");
588 }
589 st->cr();
590}
591#endif
592
593void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
594 Compile* C = ra_->C;
595 MacroAssembler _masm(&cbuf);
596
597 int framesize = C->frame_size_in_bytes();
598 int bangsize = C->bang_size_in_bytes();
599
600 if (C->clinit_barrier_on_entry()) {
601 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
602 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
603
604 Label L_skip_barrier;
605 Register klass = rscratch1;
606
607 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
608 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
609
610 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
611
612 __ bind(L_skip_barrier);
613 }
614
615 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
616
617 C->set_frame_complete(cbuf.insts_size());
618
619 if (C->has_mach_constant_base_node()) {
620 // NOTE: We set the table base offset here because users might be
621 // emitted before MachConstantBaseNode.
622 Compile::ConstantTable& constant_table = C->constant_table();
623 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
624 }
625}
626
627uint MachPrologNode::size(PhaseRegAlloc* ra_) const
628{
629 return MachNode::size(ra_); // too many variables; just compute it
630 // the hard way
631}
632
633int MachPrologNode::reloc() const
634{
635 return 0; // a large enough number
636}
637
638//=============================================================================
639#ifndef PRODUCT
640void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
641{
642 Compile* C = ra_->C;
643 if (generate_vzeroupper(C)) {
644 st->print("vzeroupper");
645 st->cr(); st->print("\t");
646 }
647
648 int framesize = C->frame_size_in_bytes();
649 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
650 // Remove word for return adr already pushed
651 // and RBP
652 framesize -= 2*wordSize;
653
654 if (framesize) {
655 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
656 st->print("\t");
657 }
658
659 st->print_cr("popq rbp");
660 if (do_polling() && C->is_method_compilation()) {
661 st->print("\t");
662 if (SafepointMechanism::uses_thread_local_poll()) {
663 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
664 "testl rax, [rscratch1]\t"
665 "# Safepoint: poll for GC");
666 } else if (Assembler::is_polling_page_far()) {
667 st->print_cr("movq rscratch1, #polling_page_address\n\t"
668 "testl rax, [rscratch1]\t"
669 "# Safepoint: poll for GC");
670 } else {
671 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
672 "# Safepoint: poll for GC");
673 }
674 }
675}
676#endif
677
678void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
679{
680 Compile* C = ra_->C;
681 MacroAssembler _masm(&cbuf);
682
683 if (generate_vzeroupper(C)) {
684 // Clear upper bits of YMM registers when current compiled code uses
685 // wide vectors to avoid AVX <-> SSE transition penalty during call.
686 __ vzeroupper();
687 }
688
689 int framesize = C->frame_size_in_bytes();
690 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
691 // Remove word for return adr already pushed
692 // and RBP
693 framesize -= 2*wordSize;
694
695 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
696
697 if (framesize) {
698 emit_opcode(cbuf, Assembler::REX_W);
699 if (framesize < 0x80) {
700 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
701 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
702 emit_d8(cbuf, framesize);
703 } else {
704 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
705 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
706 emit_d32(cbuf, framesize);
707 }
708 }
709
710 // popq rbp
711 emit_opcode(cbuf, 0x58 | RBP_enc);
712
713 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
714 __ reserved_stack_check();
715 }
716
717 if (do_polling() && C->is_method_compilation()) {
718 MacroAssembler _masm(&cbuf);
719 if (SafepointMechanism::uses_thread_local_poll()) {
720 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
721 __ relocate(relocInfo::poll_return_type);
722 __ testl(rax, Address(rscratch1, 0));
723 } else {
724 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
725 if (Assembler::is_polling_page_far()) {
726 __ lea(rscratch1, polling_page);
727 __ relocate(relocInfo::poll_return_type);
728 __ testl(rax, Address(rscratch1, 0));
729 } else {
730 __ testl(rax, polling_page);
731 }
732 }
733 }
734}
735
736uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
737{
738 return MachNode::size(ra_); // too many variables; just compute it
739 // the hard way
740}
741
742int MachEpilogNode::reloc() const
743{
744 return 2; // a large enough number
745}
746
747const Pipeline* MachEpilogNode::pipeline() const
748{
749 return MachNode::pipeline_class();
750}
751
752int MachEpilogNode::safepoint_offset() const
753{
754 return 0;
755}
756
757//=============================================================================
758
759enum RC {
760 rc_bad,
761 rc_int,
762 rc_float,
763 rc_stack
764};
765
766static enum RC rc_class(OptoReg::Name reg)
767{
768 if( !OptoReg::is_valid(reg) ) return rc_bad;
769
770 if (OptoReg::is_stack(reg)) return rc_stack;
771
772 VMReg r = OptoReg::as_VMReg(reg);
773
774 if (r->is_Register()) return rc_int;
775
776 assert(r->is_XMMRegister(), "must be");
777 return rc_float;
778}
779
780// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
781static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
782 int src_hi, int dst_hi, uint ireg, outputStream* st);
783
784static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
785 int stack_offset, int reg, uint ireg, outputStream* st);
786
787static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
788 int dst_offset, uint ireg, outputStream* st) {
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 switch (ireg) {
792 case Op_VecS:
793 __ movq(Address(rsp, -8), rax);
794 __ movl(rax, Address(rsp, src_offset));
795 __ movl(Address(rsp, dst_offset), rax);
796 __ movq(rax, Address(rsp, -8));
797 break;
798 case Op_VecD:
799 __ pushq(Address(rsp, src_offset));
800 __ popq (Address(rsp, dst_offset));
801 break;
802 case Op_VecX:
803 __ pushq(Address(rsp, src_offset));
804 __ popq (Address(rsp, dst_offset));
805 __ pushq(Address(rsp, src_offset+8));
806 __ popq (Address(rsp, dst_offset+8));
807 break;
808 case Op_VecY:
809 __ vmovdqu(Address(rsp, -32), xmm0);
810 __ vmovdqu(xmm0, Address(rsp, src_offset));
811 __ vmovdqu(Address(rsp, dst_offset), xmm0);
812 __ vmovdqu(xmm0, Address(rsp, -32));
813 break;
814 case Op_VecZ:
815 __ evmovdquq(Address(rsp, -64), xmm0, 2);
816 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
817 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
818 __ evmovdquq(xmm0, Address(rsp, -64), 2);
819 break;
820 default:
821 ShouldNotReachHere();
822 }
823#ifndef PRODUCT
824 } else {
825 switch (ireg) {
826 case Op_VecS:
827 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
828 "movl rax, [rsp + #%d]\n\t"
829 "movl [rsp + #%d], rax\n\t"
830 "movq rax, [rsp - #8]",
831 src_offset, dst_offset);
832 break;
833 case Op_VecD:
834 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
835 "popq [rsp + #%d]",
836 src_offset, dst_offset);
837 break;
838 case Op_VecX:
839 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
840 "popq [rsp + #%d]\n\t"
841 "pushq [rsp + #%d]\n\t"
842 "popq [rsp + #%d]",
843 src_offset, dst_offset, src_offset+8, dst_offset+8);
844 break;
845 case Op_VecY:
846 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
847 "vmovdqu xmm0, [rsp + #%d]\n\t"
848 "vmovdqu [rsp + #%d], xmm0\n\t"
849 "vmovdqu xmm0, [rsp - #32]",
850 src_offset, dst_offset);
851 break;
852 case Op_VecZ:
853 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
854 "vmovdqu xmm0, [rsp + #%d]\n\t"
855 "vmovdqu [rsp + #%d], xmm0\n\t"
856 "vmovdqu xmm0, [rsp - #64]",
857 src_offset, dst_offset);
858 break;
859 default:
860 ShouldNotReachHere();
861 }
862#endif
863 }
864}
865
866uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
867 PhaseRegAlloc* ra_,
868 bool do_size,
869 outputStream* st) const {
870 assert(cbuf != NULL || st != NULL, "sanity");
871 // Get registers to move
872 OptoReg::Name src_second = ra_->get_reg_second(in(1));
873 OptoReg::Name src_first = ra_->get_reg_first(in(1));
874 OptoReg::Name dst_second = ra_->get_reg_second(this);
875 OptoReg::Name dst_first = ra_->get_reg_first(this);
876
877 enum RC src_second_rc = rc_class(src_second);
878 enum RC src_first_rc = rc_class(src_first);
879 enum RC dst_second_rc = rc_class(dst_second);
880 enum RC dst_first_rc = rc_class(dst_first);
881
882 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
883 "must move at least 1 register" );
884
885 if (src_first == dst_first && src_second == dst_second) {
886 // Self copy, no move
887 return 0;
888 }
889 if (bottom_type()->isa_vect() != NULL) {
890 uint ireg = ideal_reg();
891 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
892 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
893 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
894 // mem -> mem
895 int src_offset = ra_->reg2offset(src_first);
896 int dst_offset = ra_->reg2offset(dst_first);
897 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
898 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
899 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
900 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
901 int stack_offset = ra_->reg2offset(dst_first);
902 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
903 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
904 int stack_offset = ra_->reg2offset(src_first);
905 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
906 } else {
907 ShouldNotReachHere();
908 }
909 return 0;
910 }
911 if (src_first_rc == rc_stack) {
912 // mem ->
913 if (dst_first_rc == rc_stack) {
914 // mem -> mem
915 assert(src_second != dst_first, "overlap");
916 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
917 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
918 // 64-bit
919 int src_offset = ra_->reg2offset(src_first);
920 int dst_offset = ra_->reg2offset(dst_first);
921 if (cbuf) {
922 MacroAssembler _masm(cbuf);
923 __ pushq(Address(rsp, src_offset));
924 __ popq (Address(rsp, dst_offset));
925#ifndef PRODUCT
926 } else {
927 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
928 "popq [rsp + #%d]",
929 src_offset, dst_offset);
930#endif
931 }
932 } else {
933 // 32-bit
934 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
935 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
936 // No pushl/popl, so:
937 int src_offset = ra_->reg2offset(src_first);
938 int dst_offset = ra_->reg2offset(dst_first);
939 if (cbuf) {
940 MacroAssembler _masm(cbuf);
941 __ movq(Address(rsp, -8), rax);
942 __ movl(rax, Address(rsp, src_offset));
943 __ movl(Address(rsp, dst_offset), rax);
944 __ movq(rax, Address(rsp, -8));
945#ifndef PRODUCT
946 } else {
947 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
948 "movl rax, [rsp + #%d]\n\t"
949 "movl [rsp + #%d], rax\n\t"
950 "movq rax, [rsp - #8]",
951 src_offset, dst_offset);
952#endif
953 }
954 }
955 return 0;
956 } else if (dst_first_rc == rc_int) {
957 // mem -> gpr
958 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
959 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
960 // 64-bit
961 int offset = ra_->reg2offset(src_first);
962 if (cbuf) {
963 MacroAssembler _masm(cbuf);
964 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
965#ifndef PRODUCT
966 } else {
967 st->print("movq %s, [rsp + #%d]\t# spill",
968 Matcher::regName[dst_first],
969 offset);
970#endif
971 }
972 } else {
973 // 32-bit
974 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
975 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
976 int offset = ra_->reg2offset(src_first);
977 if (cbuf) {
978 MacroAssembler _masm(cbuf);
979 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
980#ifndef PRODUCT
981 } else {
982 st->print("movl %s, [rsp + #%d]\t# spill",
983 Matcher::regName[dst_first],
984 offset);
985#endif
986 }
987 }
988 return 0;
989 } else if (dst_first_rc == rc_float) {
990 // mem-> xmm
991 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
992 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
993 // 64-bit
994 int offset = ra_->reg2offset(src_first);
995 if (cbuf) {
996 MacroAssembler _masm(cbuf);
997 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
998#ifndef PRODUCT
999 } else {
1000 st->print("%s %s, [rsp + #%d]\t# spill",
1001 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1002 Matcher::regName[dst_first],
1003 offset);
1004#endif
1005 }
1006 } else {
1007 // 32-bit
1008 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1009 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1010 int offset = ra_->reg2offset(src_first);
1011 if (cbuf) {
1012 MacroAssembler _masm(cbuf);
1013 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1014#ifndef PRODUCT
1015 } else {
1016 st->print("movss %s, [rsp + #%d]\t# spill",
1017 Matcher::regName[dst_first],
1018 offset);
1019#endif
1020 }
1021 }
1022 return 0;
1023 }
1024 } else if (src_first_rc == rc_int) {
1025 // gpr ->
1026 if (dst_first_rc == rc_stack) {
1027 // gpr -> mem
1028 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1029 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1030 // 64-bit
1031 int offset = ra_->reg2offset(dst_first);
1032 if (cbuf) {
1033 MacroAssembler _masm(cbuf);
1034 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1035#ifndef PRODUCT
1036 } else {
1037 st->print("movq [rsp + #%d], %s\t# spill",
1038 offset,
1039 Matcher::regName[src_first]);
1040#endif
1041 }
1042 } else {
1043 // 32-bit
1044 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1045 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1046 int offset = ra_->reg2offset(dst_first);
1047 if (cbuf) {
1048 MacroAssembler _masm(cbuf);
1049 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1050#ifndef PRODUCT
1051 } else {
1052 st->print("movl [rsp + #%d], %s\t# spill",
1053 offset,
1054 Matcher::regName[src_first]);
1055#endif
1056 }
1057 }
1058 return 0;
1059 } else if (dst_first_rc == rc_int) {
1060 // gpr -> gpr
1061 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1062 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1063 // 64-bit
1064 if (cbuf) {
1065 MacroAssembler _masm(cbuf);
1066 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1067 as_Register(Matcher::_regEncode[src_first]));
1068#ifndef PRODUCT
1069 } else {
1070 st->print("movq %s, %s\t# spill",
1071 Matcher::regName[dst_first],
1072 Matcher::regName[src_first]);
1073#endif
1074 }
1075 return 0;
1076 } else {
1077 // 32-bit
1078 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1079 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1080 if (cbuf) {
1081 MacroAssembler _masm(cbuf);
1082 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1083 as_Register(Matcher::_regEncode[src_first]));
1084#ifndef PRODUCT
1085 } else {
1086 st->print("movl %s, %s\t# spill",
1087 Matcher::regName[dst_first],
1088 Matcher::regName[src_first]);
1089#endif
1090 }
1091 return 0;
1092 }
1093 } else if (dst_first_rc == rc_float) {
1094 // gpr -> xmm
1095 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1096 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1097 // 64-bit
1098 if (cbuf) {
1099 MacroAssembler _masm(cbuf);
1100 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1101#ifndef PRODUCT
1102 } else {
1103 st->print("movdq %s, %s\t# spill",
1104 Matcher::regName[dst_first],
1105 Matcher::regName[src_first]);
1106#endif
1107 }
1108 } else {
1109 // 32-bit
1110 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1111 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1112 if (cbuf) {
1113 MacroAssembler _masm(cbuf);
1114 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1115#ifndef PRODUCT
1116 } else {
1117 st->print("movdl %s, %s\t# spill",
1118 Matcher::regName[dst_first],
1119 Matcher::regName[src_first]);
1120#endif
1121 }
1122 }
1123 return 0;
1124 }
1125 } else if (src_first_rc == rc_float) {
1126 // xmm ->
1127 if (dst_first_rc == rc_stack) {
1128 // xmm -> mem
1129 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1130 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1131 // 64-bit
1132 int offset = ra_->reg2offset(dst_first);
1133 if (cbuf) {
1134 MacroAssembler _masm(cbuf);
1135 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1136#ifndef PRODUCT
1137 } else {
1138 st->print("movsd [rsp + #%d], %s\t# spill",
1139 offset,
1140 Matcher::regName[src_first]);
1141#endif
1142 }
1143 } else {
1144 // 32-bit
1145 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1146 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1147 int offset = ra_->reg2offset(dst_first);
1148 if (cbuf) {
1149 MacroAssembler _masm(cbuf);
1150 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1151#ifndef PRODUCT
1152 } else {
1153 st->print("movss [rsp + #%d], %s\t# spill",
1154 offset,
1155 Matcher::regName[src_first]);
1156#endif
1157 }
1158 }
1159 return 0;
1160 } else if (dst_first_rc == rc_int) {
1161 // xmm -> gpr
1162 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1163 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1164 // 64-bit
1165 if (cbuf) {
1166 MacroAssembler _masm(cbuf);
1167 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1168#ifndef PRODUCT
1169 } else {
1170 st->print("movdq %s, %s\t# spill",
1171 Matcher::regName[dst_first],
1172 Matcher::regName[src_first]);
1173#endif
1174 }
1175 } else {
1176 // 32-bit
1177 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1178 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1179 if (cbuf) {
1180 MacroAssembler _masm(cbuf);
1181 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1182#ifndef PRODUCT
1183 } else {
1184 st->print("movdl %s, %s\t# spill",
1185 Matcher::regName[dst_first],
1186 Matcher::regName[src_first]);
1187#endif
1188 }
1189 }
1190 return 0;
1191 } else if (dst_first_rc == rc_float) {
1192 // xmm -> xmm
1193 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1194 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1195 // 64-bit
1196 if (cbuf) {
1197 MacroAssembler _masm(cbuf);
1198 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1199#ifndef PRODUCT
1200 } else {
1201 st->print("%s %s, %s\t# spill",
1202 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1203 Matcher::regName[dst_first],
1204 Matcher::regName[src_first]);
1205#endif
1206 }
1207 } else {
1208 // 32-bit
1209 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1210 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1211 if (cbuf) {
1212 MacroAssembler _masm(cbuf);
1213 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1214#ifndef PRODUCT
1215 } else {
1216 st->print("%s %s, %s\t# spill",
1217 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1218 Matcher::regName[dst_first],
1219 Matcher::regName[src_first]);
1220#endif
1221 }
1222 }
1223 return 0;
1224 }
1225 }
1226
1227 assert(0," foo ");
1228 Unimplemented();
1229 return 0;
1230}
1231
1232#ifndef PRODUCT
1233void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1234 implementation(NULL, ra_, false, st);
1235}
1236#endif
1237
1238void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1239 implementation(&cbuf, ra_, false, NULL);
1240}
1241
1242uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1243 return MachNode::size(ra_);
1244}
1245
1246//=============================================================================
1247#ifndef PRODUCT
1248void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1249{
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 int reg = ra_->get_reg_first(this);
1252 st->print("leaq %s, [rsp + #%d]\t# box lock",
1253 Matcher::regName[reg], offset);
1254}
1255#endif
1256
1257void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1258{
1259 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1260 int reg = ra_->get_encode(this);
1261 if (offset >= 0x80) {
1262 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1263 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1264 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1265 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1266 emit_d32(cbuf, offset);
1267 } else {
1268 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1269 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1270 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1271 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1272 emit_d8(cbuf, offset);
1273 }
1274}
1275
1276uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1277{
1278 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1279 return (offset < 0x80) ? 5 : 8; // REX
1280}
1281
1282//=============================================================================
1283#ifndef PRODUCT
1284void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1285{
1286 if (UseCompressedClassPointers) {
1287 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1288 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1289 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1290 } else {
1291 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1292 "# Inline cache check");
1293 }
1294 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1295 st->print_cr("\tnop\t# nops to align entry point");
1296}
1297#endif
1298
1299void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1300{
1301 MacroAssembler masm(&cbuf);
1302 uint insts_size = cbuf.insts_size();
1303 if (UseCompressedClassPointers) {
1304 masm.load_klass(rscratch1, j_rarg0);
1305 masm.cmpptr(rax, rscratch1);
1306 } else {
1307 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1308 }
1309
1310 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1311
1312 /* WARNING these NOPs are critical so that verified entry point is properly
1313 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1314 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1315 if (OptoBreakpoint) {
1316 // Leave space for int3
1317 nops_cnt -= 1;
1318 }
1319 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1320 if (nops_cnt > 0)
1321 masm.nop(nops_cnt);
1322}
1323
1324uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1325{
1326 return MachNode::size(ra_); // too many variables; just compute it
1327 // the hard way
1328}
1329
1330
1331//=============================================================================
1332
1333int Matcher::regnum_to_fpu_offset(int regnum)
1334{
1335 return regnum - 32; // The FP registers are in the second chunk
1336}
1337
1338// This is UltraSparc specific, true just means we have fast l2f conversion
1339const bool Matcher::convL2FSupported(void) {
1340 return true;
1341}
1342
1343// Is this branch offset short enough that a short branch can be used?
1344//
1345// NOTE: If the platform does not provide any short branch variants, then
1346// this method should return false for offset 0.
1347bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1348 // The passed offset is relative to address of the branch.
1349 // On 86 a branch displacement is calculated relative to address
1350 // of a next instruction.
1351 offset -= br_size;
1352
1353 // the short version of jmpConUCF2 contains multiple branches,
1354 // making the reach slightly less
1355 if (rule == jmpConUCF2_rule)
1356 return (-126 <= offset && offset <= 125);
1357 return (-128 <= offset && offset <= 127);
1358}
1359
1360const bool Matcher::isSimpleConstant64(jlong value) {
1361 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1362 //return value == (int) value; // Cf. storeImmL and immL32.
1363
1364 // Probably always true, even if a temp register is required.
1365 return true;
1366}
1367
1368// The ecx parameter to rep stosq for the ClearArray node is in words.
1369const bool Matcher::init_array_count_is_in_bytes = false;
1370
1371// No additional cost for CMOVL.
1372const int Matcher::long_cmove_cost() { return 0; }
1373
1374// No CMOVF/CMOVD with SSE2
1375const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1376
1377// Does the CPU require late expand (see block.cpp for description of late expand)?
1378const bool Matcher::require_postalloc_expand = false;
1379
1380// Do we need to mask the count passed to shift instructions or does
1381// the cpu only look at the lower 5/6 bits anyway?
1382const bool Matcher::need_masked_shift_count = false;
1383
1384bool Matcher::narrow_oop_use_complex_address() {
1385 assert(UseCompressedOops, "only for compressed oops code");
1386 return (LogMinObjAlignmentInBytes <= 3);
1387}
1388
1389bool Matcher::narrow_klass_use_complex_address() {
1390 assert(UseCompressedClassPointers, "only for compressed klass code");
1391 return (LogKlassAlignmentInBytes <= 3);
1392}
1393
1394bool Matcher::const_oop_prefer_decode() {
1395 // Prefer ConN+DecodeN over ConP.
1396 return true;
1397}
1398
1399bool Matcher::const_klass_prefer_decode() {
1400 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1401 // or condisider the following:
1402 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1403 //return CompressedKlassPointers::base() == NULL;
1404 return true;
1405}
1406
1407// Is it better to copy float constants, or load them directly from
1408// memory? Intel can load a float constant from a direct address,
1409// requiring no extra registers. Most RISCs will have to materialize
1410// an address into a register first, so they would do better to copy
1411// the constant from stack.
1412const bool Matcher::rematerialize_float_constants = true; // XXX
1413
1414// If CPU can load and store mis-aligned doubles directly then no
1415// fixup is needed. Else we split the double into 2 integer pieces
1416// and move it piece-by-piece. Only happens when passing doubles into
1417// C code as the Java calling convention forces doubles to be aligned.
1418const bool Matcher::misaligned_doubles_ok = true;
1419
1420// No-op on amd64
1421void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1422
1423// Advertise here if the CPU requires explicit rounding operations to
1424// implement the UseStrictFP mode.
1425const bool Matcher::strict_fp_requires_explicit_rounding = true;
1426
1427// Are floats conerted to double when stored to stack during deoptimization?
1428// On x64 it is stored without convertion so we can use normal access.
1429bool Matcher::float_in_double() { return false; }
1430
1431// Do ints take an entire long register or just half?
1432const bool Matcher::int_in_long = true;
1433
1434// Return whether or not this register is ever used as an argument.
1435// This function is used on startup to build the trampoline stubs in
1436// generateOptoStub. Registers not mentioned will be killed by the VM
1437// call in the trampoline, and arguments in those registers not be
1438// available to the callee.
1439bool Matcher::can_be_java_arg(int reg)
1440{
1441 return
1442 reg == RDI_num || reg == RDI_H_num ||
1443 reg == RSI_num || reg == RSI_H_num ||
1444 reg == RDX_num || reg == RDX_H_num ||
1445 reg == RCX_num || reg == RCX_H_num ||
1446 reg == R8_num || reg == R8_H_num ||
1447 reg == R9_num || reg == R9_H_num ||
1448 reg == R12_num || reg == R12_H_num ||
1449 reg == XMM0_num || reg == XMM0b_num ||
1450 reg == XMM1_num || reg == XMM1b_num ||
1451 reg == XMM2_num || reg == XMM2b_num ||
1452 reg == XMM3_num || reg == XMM3b_num ||
1453 reg == XMM4_num || reg == XMM4b_num ||
1454 reg == XMM5_num || reg == XMM5b_num ||
1455 reg == XMM6_num || reg == XMM6b_num ||
1456 reg == XMM7_num || reg == XMM7b_num;
1457}
1458
1459bool Matcher::is_spillable_arg(int reg)
1460{
1461 return can_be_java_arg(reg);
1462}
1463
1464bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1465 // In 64 bit mode a code which use multiply when
1466 // devisor is constant is faster than hardware
1467 // DIV instruction (it uses MulHiL).
1468 return false;
1469}
1470
1471// Register for DIVI projection of divmodI
1472RegMask Matcher::divI_proj_mask() {
1473 return INT_RAX_REG_mask();
1474}
1475
1476// Register for MODI projection of divmodI
1477RegMask Matcher::modI_proj_mask() {
1478 return INT_RDX_REG_mask();
1479}
1480
1481// Register for DIVL projection of divmodL
1482RegMask Matcher::divL_proj_mask() {
1483 return LONG_RAX_REG_mask();
1484}
1485
1486// Register for MODL projection of divmodL
1487RegMask Matcher::modL_proj_mask() {
1488 return LONG_RDX_REG_mask();
1489}
1490
1491// Register for saving SP into on method handle invokes. Not used on x86_64.
1492const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1493 return NO_REG_mask();
1494}
1495
1496
1497#line 1497 "ad_x86.cpp"
1498
1499
1500//SourceForm
1501
1502#line 1302 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
1503
1504
1505#include "opto/addnode.hpp"
1506
1507// Emit exception handler code.
1508// Stuff framesize into a register and call a VM stub routine.
1509int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1510
1511 // Note that the code buffer's insts_mark is always relative to insts.
1512 // That's why we must use the macroassembler to generate a handler.
1513 MacroAssembler _masm(&cbuf);
1514 address base = __ start_a_stub(size_exception_handler());
1515 if (base == NULL) {
1516 ciEnv::current()->record_failure("CodeCache is full");
1517 return 0; // CodeBuffer::expand failed
1518 }
1519 int offset = __ offset();
1520 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1521 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1522 __ end_a_stub();
1523 return offset;
1524}
1525
1526// Emit deopt handler code.
1527int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1528
1529 // Note that the code buffer's insts_mark is always relative to insts.
1530 // That's why we must use the macroassembler to generate a handler.
1531 MacroAssembler _masm(&cbuf);
1532 address base = __ start_a_stub(size_deopt_handler());
1533 if (base == NULL) {
1534 ciEnv::current()->record_failure("CodeCache is full");
1535 return 0; // CodeBuffer::expand failed
1536 }
1537 int offset = __ offset();
1538
1539#ifdef _LP64
1540 address the_pc = (address) __ pc();
1541 Label next;
1542 // push a "the_pc" on the stack without destroying any registers
1543 // as they all may be live.
1544
1545 // push address of "next"
1546 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1547 __ bind(next);
1548 // adjust it so it matches "the_pc"
1549 __ subptr(Address(rsp, 0), __ offset() - offset);
1550#else
1551 InternalAddress here(__ pc());
1552 __ pushptr(here.addr());
1553#endif
1554
1555 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1556 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow %d", (__ offset() - offset));
1557 __ end_a_stub();
1558 return offset;
1559}
1560
1561
1562//=============================================================================
1563
1564 // Float masks come from different places depending on platform.
1565#ifdef _LP64
1566 static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
1567 static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
1568 static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
1569 static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
1570#else
1571 static address float_signmask() { return (address)float_signmask_pool; }
1572 static address float_signflip() { return (address)float_signflip_pool; }
1573 static address double_signmask() { return (address)double_signmask_pool; }
1574 static address double_signflip() { return (address)double_signflip_pool; }
1575#endif
1576 static address vector_short_to_byte_mask() { return StubRoutines::x86::vector_short_to_byte_mask(); }
1577 static address vector_byte_perm_mask() { return StubRoutines::x86::vector_byte_perm_mask(); }
1578 static address vector_long_sign_mask() { return StubRoutines::x86::vector_long_sign_mask(); }
1579
1580//=============================================================================
1581const bool Matcher::match_rule_supported(int opcode) {
1582 if (!has_match_rule(opcode))
1583 return false;
1584
1585 bool ret_value = true;
1586 switch (opcode) {
1587 case Op_AbsVL:
1588 if (UseAVX < 3)
1589 ret_value = false;
1590 case Op_PopCountI:
1591 case Op_PopCountL:
1592 if (!UsePopCountInstruction)
1593 ret_value = false;
1594 break;
1595 case Op_PopCountVI:
1596 if (!UsePopCountInstruction || !VM_Version::supports_vpopcntdq())
1597 ret_value = false;
1598 break;
1599 case Op_MulVI:
1600 if ((UseSSE < 4) && (UseAVX < 1)) // only with SSE4_1 or AVX
1601 ret_value = false;
1602 break;
1603 case Op_MulVL:
1604 case Op_MulReductionVL:
1605 if (VM_Version::supports_avx512dq() == false)
1606 ret_value = false;
1607 break;
1608 case Op_AddReductionVL:
1609 if (UseAVX < 3) // only EVEX : vector connectivity becomes an issue here
1610 ret_value = false;
1611 break;
1612 case Op_AbsVB:
1613 case Op_AbsVS:
1614 case Op_AbsVI:
1615 case Op_AddReductionVI:
1616 if (UseSSE < 3) // requires at least SSE3
1617 ret_value = false;
1618 break;
1619 case Op_MulReductionVI:
1620 if (UseSSE < 4) // requires at least SSE4
1621 ret_value = false;
1622 break;
1623 case Op_AddReductionVF:
1624 case Op_AddReductionVD:
1625 case Op_MulReductionVF:
1626 case Op_MulReductionVD:
1627 if (UseSSE < 1) // requires at least SSE
1628 ret_value = false;
1629 break;
1630 case Op_SqrtVD:
1631 case Op_SqrtVF:
1632 if (UseAVX < 1) // enabled for AVX only
1633 ret_value = false;
1634 break;
1635 case Op_CompareAndSwapL:
1636#ifdef _LP64
1637 case Op_CompareAndSwapP:
1638#endif
1639 if (!VM_Version::supports_cx8())
1640 ret_value = false;
1641 break;
1642 case Op_CMoveVF:
1643 case Op_CMoveVD:
1644 if (UseAVX < 1 || UseAVX > 2)
1645 ret_value = false;
1646 break;
1647 case Op_StrIndexOf:
1648 if (!UseSSE42Intrinsics)
1649 ret_value = false;
1650 break;
1651 case Op_StrIndexOfChar:
1652 if (!UseSSE42Intrinsics)
1653 ret_value = false;
1654 break;
1655 case Op_OnSpinWait:
1656 if (VM_Version::supports_on_spin_wait() == false)
1657 ret_value = false;
1658 break;
1659 case Op_MulAddVS2VI:
1660 case Op_RShiftVL:
1661 case Op_AbsVD:
1662 case Op_NegVD:
1663 if (UseSSE < 2)
1664 ret_value = false;
1665 break;
1666 case Op_MulVB:
1667 case Op_LShiftVB:
1668 case Op_RShiftVB:
1669 case Op_URShiftVB:
1670 if (UseSSE < 4)
1671 ret_value = false;
1672 break;
1673#ifdef _LP64
1674 case Op_MaxD:
1675 case Op_MaxF:
1676 case Op_MinD:
1677 case Op_MinF:
1678 if (UseAVX < 1) // enabled for AVX only
1679 ret_value = false;
1680 break;
1681#endif
1682 }
1683
1684 return ret_value; // Per default match rules are supported.
1685}
1686
1687const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1688 // identify extra cases that we might want to provide match rules for
1689 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1690 bool ret_value = match_rule_supported(opcode);
1691 if (ret_value) {
1692 switch (opcode) {
1693 case Op_AbsVB:
1694 case Op_AddVB:
1695 case Op_SubVB:
1696 if ((vlen == 64) && (VM_Version::supports_avx512bw() == false))
1697 ret_value = false;
1698 break;
1699 case Op_AbsVS:
1700 case Op_AddVS:
1701 case Op_SubVS:
1702 case Op_MulVS:
1703 case Op_LShiftVS:
1704 case Op_RShiftVS:
1705 case Op_URShiftVS:
1706 if ((vlen == 32) && (VM_Version::supports_avx512bw() == false))
1707 ret_value = false;
1708 break;
1709 case Op_MulVB:
1710 case Op_LShiftVB:
1711 case Op_RShiftVB:
1712 case Op_URShiftVB:
1713 if ((vlen == 32 && UseAVX < 2) ||
1714 ((vlen == 64) && (VM_Version::supports_avx512bw() == false)))
1715 ret_value = false;
1716 break;
1717 case Op_NegVF:
1718 if ((vlen == 16) && (VM_Version::supports_avx512dq() == false))
1719 ret_value = false;
1720 break;
1721 case Op_CMoveVF:
1722 if (vlen != 8)
1723 ret_value = false;
1724 break;
1725 case Op_NegVD:
1726 if ((vlen == 8) && (VM_Version::supports_avx512dq() == false))
1727 ret_value = false;
1728 break;
1729 case Op_CMoveVD:
1730 if (vlen != 4)
1731 ret_value = false;
1732 break;
1733 }
1734 }
1735
1736 return ret_value; // Per default match rules are supported.
1737}
1738
1739const bool Matcher::has_predicated_vectors(void) {
1740 bool ret_value = false;
1741 if (UseAVX > 2) {
1742 ret_value = VM_Version::supports_avx512vl();
1743 }
1744
1745 return ret_value;
1746}
1747
1748const int Matcher::float_pressure(int default_pressure_threshold) {
1749 int float_pressure_threshold = default_pressure_threshold;
1750#ifdef _LP64
1751 if (UseAVX > 2) {
1752 // Increase pressure threshold on machines with AVX3 which have
1753 // 2x more XMM registers.
1754 float_pressure_threshold = default_pressure_threshold * 2;
1755 }
1756#endif
1757 return float_pressure_threshold;
1758}
1759
1760// Max vector size in bytes. 0 if not supported.
1761const int Matcher::vector_width_in_bytes(BasicType bt) {
1762 assert(is_java_primitive(bt), "only primitive type vectors");
1763 if (UseSSE < 2) return 0;
1764 // SSE2 supports 128bit vectors for all types.
1765 // AVX2 supports 256bit vectors for all types.
1766 // AVX2/EVEX supports 512bit vectors for all types.
1767 int size = (UseAVX > 1) ? (1 << UseAVX) * 8 : 16;
1768 // AVX1 supports 256bit vectors only for FLOAT and DOUBLE.
1769 if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE))
1770 size = (UseAVX > 2) ? 64 : 32;
1771 if (UseAVX > 2 && (bt == T_BYTE || bt == T_SHORT || bt == T_CHAR))
1772 size = (VM_Version::supports_avx512bw()) ? 64 : 32;
1773 // Use flag to limit vector size.
1774 size = MIN2(size,(int)MaxVectorSize);
1775 // Minimum 2 values in vector (or 4 for bytes).
1776 switch (bt) {
1777 case T_DOUBLE:
1778 case T_LONG:
1779 if (size < 16) return 0;
1780 break;
1781 case T_FLOAT:
1782 case T_INT:
1783 if (size < 8) return 0;
1784 break;
1785 case T_BOOLEAN:
1786 if (size < 4) return 0;
1787 break;
1788 case T_CHAR:
1789 if (size < 4) return 0;
1790 break;
1791 case T_BYTE:
1792 if (size < 4) return 0;
1793 break;
1794 case T_SHORT:
1795 if (size < 4) return 0;
1796 break;
1797 default:
1798 ShouldNotReachHere();
1799 }
1800 return size;
1801}
1802
1803// Limits on vector size (number of elements) loaded into vector.
1804const int Matcher::max_vector_size(const BasicType bt) {
1805 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1806}
1807const int Matcher::min_vector_size(const BasicType bt) {
1808 int max_size = max_vector_size(bt);
1809 // Min size which can be loaded into vector is 4 bytes.
1810 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
1811 return MIN2(size,max_size);
1812}
1813
1814// Vector ideal reg corresponding to specified size in bytes
1815const uint Matcher::vector_ideal_reg(int size) {
1816 assert(MaxVectorSize >= size, "");
1817 switch(size) {
1818 case 4: return Op_VecS;
1819 case 8: return Op_VecD;
1820 case 16: return Op_VecX;
1821 case 32: return Op_VecY;
1822 case 64: return Op_VecZ;
1823 }
1824 ShouldNotReachHere();
1825 return 0;
1826}
1827
1828// Only lowest bits of xmm reg are used for vector shift count.
1829const uint Matcher::vector_shift_count_ideal_reg(int size) {
1830 return Op_VecS;
1831}
1832
1833// x86 supports misaligned vectors store/load.
1834const bool Matcher::misaligned_vectors_ok() {
1835 return true;
1836}
1837
1838// x86 AES instructions are compatible with SunJCE expanded
1839// keys, hence we do not need to pass the original key to stubs
1840const bool Matcher::pass_original_key_for_aes() {
1841 return false;
1842}
1843
1844
1845const bool Matcher::convi2l_type_required = true;
1846
1847// Check for shift by small constant as well
1848static bool clone_shift(Node* shift, Matcher* matcher, Matcher::MStack& mstack, VectorSet& address_visited) {
1849 if (shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
1850 shift->in(2)->get_int() <= 3 &&
1851 // Are there other uses besides address expressions?
1852 !matcher->is_visited(shift)) {
1853 address_visited.set(shift->_idx); // Flag as address_visited
1854 mstack.push(shift->in(2), Matcher::Visit);
1855 Node *conv = shift->in(1);
1856#ifdef _LP64
1857 // Allow Matcher to match the rule which bypass
1858 // ConvI2L operation for an array index on LP64
1859 // if the index value is positive.
1860 if (conv->Opcode() == Op_ConvI2L &&
1861 conv->as_Type()->type()->is_long()->_lo >= 0 &&
1862 // Are there other uses besides address expressions?
1863 !matcher->is_visited(conv)) {
1864 address_visited.set(conv->_idx); // Flag as address_visited
1865 mstack.push(conv->in(1), Matcher::Pre_Visit);
1866 } else
1867#endif
1868 mstack.push(conv, Matcher::Pre_Visit);
1869 return true;
1870 }
1871 return false;
1872}
1873
1874// Should the Matcher clone shifts on addressing modes, expecting them
1875// to be subsumed into complex addressing expressions or compute them
1876// into registers?
1877bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1878 Node *off = m->in(AddPNode::Offset);
1879 if (off->is_Con()) {
1880 address_visited.test_set(m->_idx); // Flag as address_visited
1881 Node *adr = m->in(AddPNode::Address);
1882
1883 // Intel can handle 2 adds in addressing mode
1884 // AtomicAdd is not an addressing expression.
1885 // Cheap to find it by looking for screwy base.
1886 if (adr->is_AddP() &&
1887 !adr->in(AddPNode::Base)->is_top() &&
1888 LP64_ONLY( off->get_long() == (int) (off->get_long()) && ) // immL32
1889 // Are there other uses besides address expressions?
1890 !is_visited(adr)) {
1891 address_visited.set(adr->_idx); // Flag as address_visited
1892 Node *shift = adr->in(AddPNode::Offset);
1893 if (!clone_shift(shift, this, mstack, address_visited)) {
1894 mstack.push(shift, Pre_Visit);
1895 }
1896 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
1897 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
1898 } else {
1899 mstack.push(adr, Pre_Visit);
1900 }
1901
1902 // Clone X+offset as it also folds into most addressing expressions
1903 mstack.push(off, Visit);
1904 mstack.push(m->in(AddPNode::Base), Pre_Visit);
1905 return true;
1906 } else if (clone_shift(off, this, mstack, address_visited)) {
1907 address_visited.test_set(m->_idx); // Flag as address_visited
1908 mstack.push(m->in(AddPNode::Address), Pre_Visit);
1909 mstack.push(m->in(AddPNode::Base), Pre_Visit);
1910 return true;
1911 }
1912 return false;
1913}
1914
1915void Compile::reshape_address(AddPNode* addp) {
1916}
1917
1918// Helper methods for MachSpillCopyNode::implementation().
1919static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1920 int src_hi, int dst_hi, uint ireg, outputStream* st) {
1921 // In 64-bit VM size calculation is very complex. Emitting instructions
1922 // into scratch buffer is used to get size in 64-bit VM.
1923 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
1924 assert(ireg == Op_VecS || // 32bit vector
1925 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
1926 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
1927 "no non-adjacent vector moves" );
1928 if (cbuf) {
1929 MacroAssembler _masm(cbuf);
1930 int offset = __ offset();
1931 switch (ireg) {
1932 case Op_VecS: // copy whole register
1933 case Op_VecD:
1934 case Op_VecX:
1935#ifndef _LP64
1936 __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
1937#else
1938 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
1939 __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
1940 } else {
1941 __ vextractf32x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0);
1942 }
1943#endif
1944 break;
1945 case Op_VecY:
1946#ifndef _LP64
1947 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
1948#else
1949 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
1950 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
1951 } else {
1952 __ vextractf64x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0);
1953 }
1954#endif
1955 break;
1956 case Op_VecZ:
1957 __ evmovdquq(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 2);
1958 break;
1959 default:
1960 ShouldNotReachHere();
1961 }
1962 int size = __ offset() - offset;
1963#ifdef ASSERT
1964 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
1965 assert(!do_size || size == 4, "incorrect size calculattion");
1966#endif
1967 return size;
1968#ifndef PRODUCT
1969 } else if (!do_size) {
1970 switch (ireg) {
1971 case Op_VecS:
1972 case Op_VecD:
1973 case Op_VecX:
1974 st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
1975 break;
1976 case Op_VecY:
1977 case Op_VecZ:
1978 st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
1979 break;
1980 default:
1981 ShouldNotReachHere();
1982 }
1983#endif
1984 }
1985 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
1986 return (UseAVX > 2) ? 6 : 4;
1987}
1988
1989static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1990 int stack_offset, int reg, uint ireg, outputStream* st) {
1991 // In 64-bit VM size calculation is very complex. Emitting instructions
1992 // into scratch buffer is used to get size in 64-bit VM.
1993 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
1994 if (cbuf) {
1995 MacroAssembler _masm(cbuf);
1996 int offset = __ offset();
1997 if (is_load) {
1998 switch (ireg) {
1999 case Op_VecS:
2000 __ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2001 break;
2002 case Op_VecD:
2003 __ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2004 break;
2005 case Op_VecX:
2006#ifndef _LP64
2007 __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2008#else
2009 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2010 __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2011 } else {
2012 __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2013 __ vinsertf32x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0);
2014 }
2015#endif
2016 break;
2017 case Op_VecY:
2018#ifndef _LP64
2019 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2020#else
2021 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2022 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2023 } else {
2024 __ vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2025 __ vinsertf64x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0);
2026 }
2027#endif
2028 break;
2029 case Op_VecZ:
2030 __ evmovdquq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset), 2);
2031 break;
2032 default:
2033 ShouldNotReachHere();
2034 }
2035 } else { // store
2036 switch (ireg) {
2037 case Op_VecS:
2038 __ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2039 break;
2040 case Op_VecD:
2041 __ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2042 break;
2043 case Op_VecX:
2044#ifndef _LP64
2045 __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2046#else
2047 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2048 __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2049 }
2050 else {
2051 __ vextractf32x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0);
2052 }
2053#endif
2054 break;
2055 case Op_VecY:
2056#ifndef _LP64
2057 __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2058#else
2059 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2060 __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2061 }
2062 else {
2063 __ vextractf64x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0);
2064 }
2065#endif
2066 break;
2067 case Op_VecZ:
2068 __ evmovdquq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2069 break;
2070 default:
2071 ShouldNotReachHere();
2072 }
2073 }
2074 int size = __ offset() - offset;
2075#ifdef ASSERT
2076 int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : (UseAVX > 2) ? 6 : 4);
2077 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
2078 assert(!do_size || size == (5+offset_size), "incorrect size calculattion");
2079#endif
2080 return size;
2081#ifndef PRODUCT
2082 } else if (!do_size) {
2083 if (is_load) {
2084 switch (ireg) {
2085 case Op_VecS:
2086 st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2087 break;
2088 case Op_VecD:
2089 st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2090 break;
2091 case Op_VecX:
2092 st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2093 break;
2094 case Op_VecY:
2095 case Op_VecZ:
2096 st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2097 break;
2098 default:
2099 ShouldNotReachHere();
2100 }
2101 } else { // store
2102 switch (ireg) {
2103 case Op_VecS:
2104 st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2105 break;
2106 case Op_VecD:
2107 st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2108 break;
2109 case Op_VecX:
2110 st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2111 break;
2112 case Op_VecY:
2113 case Op_VecZ:
2114 st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2115 break;
2116 default:
2117 ShouldNotReachHere();
2118 }
2119 }
2120#endif
2121 }
2122 bool is_single_byte = false;
2123 int vec_len = 0;
2124 if ((UseAVX > 2) && (stack_offset != 0)) {
2125 int tuple_type = Assembler::EVEX_FVM;
2126 int input_size = Assembler::EVEX_32bit;
2127 switch (ireg) {
2128 case Op_VecS:
2129 tuple_type = Assembler::EVEX_T1S;
2130 break;
2131 case Op_VecD:
2132 tuple_type = Assembler::EVEX_T1S;
2133 input_size = Assembler::EVEX_64bit;
2134 break;
2135 case Op_VecX:
2136 break;
2137 case Op_VecY:
2138 vec_len = 1;
2139 break;
2140 case Op_VecZ:
2141 vec_len = 2;
2142 break;
2143 }
2144 is_single_byte = Assembler::query_compressed_disp_byte(stack_offset, true, vec_len, tuple_type, input_size, 0);
2145 }
2146 int offset_size = 0;
2147 int size = 5;
2148 if (UseAVX > 2 ) {
2149 if (VM_Version::supports_avx512novl() && (vec_len == 2)) {
2150 offset_size = (stack_offset == 0) ? 0 : ((is_single_byte) ? 1 : 4);
2151 size += 2; // Need an additional two bytes for EVEX encoding
2152 } else if (VM_Version::supports_avx512novl() && (vec_len < 2)) {
2153 offset_size = (stack_offset == 0) ? 0 : ((stack_offset <= 127) ? 1 : 4);
2154 } else {
2155 offset_size = (stack_offset == 0) ? 0 : ((is_single_byte) ? 1 : 4);
2156 size += 2; // Need an additional two bytes for EVEX encodding
2157 }
2158 } else {
2159 offset_size = (stack_offset == 0) ? 0 : ((stack_offset <= 127) ? 1 : 4);
2160 }
2161 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
2162 return size+offset_size;
2163}
2164
2165static inline jint replicate4_imm(int con, int width) {
2166 // Load a constant of "width" (in bytes) and replicate it to fill 32bit.
2167 assert(width == 1 || width == 2, "only byte or short types here");
2168 int bit_width = width * 8;
2169 jint val = con;
2170 val &= (1 << bit_width) - 1; // mask off sign bits
2171 while(bit_width < 32) {
2172 val |= (val << bit_width);
2173 bit_width <<= 1;
2174 }
2175 return val;
2176}
2177
2178static inline jlong replicate8_imm(int con, int width) {
2179 // Load a constant of "width" (in bytes) and replicate it to fill 64bit.
2180 assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here");
2181 int bit_width = width * 8;
2182 jlong val = con;
2183 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
2184 while(bit_width < 64) {
2185 val |= (val << bit_width);
2186 bit_width <<= 1;
2187 }
2188 return val;
2189}
2190
2191#ifndef PRODUCT
2192 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
2193 st->print("nop \t# %d bytes pad for loops and calls", _count);
2194 }
2195#endif
2196
2197 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
2198 MacroAssembler _masm(&cbuf);
2199 __ nop(_count);
2200 }
2201
2202 uint MachNopNode::size(PhaseRegAlloc*) const {
2203 return _count;
2204 }
2205
2206#ifndef PRODUCT
2207 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
2208 st->print("# breakpoint");
2209 }
2210#endif
2211
2212 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
2213 MacroAssembler _masm(&cbuf);
2214 __ int3();
2215 }
2216
2217 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2218 return MachNode::size(ra_);
2219 }
2220
2221
2222#line 2222 "ad_x86.cpp"
2223
2224
2225//SourceForm
2226
2227#line 30 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
2228
2229
2230#include "gc/z/zBarrierSetAssembler.hpp"
2231
2232static void z_load_barrier_slow_reg(MacroAssembler& _masm, Register dst, Address src, bool weak) {
2233 assert(dst != rsp, "Invalid register");
2234 assert(dst != r15, "Invalid register");
2235
2236 const address stub = weak ? ZBarrierSet::assembler()->load_barrier_weak_slow_stub(dst)
2237 : ZBarrierSet::assembler()->load_barrier_slow_stub(dst);
2238 __ lea(dst, src);
2239 __ call(RuntimeAddress(stub));
2240}
2241
2242
2243#line 2243 "ad_x86.cpp"
2244
2245
2246#ifndef PRODUCT
2247void Compile::adlc_verification() {
2248
2249 // Following assertions generated from definition section
2250}
2251#endif
2252
2253// Map from machine-independent register number to register_save_policy
2254const char register_save_policy[] = {
2255 'C', // R10
2256 'C', // R10_H
2257 'C', // R11
2258 'C', // R11_H
2259 'C', // R8
2260 'C', // R8_H
2261 'C', // R9
2262 'C', // R9_H
2263 'C', // R12
2264 'C', // R12_H
2265 'C', // RCX
2266 'C', // RCX_H
2267 'C', // RBX
2268 'C', // RBX_H
2269 'C', // RDI
2270 'C', // RDI_H
2271 'C', // RDX
2272 'C', // RDX_H
2273 'C', // RSI
2274 'C', // RSI_H
2275 'C', // RAX
2276 'C', // RAX_H
2277 'N', // RBP
2278 'N', // RBP_H
2279 'C', // R13
2280 'C', // R13_H
2281 'C', // R14
2282 'C', // R14_H
2283 'C', // R15
2284 'C', // R15_H
2285 'N', // RSP
2286 'N', // RSP_H
2287 'C', // XMM0
2288 'C', // XMM0b
2289 'C', // XMM0c
2290 'C', // XMM0d
2291 'C', // XMM0e
2292 'C', // XMM0f
2293 'C', // XMM0g
2294 'C', // XMM0h
2295 'C', // XMM0i
2296 'C', // XMM0j
2297 'C', // XMM0k
2298 'C', // XMM0l
2299 'C', // XMM0m
2300 'C', // XMM0n
2301 'C', // XMM0o
2302 'C', // XMM0p
2303 'C', // XMM1
2304 'C', // XMM1b
2305 'C', // XMM1c
2306 'C', // XMM1d
2307 'C', // XMM1e
2308 'C', // XMM1f
2309 'C', // XMM1g
2310 'C', // XMM1h
2311 'C', // XMM1i
2312 'C', // XMM1j
2313 'C', // XMM1k
2314 'C', // XMM1l
2315 'C', // XMM1m
2316 'C', // XMM1n
2317 'C', // XMM1o
2318 'C', // XMM1p
2319 'C', // XMM2
2320 'C', // XMM2b
2321 'C', // XMM2c
2322 'C', // XMM2d
2323 'C', // XMM2e
2324 'C', // XMM2f
2325 'C', // XMM2g
2326 'C', // XMM2h
2327 'C', // XMM2i
2328 'C', // XMM2j
2329 'C', // XMM2k
2330 'C', // XMM2l
2331 'C', // XMM2m
2332 'C', // XMM2n
2333 'C', // XMM2o
2334 'C', // XMM2p
2335 'C', // XMM3
2336 'C', // XMM3b
2337 'C', // XMM3c
2338 'C', // XMM3d
2339 'C', // XMM3e
2340 'C', // XMM3f
2341 'C', // XMM3g
2342 'C', // XMM3h
2343 'C', // XMM3i
2344 'C', // XMM3j
2345 'C', // XMM3k
2346 'C', // XMM3l
2347 'C', // XMM3m
2348 'C', // XMM3n
2349 'C', // XMM3o
2350 'C', // XMM3p
2351 'C', // XMM4
2352 'C', // XMM4b
2353 'C', // XMM4c
2354 'C', // XMM4d
2355 'C', // XMM4e
2356 'C', // XMM4f
2357 'C', // XMM4g
2358 'C', // XMM4h
2359 'C', // XMM4i
2360 'C', // XMM4j
2361 'C', // XMM4k
2362 'C', // XMM4l
2363 'C', // XMM4m
2364 'C', // XMM4n
2365 'C', // XMM4o
2366 'C', // XMM4p
2367 'C', // XMM5
2368 'C', // XMM5b
2369 'C', // XMM5c
2370 'C', // XMM5d
2371 'C', // XMM5e
2372 'C', // XMM5f
2373 'C', // XMM5g
2374 'C', // XMM5h
2375 'C', // XMM5i
2376 'C', // XMM5j
2377 'C', // XMM5k
2378 'C', // XMM5l
2379 'C', // XMM5m
2380 'C', // XMM5n
2381 'C', // XMM5o
2382 'C', // XMM5p
2383 'C', // XMM6
2384 'C', // XMM6b
2385 'C', // XMM6c
2386 'C', // XMM6d
2387 'C', // XMM6e
2388 'C', // XMM6f
2389 'C', // XMM6g
2390 'C', // XMM6h
2391 'C', // XMM6i
2392 'C', // XMM6j
2393 'C', // XMM6k
2394 'C', // XMM6l
2395 'C', // XMM6m
2396 'C', // XMM6n
2397 'C', // XMM6o
2398 'C', // XMM6p
2399 'C', // XMM7
2400 'C', // XMM7b
2401 'C', // XMM7c
2402 'C', // XMM7d
2403 'C', // XMM7e
2404 'C', // XMM7f
2405 'C', // XMM7g
2406 'C', // XMM7h
2407 'C', // XMM7i
2408 'C', // XMM7j
2409 'C', // XMM7k
2410 'C', // XMM7l
2411 'C', // XMM7m
2412 'C', // XMM7n
2413 'C', // XMM7o
2414 'C', // XMM7p
2415 'C', // XMM8
2416 'C', // XMM8b
2417 'C', // XMM8c
2418 'C', // XMM8d
2419 'C', // XMM8e
2420 'C', // XMM8f
2421 'C', // XMM8g
2422 'C', // XMM8h
2423 'C', // XMM8i
2424 'C', // XMM8j
2425 'C', // XMM8k
2426 'C', // XMM8l
2427 'C', // XMM8m
2428 'C', // XMM8n
2429 'C', // XMM8o
2430 'C', // XMM8p
2431 'C', // XMM9
2432 'C', // XMM9b
2433 'C', // XMM9c
2434 'C', // XMM9d
2435 'C', // XMM9e
2436 'C', // XMM9f
2437 'C', // XMM9g
2438 'C', // XMM9h
2439 'C', // XMM9i
2440 'C', // XMM9j
2441 'C', // XMM9k
2442 'C', // XMM9l
2443 'C', // XMM9m
2444 'C', // XMM9n
2445 'C', // XMM9o
2446 'C', // XMM9p
2447 'C', // XMM10
2448 'C', // XMM10b
2449 'C', // XMM10c
2450 'C', // XMM10d
2451 'C', // XMM10e
2452 'C', // XMM10f
2453 'C', // XMM10g
2454 'C', // XMM10h
2455 'C', // XMM10i
2456 'C', // XMM10j
2457 'C', // XMM10k
2458 'C', // XMM10l
2459 'C', // XMM10m
2460 'C', // XMM10n
2461 'C', // XMM10o
2462 'C', // XMM10p
2463 'C', // XMM11
2464 'C', // XMM11b
2465 'C', // XMM11c
2466 'C', // XMM11d
2467 'C', // XMM11e
2468 'C', // XMM11f
2469 'C', // XMM11g
2470 'C', // XMM11h
2471 'C', // XMM11i
2472 'C', // XMM11j
2473 'C', // XMM11k
2474 'C', // XMM11l
2475 'C', // XMM11m
2476 'C', // XMM11n
2477 'C', // XMM11o
2478 'C', // XMM11p
2479 'C', // XMM12
2480 'C', // XMM12b
2481 'C', // XMM12c
2482 'C', // XMM12d
2483 'C', // XMM12e
2484 'C', // XMM12f
2485 'C', // XMM12g
2486 'C', // XMM12h
2487 'C', // XMM12i
2488 'C', // XMM12j
2489 'C', // XMM12k
2490 'C', // XMM12l
2491 'C', // XMM12m
2492 'C', // XMM12n
2493 'C', // XMM12o
2494 'C', // XMM12p
2495 'C', // XMM13
2496 'C', // XMM13b
2497 'C', // XMM13c
2498 'C', // XMM13d
2499 'C', // XMM13e
2500 'C', // XMM13f
2501 'C', // XMM13g
2502 'C', // XMM13h
2503 'C', // XMM13i
2504 'C', // XMM13j
2505 'C', // XMM13k
2506 'C', // XMM13l
2507 'C', // XMM13m
2508 'C', // XMM13n
2509 'C', // XMM13o
2510 'C', // XMM13p
2511 'C', // XMM14
2512 'C', // XMM14b
2513 'C', // XMM14c
2514 'C', // XMM14d
2515 'C', // XMM14e
2516 'C', // XMM14f
2517 'C', // XMM14g
2518 'C', // XMM14h
2519 'C', // XMM14i
2520 'C', // XMM14j
2521 'C', // XMM14k
2522 'C', // XMM14l
2523 'C', // XMM14m
2524 'C', // XMM14n
2525 'C', // XMM14o
2526 'C', // XMM14p
2527 'C', // XMM15
2528 'C', // XMM15b
2529 'C', // XMM15c
2530 'C', // XMM15d
2531 'C', // XMM15e
2532 'C', // XMM15f
2533 'C', // XMM15g
2534 'C', // XMM15h
2535 'C', // XMM15i
2536 'C', // XMM15j
2537 'C', // XMM15k
2538 'C', // XMM15l
2539 'C', // XMM15m
2540 'C', // XMM15n
2541 'C', // XMM15o
2542 'C', // XMM15p
2543 'C', // XMM16
2544 'C', // XMM16b
2545 'C', // XMM16c
2546 'C', // XMM16d
2547 'C', // XMM16e
2548 'C', // XMM16f
2549 'C', // XMM16g
2550 'C', // XMM16h
2551 'C', // XMM16i
2552 'C', // XMM16j
2553 'C', // XMM16k
2554 'C', // XMM16l
2555 'C', // XMM16m
2556 'C', // XMM16n
2557 'C', // XMM16o
2558 'C', // XMM16p
2559 'C', // XMM17
2560 'C', // XMM17b
2561 'C', // XMM17c
2562 'C', // XMM17d
2563 'C', // XMM17e
2564 'C', // XMM17f
2565 'C', // XMM17g
2566 'C', // XMM17h
2567 'C', // XMM17i
2568 'C', // XMM17j
2569 'C', // XMM17k
2570 'C', // XMM17l
2571 'C', // XMM17m
2572 'C', // XMM17n
2573 'C', // XMM17o
2574 'C', // XMM17p
2575 'C', // XMM18
2576 'C', // XMM18b
2577 'C', // XMM18c
2578 'C', // XMM18d
2579 'C', // XMM18e
2580 'C', // XMM18f
2581 'C', // XMM18g
2582 'C', // XMM18h
2583 'C', // XMM18i
2584 'C', // XMM18j
2585 'C', // XMM18k
2586 'C', // XMM18l
2587 'C', // XMM18m
2588 'C', // XMM18n
2589 'C', // XMM18o
2590 'C', // XMM18p
2591 'C', // XMM19
2592 'C', // XMM19b
2593 'C', // XMM19c
2594 'C', // XMM19d
2595 'C', // XMM19e
2596 'C', // XMM19f
2597 'C', // XMM19g
2598 'C', // XMM19h
2599 'C', // XMM19i
2600 'C', // XMM19j
2601 'C', // XMM19k
2602 'C', // XMM19l
2603 'C', // XMM19m
2604 'C', // XMM19n
2605 'C', // XMM19o
2606 'C', // XMM19p
2607 'C', // XMM20
2608 'C', // XMM20b
2609 'C', // XMM20c
2610 'C', // XMM20d
2611 'C', // XMM20e
2612 'C', // XMM20f
2613 'C', // XMM20g
2614 'C', // XMM20h
2615 'C', // XMM20i
2616 'C', // XMM20j
2617 'C', // XMM20k
2618 'C', // XMM20l
2619 'C', // XMM20m
2620 'C', // XMM20n
2621 'C', // XMM20o
2622 'C', // XMM20p
2623 'C', // XMM21
2624 'C', // XMM21b
2625 'C', // XMM21c
2626 'C', // XMM21d
2627 'C', // XMM21e
2628 'C', // XMM21f
2629 'C', // XMM21g
2630 'C', // XMM21h
2631 'C', // XMM21i
2632 'C', // XMM21j
2633 'C', // XMM21k
2634 'C', // XMM21l
2635 'C', // XMM21m
2636 'C', // XMM21n
2637 'C', // XMM21o
2638 'C', // XMM21p
2639 'C', // XMM22
2640 'C', // XMM22b
2641 'C', // XMM22c
2642 'C', // XMM22d
2643 'C', // XMM22e
2644 'C', // XMM22f
2645 'C', // XMM22g
2646 'C', // XMM22h
2647 'C', // XMM22i
2648 'C', // XMM22j
2649 'C', // XMM22k
2650 'C', // XMM22l
2651 'C', // XMM22m
2652 'C', // XMM22n
2653 'C', // XMM22o
2654 'C', // XMM22p
2655 'C', // XMM23
2656 'C', // XMM23b
2657 'C', // XMM23c
2658 'C', // XMM23d
2659 'C', // XMM23e
2660 'C', // XMM23f
2661 'C', // XMM23g
2662 'C', // XMM23h
2663 'C', // XMM23i
2664 'C', // XMM23j
2665 'C', // XMM23k
2666 'C', // XMM23l
2667 'C', // XMM23m
2668 'C', // XMM23n
2669 'C', // XMM23o
2670 'C', // XMM23p
2671 'C', // XMM24
2672 'C', // XMM24b
2673 'C', // XMM24c
2674 'C', // XMM24d
2675 'C', // XMM24e
2676 'C', // XMM24f
2677 'C', // XMM24g
2678 'C', // XMM24h
2679 'C', // XMM24i
2680 'C', // XMM24j
2681 'C', // XMM24k
2682 'C', // XMM24l
2683 'C', // XMM24m
2684 'C', // XMM24n
2685 'C', // XMM24o
2686 'C', // XMM24p
2687 'C', // XMM25
2688 'C', // XMM25b
2689 'C', // XMM25c
2690 'C', // XMM25d
2691 'C', // XMM25e
2692 'C', // XMM25f
2693 'C', // XMM25g
2694 'C', // XMM25h
2695 'C', // XMM25i
2696 'C', // XMM25j
2697 'C', // XMM25k
2698 'C', // XMM25l
2699 'C', // XMM25m
2700 'C', // XMM25n
2701 'C', // XMM25o
2702 'C', // XMM25p
2703 'C', // XMM26
2704 'C', // XMM26b
2705 'C', // XMM26c
2706 'C', // XMM26d
2707 'C', // XMM26e
2708 'C', // XMM26f
2709 'C', // XMM26g
2710 'C', // XMM26h
2711 'C', // XMM26i
2712 'C', // XMM26j
2713 'C', // XMM26k
2714 'C', // XMM26l
2715 'C', // XMM26m
2716 'C', // XMM26n
2717 'C', // XMM26o
2718 'C', // XMM26p
2719 'C', // XMM27
2720 'C', // XMM27b
2721 'C', // XMM27c
2722 'C', // XMM27d
2723 'C', // XMM27e
2724 'C', // XMM27f
2725 'C', // XMM27g
2726 'C', // XMM27h
2727 'C', // XMM27i
2728 'C', // XMM27j
2729 'C', // XMM27k
2730 'C', // XMM27l
2731 'C', // XMM27m
2732 'C', // XMM27n
2733 'C', // XMM27o
2734 'C', // XMM27p
2735 'C', // XMM28
2736 'C', // XMM28b
2737 'C', // XMM28c
2738 'C', // XMM28d
2739 'C', // XMM28e
2740 'C', // XMM28f
2741 'C', // XMM28g
2742 'C', // XMM28h
2743 'C', // XMM28i
2744 'C', // XMM28j
2745 'C', // XMM28k
2746 'C', // XMM28l
2747 'C', // XMM28m
2748 'C', // XMM28n
2749 'C', // XMM28o
2750 'C', // XMM28p
2751 'C', // XMM29
2752 'C', // XMM29b
2753 'C', // XMM29c
2754 'C', // XMM29d
2755 'C', // XMM29e
2756 'C', // XMM29f
2757 'C', // XMM29g
2758 'C', // XMM29h
2759 'C', // XMM29i
2760 'C', // XMM29j
2761 'C', // XMM29k
2762 'C', // XMM29l
2763 'C', // XMM29m
2764 'C', // XMM29n
2765 'C', // XMM29o
2766 'C', // XMM29p
2767 'C', // XMM30
2768 'C', // XMM30b
2769 'C', // XMM30c
2770 'C', // XMM30d
2771 'C', // XMM30e
2772 'C', // XMM30f
2773 'C', // XMM30g
2774 'C', // XMM30h
2775 'C', // XMM30i
2776 'C', // XMM30j
2777 'C', // XMM30k
2778 'C', // XMM30l
2779 'C', // XMM30m
2780 'C', // XMM30n
2781 'C', // XMM30o
2782 'C', // XMM30p
2783 'C', // XMM31
2784 'C', // XMM31b
2785 'C', // XMM31c
2786 'C', // XMM31d
2787 'C', // XMM31e
2788 'C', // XMM31f
2789 'C', // XMM31g
2790 'C', // XMM31h
2791 'C', // XMM31i
2792 'C', // XMM31j
2793 'C', // XMM31k
2794 'C', // XMM31l
2795 'C', // XMM31m
2796 'C', // XMM31n
2797 'C', // XMM31o
2798 'C', // XMM31p
2799 'C' // no trailing comma // RFLAGS
2800};
2801
2802// Map from machine-independent register number to c_reg_save_policy
2803const char c_reg_save_policy[] = {
2804 'C', // R10
2805 'C', // R10_H
2806 'C', // R11
2807 'C', // R11_H
2808 'C', // R8
2809 'C', // R8_H
2810 'C', // R9
2811 'C', // R9_H
2812 'E', // R12
2813 'E', // R12_H
2814 'C', // RCX
2815 'C', // RCX_H
2816 'E', // RBX
2817 'E', // RBX_H
2818 'C', // RDI
2819 'C', // RDI_H
2820 'C', // RDX
2821 'C', // RDX_H
2822 'C', // RSI
2823 'C', // RSI_H
2824 'C', // RAX
2825 'C', // RAX_H
2826 'E', // RBP
2827 'E', // RBP_H
2828 'E', // R13
2829 'E', // R13_H
2830 'E', // R14
2831 'E', // R14_H
2832 'E', // R15
2833 'E', // R15_H
2834 'N', // RSP
2835 'N', // RSP_H
2836 'C', // XMM0
2837 'C', // XMM0b
2838 'C', // XMM0c
2839 'C', // XMM0d
2840 'C', // XMM0e
2841 'C', // XMM0f
2842 'C', // XMM0g
2843 'C', // XMM0h
2844 'C', // XMM0i
2845 'C', // XMM0j
2846 'C', // XMM0k
2847 'C', // XMM0l
2848 'C', // XMM0m
2849 'C', // XMM0n
2850 'C', // XMM0o
2851 'C', // XMM0p
2852 'C', // XMM1
2853 'C', // XMM1b
2854 'C', // XMM1c
2855 'C', // XMM1d
2856 'C', // XMM1e
2857 'C', // XMM1f
2858 'C', // XMM1g
2859 'C', // XMM1h
2860 'C', // XMM1i
2861 'C', // XMM1j
2862 'C', // XMM1k
2863 'C', // XMM1l
2864 'C', // XMM1m
2865 'C', // XMM1n
2866 'C', // XMM1o
2867 'C', // XMM1p
2868 'C', // XMM2
2869 'C', // XMM2b
2870 'C', // XMM2c
2871 'C', // XMM2d
2872 'C', // XMM2e
2873 'C', // XMM2f
2874 'C', // XMM2g
2875 'C', // XMM2h
2876 'C', // XMM2i
2877 'C', // XMM2j
2878 'C', // XMM2k
2879 'C', // XMM2l
2880 'C', // XMM2m
2881 'C', // XMM2n
2882 'C', // XMM2o
2883 'C', // XMM2p
2884 'C', // XMM3
2885 'C', // XMM3b
2886 'C', // XMM3c
2887 'C', // XMM3d
2888 'C', // XMM3e
2889 'C', // XMM3f
2890 'C', // XMM3g
2891 'C', // XMM3h
2892 'C', // XMM3i
2893 'C', // XMM3j
2894 'C', // XMM3k
2895 'C', // XMM3l
2896 'C', // XMM3m
2897 'C', // XMM3n
2898 'C', // XMM3o
2899 'C', // XMM3p
2900 'C', // XMM4
2901 'C', // XMM4b
2902 'C', // XMM4c
2903 'C', // XMM4d
2904 'C', // XMM4e
2905 'C', // XMM4f
2906 'C', // XMM4g
2907 'C', // XMM4h
2908 'C', // XMM4i
2909 'C', // XMM4j
2910 'C', // XMM4k
2911 'C', // XMM4l
2912 'C', // XMM4m
2913 'C', // XMM4n
2914 'C', // XMM4o
2915 'C', // XMM4p
2916 'C', // XMM5
2917 'C', // XMM5b
2918 'C', // XMM5c
2919 'C', // XMM5d
2920 'C', // XMM5e
2921 'C', // XMM5f
2922 'C', // XMM5g
2923 'C', // XMM5h
2924 'C', // XMM5i
2925 'C', // XMM5j
2926 'C', // XMM5k
2927 'C', // XMM5l
2928 'C', // XMM5m
2929 'C', // XMM5n
2930 'C', // XMM5o
2931 'C', // XMM5p
2932 'C', // XMM6
2933 'C', // XMM6b
2934 'C', // XMM6c
2935 'C', // XMM6d
2936 'C', // XMM6e
2937 'C', // XMM6f
2938 'C', // XMM6g
2939 'C', // XMM6h
2940 'C', // XMM6i
2941 'C', // XMM6j
2942 'C', // XMM6k
2943 'C', // XMM6l
2944 'C', // XMM6m
2945 'C', // XMM6n
2946 'C', // XMM6o
2947 'C', // XMM6p
2948 'C', // XMM7
2949 'C', // XMM7b
2950 'C', // XMM7c
2951 'C', // XMM7d
2952 'C', // XMM7e
2953 'C', // XMM7f
2954 'C', // XMM7g
2955 'C', // XMM7h
2956 'C', // XMM7i
2957 'C', // XMM7j
2958 'C', // XMM7k
2959 'C', // XMM7l
2960 'C', // XMM7m
2961 'C', // XMM7n
2962 'C', // XMM7o
2963 'C', // XMM7p
2964 'C', // XMM8
2965 'C', // XMM8b
2966 'C', // XMM8c
2967 'C', // XMM8d
2968 'C', // XMM8e
2969 'C', // XMM8f
2970 'C', // XMM8g
2971 'C', // XMM8h
2972 'C', // XMM8i
2973 'C', // XMM8j
2974 'C', // XMM8k
2975 'C', // XMM8l
2976 'C', // XMM8m
2977 'C', // XMM8n
2978 'C', // XMM8o
2979 'C', // XMM8p
2980 'C', // XMM9
2981 'C', // XMM9b
2982 'C', // XMM9c
2983 'C', // XMM9d
2984 'C', // XMM9e
2985 'C', // XMM9f
2986 'C', // XMM9g
2987 'C', // XMM9h
2988 'C', // XMM9i
2989 'C', // XMM9j
2990 'C', // XMM9k
2991 'C', // XMM9l
2992 'C', // XMM9m
2993 'C', // XMM9n
2994 'C', // XMM9o
2995 'C', // XMM9p
2996 'C', // XMM10
2997 'C', // XMM10b
2998 'C', // XMM10c
2999 'C', // XMM10d
3000 'C', // XMM10e
3001 'C', // XMM10f
3002 'C', // XMM10g
3003 'C', // XMM10h
3004 'C', // XMM10i
3005 'C', // XMM10j
3006 'C', // XMM10k
3007 'C', // XMM10l
3008 'C', // XMM10m
3009 'C', // XMM10n
3010 'C', // XMM10o
3011 'C', // XMM10p
3012 'C', // XMM11
3013 'C', // XMM11b
3014 'C', // XMM11c
3015 'C', // XMM11d
3016 'C', // XMM11e
3017 'C', // XMM11f
3018 'C', // XMM11g
3019 'C', // XMM11h
3020 'C', // XMM11i
3021 'C', // XMM11j
3022 'C', // XMM11k
3023 'C', // XMM11l
3024 'C', // XMM11m
3025 'C', // XMM11n
3026 'C', // XMM11o
3027 'C', // XMM11p
3028 'C', // XMM12
3029 'C', // XMM12b
3030 'C', // XMM12c
3031 'C', // XMM12d
3032 'C', // XMM12e
3033 'C', // XMM12f
3034 'C', // XMM12g
3035 'C', // XMM12h
3036 'C', // XMM12i
3037 'C', // XMM12j
3038 'C', // XMM12k
3039 'C', // XMM12l
3040 'C', // XMM12m
3041 'C', // XMM12n
3042 'C', // XMM12o
3043 'C', // XMM12p
3044 'C', // XMM13
3045 'C', // XMM13b
3046 'C', // XMM13c
3047 'C', // XMM13d
3048 'C', // XMM13e
3049 'C', // XMM13f
3050 'C', // XMM13g
3051 'C', // XMM13h
3052 'C', // XMM13i
3053 'C', // XMM13j
3054 'C', // XMM13k
3055 'C', // XMM13l
3056 'C', // XMM13m
3057 'C', // XMM13n
3058 'C', // XMM13o
3059 'C', // XMM13p
3060 'C', // XMM14
3061 'C', // XMM14b
3062 'C', // XMM14c
3063 'C', // XMM14d
3064 'C', // XMM14e
3065 'C', // XMM14f
3066 'C', // XMM14g
3067 'C', // XMM14h
3068 'C', // XMM14i
3069 'C', // XMM14j
3070 'C', // XMM14k
3071 'C', // XMM14l
3072 'C', // XMM14m
3073 'C', // XMM14n
3074 'C', // XMM14o
3075 'C', // XMM14p
3076 'C', // XMM15
3077 'C', // XMM15b
3078 'C', // XMM15c
3079 'C', // XMM15d
3080 'C', // XMM15e
3081 'C', // XMM15f
3082 'C', // XMM15g
3083 'C', // XMM15h
3084 'C', // XMM15i
3085 'C', // XMM15j
3086 'C', // XMM15k
3087 'C', // XMM15l
3088 'C', // XMM15m
3089 'C', // XMM15n
3090 'C', // XMM15o
3091 'C', // XMM15p
3092 'C', // XMM16
3093 'C', // XMM16b
3094 'C', // XMM16c
3095 'C', // XMM16d
3096 'C', // XMM16e
3097 'C', // XMM16f
3098 'C', // XMM16g
3099 'C', // XMM16h
3100 'C', // XMM16i
3101 'C', // XMM16j
3102 'C', // XMM16k
3103 'C', // XMM16l
3104 'C', // XMM16m
3105 'C', // XMM16n
3106 'C', // XMM16o
3107 'C', // XMM16p
3108 'C', // XMM17
3109 'C', // XMM17b
3110 'C', // XMM17c
3111 'C', // XMM17d
3112 'C', // XMM17e
3113 'C', // XMM17f
3114 'C', // XMM17g
3115 'C', // XMM17h
3116 'C', // XMM17i
3117 'C', // XMM17j
3118 'C', // XMM17k
3119 'C', // XMM17l
3120 'C', // XMM17m
3121 'C', // XMM17n
3122 'C', // XMM17o
3123 'C', // XMM17p
3124 'C', // XMM18
3125 'C', // XMM18b
3126 'C', // XMM18c
3127 'C', // XMM18d
3128 'C', // XMM18e
3129 'C', // XMM18f
3130 'C', // XMM18g
3131 'C', // XMM18h
3132 'C', // XMM18i
3133 'C', // XMM18j
3134 'C', // XMM18k
3135 'C', // XMM18l
3136 'C', // XMM18m
3137 'C', // XMM18n
3138 'C', // XMM18o
3139 'C', // XMM18p
3140 'C', // XMM19
3141 'C', // XMM19b
3142 'C', // XMM19c
3143 'C', // XMM19d
3144 'C', // XMM19e
3145 'C', // XMM19f
3146 'C', // XMM19g
3147 'C', // XMM19h
3148 'C', // XMM19i
3149 'C', // XMM19j
3150 'C', // XMM19k
3151 'C', // XMM19l
3152 'C', // XMM19m
3153 'C', // XMM19n
3154 'C', // XMM19o
3155 'C', // XMM19p
3156 'C', // XMM20
3157 'C', // XMM20b
3158 'C', // XMM20c
3159 'C', // XMM20d
3160 'C', // XMM20e
3161 'C', // XMM20f
3162 'C', // XMM20g
3163 'C', // XMM20h
3164 'C', // XMM20i
3165 'C', // XMM20j
3166 'C', // XMM20k
3167 'C', // XMM20l
3168 'C', // XMM20m
3169 'C', // XMM20n
3170 'C', // XMM20o
3171 'C', // XMM20p
3172 'C', // XMM21
3173 'C', // XMM21b
3174 'C', // XMM21c
3175 'C', // XMM21d
3176 'C', // XMM21e
3177 'C', // XMM21f
3178 'C', // XMM21g
3179 'C', // XMM21h
3180 'C', // XMM21i
3181 'C', // XMM21j
3182 'C', // XMM21k
3183 'C', // XMM21l
3184 'C', // XMM21m
3185 'C', // XMM21n
3186 'C', // XMM21o
3187 'C', // XMM21p
3188 'C', // XMM22
3189 'C', // XMM22b
3190 'C', // XMM22c
3191 'C', // XMM22d
3192 'C', // XMM22e
3193 'C', // XMM22f
3194 'C', // XMM22g
3195 'C', // XMM22h
3196 'C', // XMM22i
3197 'C', // XMM22j
3198 'C', // XMM22k
3199 'C', // XMM22l
3200 'C', // XMM22m
3201 'C', // XMM22n
3202 'C', // XMM22o
3203 'C', // XMM22p
3204 'C', // XMM23
3205 'C', // XMM23b
3206 'C', // XMM23c
3207 'C', // XMM23d
3208 'C', // XMM23e
3209 'C', // XMM23f
3210 'C', // XMM23g
3211 'C', // XMM23h
3212 'C', // XMM23i
3213 'C', // XMM23j
3214 'C', // XMM23k
3215 'C', // XMM23l
3216 'C', // XMM23m
3217 'C', // XMM23n
3218 'C', // XMM23o
3219 'C', // XMM23p
3220 'C', // XMM24
3221 'C', // XMM24b
3222 'C', // XMM24c
3223 'C', // XMM24d
3224 'C', // XMM24e
3225 'C', // XMM24f
3226 'C', // XMM24g
3227 'C', // XMM24h
3228 'C', // XMM24i
3229 'C', // XMM24j
3230 'C', // XMM24k
3231 'C', // XMM24l
3232 'C', // XMM24m
3233 'C', // XMM24n
3234 'C', // XMM24o
3235 'C', // XMM24p
3236 'C', // XMM25
3237 'C', // XMM25b
3238 'C', // XMM25c
3239 'C', // XMM25d
3240 'C', // XMM25e
3241 'C', // XMM25f
3242 'C', // XMM25g
3243 'C', // XMM25h
3244 'C', // XMM25i
3245 'C', // XMM25j
3246 'C', // XMM25k
3247 'C', // XMM25l
3248 'C', // XMM25m
3249 'C', // XMM25n
3250 'C', // XMM25o
3251 'C', // XMM25p
3252 'C', // XMM26
3253 'C', // XMM26b
3254 'C', // XMM26c
3255 'C', // XMM26d
3256 'C', // XMM26e
3257 'C', // XMM26f
3258 'C', // XMM26g
3259 'C', // XMM26h
3260 'C', // XMM26i
3261 'C', // XMM26j
3262 'C', // XMM26k
3263 'C', // XMM26l
3264 'C', // XMM26m
3265 'C', // XMM26n
3266 'C', // XMM26o
3267 'C', // XMM26p
3268 'C', // XMM27
3269 'C', // XMM27b
3270 'C', // XMM27c
3271 'C', // XMM27d
3272 'C', // XMM27e
3273 'C', // XMM27f
3274 'C', // XMM27g
3275 'C', // XMM27h
3276 'C', // XMM27i
3277 'C', // XMM27j
3278 'C', // XMM27k
3279 'C', // XMM27l
3280 'C', // XMM27m
3281 'C', // XMM27n
3282 'C', // XMM27o
3283 'C', // XMM27p
3284 'C', // XMM28
3285 'C', // XMM28b
3286 'C', // XMM28c
3287 'C', // XMM28d
3288 'C', // XMM28e
3289 'C', // XMM28f
3290 'C', // XMM28g
3291 'C', // XMM28h
3292 'C', // XMM28i
3293 'C', // XMM28j
3294 'C', // XMM28k
3295 'C', // XMM28l
3296 'C', // XMM28m
3297 'C', // XMM28n
3298 'C', // XMM28o
3299 'C', // XMM28p
3300 'C', // XMM29
3301 'C', // XMM29b
3302 'C', // XMM29c
3303 'C', // XMM29d
3304 'C', // XMM29e
3305 'C', // XMM29f
3306 'C', // XMM29g
3307 'C', // XMM29h
3308 'C', // XMM29i
3309 'C', // XMM29j
3310 'C', // XMM29k
3311 'C', // XMM29l
3312 'C', // XMM29m
3313 'C', // XMM29n
3314 'C', // XMM29o
3315 'C', // XMM29p
3316 'C', // XMM30
3317 'C', // XMM30b
3318 'C', // XMM30c
3319 'C', // XMM30d
3320 'C', // XMM30e
3321 'C', // XMM30f
3322 'C', // XMM30g
3323 'C', // XMM30h
3324 'C', // XMM30i
3325 'C', // XMM30j
3326 'C', // XMM30k
3327 'C', // XMM30l
3328 'C', // XMM30m
3329 'C', // XMM30n
3330 'C', // XMM30o
3331 'C', // XMM30p
3332 'C', // XMM31
3333 'C', // XMM31b
3334 'C', // XMM31c
3335 'C', // XMM31d
3336 'C', // XMM31e
3337 'C', // XMM31f
3338 'C', // XMM31g
3339 'C', // XMM31h
3340 'C', // XMM31i
3341 'C', // XMM31j
3342 'C', // XMM31k
3343 'C', // XMM31l
3344 'C', // XMM31m
3345 'C', // XMM31n
3346 'C', // XMM31o
3347 'C', // XMM31p
3348 'C' // no trailing comma // RFLAGS
3349};
3350
3351// Map from machine-independent register number to register_save_type
3352const int register_save_type[] = {
3353 Op_RegI,
3354 Op_RegI,
3355 Op_RegI,
3356 Op_RegI,
3357 Op_RegI,
3358 Op_RegI,
3359 Op_RegI,
3360 Op_RegI,
3361 Op_RegI,
3362 Op_RegI,
3363 Op_RegI,
3364 Op_RegI,
3365 Op_RegI,
3366 Op_RegI,
3367 Op_RegI,
3368 Op_RegI,
3369 Op_RegI,
3370 Op_RegI,
3371 Op_RegI,
3372 Op_RegI,
3373 Op_RegI,
3374 Op_RegI,
3375 Op_RegI,
3376 Op_RegI,
3377 Op_RegI,
3378 Op_RegI,
3379 Op_RegI,
3380 Op_RegI,
3381 Op_RegI,
3382 Op_RegI,
3383 Op_RegI,
3384 Op_RegI,
3385 Op_RegF,
3386 Op_RegF,
3387 Op_RegF,
3388 Op_RegF,
3389 Op_RegF,
3390 Op_RegF,
3391 Op_RegF,
3392 Op_RegF,
3393 Op_RegF,
3394 Op_RegF,
3395 Op_RegF,
3396 Op_RegF,
3397 Op_RegF,
3398 Op_RegF,
3399 Op_RegF,
3400 Op_RegF,
3401 Op_RegF,
3402 Op_RegF,
3403 Op_RegF,
3404 Op_RegF,
3405 Op_RegF,
3406 Op_RegF,
3407 Op_RegF,
3408 Op_RegF,
3409 Op_RegF,
3410 Op_RegF,
3411 Op_RegF,
3412 Op_RegF,
3413 Op_RegF,
3414 Op_RegF,
3415 Op_RegF,
3416 Op_RegF,
3417 Op_RegF,
3418 Op_RegF,
3419 Op_RegF,
3420 Op_RegF,
3421 Op_RegF,
3422 Op_RegF,
3423 Op_RegF,
3424 Op_RegF,
3425 Op_RegF,
3426 Op_RegF,
3427 Op_RegF,
3428 Op_RegF,
3429 Op_RegF,
3430 Op_RegF,
3431 Op_RegF,
3432 Op_RegF,
3433 Op_RegF,
3434 Op_RegF,
3435 Op_RegF,
3436 Op_RegF,
3437 Op_RegF,
3438 Op_RegF,
3439 Op_RegF,
3440 Op_RegF,
3441 Op_RegF,
3442 Op_RegF,
3443 Op_RegF,
3444 Op_RegF,
3445 Op_RegF,
3446 Op_RegF,
3447 Op_RegF,
3448 Op_RegF,
3449 Op_RegF,
3450 Op_RegF,
3451 Op_RegF,
3452 Op_RegF,
3453 Op_RegF,
3454 Op_RegF,
3455 Op_RegF,
3456 Op_RegF,
3457 Op_RegF,
3458 Op_RegF,
3459 Op_RegF,
3460 Op_RegF,
3461 Op_RegF,
3462 Op_RegF,
3463 Op_RegF,
3464 Op_RegF,
3465 Op_RegF,
3466 Op_RegF,
3467 Op_RegF,
3468 Op_RegF,
3469 Op_RegF,
3470 Op_RegF,
3471 Op_RegF,
3472 Op_RegF,
3473 Op_RegF,
3474 Op_RegF,
3475 Op_RegF,
3476 Op_RegF,
3477 Op_RegF,
3478 Op_RegF,
3479 Op_RegF,
3480 Op_RegF,
3481 Op_RegF,
3482 Op_RegF,
3483 Op_RegF,
3484 Op_RegF,
3485 Op_RegF,
3486 Op_RegF,
3487 Op_RegF,
3488 Op_RegF,
3489 Op_RegF,
3490 Op_RegF,
3491 Op_RegF,
3492 Op_RegF,
3493 Op_RegF,
3494 Op_RegF,
3495 Op_RegF,
3496 Op_RegF,
3497 Op_RegF,
3498 Op_RegF,
3499 Op_RegF,
3500 Op_RegF,
3501 Op_RegF,
3502 Op_RegF,
3503 Op_RegF,
3504 Op_RegF,
3505 Op_RegF,
3506 Op_RegF,
3507 Op_RegF,
3508 Op_RegF,
3509 Op_RegF,
3510 Op_RegF,
3511 Op_RegF,
3512 Op_RegF,
3513 Op_RegF,
3514 Op_RegF,
3515 Op_RegF,
3516 Op_RegF,
3517 Op_RegF,
3518 Op_RegF,
3519 Op_RegF,
3520 Op_RegF,
3521 Op_RegF,
3522 Op_RegF,
3523 Op_RegF,
3524 Op_RegF,
3525 Op_RegF,
3526 Op_RegF,
3527 Op_RegF,
3528 Op_RegF,
3529 Op_RegF,
3530 Op_RegF,
3531 Op_RegF,
3532 Op_RegF,
3533 Op_RegF,
3534 Op_RegF,
3535 Op_RegF,
3536 Op_RegF,
3537 Op_RegF,
3538 Op_RegF,
3539 Op_RegF,
3540 Op_RegF,
3541 Op_RegF,
3542 Op_RegF,
3543 Op_RegF,
3544 Op_RegF,
3545 Op_RegF,
3546 Op_RegF,
3547 Op_RegF,
3548 Op_RegF,
3549 Op_RegF,
3550 Op_RegF,
3551 Op_RegF,
3552 Op_RegF,
3553 Op_RegF,
3554 Op_RegF,
3555 Op_RegF,
3556 Op_RegF,
3557 Op_RegF,
3558 Op_RegF,
3559 Op_RegF,
3560 Op_RegF,
3561 Op_RegF,
3562 Op_RegF,
3563 Op_RegF,
3564 Op_RegF,
3565 Op_RegF,
3566 Op_RegF,
3567 Op_RegF,
3568 Op_RegF,
3569 Op_RegF,
3570 Op_RegF,
3571 Op_RegF,
3572 Op_RegF,
3573 Op_RegF,
3574 Op_RegF,
3575 Op_RegF,
3576 Op_RegF,
3577 Op_RegF,
3578 Op_RegF,
3579 Op_RegF,
3580 Op_RegF,
3581 Op_RegF,
3582 Op_RegF,
3583 Op_RegF,
3584 Op_RegF,
3585 Op_RegF,
3586 Op_RegF,
3587 Op_RegF,
3588 Op_RegF,
3589 Op_RegF,
3590 Op_RegF,
3591 Op_RegF,
3592 Op_RegF,
3593 Op_RegF,
3594 Op_RegF,
3595 Op_RegF,
3596 Op_RegF,
3597 Op_RegF,
3598 Op_RegF,
3599 Op_RegF,
3600 Op_RegF,
3601 Op_RegF,
3602 Op_RegF,
3603 Op_RegF,
3604 Op_RegF,
3605 Op_RegF,
3606 Op_RegF,
3607 Op_RegF,
3608 Op_RegF,
3609 Op_RegF,
3610 Op_RegF,
3611 Op_RegF,
3612 Op_RegF,
3613 Op_RegF,
3614 Op_RegF,
3615 Op_RegF,
3616 Op_RegF,
3617 Op_RegF,
3618 Op_RegF,
3619 Op_RegF,
3620 Op_RegF,
3621 Op_RegF,
3622 Op_RegF,
3623 Op_RegF,
3624 Op_RegF,
3625 Op_RegF,
3626 Op_RegF,
3627 Op_RegF,
3628 Op_RegF,
3629 Op_RegF,
3630 Op_RegF,
3631 Op_RegF,
3632 Op_RegF,
3633 Op_RegF,
3634 Op_RegF,
3635 Op_RegF,
3636 Op_RegF,
3637 Op_RegF,
3638 Op_RegF,
3639 Op_RegF,
3640 Op_RegF,
3641 Op_RegF,
3642 Op_RegF,
3643 Op_RegF,
3644 Op_RegF,
3645 Op_RegF,
3646 Op_RegF,
3647 Op_RegF,
3648 Op_RegF,
3649 Op_RegF,
3650 Op_RegF,
3651 Op_RegF,
3652 Op_RegF,
3653 Op_RegF,
3654 Op_RegF,
3655 Op_RegF,
3656 Op_RegF,
3657 Op_RegF,
3658 Op_RegF,
3659 Op_RegF,
3660 Op_RegF,
3661 Op_RegF,
3662 Op_RegF,
3663 Op_RegF,
3664 Op_RegF,
3665 Op_RegF,
3666 Op_RegF,
3667 Op_RegF,
3668 Op_RegF,
3669 Op_RegF,
3670 Op_RegF,
3671 Op_RegF,
3672 Op_RegF,
3673 Op_RegF,
3674 Op_RegF,
3675 Op_RegF,
3676 Op_RegF,
3677 Op_RegF,
3678 Op_RegF,
3679 Op_RegF,
3680 Op_RegF,
3681 Op_RegF,
3682 Op_RegF,
3683 Op_RegF,
3684 Op_RegF,
3685 Op_RegF,
3686 Op_RegF,
3687 Op_RegF,
3688 Op_RegF,
3689 Op_RegF,
3690 Op_RegF,
3691 Op_RegF,
3692 Op_RegF,
3693 Op_RegF,
3694 Op_RegF,
3695 Op_RegF,
3696 Op_RegF,
3697 Op_RegF,
3698 Op_RegF,
3699 Op_RegF,
3700 Op_RegF,
3701 Op_RegF,
3702 Op_RegF,
3703 Op_RegF,
3704 Op_RegF,
3705 Op_RegF,
3706 Op_RegF,
3707 Op_RegF,
3708 Op_RegF,
3709 Op_RegF,
3710 Op_RegF,
3711 Op_RegF,
3712 Op_RegF,
3713 Op_RegF,
3714 Op_RegF,
3715 Op_RegF,
3716 Op_RegF,
3717 Op_RegF,
3718 Op_RegF,
3719 Op_RegF,
3720 Op_RegF,
3721 Op_RegF,
3722 Op_RegF,
3723 Op_RegF,
3724 Op_RegF,
3725 Op_RegF,
3726 Op_RegF,
3727 Op_RegF,
3728 Op_RegF,
3729 Op_RegF,
3730 Op_RegF,
3731 Op_RegF,
3732 Op_RegF,
3733 Op_RegF,
3734 Op_RegF,
3735 Op_RegF,
3736 Op_RegF,
3737 Op_RegF,
3738 Op_RegF,
3739 Op_RegF,
3740 Op_RegF,
3741 Op_RegF,
3742 Op_RegF,
3743 Op_RegF,
3744 Op_RegF,
3745 Op_RegF,
3746 Op_RegF,
3747 Op_RegF,
3748 Op_RegF,
3749 Op_RegF,
3750 Op_RegF,
3751 Op_RegF,
3752 Op_RegF,
3753 Op_RegF,
3754 Op_RegF,
3755 Op_RegF,
3756 Op_RegF,
3757 Op_RegF,
3758 Op_RegF,
3759 Op_RegF,
3760 Op_RegF,
3761 Op_RegF,
3762 Op_RegF,
3763 Op_RegF,
3764 Op_RegF,
3765 Op_RegF,
3766 Op_RegF,
3767 Op_RegF,
3768 Op_RegF,
3769 Op_RegF,
3770 Op_RegF,
3771 Op_RegF,
3772 Op_RegF,
3773 Op_RegF,
3774 Op_RegF,
3775 Op_RegF,
3776 Op_RegF,
3777 Op_RegF,
3778 Op_RegF,
3779 Op_RegF,
3780 Op_RegF,
3781 Op_RegF,
3782 Op_RegF,
3783 Op_RegF,
3784 Op_RegF,
3785 Op_RegF,
3786 Op_RegF,
3787 Op_RegF,
3788 Op_RegF,
3789 Op_RegF,
3790 Op_RegF,
3791 Op_RegF,
3792 Op_RegF,
3793 Op_RegF,
3794 Op_RegF,
3795 Op_RegF,
3796 Op_RegF,
3797 Op_RegF,
3798 Op_RegF,
3799 Op_RegF,
3800 Op_RegF,
3801 Op_RegF,
3802 Op_RegF,
3803 Op_RegF,
3804 Op_RegF,
3805 Op_RegF,
3806 Op_RegF,
3807 Op_RegF,
3808 Op_RegF,
3809 Op_RegF,
3810 Op_RegF,
3811 Op_RegF,
3812 Op_RegF,
3813 Op_RegF,
3814 Op_RegF,
3815 Op_RegF,
3816 Op_RegF,
3817 Op_RegF,
3818 Op_RegF,
3819 Op_RegF,
3820 Op_RegF,
3821 Op_RegF,
3822 Op_RegF,
3823 Op_RegF,
3824 Op_RegF,
3825 Op_RegF,
3826 Op_RegF,
3827 Op_RegF,
3828 Op_RegF,
3829 Op_RegF,
3830 Op_RegF,
3831 Op_RegF,
3832 Op_RegF,
3833 Op_RegF,
3834 Op_RegF,
3835 Op_RegF,
3836 Op_RegF,
3837 Op_RegF,
3838 Op_RegF,
3839 Op_RegF,
3840 Op_RegF,
3841 Op_RegF,
3842 Op_RegF,
3843 Op_RegF,
3844 Op_RegF,
3845 Op_RegF,
3846 Op_RegF,
3847 Op_RegF,
3848 Op_RegF,
3849 Op_RegF,
3850 Op_RegF,
3851 Op_RegF,
3852 Op_RegF,
3853 Op_RegF,
3854 Op_RegF,
3855 Op_RegF,
3856 Op_RegF,
3857 Op_RegF,
3858 Op_RegF,
3859 Op_RegF,
3860 Op_RegF,
3861 Op_RegF,
3862 Op_RegF,
3863 Op_RegF,
3864 Op_RegF,
3865 Op_RegF,
3866 Op_RegF,
3867 Op_RegF,
3868 Op_RegF,
3869 Op_RegF,
3870 Op_RegF,
3871 Op_RegF,
3872 Op_RegF,
3873 Op_RegF,
3874 Op_RegF,
3875 Op_RegF,
3876 Op_RegF,
3877 Op_RegF,
3878 Op_RegF,
3879 Op_RegF,
3880 Op_RegF,
3881 Op_RegF,
3882 Op_RegF,
3883 Op_RegF,
3884 Op_RegF,
3885 Op_RegF,
3886 Op_RegF,
3887 Op_RegF,
3888 Op_RegF,
3889 Op_RegF,
3890 Op_RegF,
3891 Op_RegF,
3892 Op_RegF,
3893 Op_RegF,
3894 Op_RegF,
3895 Op_RegF,
3896 Op_RegF,
3897 0 // no trailing comma
3898};
3899
3900
3901const int reduceOp[] = {
3902 /* 0 */ 0,
3903 /* 1 */ 0,
3904 /* 2 */ 0,
3905 /* 3 */ 0,
3906 /* 4 */ 0,
3907 /* 5 */ 0,
3908 /* 6 */ 0,
3909 /* 7 */ 0,
3910 /* 8 */ immI_rule,
3911 /* 9 */ immI0_rule,
3912 /* 10 */ immI1_rule,
3913 /* 11 */ immI_M1_rule,
3914 /* 12 */ immI2_rule,
3915 /* 13 */ immI8_rule,
3916 /* 14 */ immU8_rule,
3917 /* 15 */ immI16_rule,
3918 /* 16 */ immU31_rule,
3919 /* 17 */ immI_32_rule,
3920 /* 18 */ immI_64_rule,
3921 /* 19 */ immP_rule,
3922 /* 20 */ immP0_rule,
3923 /* 21 */ immN_rule,
3924 /* 22 */ immNKlass_rule,
3925 /* 23 */ immN0_rule,
3926 /* 24 */ immP31_rule,
3927 /* 25 */ immL_rule,
3928 /* 26 */ immL8_rule,
3929 /* 27 */ immUL32_rule,
3930 /* 28 */ immL32_rule,
3931 /* 29 */ immL0_rule,
3932 /* 30 */ immL1_rule,
3933 /* 31 */ immL_M1_rule,
3934 /* 32 */ immL10_rule,
3935 /* 33 */ immL_127_rule,
3936 /* 34 */ immL_32bits_rule,
3937 /* 35 */ immF0_rule,
3938 /* 36 */ immF_rule,
3939 /* 37 */ immD0_rule,
3940 /* 38 */ immD_rule,
3941 /* 39 */ immI_16_rule,
3942 /* 40 */ immI_24_rule,
3943 /* 41 */ immI_255_rule,
3944 /* 42 */ immI_65535_rule,
3945 /* 43 */ immL_255_rule,
3946 /* 44 */ immL_65535_rule,
3947 /* 45 */ rRegI_rule,
3948 /* 46 */ rax_RegI_rule,
3949 /* 47 */ rbx_RegI_rule,
3950 /* 48 */ rcx_RegI_rule,
3951 /* 49 */ rdx_RegI_rule,
3952 /* 50 */ rdi_RegI_rule,
3953 /* 51 */ no_rcx_RegI_rule,
3954 /* 52 */ no_rax_rdx_RegI_rule,
3955 /* 53 */ any_RegP_rule,
3956 /* 54 */ rRegP_rule,
3957 /* 55 */ rRegN_rule,
3958 /* 56 */ no_rax_RegP_rule,
3959 /* 57 */ no_rbp_RegP_rule,
3960 /* 58 */ no_rax_rbx_RegP_rule,
3961 /* 59 */ rax_RegP_rule,
3962 /* 60 */ rax_RegN_rule,
3963 /* 61 */ rbx_RegP_rule,
3964 /* 62 */ rsi_RegP_rule,
3965 /* 63 */ rdi_RegP_rule,
3966 /* 64 */ r15_RegP_rule,
3967 /* 65 */ rRegL_rule,
3968 /* 66 */ no_rax_rdx_RegL_rule,
3969 /* 67 */ no_rax_RegL_rule,
3970 /* 68 */ no_rcx_RegL_rule,
3971 /* 69 */ rax_RegL_rule,
3972 /* 70 */ rcx_RegL_rule,
3973 /* 71 */ rdx_RegL_rule,
3974 /* 72 */ rFlagsReg_rule,
3975 /* 73 */ rFlagsRegU_rule,
3976 /* 74 */ rFlagsRegUCF_rule,
3977 /* 75 */ regF_rule,
3978 /* 76 */ legRegF_rule,
3979 /* 77 */ vlRegF_rule,
3980 /* 78 */ regD_rule,
3981 /* 79 */ legRegD_rule,
3982 /* 80 */ vlRegD_rule,
3983 /* 81 */ vecS_rule,
3984 /* 82 */ legVecS_rule,
3985 /* 83 */ vecD_rule,
3986 /* 84 */ legVecD_rule,
3987 /* 85 */ vecX_rule,
3988 /* 86 */ legVecX_rule,
3989 /* 87 */ vecY_rule,
3990 /* 88 */ legVecY_rule,
3991 /* 89 */ indirect_rule,
3992 /* 90 */ indOffset8_rule,
3993 /* 91 */ indOffset32_rule,
3994 /* 92 */ indIndexOffset_rule,
3995 /* 93 */ indIndex_rule,
3996 /* 94 */ indIndexScale_rule,
3997 /* 95 */ indPosIndexScale_rule,
3998 /* 96 */ indIndexScaleOffset_rule,
3999 /* 97 */ indPosIndexOffset_rule,
4000 /* 98 */ indPosIndexScaleOffset_rule,
4001 /* 99 */ indCompressedOopOffset_rule,
4002 /* 100 */ indirectNarrow_rule,
4003 /* 101 */ indOffset8Narrow_rule,
4004 /* 102 */ indOffset32Narrow_rule,
4005 /* 103 */ indIndexOffsetNarrow_rule,
4006 /* 104 */ indIndexNarrow_rule,
4007 /* 105 */ indIndexScaleNarrow_rule,
4008 /* 106 */ indIndexScaleOffsetNarrow_rule,
4009 /* 107 */ indPosIndexOffsetNarrow_rule,
4010 /* 108 */ indPosIndexScaleOffsetNarrow_rule,
4011 /* 109 */ stackSlotP_rule,
4012 /* 110 */ stackSlotI_rule,
4013 /* 111 */ stackSlotF_rule,
4014 /* 112 */ stackSlotD_rule,
4015 /* 113 */ stackSlotL_rule,
4016 /* 114 */ cmpOp_rule,
4017 /* 115 */ cmpOpU_rule,
4018 /* 116 */ cmpOpUCF_rule,
4019 /* 117 */ cmpOpUCF2_rule,
4020 /* 118 */ rxmm0_rule,
4021 /* 119 */ rxmm1_rule,
4022 /* 120 */ rxmm2_rule,
4023 /* 121 */ rxmm3_rule,
4024 /* 122 */ rxmm4_rule,
4025 /* 123 */ rxmm5_rule,
4026 /* 124 */ rxmm6_rule,
4027 /* 125 */ rxmm7_rule,
4028 /* 126 */ rxmm8_rule,
4029 /* 127 */ rxmm9_rule,
4030 /* 128 */ rxmm10_rule,
4031 /* 129 */ rxmm11_rule,
4032 /* 130 */ rxmm12_rule,
4033 /* 131 */ rxmm13_rule,
4034 /* 132 */ rxmm14_rule,
4035 /* 133 */ rxmm15_rule,
4036 /* 134 */ rxmm16_rule,
4037 /* 135 */ rxmm17_rule,
4038 /* 136 */ rxmm18_rule,
4039 /* 137 */ rxmm19_rule,
4040 /* 138 */ rxmm20_rule,
4041 /* 139 */ rxmm21_rule,
4042 /* 140 */ rxmm22_rule,
4043 /* 141 */ rxmm23_rule,
4044 /* 142 */ rxmm24_rule,
4045 /* 143 */ rxmm25_rule,
4046 /* 144 */ rxmm26_rule,
4047 /* 145 */ rxmm27_rule,
4048 /* 146 */ rxmm28_rule,
4049 /* 147 */ rxmm29_rule,
4050 /* 148 */ rxmm30_rule,
4051 /* 149 */ rxmm31_rule,
4052 /* 150 */ vecZ_rule,
4053 /* 151 */ legVecZ_rule,
4054 /* 152 */ cmpOp_vcmppd_rule,
4055 // last operand
4056 /* 153 */ memory_rule,
4057 // last operand class
4058 /* 154 */ _AddP_any_RegP_rRegL_rule,
4059 /* 155 */ _LShiftL_rRegL_immI2_rule,
4060 /* 156 */ _ConvI2L_rRegI__rule,
4061 /* 157 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
4062 /* 158 */ _AddP_any_RegP__LShiftL_rRegL_immI2_rule,
4063 /* 159 */ _AddP_any_RegP__ConvI2L_rRegI__rule,
4064 /* 160 */ _AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2_rule,
4065 /* 161 */ _DecodeN_rRegN__rule,
4066 /* 162 */ _AddP__DecodeN_rRegN__rRegL_rule,
4067 /* 163 */ _AddP__DecodeN_rRegN___LShiftL_rRegL_immI2_rule,
4068 /* 164 */ _AddP__DecodeN_rRegN___ConvI2L_rRegI__rule,
4069 /* 165 */ _AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2_rule,
4070 /* 166 */ _LoadB_memory__rule,
4071 /* 167 */ _LoadUB_memory__rule,
4072 /* 168 */ _AndI__LoadUB_memory__immI_rule,
4073 /* 169 */ _LoadS_memory__rule,
4074 /* 170 */ _LShiftI__LoadS_memory__immI_24_rule,
4075 /* 171 */ _LoadUS_memory__rule,
4076 /* 172 */ _LShiftI__LoadUS_memory__immI_24_rule,
4077 /* 173 */ _AndI__LoadUS_memory__immI_255_rule,
4078 /* 174 */ _AndI__LoadUS_memory__immI_rule,
4079 /* 175 */ _LoadI_memory__rule,
4080 /* 176 */ _LShiftI__LoadI_memory__immI_24_rule,
4081 /* 177 */ _LShiftI__LoadI_memory__immI_16_rule,
4082 /* 178 */ _AndI__LoadI_memory__immI_255_rule,
4083 /* 179 */ _AndI__LoadI_memory__immI_65535_rule,
4084 /* 180 */ _AndI__LoadI_memory__immU31_rule,
4085 /* 181 */ _ConvI2L__LoadI_memory___rule,
4086 /* 182 */ _LoadL_memory__rule,
4087 /* 183 */ _CastP2X_rRegP__rule,
4088 /* 184 */ _CastP2X__DecodeN_rRegN___rule,
4089 /* 185 */ _AddL__LShiftL_rRegL_immI2_immL32_rule,
4090 /* 186 */ _Binary_cmpOp_rFlagsReg_rule,
4091 /* 187 */ _Binary_rRegI_rRegI_rule,
4092 /* 188 */ _Binary_cmpOpU_rFlagsRegU_rule,
4093 /* 189 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
4094 /* 190 */ _Binary_rRegI__LoadI_memory__rule,
4095 /* 191 */ _Binary_rRegN_rRegN_rule,
4096 /* 192 */ _Binary_rRegP_rRegP_rule,
4097 /* 193 */ _Binary_rRegL_rRegL_rule,
4098 /* 194 */ _Binary_rRegL__LoadL_memory__rule,
4099 /* 195 */ _Binary_regF_regF_rule,
4100 /* 196 */ _Binary_regD_regD_rule,
4101 /* 197 */ _AddI__LoadI_memory__rRegI_rule,
4102 /* 198 */ _AddI_rRegI__LoadI_memory__rule,
4103 /* 199 */ _AddI__LoadI_memory__immI_rule,
4104 /* 200 */ _AddI__LoadI_memory__immI1_rule,
4105 /* 201 */ _AddI__LoadI_memory__immI_M1_rule,
4106 /* 202 */ _AddL__LoadL_memory__rRegL_rule,
4107 /* 203 */ _AddL_rRegL__LoadL_memory__rule,
4108 /* 204 */ _AddL__LoadL_memory__immL32_rule,
4109 /* 205 */ _AddL__LoadL_memory__immL1_rule,
4110 /* 206 */ _AddL__LoadL_memory__immL_M1_rule,
4111 /* 207 */ _Binary_rax_RegP_rRegP_rule,
4112 /* 208 */ _Binary_rax_RegI_rRegI_rule,
4113 /* 209 */ _Binary_rax_RegL_rRegL_rule,
4114 /* 210 */ _Binary_rax_RegN_rRegN_rule,
4115 /* 211 */ _SubI__LoadI_memory__rRegI_rule,
4116 /* 212 */ _SubI__LoadI_memory__immI_rule,
4117 /* 213 */ _SubL__LoadL_memory__rRegL_rule,
4118 /* 214 */ _SubL__LoadL_memory__immL32_rule,
4119 /* 215 */ _SubI_immI0_rRegI_rule,
4120 /* 216 */ _SubI_immI0__LoadI_memory__rule,
4121 /* 217 */ _SubL_immL0__LoadL_memory__rule,
4122 /* 218 */ _LShiftI__LoadI_memory__immI1_rule,
4123 /* 219 */ _LShiftI__LoadI_memory__immI8_rule,
4124 /* 220 */ _LShiftI__LoadI_memory__rcx_RegI_rule,
4125 /* 221 */ _RShiftI__LoadI_memory__immI1_rule,
4126 /* 222 */ _RShiftI__LoadI_memory__immI8_rule,
4127 /* 223 */ _RShiftI__LoadI_memory__rcx_RegI_rule,
4128 /* 224 */ _URShiftI__LoadI_memory__immI1_rule,
4129 /* 225 */ _URShiftI__LoadI_memory__immI8_rule,
4130 /* 226 */ _URShiftI__LoadI_memory__rcx_RegI_rule,
4131 /* 227 */ _LShiftL__LoadL_memory__immI1_rule,
4132 /* 228 */ _LShiftL__LoadL_memory__immI8_rule,
4133 /* 229 */ _LShiftL__LoadL_memory__rcx_RegI_rule,
4134 /* 230 */ _RShiftL__LoadL_memory__immI1_rule,
4135 /* 231 */ _RShiftL__LoadL_memory__immI8_rule,
4136 /* 232 */ _RShiftL__LoadL_memory__rcx_RegI_rule,
4137 /* 233 */ _URShiftL__LoadL_memory__immI1_rule,
4138 /* 234 */ _URShiftL__LoadL_memory__immI8_rule,
4139 /* 235 */ _URShiftL__LoadL_memory__rcx_RegI_rule,
4140 /* 236 */ _LShiftI_rRegI_immI_24_rule,
4141 /* 237 */ _LShiftI_rRegI_immI_16_rule,
4142 /* 238 */ _LShiftI_rRegI_immI1_rule,
4143 /* 239 */ _URShiftI_rRegI_immI_M1_rule,
4144 /* 240 */ _LShiftI_rRegI_immI8_rule,
4145 /* 241 */ _URShiftI_rRegI_immI8_rule,
4146 /* 242 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule,
4147 /* 243 */ _SubI_immI0_rcx_RegI_rule,
4148 /* 244 */ _URShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
4149 /* 245 */ _SubI_immI_32_rcx_RegI_rule,
4150 /* 246 */ _URShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
4151 /* 247 */ _URShiftI_rRegI_immI1_rule,
4152 /* 248 */ _LShiftI_rRegI_immI_M1_rule,
4153 /* 249 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule,
4154 /* 250 */ _LShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
4155 /* 251 */ _LShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
4156 /* 252 */ _LShiftL_rRegL_immI1_rule,
4157 /* 253 */ _URShiftL_rRegL_immI_M1_rule,
4158 /* 254 */ _LShiftL_rRegL_immI8_rule,
4159 /* 255 */ _URShiftL_rRegL_immI8_rule,
4160 /* 256 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule,
4161 /* 257 */ _URShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
4162 /* 258 */ _SubI_immI_64_rcx_RegI_rule,
4163 /* 259 */ _URShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
4164 /* 260 */ _URShiftL_rRegL_immI1_rule,
4165 /* 261 */ _LShiftL_rRegL_immI_M1_rule,
4166 /* 262 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule,
4167 /* 263 */ _LShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
4168 /* 264 */ _LShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
4169 /* 265 */ _AndI_rRegI_immI_255_rule,
4170 /* 266 */ _AndI_rRegI_immI_65535_rule,
4171 /* 267 */ _AndI__LoadB_memory__rRegI_rule,
4172 /* 268 */ _AndI_rRegI__LoadB_memory__rule,
4173 /* 269 */ _AndI__LoadI_memory__rRegI_rule,
4174 /* 270 */ _AndI_rRegI__LoadI_memory__rule,
4175 /* 271 */ _AndI__LoadI_memory__immI_rule,
4176 /* 272 */ _XorI_rRegI_immI_M1_rule,
4177 /* 273 */ _AddI_rRegI_immI_M1_rule,
4178 /* 274 */ _OrI__LoadB_memory__rRegI_rule,
4179 /* 275 */ _OrI_rRegI__LoadB_memory__rule,
4180 /* 276 */ _OrI__LoadI_memory__rRegI_rule,
4181 /* 277 */ _OrI_rRegI__LoadI_memory__rule,
4182 /* 278 */ _OrI__LoadI_memory__immI_rule,
4183 /* 279 */ _XorI__LoadB_memory__rRegI_rule,
4184 /* 280 */ _XorI_rRegI__LoadB_memory__rule,
4185 /* 281 */ _XorI__LoadI_memory__rRegI_rule,
4186 /* 282 */ _XorI_rRegI__LoadI_memory__rule,
4187 /* 283 */ _XorI__LoadI_memory__immI_rule,
4188 /* 284 */ _AndL__LoadL_memory__rRegL_rule,
4189 /* 285 */ _AndL_rRegL__LoadL_memory__rule,
4190 /* 286 */ _AndL__LoadL_memory__immL32_rule,
4191 /* 287 */ _XorL_rRegL_immL_M1_rule,
4192 /* 288 */ _SubL_immL0_rRegL_rule,
4193 /* 289 */ _AddL_rRegL_immL_M1_rule,
4194 /* 290 */ _CastP2X_any_RegP__rule,
4195 /* 291 */ _OrL__LoadL_memory__rRegL_rule,
4196 /* 292 */ _OrL_rRegL__LoadL_memory__rule,
4197 /* 293 */ _OrL__LoadL_memory__immL32_rule,
4198 /* 294 */ _XorL__LoadL_memory__rRegL_rule,
4199 /* 295 */ _XorL_rRegL__LoadL_memory__rule,
4200 /* 296 */ _XorL__LoadL_memory__immL32_rule,
4201 /* 297 */ _CmpLTMask_rRegI_rRegI_rule,
4202 /* 298 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
4203 /* 299 */ _SubI_rRegI_rRegI_rule,
4204 /* 300 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
4205 /* 301 */ _LoadF_memory__rule,
4206 /* 302 */ _LoadD_memory__rule,
4207 /* 303 */ _Binary_rdi_RegP_rcx_RegI_rule,
4208 /* 304 */ _Binary_rsi_RegP_rdx_RegI_rule,
4209 /* 305 */ _Binary_rdi_RegP_rdx_RegI_rule,
4210 /* 306 */ _Binary_rsi_RegP_immI_rule,
4211 /* 307 */ _Binary_rsi_RegP_rax_RegI_rule,
4212 /* 308 */ _Binary_rdi_RegP_rsi_RegP_rule,
4213 /* 309 */ _AndI_rRegI_immI_rule,
4214 /* 310 */ _LoadP_memory__rule,
4215 /* 311 */ _LoadN_memory__rule,
4216 /* 312 */ _LoadNKlass_memory__rule,
4217 /* 313 */ _AndL_rRegL_immL32_rule,
4218 /* 314 */ _AndL__CastP2X_rRegP___LoadL_memory__rule,
4219 /* 315 */ _AndL__LoadL_memory___CastP2X_rRegP__rule,
4220 /* 316 */ _AndI__LoadUB_memory__immU8_rule,
4221 /* 317 */ _AndI__LoadB_memory__immI8_rule,
4222 /* 318 */ _PartialSubtypeCheck_rsi_RegP_rax_RegP_rule,
4223 /* 319 */ _LoadVector_memory__rule,
4224 /* 320 */ _Binary_cmpOp_vcmppd_immI8_rule,
4225 /* 321 */ _Binary_legVecY_legVecY_rule,
4226 /* 322 */ _Binary_vecX_vecX_rule,
4227 /* 323 */ _Binary_vecX__LoadVector_memory__rule,
4228 /* 324 */ _Binary_vecY_vecY_rule,
4229 /* 325 */ _Binary_vecY__LoadVector_memory__rule,
4230 /* 326 */ _Binary_vecZ_vecZ_rule,
4231 /* 327 */ _Binary_vecZ__LoadVector_memory__rule,
4232 /* 328 */ _MulAddVS2VI_vecD_vecD_rule,
4233 /* 329 */ _MulAddVS2VI_vecX_vecX_rule,
4234 /* 330 */ _MulAddVS2VI_vecY_vecY_rule,
4235 /* 331 */ _MulAddVS2VI_vecZ_vecZ_rule,
4236 /* 332 */ _Binary_memory_rRegP_rule,
4237 // last internally defined operand
4238 /* 333 */ stackSlotI_rule,
4239 /* 334 */ stackSlotL_rule,
4240 /* 335 */ stackSlotP_rule,
4241 /* 336 */ stackSlotF_rule,
4242 /* 337 */ stackSlotD_rule,
4243 /* 338 */ vlRegF_rule,
4244 /* 339 */ legRegF_rule,
4245 /* 340 */ regF_rule,
4246 /* 341 */ regF_rule,
4247 /* 342 */ vlRegD_rule,
4248 /* 343 */ legRegD_rule,
4249 /* 344 */ regD_rule,
4250 /* 345 */ regD_rule,
4251 /* 346 */ rRegP_rule,
4252 /* 347 */ rRegP_rule,
4253 /* 348 */ rRegP_rule,
4254 /* 349 */ rRegP_rule,
4255 /* 350 */ rRegP_rule,
4256 /* 351 */ rRegP_rule,
4257 /* 352 */ rRegP_rule,
4258 /* 353 */ rRegP_rule,
4259 /* 354 */ rRegP_rule,
4260 /* 355 */ rRegP_rule,
4261 /* 356 */ rRegP_rule,
4262 /* 357 */ rRegP_rule,
4263 /* 358 */ rRegP_rule,
4264 /* 359 */ rRegP_rule,
4265 /* 360 */ rRegP_rule,
4266 /* 361 */ rRegP_rule,
4267 /* 362 */ rRegI_rule,
4268 /* 363 */ rRegI_rule,
4269 /* 364 */ rRegL_rule,
4270 /* 365 */ rRegL_rule,
4271 /* 366 */ rRegL_rule,
4272 /* 367 */ rRegL_rule,
4273 /* 368 */ rRegP_rule,
4274 /* 369 */ rRegP_rule,
4275 /* 370 */ rRegP_rule,
4276 /* 371 */ regF_rule,
4277 /* 372 */ rRegN_rule,
4278 /* 373 */ rRegN_rule,
4279 /* 374 */ rRegN_rule,
4280 /* 375 */ regF_rule,
4281 /* 376 */ regD_rule,
4282 /* 377 */ regD_rule,
4283 /* 378 */ rRegI_rule,
4284 /* 379 */ rRegL_rule,
4285 /* 380 */ rRegP_rule,
4286 /* 381 */ regF_rule,
4287 /* 382 */ regD_rule,
4288 /* 383 */ legVecS_rule,
4289 /* 384 */ vecS_rule,
4290 /* 385 */ legVecD_rule,
4291 /* 386 */ vecD_rule,
4292 /* 387 */ legVecX_rule,
4293 /* 388 */ vecX_rule,
4294 /* 389 */ legVecY_rule,
4295 /* 390 */ vecY_rule,
4296 /* 391 */ legVecZ_rule,
4297 /* 392 */ vecZ_rule,
4298 /* 393 */ vecS_rule,
4299 /* 394 */ Universe_rule,
4300 /* 395 */ rRegP_rule,
4301 /* 396 */ rRegL_rule,
4302 /* 397 */ rRegP_rule,
4303 /* 398 */ rRegP_rule,
4304 /* 399 */ rRegI_rule,
4305 /* 400 */ rFlagsReg_rule,
4306 /* 401 */ rFlagsReg_rule,
4307 /* 402 */ rFlagsReg_rule,
4308 /* 403 */ rFlagsRegU_rule,
4309 /* 404 */ rFlagsRegUCF_rule,
4310 /* 405 */ rFlagsRegU_rule,
4311 /* 406 */ rFlagsRegUCF_rule,
4312 /* 407 */ rFlagsRegU_rule,
4313 /* 408 */ rFlagsRegUCF_rule,
4314 /* 409 */ rFlagsRegU_rule,
4315 /* 410 */ rFlagsRegUCF_rule,
4316 /* 411 */ rFlagsRegU_rule,
4317 /* 412 */ rFlagsRegUCF_rule,
4318 /* 413 */ rFlagsRegU_rule,
4319 /* 414 */ rFlagsRegUCF_rule,
4320 /* 415 */ regF_rule,
4321 /* 416 */ regD_rule,
4322 /* 417 */ rRegI_rule,
4323 /* 418 */ regF_rule,
4324 /* 419 */ rRegL_rule,
4325 /* 420 */ regD_rule,
4326 /* 421 */ regD_rule,
4327 /* 422 */ rRegI_rule,
4328 /* 423 */ rRegL_rule,
4329 /* 424 */ regF_rule,
4330 /* 425 */ regD_rule,
4331 /* 426 */ rFlagsReg_rule,
4332 /* 427 */ rFlagsReg_rule,
4333 /* 428 */ rFlagsReg_rule,
4334 /* 429 */ rFlagsReg_rule,
4335 /* 430 */ rFlagsReg_rule,
4336 /* 431 */ rFlagsReg_rule,
4337 /* 432 */ rFlagsReg_rule,
4338 /* 433 */ rFlagsReg_rule,
4339 /* 434 */ rFlagsReg_rule,
4340 /* 435 */ rFlagsReg_rule,
4341 /* 436 */ rFlagsReg_rule,
4342 /* 437 */ rFlagsReg_rule,
4343 /* 438 */ rFlagsReg_rule,
4344 /* 439 */ rFlagsReg_rule,
4345 /* 440 */ rFlagsReg_rule,
4346 /* 441 */ rFlagsReg_rule,
4347 /* 442 */ rFlagsReg_rule,
4348 /* 443 */ rFlagsReg_rule,
4349 /* 444 */ rFlagsReg_rule,
4350 /* 445 */ rFlagsReg_rule,
4351 /* 446 */ rFlagsReg_rule,
4352 /* 447 */ rFlagsRegU_rule,
4353 /* 448 */ rFlagsRegU_rule,
4354 /* 449 */ rFlagsRegU_rule,
4355 /* 450 */ rFlagsRegU_rule,
4356 /* 451 */ rFlagsRegU_rule,
4357 /* 452 */ rFlagsRegU_rule,
4358 /* 453 */ rFlagsRegU_rule,
4359 /* 454 */ rFlagsReg_rule,
4360 /* 455 */ rFlagsReg_rule,
4361 /* 456 */ rFlagsReg_rule,
4362 /* 457 */ rFlagsRegU_rule,
4363 /* 458 */ rFlagsRegU_rule,
4364 /* 459 */ rFlagsRegU_rule,
4365 /* 460 */ rFlagsRegU_rule,
4366 /* 461 */ rFlagsRegU_rule,
4367 /* 462 */ rFlagsRegU_rule,
4368 /* 463 */ rFlagsReg_rule,
4369 /* 464 */ rFlagsReg_rule,
4370 /* 465 */ rFlagsReg_rule,
4371 /* 466 */ rFlagsReg_rule,
4372 /* 467 */ rFlagsReg_rule,
4373 /* 468 */ rFlagsReg_rule,
4374 /* 469 */ rFlagsReg_rule,
4375 /* 470 */ rFlagsReg_rule,
4376 /* 471 */ rFlagsReg_rule,
4377 /* 472 */ rFlagsReg_rule,
4378 /* 473 */ rFlagsReg_rule,
4379 /* 474 */ rFlagsReg_rule,
4380 /* 475 */ rFlagsRegU_rule,
4381 /* 476 */ rFlagsRegU_rule,
4382 /* 477 */ rFlagsRegU_rule,
4383 /* 478 */ rFlagsRegU_rule,
4384 /* 479 */ rFlagsReg_rule,
4385 /* 480 */ rFlagsReg_rule,
4386 /* 481 */ rFlagsReg_rule,
4387 /* 482 */ rFlagsReg_rule,
4388 /* 483 */ rFlagsReg_rule,
4389 /* 484 */ rFlagsReg_rule,
4390 /* 485 */ rFlagsReg_rule,
4391 /* 486 */ Universe_rule,
4392 /* 487 */ r15_RegP_rule,
4393 /* 488 */ regF_rule,
4394 /* 489 */ vlRegF_rule,
4395 /* 490 */ regD_rule,
4396 /* 491 */ vlRegD_rule,
4397 /* 492 */ regF_rule,
4398 /* 493 */ vlRegF_rule,
4399 /* 494 */ regD_rule,
4400 /* 495 */ vlRegD_rule,
4401 /* 496 */ vecX_rule,
4402 /* 497 */ vecX_rule,
4403 /* 498 */ vecY_rule,
4404 /* 499 */ vecY_rule,
4405 /* 500 */ vecZ_rule,
4406 /* 501 */ vecZ_rule,
4407 /* 502 */ vecD_rule,
4408 /* 503 */ vecD_rule,
4409 /* 504 */ vecX_rule,
4410 /* 505 */ vecX_rule,
4411 /* 506 */ vecY_rule,
4412 /* 507 */ vecY_rule,
4413 /* 508 */ vecZ_rule,
4414 /* 509 */ vecZ_rule,
4415 /* 510 */ vecS_rule,
4416 /* 511 */ vecS_rule,
4417 /* 512 */ vecS_rule,
4418 /* 513 */ vecD_rule,
4419 /* 514 */ vecX_rule,
4420 /* 515 */ vecY_rule,
4421 /* 516 */ vecZ_rule,
4422 /* 517 */ vecD_rule,
4423 /* 518 */ vecD_rule,
4424 /* 519 */ vecX_rule,
4425 /* 520 */ vecY_rule,
4426 /* 521 */ vecZ_rule,
4427 /* 522 */ vecD_rule,
4428 /* 523 */ vecX_rule,
4429 /* 524 */ vecY_rule,
4430 /* 525 */ vecZ_rule,
4431 /* 526 */ vecX_rule,
4432 /* 527 */ vecY_rule,
4433 /* 528 */ vecZ_rule,
4434 /* 529 */ vecD_rule,
4435 /* 530 */ vecX_rule,
4436 /* 531 */ vecY_rule,
4437 /* 532 */ vecZ_rule,
4438 /* 533 */ rRegI_rule,
4439 /* 534 */ rRegL_rule,
4440 /* 535 */ rRegI_rule,
4441 /* 536 */ rRegL_rule,
4442 /* 537 */ rRegL_rule,
4443 /* 538 */ rRegI_rule,
4444 /* 539 */ rRegI_rule,
4445 /* 540 */ rRegL_rule,
4446 /* 541 */ rRegI_rule,
4447 /* 542 */ rRegI_rule,
4448 /* 543 */ rRegL_rule,
4449 /* 544 */ rRegL_rule,
4450 /* 545 */ rRegL_rule,
4451 /* 546 */ rRegI_rule,
4452 /* 547 */ rRegI_rule,
4453 /* 548 */ rRegI_rule,
4454 /* 549 */ rRegI_rule,
4455 /* 550 */ rRegI_rule,
4456 /* 551 */ rRegL_rule,
4457 /* 552 */ rRegL_rule,
4458 /* 553 */ rRegL_rule,
4459 /* 554 */ rRegL_rule,
4460 /* 555 */ rRegL_rule,
4461 /* 556 */ rRegL_rule,
4462 /* 557 */ rRegI_rule,
4463 /* 558 */ rRegP_rule,
4464 /* 559 */ rRegN_rule,
4465 /* 560 */ rRegP_rule,
4466 /* 561 */ rRegN_rule,
4467 /* 562 */ regF_rule,
4468 /* 563 */ regD_rule,
4469 /* 564 */ regD_rule,
4470 /* 565 */ legRegF_rule,
4471 /* 566 */ legRegF_rule,
4472 /* 567 */ legRegD_rule,
4473 /* 568 */ legRegD_rule,
4474 /* 569 */ legRegF_rule,
4475 /* 570 */ legRegF_rule,
4476 /* 571 */ legRegD_rule,
4477 /* 572 */ legRegD_rule,
4478 /* 573 */ Universe_rule,
4479 /* 574 */ Universe_rule,
4480 /* 575 */ Universe_rule,
4481 /* 576 */ Universe_rule,
4482 /* 577 */ Universe_rule,
4483 /* 578 */ Universe_rule,
4484 /* 579 */ Universe_rule,
4485 /* 580 */ Universe_rule,
4486 /* 581 */ Universe_rule,
4487 /* 582 */ Universe_rule,
4488 /* 583 */ Universe_rule,
4489 /* 584 */ Universe_rule,
4490 /* 585 */ Universe_rule,
4491 /* 586 */ Universe_rule,
4492 /* 587 */ Universe_rule,
4493 /* 588 */ Universe_rule,
4494 /* 589 */ Universe_rule,
4495 /* 590 */ Universe_rule,
4496 /* 591 */ Universe_rule,
4497 /* 592 */ Universe_rule,
4498 /* 593 */ Universe_rule,
4499 /* 594 */ Universe_rule,
4500 /* 595 */ Universe_rule,
4501 /* 596 */ Universe_rule,
4502 /* 597 */ Universe_rule,
4503 /* 598 */ Universe_rule,
4504 /* 599 */ Universe_rule,
4505 /* 600 */ Universe_rule,
4506 /* 601 */ Universe_rule,
4507 /* 602 */ Universe_rule,
4508 /* 603 */ Universe_rule,
4509 /* 604 */ Universe_rule,
4510 /* 605 */ rRegI_rule,
4511 /* 606 */ rRegL_rule,
4512 /* 607 */ rRegI_rule,
4513 /* 608 */ rRegI_rule,
4514 /* 609 */ rRegI_rule,
4515 /* 610 */ rRegI_rule,
4516 /* 611 */ rRegI_rule,
4517 /* 612 */ rRegI_rule,
4518 /* 613 */ rRegI_rule,
4519 /* 614 */ rRegI_rule,
4520 /* 615 */ rRegI_rule,
4521 /* 616 */ rRegI_rule,
4522 /* 617 */ rRegI_rule,
4523 /* 618 */ rRegI_rule,
4524 /* 619 */ rRegI_rule,
4525 /* 620 */ rRegI_rule,
4526 /* 621 */ Universe_rule,
4527 /* 622 */ Universe_rule,
4528 /* 623 */ Universe_rule,
4529 /* 624 */ Universe_rule,
4530 /* 625 */ Universe_rule,
4531 /* 626 */ Universe_rule,
4532 /* 627 */ Universe_rule,
4533 /* 628 */ Universe_rule,
4534 /* 629 */ rRegI_rule,
4535 /* 630 */ rRegI_rule,
4536 /* 631 */ rRegN_rule,
4537 /* 632 */ rRegN_rule,
4538 /* 633 */ rRegP_rule,
4539 /* 634 */ rRegP_rule,
4540 /* 635 */ rRegN_rule,
4541 /* 636 */ rRegP_rule,
4542 /* 637 */ Universe_rule,
4543 /* 638 */ Universe_rule,
4544 /* 639 */ Universe_rule,
4545 /* 640 */ rRegI_rule,
4546 /* 641 */ rRegI_rule,
4547 /* 642 */ rRegI_rule,
4548 /* 643 */ rRegI_rule,
4549 /* 644 */ rRegI_rule,
4550 /* 645 */ rRegI_rule,
4551 /* 646 */ rRegN_rule,
4552 /* 647 */ rRegN_rule,
4553 /* 648 */ rRegN_rule,
4554 /* 649 */ rRegP_rule,
4555 /* 650 */ rRegP_rule,
4556 /* 651 */ rRegP_rule,
4557 /* 652 */ rRegL_rule,
4558 /* 653 */ rRegL_rule,
4559 /* 654 */ rRegL_rule,
4560 /* 655 */ rRegL_rule,
4561 /* 656 */ rRegL_rule,
4562 /* 657 */ rRegL_rule,
4563 /* 658 */ regF_rule,
4564 /* 659 */ regF_rule,
4565 /* 660 */ regF_rule,
4566 /* 661 */ regD_rule,
4567 /* 662 */ regD_rule,
4568 /* 663 */ regD_rule,
4569 /* 664 */ rRegI_rule,
4570 /* 665 */ rRegI_rule,
4571 /* 666 */ rRegI_rule,
4572 /* 667 */ rRegI_rule,
4573 /* 668 */ Universe_rule,
4574 /* 669 */ Universe_rule,
4575 /* 670 */ Universe_rule,
4576 /* 671 */ rRegI_rule,
4577 /* 672 */ Universe_rule,
4578 /* 673 */ rRegI_rule,
4579 /* 674 */ Universe_rule,
4580 /* 675 */ rRegI_rule,
4581 /* 676 */ rRegL_rule,
4582 /* 677 */ rRegL_rule,
4583 /* 678 */ rRegL_rule,
4584 /* 679 */ rRegL_rule,
4585 /* 680 */ Universe_rule,
4586 /* 681 */ Universe_rule,
4587 /* 682 */ Universe_rule,
4588 /* 683 */ rRegI_rule,
4589 /* 684 */ Universe_rule,
4590 /* 685 */ rRegL_rule,
4591 /* 686 */ Universe_rule,
4592 /* 687 */ rRegL_rule,
4593 /* 688 */ rRegP_rule,
4594 /* 689 */ rRegP_rule,
4595 /* 690 */ rRegP_rule,
4596 /* 691 */ rRegP_rule,
4597 /* 692 */ rRegI_rule,
4598 /* 693 */ rRegI_rule,
4599 /* 694 */ rRegI_rule,
4600 /* 695 */ rRegI_rule,
4601 /* 696 */ rRegI_rule,
4602 /* 697 */ rRegI_rule,
4603 /* 698 */ rRegI_rule,
4604 /* 699 */ rRegI_rule,
4605 /* 700 */ rRegI_rule,
4606 /* 701 */ rRegI_rule,
4607 /* 702 */ rRegI_rule,
4608 /* 703 */ rRegI_rule,
4609 /* 704 */ rax_RegI_rule,
4610 /* 705 */ rax_RegI_rule,
4611 /* 706 */ rax_RegI_rule,
4612 /* 707 */ rax_RegL_rule,
4613 /* 708 */ rax_RegN_rule,
4614 /* 709 */ rax_RegP_rule,
4615 /* 710 */ Universe_rule,
4616 /* 711 */ rRegI_rule,
4617 /* 712 */ Universe_rule,
4618 /* 713 */ rRegI_rule,
4619 /* 714 */ Universe_rule,
4620 /* 715 */ rRegI_rule,
4621 /* 716 */ Universe_rule,
4622 /* 717 */ rRegL_rule,
4623 /* 718 */ rRegI_rule,
4624 /* 719 */ rRegI_rule,
4625 /* 720 */ rRegI_rule,
4626 /* 721 */ rRegL_rule,
4627 /* 722 */ rRegP_rule,
4628 /* 723 */ rRegN_rule,
4629 /* 724 */ rRegI_rule,
4630 /* 725 */ rRegL_rule,
4631 /* 726 */ rRegI_rule,
4632 /* 727 */ rRegI_rule,
4633 /* 728 */ rRegI_rule,
4634 /* 729 */ Universe_rule,
4635 /* 730 */ Universe_rule,
4636 /* 731 */ rRegL_rule,
4637 /* 732 */ rRegI_rule,
4638 /* 733 */ rRegL_rule,
4639 /* 734 */ Universe_rule,
4640 /* 735 */ Universe_rule,
4641 /* 736 */ rRegP_rule,
4642 /* 737 */ rRegI_rule,
4643 /* 738 */ Universe_rule,
4644 /* 739 */ rRegL_rule,
4645 /* 740 */ Universe_rule,
4646 /* 741 */ rRegI_rule,
4647 /* 742 */ rRegI_rule,
4648 /* 743 */ rRegI_rule,
4649 /* 744 */ rRegI_rule,
4650 /* 745 */ rRegI_rule,
4651 /* 746 */ rRegI_rule,
4652 /* 747 */ rRegL_rule,
4653 /* 748 */ rRegL_rule,
4654 /* 749 */ rRegL_rule,
4655 /* 750 */ rRegL_rule,
4656 /* 751 */ rRegL_rule,
4657 /* 752 */ rdx_RegL_rule,
4658 /* 753 */ rax_RegI_rule,
4659 /* 754 */ rax_RegL_rule,
4660 /* 755 */ Universe_rule,
4661 /* 756 */ Universe_rule,
4662 /* 757 */ 0,
4663 /* 758 */ 0,
4664 /* 759 */ 0,
4665 /* 760 */ 0,
4666 /* 761 */ rdx_RegL_rule,
4667 /* 762 */ rdx_RegI_rule,
4668 /* 763 */ rdx_RegL_rule,
4669 /* 764 */ rRegI_rule,
4670 /* 765 */ Universe_rule,
4671 /* 766 */ rRegI_rule,
4672 /* 767 */ Universe_rule,
4673 /* 768 */ rRegI_rule,
4674 /* 769 */ Universe_rule,
4675 /* 770 */ rRegI_rule,
4676 /* 771 */ Universe_rule,
4677 /* 772 */ rRegI_rule,
4678 /* 773 */ Universe_rule,
4679 /* 774 */ rRegI_rule,
4680 /* 775 */ Universe_rule,
4681 /* 776 */ rRegI_rule,
4682 /* 777 */ Universe_rule,
4683 /* 778 */ rRegI_rule,
4684 /* 779 */ Universe_rule,
4685 /* 780 */ rRegI_rule,
4686 /* 781 */ Universe_rule,
4687 /* 782 */ rRegL_rule,
4688 /* 783 */ Universe_rule,
4689 /* 784 */ rRegL_rule,
4690 /* 785 */ Universe_rule,
4691 /* 786 */ rRegL_rule,
4692 /* 787 */ Universe_rule,
4693 /* 788 */ rRegL_rule,
4694 /* 789 */ Universe_rule,
4695 /* 790 */ rRegL_rule,
4696 /* 791 */ Universe_rule,
4697 /* 792 */ rRegL_rule,
4698 /* 793 */ Universe_rule,
4699 /* 794 */ rRegL_rule,
4700 /* 795 */ Universe_rule,
4701 /* 796 */ rRegL_rule,
4702 /* 797 */ Universe_rule,
4703 /* 798 */ rRegL_rule,
4704 /* 799 */ Universe_rule,
4705 /* 800 */ rRegI_rule,
4706 /* 801 */ rRegI_rule,
4707 /* 802 */ 0,
4708 /* 803 */ 0,
4709 /* 804 */ 0,
4710 /* 805 */ rRegI_rule,
4711 /* 806 */ rRegI_rule,
4712 /* 807 */ rRegI_rule,
4713 /* 808 */ rRegI_rule,
4714 /* 809 */ no_rcx_RegI_rule,
4715 /* 810 */ no_rcx_RegI_rule,
4716 /* 811 */ no_rcx_RegI_rule,
4717 /* 812 */ no_rcx_RegI_rule,
4718 /* 813 */ 0,
4719 /* 814 */ 0,
4720 /* 815 */ 0,
4721 /* 816 */ rRegI_rule,
4722 /* 817 */ rRegI_rule,
4723 /* 818 */ rRegI_rule,
4724 /* 819 */ rRegI_rule,
4725 /* 820 */ no_rcx_RegI_rule,
4726 /* 821 */ no_rcx_RegI_rule,
4727 /* 822 */ no_rcx_RegI_rule,
4728 /* 823 */ no_rcx_RegI_rule,
4729 /* 824 */ 0,
4730 /* 825 */ 0,
4731 /* 826 */ 0,
4732 /* 827 */ rRegL_rule,
4733 /* 828 */ rRegL_rule,
4734 /* 829 */ rRegL_rule,
4735 /* 830 */ rRegL_rule,
4736 /* 831 */ no_rcx_RegL_rule,
4737 /* 832 */ no_rcx_RegL_rule,
4738 /* 833 */ no_rcx_RegL_rule,
4739 /* 834 */ no_rcx_RegL_rule,
4740 /* 835 */ 0,
4741 /* 836 */ 0,
4742 /* 837 */ 0,
4743 /* 838 */ rRegL_rule,
4744 /* 839 */ rRegL_rule,
4745 /* 840 */ rRegL_rule,
4746 /* 841 */ rRegL_rule,
4747 /* 842 */ no_rcx_RegL_rule,
4748 /* 843 */ no_rcx_RegL_rule,
4749 /* 844 */ no_rcx_RegL_rule,
4750 /* 845 */ no_rcx_RegL_rule,
4751 /* 846 */ rRegI_rule,
4752 /* 847 */ rRegI_rule,
4753 /* 848 */ rRegL_rule,
4754 /* 849 */ rRegI_rule,
4755 /* 850 */ rRegL_rule,
4756 /* 851 */ rRegI_rule,
4757 /* 852 */ rRegI_rule,
4758 /* 853 */ rRegI_rule,
4759 /* 854 */ Universe_rule,
4760 /* 855 */ Universe_rule,
4761 /* 856 */ Universe_rule,
4762 /* 857 */ Universe_rule,
4763 /* 858 */ Universe_rule,
4764 /* 859 */ rRegI_rule,
4765 /* 860 */ rRegI_rule,
4766 /* 861 */ rRegI_rule,
4767 /* 862 */ rRegI_rule,
4768 /* 863 */ rRegI_rule,
4769 /* 864 */ rRegI_rule,
4770 /* 865 */ rRegI_rule,
4771 /* 866 */ rRegI_rule,
4772 /* 867 */ rRegI_rule,
4773 /* 868 */ rRegI_rule,
4774 /* 869 */ rRegI_rule,
4775 /* 870 */ rRegI_rule,
4776 /* 871 */ rRegI_rule,
4777 /* 872 */ rRegI_rule,
4778 /* 873 */ rRegI_rule,
4779 /* 874 */ rRegI_rule,
4780 /* 875 */ rRegI_rule,
4781 /* 876 */ rRegI_rule,
4782 /* 877 */ rRegI_rule,
4783 /* 878 */ rRegI_rule,
4784 /* 879 */ Universe_rule,
4785 /* 880 */ Universe_rule,
4786 /* 881 */ Universe_rule,
4787 /* 882 */ Universe_rule,
4788 /* 883 */ Universe_rule,
4789 /* 884 */ rRegI_rule,
4790 /* 885 */ rRegI_rule,
4791 /* 886 */ rRegI_rule,
4792 /* 887 */ rRegI_rule,
4793 /* 888 */ rRegI_rule,
4794 /* 889 */ Universe_rule,
4795 /* 890 */ Universe_rule,
4796 /* 891 */ Universe_rule,
4797 /* 892 */ Universe_rule,
4798 /* 893 */ Universe_rule,
4799 /* 894 */ rRegL_rule,
4800 /* 895 */ rRegL_rule,
4801 /* 896 */ rRegL_rule,
4802 /* 897 */ rRegL_rule,
4803 /* 898 */ rRegL_rule,
4804 /* 899 */ rRegL_rule,
4805 /* 900 */ Universe_rule,
4806 /* 901 */ Universe_rule,
4807 /* 902 */ Universe_rule,
4808 /* 903 */ rRegL_rule,
4809 /* 904 */ rRegL_rule,
4810 /* 905 */ rRegL_rule,
4811 /* 906 */ rRegL_rule,
4812 /* 907 */ rRegL_rule,
4813 /* 908 */ rRegL_rule,
4814 /* 909 */ rRegL_rule,
4815 /* 910 */ rRegL_rule,
4816 /* 911 */ rRegL_rule,
4817 /* 912 */ rRegL_rule,
4818 /* 913 */ rRegL_rule,
4819 /* 914 */ rRegL_rule,
4820 /* 915 */ rRegL_rule,
4821 /* 916 */ rRegL_rule,
4822 /* 917 */ rRegL_rule,
4823 /* 918 */ rRegL_rule,
4824 /* 919 */ rRegL_rule,
4825 /* 920 */ rRegL_rule,
4826 /* 921 */ rRegL_rule,
4827 /* 922 */ rRegL_rule,
4828 /* 923 */ rRegL_rule,
4829 /* 924 */ rRegL_rule,
4830 /* 925 */ Universe_rule,
4831 /* 926 */ Universe_rule,
4832 /* 927 */ Universe_rule,
4833 /* 928 */ rRegL_rule,
4834 /* 929 */ rRegL_rule,
4835 /* 930 */ rRegL_rule,
4836 /* 931 */ rRegL_rule,
4837 /* 932 */ rRegL_rule,
4838 /* 933 */ Universe_rule,
4839 /* 934 */ Universe_rule,
4840 /* 935 */ Universe_rule,
4841 /* 936 */ rRegI_rule,
4842 /* 937 */ rRegI_rule,
4843 /* 938 */ rRegI_rule,
4844 /* 939 */ rRegI_rule,
4845 /* 940 */ rRegI_rule,
4846 /* 941 */ rRegI_rule,
4847 /* 942 */ rRegI_rule,
4848 /* 943 */ rRegI_rule,
4849 /* 944 */ rRegI_rule,
4850 /* 945 */ rRegI_rule,
4851 /* 946 */ rRegI_rule,
4852 /* 947 */ rRegI_rule,
4853 /* 948 */ rRegI_rule,
4854 /* 949 */ rRegI_rule,
4855 /* 950 */ rRegI_rule,
4856 /* 951 */ rRegI_rule,
4857 /* 952 */ regD_rule,
4858 /* 953 */ regD_rule,
4859 /* 954 */ regF_rule,
4860 /* 955 */ regF_rule,
4861 /* 956 */ rRegI_rule,
4862 /* 957 */ rRegL_rule,
4863 /* 958 */ rRegI_rule,
4864 /* 959 */ rRegL_rule,
4865 /* 960 */ regF_rule,
4866 /* 961 */ regF_rule,
4867 /* 962 */ regD_rule,
4868 /* 963 */ regD_rule,
4869 /* 964 */ regF_rule,
4870 /* 965 */ regD_rule,
4871 /* 966 */ regF_rule,
4872 /* 967 */ regF_rule,
4873 /* 968 */ regD_rule,
4874 /* 969 */ regD_rule,
4875 /* 970 */ rRegL_rule,
4876 /* 971 */ rRegL_rule,
4877 /* 972 */ rRegL_rule,
4878 /* 973 */ rRegL_rule,
4879 /* 974 */ rRegI_rule,
4880 /* 975 */ stackSlotI_rule,
4881 /* 976 */ stackSlotF_rule,
4882 /* 977 */ stackSlotL_rule,
4883 /* 978 */ stackSlotD_rule,
4884 /* 979 */ Universe_rule,
4885 /* 980 */ Universe_rule,
4886 /* 981 */ rax_RegI_rule,
4887 /* 982 */ rax_RegI_rule,
4888 /* 983 */ rax_RegI_rule,
4889 /* 984 */ rax_RegI_rule,
4890 /* 985 */ rbx_RegI_rule,
4891 /* 986 */ rbx_RegI_rule,
4892 /* 987 */ rbx_RegI_rule,
4893 /* 988 */ rbx_RegI_rule,
4894 /* 989 */ rbx_RegI_rule,
4895 /* 990 */ rbx_RegI_rule,
4896 /* 991 */ rbx_RegI_rule,
4897 /* 992 */ rax_RegI_rule,
4898 /* 993 */ rax_RegI_rule,
4899 /* 994 */ rax_RegI_rule,
4900 /* 995 */ rax_RegI_rule,
4901 /* 996 */ rax_RegI_rule,
4902 /* 997 */ Universe_rule,
4903 /* 998 */ rax_RegI_rule,
4904 /* 999 */ rRegI_rule,
4905 /* 1000 */ 0,
4906 /* 1001 */ rRegI_rule,
4907 /* 1002 */ 0,
4908 /* 1003 */ rRegI_rule,
4909 /* 1004 */ Universe_rule,
4910 /* 1005 */ Universe_rule,
4911 /* 1006 */ Universe_rule,
4912 /* 1007 */ Universe_rule,
4913 /* 1008 */ Universe_rule,
4914 /* 1009 */ Universe_rule,
4915 /* 1010 */ Universe_rule,
4916 /* 1011 */ Universe_rule,
4917 /* 1012 */ Universe_rule,
4918 /* 1013 */ Universe_rule,
4919 /* 1014 */ Universe_rule,
4920 /* 1015 */ rdi_RegP_rule,
4921 /* 1016 */ Universe_rule,
4922 /* 1017 */ Universe_rule,
4923 /* 1018 */ Universe_rule,
4924 /* 1019 */ Universe_rule,
4925 /* 1020 */ Universe_rule,
4926 /* 1021 */ Universe_rule,
4927 /* 1022 */ Universe_rule,
4928 /* 1023 */ Universe_rule,
4929 /* 1024 */ Universe_rule,
4930 /* 1025 */ Universe_rule,
4931 /* 1026 */ Universe_rule,
4932 /* 1027 */ Universe_rule,
4933 /* 1028 */ Universe_rule,
4934 /* 1029 */ Universe_rule,
4935 /* 1030 */ Universe_rule,
4936 /* 1031 */ Universe_rule,
4937 /* 1032 */ Universe_rule,
4938 /* 1033 */ Universe_rule,
4939 /* 1034 */ rax_RegP_rule,
4940 /* 1035 */ Universe_rule,
4941 /* 1036 */ Universe_rule,
4942 /* 1037 */ rRegI_rule,
4943 /* 1038 */ regF_rule,
4944 /* 1039 */ regF_rule,
4945 /* 1040 */ regF_rule,
4946 /* 1041 */ regF_rule,
4947 /* 1042 */ regF_rule,
4948 /* 1043 */ regF_rule,
4949 /* 1044 */ regF_rule,
4950 /* 1045 */ regF_rule,
4951 /* 1046 */ regD_rule,
4952 /* 1047 */ regD_rule,
4953 /* 1048 */ regD_rule,
4954 /* 1049 */ regD_rule,
4955 /* 1050 */ regD_rule,
4956 /* 1051 */ regD_rule,
4957 /* 1052 */ regD_rule,
4958 /* 1053 */ regD_rule,
4959 /* 1054 */ regF_rule,
4960 /* 1055 */ regF_rule,
4961 /* 1056 */ regF_rule,
4962 /* 1057 */ regF_rule,
4963 /* 1058 */ regF_rule,
4964 /* 1059 */ regF_rule,
4965 /* 1060 */ regD_rule,
4966 /* 1061 */ regD_rule,
4967 /* 1062 */ regD_rule,
4968 /* 1063 */ regD_rule,
4969 /* 1064 */ regD_rule,
4970 /* 1065 */ regD_rule,
4971 /* 1066 */ regF_rule,
4972 /* 1067 */ regF_rule,
4973 /* 1068 */ regF_rule,
4974 /* 1069 */ regF_rule,
4975 /* 1070 */ regF_rule,
4976 /* 1071 */ regF_rule,
4977 /* 1072 */ regF_rule,
4978 /* 1073 */ regF_rule,
4979 /* 1074 */ regD_rule,
4980 /* 1075 */ regD_rule,
4981 /* 1076 */ regD_rule,
4982 /* 1077 */ regD_rule,
4983 /* 1078 */ regD_rule,
4984 /* 1079 */ regD_rule,
4985 /* 1080 */ regD_rule,
4986 /* 1081 */ regD_rule,
4987 /* 1082 */ regF_rule,
4988 /* 1083 */ regF_rule,
4989 /* 1084 */ regF_rule,
4990 /* 1085 */ regF_rule,
4991 /* 1086 */ regF_rule,
4992 /* 1087 */ regF_rule,
4993 /* 1088 */ regD_rule,
4994 /* 1089 */ regD_rule,
4995 /* 1090 */ regD_rule,
4996 /* 1091 */ regD_rule,
4997 /* 1092 */ regD_rule,
4998 /* 1093 */ regD_rule,
4999 /* 1094 */ regF_rule,
5000 /* 1095 */ regF_rule,
5001 /* 1096 */ regF_rule,
5002 /* 1097 */ regD_rule,
5003 /* 1098 */ regD_rule,
5004 /* 1099 */ regD_rule,
5005 /* 1100 */ Universe_rule,
5006 /* 1101 */ regD_rule,
5007 /* 1102 */ regF_rule,
5008 /* 1103 */ vecS_rule,
5009 /* 1104 */ vecD_rule,
5010 /* 1105 */ vecX_rule,
5011 /* 1106 */ vecY_rule,
5012 /* 1107 */ vecZ_rule,
5013 /* 1108 */ vecZ_rule,
5014 /* 1109 */ Universe_rule,
5015 /* 1110 */ Universe_rule,
5016 /* 1111 */ Universe_rule,
5017 /* 1112 */ Universe_rule,
5018 /* 1113 */ Universe_rule,
5019 /* 1114 */ Universe_rule,
5020 /* 1115 */ vecX_rule,
5021 /* 1116 */ vecY_rule,
5022 /* 1117 */ legVecZ_rule,
5023 /* 1118 */ vecX_rule,
5024 /* 1119 */ vecY_rule,
5025 /* 1120 */ legVecZ_rule,
5026 /* 1121 */ vecD_rule,
5027 /* 1122 */ vecD_rule,
5028 /* 1123 */ vecX_rule,
5029 /* 1124 */ vecX_rule,
5030 /* 1125 */ vecX_rule,
5031 /* 1126 */ vecY_rule,
5032 /* 1127 */ vecY_rule,
5033 /* 1128 */ vecY_rule,
5034 /* 1129 */ legVecZ_rule,
5035 /* 1130 */ legVecZ_rule,
5036 /* 1131 */ legVecZ_rule,
5037 /* 1132 */ vecX_rule,
5038 /* 1133 */ vecX_rule,
5039 /* 1134 */ vecY_rule,
5040 /* 1135 */ vecY_rule,
5041 /* 1136 */ legVecZ_rule,
5042 /* 1137 */ legVecZ_rule,
5043 /* 1138 */ vecX_rule,
5044 /* 1139 */ vecY_rule,
5045 /* 1140 */ legVecZ_rule,
5046 /* 1141 */ vecX_rule,
5047 /* 1142 */ vecY_rule,
5048 /* 1143 */ legVecZ_rule,
5049 /* 1144 */ vecY_rule,
5050 /* 1145 */ legVecZ_rule,
5051 /* 1146 */ vecY_rule,
5052 /* 1147 */ legVecZ_rule,
5053 /* 1148 */ vecD_rule,
5054 /* 1149 */ vecX_rule,
5055 /* 1150 */ vecY_rule,
5056 /* 1151 */ vecY_rule,
5057 /* 1152 */ legVecZ_rule,
5058 /* 1153 */ legVecZ_rule,
5059 /* 1154 */ vecD_rule,
5060 /* 1155 */ vecX_rule,
5061 /* 1156 */ vecY_rule,
5062 /* 1157 */ vecX_rule,
5063 /* 1158 */ vecY_rule,
5064 /* 1159 */ vecY_rule,
5065 /* 1160 */ legVecZ_rule,
5066 /* 1161 */ legVecZ_rule,
5067 /* 1162 */ vecX_rule,
5068 /* 1163 */ vecY_rule,
5069 /* 1164 */ vecS_rule,
5070 /* 1165 */ vecD_rule,
5071 /* 1166 */ vecS_rule,
5072 /* 1167 */ vecD_rule,
5073 /* 1168 */ vecS_rule,
5074 /* 1169 */ vecD_rule,
5075 /* 1170 */ vecX_rule,
5076 /* 1171 */ vecY_rule,
5077 /* 1172 */ vecS_rule,
5078 /* 1173 */ vecS_rule,
5079 /* 1174 */ vecD_rule,
5080 /* 1175 */ vecS_rule,
5081 /* 1176 */ vecD_rule,
5082 /* 1177 */ vecX_rule,
5083 /* 1178 */ vecY_rule,
5084 /* 1179 */ vecD_rule,
5085 /* 1180 */ vecD_rule,
5086 /* 1181 */ vecD_rule,
5087 /* 1182 */ vecD_rule,
5088 /* 1183 */ vecX_rule,
5089 /* 1184 */ vecY_rule,
5090 /* 1185 */ vecX_rule,
5091 /* 1186 */ vecX_rule,
5092 /* 1187 */ vecX_rule,
5093 /* 1188 */ vecY_rule,
5094 /* 1189 */ vecD_rule,
5095 /* 1190 */ vecX_rule,
5096 /* 1191 */ vecX_rule,
5097 /* 1192 */ vecS_rule,
5098 /* 1193 */ vecD_rule,
5099 /* 1194 */ vecX_rule,
5100 /* 1195 */ vecX_rule,
5101 /* 1196 */ vecY_rule,
5102 /* 1197 */ vecY_rule,
5103 /* 1198 */ vecZ_rule,
5104 /* 1199 */ vecZ_rule,
5105 /* 1200 */ vecX_rule,
5106 /* 1201 */ vecY_rule,
5107 /* 1202 */ vecZ_rule,
5108 /* 1203 */ vecZ_rule,
5109 /* 1204 */ vecD_rule,
5110 /* 1205 */ vecD_rule,
5111 /* 1206 */ vecX_rule,
5112 /* 1207 */ vecX_rule,
5113 /* 1208 */ vecY_rule,
5114 /* 1209 */ vecY_rule,
5115 /* 1210 */ vecZ_rule,
5116 /* 1211 */ vecZ_rule,
5117 /* 1212 */ vecX_rule,
5118 /* 1213 */ vecY_rule,
5119 /* 1214 */ vecZ_rule,
5120 /* 1215 */ vecZ_rule,
5121 /* 1216 */ vecX_rule,
5122 /* 1217 */ vecX_rule,
5123 /* 1218 */ vecY_rule,
5124 /* 1219 */ vecY_rule,
5125 /* 1220 */ vecZ_rule,
5126 /* 1221 */ vecZ_rule,
5127 /* 1222 */ vecX_rule,
5128 /* 1223 */ vecY_rule,
5129 /* 1224 */ vecZ_rule,
5130 /* 1225 */ vecZ_rule,
5131 /* 1226 */ vecY_rule,
5132 /* 1227 */ vecZ_rule,
5133 /* 1228 */ vecY_rule,
5134 /* 1229 */ vecZ_rule,
5135 /* 1230 */ vecX_rule,
5136 /* 1231 */ vecY_rule,
5137 /* 1232 */ vecZ_rule,
5138 /* 1233 */ vecZ_rule,
5139 /* 1234 */ vecY_rule,
5140 /* 1235 */ vecY_rule,
5141 /* 1236 */ vecZ_rule,
5142 /* 1237 */ vecZ_rule,
5143 /* 1238 */ vecD_rule,
5144 /* 1239 */ vecX_rule,
5145 /* 1240 */ vecY_rule,
5146 /* 1241 */ vecZ_rule,
5147 /* 1242 */ vecY_rule,
5148 /* 1243 */ vecY_rule,
5149 /* 1244 */ vecZ_rule,
5150 /* 1245 */ vecZ_rule,
5151 /* 1246 */ vecX_rule,
5152 /* 1247 */ vecY_rule,
5153 /* 1248 */ vecZ_rule,
5154 /* 1249 */ rRegI_rule,
5155 /* 1250 */ rRegI_rule,
5156 /* 1251 */ rRegI_rule,
5157 /* 1252 */ rRegI_rule,
5158 /* 1253 */ rRegI_rule,
5159 /* 1254 */ rRegI_rule,
5160 /* 1255 */ rRegI_rule,
5161 /* 1256 */ rRegI_rule,
5162 /* 1257 */ rRegI_rule,
5163 /* 1258 */ rRegL_rule,
5164 /* 1259 */ rRegL_rule,
5165 /* 1260 */ rRegL_rule,
5166 /* 1261 */ regF_rule,
5167 /* 1262 */ regF_rule,
5168 /* 1263 */ regF_rule,
5169 /* 1264 */ regF_rule,
5170 /* 1265 */ regF_rule,
5171 /* 1266 */ regF_rule,
5172 /* 1267 */ regD_rule,
5173 /* 1268 */ regD_rule,
5174 /* 1269 */ regD_rule,
5175 /* 1270 */ regD_rule,
5176 /* 1271 */ rRegI_rule,
5177 /* 1272 */ rRegI_rule,
5178 /* 1273 */ rRegI_rule,
5179 /* 1274 */ rRegI_rule,
5180 /* 1275 */ rRegI_rule,
5181 /* 1276 */ rRegI_rule,
5182 /* 1277 */ rRegL_rule,
5183 /* 1278 */ rRegL_rule,
5184 /* 1279 */ rRegL_rule,
5185 /* 1280 */ regF_rule,
5186 /* 1281 */ regF_rule,
5187 /* 1282 */ regF_rule,
5188 /* 1283 */ regF_rule,
5189 /* 1284 */ regF_rule,
5190 /* 1285 */ regF_rule,
5191 /* 1286 */ regD_rule,
5192 /* 1287 */ regD_rule,
5193 /* 1288 */ regD_rule,
5194 /* 1289 */ regD_rule,
5195 /* 1290 */ vecS_rule,
5196 /* 1291 */ vecS_rule,
5197 /* 1292 */ vecS_rule,
5198 /* 1293 */ vecS_rule,
5199 /* 1294 */ vecD_rule,
5200 /* 1295 */ vecD_rule,
5201 /* 1296 */ vecD_rule,
5202 /* 1297 */ vecD_rule,
5203 /* 1298 */ vecX_rule,
5204 /* 1299 */ vecX_rule,
5205 /* 1300 */ vecX_rule,
5206 /* 1301 */ vecX_rule,
5207 /* 1302 */ vecY_rule,
5208 /* 1303 */ vecY_rule,
5209 /* 1304 */ vecY_rule,
5210 /* 1305 */ vecZ_rule,
5211 /* 1306 */ vecZ_rule,
5212 /* 1307 */ vecZ_rule,
5213 /* 1308 */ vecS_rule,
5214 /* 1309 */ vecS_rule,
5215 /* 1310 */ vecS_rule,
5216 /* 1311 */ vecS_rule,
5217 /* 1312 */ vecD_rule,
5218 /* 1313 */ vecD_rule,
5219 /* 1314 */ vecD_rule,
5220 /* 1315 */ vecD_rule,
5221 /* 1316 */ vecX_rule,
5222 /* 1317 */ vecX_rule,
5223 /* 1318 */ vecX_rule,
5224 /* 1319 */ vecX_rule,
5225 /* 1320 */ vecY_rule,
5226 /* 1321 */ vecY_rule,
5227 /* 1322 */ vecY_rule,
5228 /* 1323 */ vecZ_rule,
5229 /* 1324 */ vecZ_rule,
5230 /* 1325 */ vecZ_rule,
5231 /* 1326 */ vecD_rule,
5232 /* 1327 */ vecD_rule,
5233 /* 1328 */ vecD_rule,
5234 /* 1329 */ vecD_rule,
5235 /* 1330 */ vecX_rule,
5236 /* 1331 */ vecX_rule,
5237 /* 1332 */ vecX_rule,
5238 /* 1333 */ vecX_rule,
5239 /* 1334 */ vecY_rule,
5240 /* 1335 */ vecY_rule,
5241 /* 1336 */ vecY_rule,
5242 /* 1337 */ vecZ_rule,
5243 /* 1338 */ vecZ_rule,
5244 /* 1339 */ vecZ_rule,
5245 /* 1340 */ vecX_rule,
5246 /* 1341 */ vecX_rule,
5247 /* 1342 */ vecX_rule,
5248 /* 1343 */ vecX_rule,
5249 /* 1344 */ vecY_rule,
5250 /* 1345 */ vecY_rule,
5251 /* 1346 */ vecY_rule,
5252 /* 1347 */ vecZ_rule,
5253 /* 1348 */ vecZ_rule,
5254 /* 1349 */ vecZ_rule,
5255 /* 1350 */ vecD_rule,
5256 /* 1351 */ vecD_rule,
5257 /* 1352 */ vecD_rule,
5258 /* 1353 */ vecD_rule,
5259 /* 1354 */ vecX_rule,
5260 /* 1355 */ vecX_rule,
5261 /* 1356 */ vecX_rule,
5262 /* 1357 */ vecX_rule,
5263 /* 1358 */ vecY_rule,
5264 /* 1359 */ vecY_rule,
5265 /* 1360 */ vecY_rule,
5266 /* 1361 */ vecZ_rule,
5267 /* 1362 */ vecZ_rule,
5268 /* 1363 */ vecZ_rule,
5269 /* 1364 */ vecX_rule,
5270 /* 1365 */ vecX_rule,
5271 /* 1366 */ vecX_rule,
5272 /* 1367 */ vecX_rule,
5273 /* 1368 */ vecY_rule,
5274 /* 1369 */ vecY_rule,
5275 /* 1370 */ vecY_rule,
5276 /* 1371 */ vecZ_rule,
5277 /* 1372 */ vecZ_rule,
5278 /* 1373 */ vecZ_rule,
5279 /* 1374 */ vecS_rule,
5280 /* 1375 */ vecS_rule,
5281 /* 1376 */ vecS_rule,
5282 /* 1377 */ vecD_rule,
5283 /* 1378 */ vecD_rule,
5284 /* 1379 */ vecD_rule,
5285 /* 1380 */ vecX_rule,
5286 /* 1381 */ vecX_rule,
5287 /* 1382 */ vecX_rule,
5288 /* 1383 */ vecY_rule,
5289 /* 1384 */ vecY_rule,
5290 /* 1385 */ vecZ_rule,
5291 /* 1386 */ vecZ_rule,
5292 /* 1387 */ vecS_rule,
5293 /* 1388 */ vecS_rule,
5294 /* 1389 */ vecS_rule,
5295 /* 1390 */ vecD_rule,
5296 /* 1391 */ vecD_rule,
5297 /* 1392 */ vecD_rule,
5298 /* 1393 */ vecX_rule,
5299 /* 1394 */ vecX_rule,
5300 /* 1395 */ vecX_rule,
5301 /* 1396 */ vecY_rule,
5302 /* 1397 */ vecY_rule,
5303 /* 1398 */ vecZ_rule,
5304 /* 1399 */ vecZ_rule,
5305 /* 1400 */ vecD_rule,
5306 /* 1401 */ vecD_rule,
5307 /* 1402 */ vecD_rule,
5308 /* 1403 */ vecX_rule,
5309 /* 1404 */ vecX_rule,
5310 /* 1405 */ vecX_rule,
5311 /* 1406 */ vecY_rule,
5312 /* 1407 */ vecY_rule,
5313 /* 1408 */ vecZ_rule,
5314 /* 1409 */ vecZ_rule,
5315 /* 1410 */ vecX_rule,
5316 /* 1411 */ vecX_rule,
5317 /* 1412 */ vecX_rule,
5318 /* 1413 */ vecY_rule,
5319 /* 1414 */ vecY_rule,
5320 /* 1415 */ vecZ_rule,
5321 /* 1416 */ vecZ_rule,
5322 /* 1417 */ vecD_rule,
5323 /* 1418 */ vecD_rule,
5324 /* 1419 */ vecD_rule,
5325 /* 1420 */ vecX_rule,
5326 /* 1421 */ vecX_rule,
5327 /* 1422 */ vecX_rule,
5328 /* 1423 */ vecY_rule,
5329 /* 1424 */ vecY_rule,
5330 /* 1425 */ vecZ_rule,
5331 /* 1426 */ vecZ_rule,
5332 /* 1427 */ vecX_rule,
5333 /* 1428 */ vecX_rule,
5334 /* 1429 */ vecX_rule,
5335 /* 1430 */ vecY_rule,
5336 /* 1431 */ vecY_rule,
5337 /* 1432 */ vecZ_rule,
5338 /* 1433 */ vecZ_rule,
5339 /* 1434 */ vecS_rule,
5340 /* 1435 */ vecD_rule,
5341 /* 1436 */ vecX_rule,
5342 /* 1437 */ vecX_rule,
5343 /* 1438 */ vecY_rule,
5344 /* 1439 */ vecZ_rule,
5345 /* 1440 */ vecS_rule,
5346 /* 1441 */ vecS_rule,
5347 /* 1442 */ vecS_rule,
5348 /* 1443 */ vecS_rule,
5349 /* 1444 */ vecD_rule,
5350 /* 1445 */ vecD_rule,
5351 /* 1446 */ vecD_rule,
5352 /* 1447 */ vecD_rule,
5353 /* 1448 */ vecX_rule,
5354 /* 1449 */ vecX_rule,
5355 /* 1450 */ vecX_rule,
5356 /* 1451 */ vecX_rule,
5357 /* 1452 */ vecY_rule,
5358 /* 1453 */ vecY_rule,
5359 /* 1454 */ vecY_rule,
5360 /* 1455 */ vecZ_rule,
5361 /* 1456 */ vecZ_rule,
5362 /* 1457 */ vecZ_rule,
5363 /* 1458 */ vecD_rule,
5364 /* 1459 */ vecD_rule,
5365 /* 1460 */ vecD_rule,
5366 /* 1461 */ vecD_rule,
5367 /* 1462 */ vecX_rule,
5368 /* 1463 */ vecX_rule,
5369 /* 1464 */ vecX_rule,
5370 /* 1465 */ vecX_rule,
5371 /* 1466 */ vecX_rule,
5372 /* 1467 */ vecX_rule,
5373 /* 1468 */ vecX_rule,
5374 /* 1469 */ vecY_rule,
5375 /* 1470 */ vecY_rule,
5376 /* 1471 */ vecY_rule,
5377 /* 1472 */ vecZ_rule,
5378 /* 1473 */ vecZ_rule,
5379 /* 1474 */ vecZ_rule,
5380 /* 1475 */ vecY_rule,
5381 /* 1476 */ vecY_rule,
5382 /* 1477 */ vecY_rule,
5383 /* 1478 */ vecZ_rule,
5384 /* 1479 */ vecZ_rule,
5385 /* 1480 */ vecZ_rule,
5386 /* 1481 */ vecD_rule,
5387 /* 1482 */ vecD_rule,
5388 /* 1483 */ vecD_rule,
5389 /* 1484 */ vecD_rule,
5390 /* 1485 */ vecX_rule,
5391 /* 1486 */ vecX_rule,
5392 /* 1487 */ vecX_rule,
5393 /* 1488 */ vecX_rule,
5394 /* 1489 */ vecY_rule,
5395 /* 1490 */ vecY_rule,
5396 /* 1491 */ vecY_rule,
5397 /* 1492 */ vecZ_rule,
5398 /* 1493 */ vecZ_rule,
5399 /* 1494 */ vecZ_rule,
5400 /* 1495 */ vecX_rule,
5401 /* 1496 */ vecX_rule,
5402 /* 1497 */ vecX_rule,
5403 /* 1498 */ vecX_rule,
5404 /* 1499 */ vecY_rule,
5405 /* 1500 */ vecY_rule,
5406 /* 1501 */ vecY_rule,
5407 /* 1502 */ vecZ_rule,
5408 /* 1503 */ vecZ_rule,
5409 /* 1504 */ vecZ_rule,
5410 /* 1505 */ legVecY_rule,
5411 /* 1506 */ legVecY_rule,
5412 /* 1507 */ vecD_rule,
5413 /* 1508 */ vecD_rule,
5414 /* 1509 */ vecD_rule,
5415 /* 1510 */ vecX_rule,
5416 /* 1511 */ vecX_rule,
5417 /* 1512 */ vecX_rule,
5418 /* 1513 */ vecY_rule,
5419 /* 1514 */ vecY_rule,
5420 /* 1515 */ vecZ_rule,
5421 /* 1516 */ vecZ_rule,
5422 /* 1517 */ vecX_rule,
5423 /* 1518 */ vecX_rule,
5424 /* 1519 */ vecX_rule,
5425 /* 1520 */ vecY_rule,
5426 /* 1521 */ vecY_rule,
5427 /* 1522 */ vecZ_rule,
5428 /* 1523 */ vecZ_rule,
5429 /* 1524 */ vecS_rule,
5430 /* 1525 */ vecS_rule,
5431 /* 1526 */ vecS_rule,
5432 /* 1527 */ vecD_rule,
5433 /* 1528 */ vecD_rule,
5434 /* 1529 */ vecD_rule,
5435 /* 1530 */ vecX_rule,
5436 /* 1531 */ vecX_rule,
5437 /* 1532 */ vecX_rule,
5438 /* 1533 */ vecX_rule,
5439 /* 1534 */ vecX_rule,
5440 /* 1535 */ vecX_rule,
5441 /* 1536 */ vecY_rule,
5442 /* 1537 */ vecY_rule,
5443 /* 1538 */ vecY_rule,
5444 /* 1539 */ vecZ_rule,
5445 /* 1540 */ vecZ_rule,
5446 /* 1541 */ vecZ_rule,
5447 /* 1542 */ vecS_rule,
5448 /* 1543 */ vecS_rule,
5449 /* 1544 */ vecS_rule,
5450 /* 1545 */ vecD_rule,
5451 /* 1546 */ vecD_rule,
5452 /* 1547 */ vecD_rule,
5453 /* 1548 */ vecX_rule,
5454 /* 1549 */ vecX_rule,
5455 /* 1550 */ vecX_rule,
5456 /* 1551 */ vecY_rule,
5457 /* 1552 */ vecY_rule,
5458 /* 1553 */ vecY_rule,
5459 /* 1554 */ vecZ_rule,
5460 /* 1555 */ vecZ_rule,
5461 /* 1556 */ vecZ_rule,
5462 /* 1557 */ vecD_rule,
5463 /* 1558 */ vecD_rule,
5464 /* 1559 */ vecD_rule,
5465 /* 1560 */ vecX_rule,
5466 /* 1561 */ vecX_rule,
5467 /* 1562 */ vecX_rule,
5468 /* 1563 */ vecY_rule,
5469 /* 1564 */ vecY_rule,
5470 /* 1565 */ vecY_rule,
5471 /* 1566 */ vecZ_rule,
5472 /* 1567 */ vecZ_rule,
5473 /* 1568 */ vecZ_rule,
5474 /* 1569 */ vecX_rule,
5475 /* 1570 */ vecX_rule,
5476 /* 1571 */ vecY_rule,
5477 /* 1572 */ vecY_rule,
5478 /* 1573 */ vecZ_rule,
5479 /* 1574 */ vecZ_rule,
5480 /* 1575 */ vecZ_rule,
5481 /* 1576 */ vecX_rule,
5482 /* 1577 */ vecX_rule,
5483 /* 1578 */ vecY_rule,
5484 /* 1579 */ vecY_rule,
5485 /* 1580 */ vecS_rule,
5486 /* 1581 */ vecS_rule,
5487 /* 1582 */ vecS_rule,
5488 /* 1583 */ vecS_rule,
5489 /* 1584 */ vecD_rule,
5490 /* 1585 */ vecD_rule,
5491 /* 1586 */ vecD_rule,
5492 /* 1587 */ vecD_rule,
5493 /* 1588 */ vecX_rule,
5494 /* 1589 */ vecX_rule,
5495 /* 1590 */ vecX_rule,
5496 /* 1591 */ vecX_rule,
5497 /* 1592 */ vecY_rule,
5498 /* 1593 */ vecY_rule,
5499 /* 1594 */ vecY_rule,
5500 /* 1595 */ vecZ_rule,
5501 /* 1596 */ vecZ_rule,
5502 /* 1597 */ vecZ_rule,
5503 /* 1598 */ vecS_rule,
5504 /* 1599 */ vecS_rule,
5505 /* 1600 */ vecS_rule,
5506 /* 1601 */ vecS_rule,
5507 /* 1602 */ vecD_rule,
5508 /* 1603 */ vecD_rule,
5509 /* 1604 */ vecD_rule,
5510 /* 1605 */ vecD_rule,
5511 /* 1606 */ vecX_rule,
5512 /* 1607 */ vecX_rule,
5513 /* 1608 */ vecX_rule,
5514 /* 1609 */ vecX_rule,
5515 /* 1610 */ vecY_rule,
5516 /* 1611 */ vecY_rule,
5517 /* 1612 */ vecY_rule,
5518 /* 1613 */ vecZ_rule,
5519 /* 1614 */ vecZ_rule,
5520 /* 1615 */ vecZ_rule,
5521 /* 1616 */ vecS_rule,
5522 /* 1617 */ vecS_rule,
5523 /* 1618 */ vecS_rule,
5524 /* 1619 */ vecS_rule,
5525 /* 1620 */ vecD_rule,
5526 /* 1621 */ vecD_rule,
5527 /* 1622 */ vecD_rule,
5528 /* 1623 */ vecD_rule,
5529 /* 1624 */ vecX_rule,
5530 /* 1625 */ vecX_rule,
5531 /* 1626 */ vecX_rule,
5532 /* 1627 */ vecX_rule,
5533 /* 1628 */ vecY_rule,
5534 /* 1629 */ vecY_rule,
5535 /* 1630 */ vecY_rule,
5536 /* 1631 */ vecZ_rule,
5537 /* 1632 */ vecZ_rule,
5538 /* 1633 */ vecZ_rule,
5539 /* 1634 */ vecX_rule,
5540 /* 1635 */ vecX_rule,
5541 /* 1636 */ vecY_rule,
5542 /* 1637 */ vecY_rule,
5543 /* 1638 */ vecZ_rule,
5544 /* 1639 */ vecZ_rule,
5545 /* 1640 */ vecD_rule,
5546 /* 1641 */ vecD_rule,
5547 /* 1642 */ vecX_rule,
5548 /* 1643 */ vecX_rule,
5549 /* 1644 */ vecY_rule,
5550 /* 1645 */ vecY_rule,
5551 /* 1646 */ vecZ_rule,
5552 /* 1647 */ vecZ_rule,
5553 /* 1648 */ vecX_rule,
5554 /* 1649 */ vecX_rule,
5555 /* 1650 */ vecY_rule,
5556 /* 1651 */ vecY_rule,
5557 /* 1652 */ vecZ_rule,
5558 /* 1653 */ vecZ_rule,
5559 /* 1654 */ vecX_rule,
5560 /* 1655 */ vecX_rule,
5561 /* 1656 */ vecY_rule,
5562 /* 1657 */ vecY_rule,
5563 /* 1658 */ vecZ_rule,
5564 /* 1659 */ vecZ_rule,
5565 /* 1660 */ vecD_rule,
5566 /* 1661 */ vecD_rule,
5567 /* 1662 */ vecX_rule,
5568 /* 1663 */ vecX_rule,
5569 /* 1664 */ vecY_rule,
5570 /* 1665 */ vecZ_rule,
5571 /* 1666 */ vecD_rule,
5572 /* 1667 */ vecD_rule,
5573 /* 1668 */ vecX_rule,
5574 /* 1669 */ vecX_rule,
5575 /* 1670 */ vecY_rule,
5576 /* 1671 */ vecY_rule,
5577 /* 1672 */ vecZ_rule,
5578 /* 1673 */ vecZ_rule,
5579 /* 1674 */ rRegI_rule,
5580 /* 1675 */ rRegI_rule,
5581 /* 1676 */ rRegI_rule,
5582 /* 1677 */ rRegI_rule,
5583 /* 1678 */ rax_RegN_rule,
5584 /* 1679 */ rax_RegP_rule,
5585 /* 1680 */ rRegP_rule,
5586 /* 1681 */ rRegP_rule,
5587 /* 1682 */ rRegP_rule,
5588 /* 1683 */ rRegP_rule,
5589 /* 1684 */ rax_RegP_rule,
5590 /* 1685 */ rRegI_rule,
5591 /* 1686 */ rRegI_rule,
5592 /* 1687 */ rRegP_rule,
5593 // last instruction
5594 0 // no trailing comma
5595};
5596
5597const int leftOp[] = {
5598 /* 0 */ 0,
5599 /* 1 */ 0,
5600 /* 2 */ 0,
5601 /* 3 */ 0,
5602 /* 4 */ 0,
5603 /* 5 */ 0,
5604 /* 6 */ 0,
5605 /* 7 */ 0,
5606 /* 8 */ 0,
5607 /* 9 */ 0,
5608 /* 10 */ 0,
5609 /* 11 */ 0,
5610 /* 12 */ 0,
5611 /* 13 */ 0,
5612 /* 14 */ 0,
5613 /* 15 */ 0,
5614 /* 16 */ 0,
5615 /* 17 */ 0,
5616 /* 18 */ 0,
5617 /* 19 */ 0,
5618 /* 20 */ 0,
5619 /* 21 */ 0,
5620 /* 22 */ 0,
5621 /* 23 */ 0,
5622 /* 24 */ 0,
5623 /* 25 */ 0,
5624 /* 26 */ 0,
5625 /* 27 */ 0,
5626 /* 28 */ 0,
5627 /* 29 */ 0,
5628 /* 30 */ 0,
5629 /* 31 */ 0,
5630 /* 32 */ 0,
5631 /* 33 */ 0,
5632 /* 34 */ 0,
5633 /* 35 */ 0,
5634 /* 36 */ 0,
5635 /* 37 */ 0,
5636 /* 38 */ 0,
5637 /* 39 */ 0,
5638 /* 40 */ 0,
5639 /* 41 */ 0,
5640 /* 42 */ 0,
5641 /* 43 */ 0,
5642 /* 44 */ 0,
5643 /* 45 */ 0,
5644 /* 46 */ 0,
5645 /* 47 */ 0,
5646 /* 48 */ 0,
5647 /* 49 */ 0,
5648 /* 50 */ 0,
5649 /* 51 */ 0,
5650 /* 52 */ 0,
5651 /* 53 */ 0,
5652 /* 54 */ 0,
5653 /* 55 */ 0,
5654 /* 56 */ 0,
5655 /* 57 */ 0,
5656 /* 58 */ 0,
5657 /* 59 */ 0,
5658 /* 60 */ 0,
5659 /* 61 */ 0,
5660 /* 62 */ 0,
5661 /* 63 */ 0,
5662 /* 64 */ 0,
5663 /* 65 */ 0,
5664 /* 66 */ 0,
5665 /* 67 */ 0,
5666 /* 68 */ 0,
5667 /* 69 */ 0,
5668 /* 70 */ 0,
5669 /* 71 */ 0,
5670 /* 72 */ 0,
5671 /* 73 */ 0,
5672 /* 74 */ 0,
5673 /* 75 */ 0,
5674 /* 76 */ 0,
5675 /* 77 */ 0,
5676 /* 78 */ 0,
5677 /* 79 */ 0,
5678 /* 80 */ 0,
5679 /* 81 */ 0,
5680 /* 82 */ 0,
5681 /* 83 */ 0,
5682 /* 84 */ 0,
5683 /* 85 */ 0,
5684 /* 86 */ 0,
5685 /* 87 */ 0,
5686 /* 88 */ 0,
5687 /* 89 */ 0,
5688 /* 90 */ any_RegP_rule,
5689 /* 91 */ any_RegP_rule,
5690 /* 92 */ _AddP_any_RegP_rRegL_rule,
5691 /* 93 */ any_RegP_rule,
5692 /* 94 */ any_RegP_rule,
5693 /* 95 */ any_RegP_rule,
5694 /* 96 */ _AddP_any_RegP__LShiftL_rRegL_immI2_rule,
5695 /* 97 */ _AddP_any_RegP__ConvI2L_rRegI__rule,
5696 /* 98 */ _AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2_rule,
5697 /* 99 */ _DecodeN_rRegN__rule,
5698 /* 100 */ rRegN_rule,
5699 /* 101 */ _DecodeN_rRegN__rule,
5700 /* 102 */ _DecodeN_rRegN__rule,
5701 /* 103 */ _AddP__DecodeN_rRegN__rRegL_rule,
5702 /* 104 */ _DecodeN_rRegN__rule,
5703 /* 105 */ _DecodeN_rRegN__rule,
5704 /* 106 */ _AddP__DecodeN_rRegN___LShiftL_rRegL_immI2_rule,
5705 /* 107 */ _AddP__DecodeN_rRegN___ConvI2L_rRegI__rule,
5706 /* 108 */ _AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2_rule,
5707 /* 109 */ 0,
5708 /* 110 */ 0,
5709 /* 111 */ 0,
5710 /* 112 */ 0,
5711 /* 113 */ 0,
5712 /* 114 */ 0,
5713 /* 115 */ 0,
5714 /* 116 */ 0,
5715 /* 117 */ 0,
5716 /* 118 */ 0,
5717 /* 119 */ 0,
5718 /* 120 */ 0,
5719 /* 121 */ 0,
5720 /* 122 */ 0,
5721 /* 123 */ 0,
5722 /* 124 */ 0,
5723 /* 125 */ 0,
5724 /* 126 */ 0,
5725 /* 127 */ 0,
5726 /* 128 */ 0,
5727 /* 129 */ 0,
5728 /* 130 */ 0,
5729 /* 131 */ 0,
5730 /* 132 */ 0,
5731 /* 133 */ 0,
5732 /* 134 */ 0,
5733 /* 135 */ 0,
5734 /* 136 */ 0,
5735 /* 137 */ 0,
5736 /* 138 */ 0,
5737 /* 139 */ 0,
5738 /* 140 */ 0,
5739 /* 141 */ 0,
5740 /* 142 */ 0,
5741 /* 143 */ 0,
5742 /* 144 */ 0,
5743 /* 145 */ 0,
5744 /* 146 */ 0,
5745 /* 147 */ 0,
5746 /* 148 */ 0,
5747 /* 149 */ 0,
5748 /* 150 */ 0,
5749 /* 151 */ 0,
5750 /* 152 */ 0,
5751 // last operand
5752 /* 153 */ 0,
5753 // last operand class
5754 /* 154 */ any_RegP_rule,
5755 /* 155 */ rRegL_rule,
5756 /* 156 */ rRegI_rule,
5757 /* 157 */ _ConvI2L_rRegI__rule,
5758 /* 158 */ any_RegP_rule,
5759 /* 159 */ any_RegP_rule,
5760 /* 160 */ any_RegP_rule,
5761 /* 161 */ rRegN_rule,
5762 /* 162 */ _DecodeN_rRegN__rule,
5763 /* 163 */ _DecodeN_rRegN__rule,
5764 /* 164 */ _DecodeN_rRegN__rule,
5765 /* 165 */ _DecodeN_rRegN__rule,
5766 /* 166 */ memory_rule,
5767 /* 167 */ memory_rule,
5768 /* 168 */ _LoadUB_memory__rule,
5769 /* 169 */ memory_rule,
5770 /* 170 */ _LoadS_memory__rule,
5771 /* 171 */ memory_rule,
5772 /* 172 */ _LoadUS_memory__rule,
5773 /* 173 */ _LoadUS_memory__rule,
5774 /* 174 */ _LoadUS_memory__rule,
5775 /* 175 */ memory_rule,
5776 /* 176 */ _LoadI_memory__rule,
5777 /* 177 */ _LoadI_memory__rule,
5778 /* 178 */ _LoadI_memory__rule,
5779 /* 179 */ _LoadI_memory__rule,
5780 /* 180 */ _LoadI_memory__rule,
5781 /* 181 */ _LoadI_memory__rule,
5782 /* 182 */ memory_rule,
5783 /* 183 */ rRegP_rule,
5784 /* 184 */ _DecodeN_rRegN__rule,
5785 /* 185 */ _LShiftL_rRegL_immI2_rule,
5786 /* 186 */ cmpOp_rule,
5787 /* 187 */ rRegI_rule,
5788 /* 188 */ cmpOpU_rule,
5789 /* 189 */ cmpOpUCF_rule,
5790 /* 190 */ rRegI_rule,
5791 /* 191 */ rRegN_rule,
5792 /* 192 */ rRegP_rule,
5793 /* 193 */ rRegL_rule,
5794 /* 194 */ rRegL_rule,
5795 /* 195 */ regF_rule,
5796 /* 196 */ regD_rule,
5797 /* 197 */ _LoadI_memory__rule,
5798 /* 198 */ rRegI_rule,
5799 /* 199 */ _LoadI_memory__rule,
5800 /* 200 */ _LoadI_memory__rule,
5801 /* 201 */ _LoadI_memory__rule,
5802 /* 202 */ _LoadL_memory__rule,
5803 /* 203 */ rRegL_rule,
5804 /* 204 */ _LoadL_memory__rule,
5805 /* 205 */ _LoadL_memory__rule,
5806 /* 206 */ _LoadL_memory__rule,
5807 /* 207 */ rax_RegP_rule,
5808 /* 208 */ rax_RegI_rule,
5809 /* 209 */ rax_RegL_rule,
5810 /* 210 */ rax_RegN_rule,
5811 /* 211 */ _LoadI_memory__rule,
5812 /* 212 */ _LoadI_memory__rule,
5813 /* 213 */ _LoadL_memory__rule,
5814 /* 214 */ _LoadL_memory__rule,
5815 /* 215 */ immI0_rule,
5816 /* 216 */ immI0_rule,
5817 /* 217 */ immL0_rule,
5818 /* 218 */ _LoadI_memory__rule,
5819 /* 219 */ _LoadI_memory__rule,
5820 /* 220 */ _LoadI_memory__rule,
5821 /* 221 */ _LoadI_memory__rule,
5822 /* 222 */ _LoadI_memory__rule,
5823 /* 223 */ _LoadI_memory__rule,
5824 /* 224 */ _LoadI_memory__rule,
5825 /* 225 */ _LoadI_memory__rule,
5826 /* 226 */ _LoadI_memory__rule,
5827 /* 227 */ _LoadL_memory__rule,
5828 /* 228 */ _LoadL_memory__rule,
5829 /* 229 */ _LoadL_memory__rule,
5830 /* 230 */ _LoadL_memory__rule,
5831 /* 231 */ _LoadL_memory__rule,
5832 /* 232 */ _LoadL_memory__rule,
5833 /* 233 */ _LoadL_memory__rule,
5834 /* 234 */ _LoadL_memory__rule,
5835 /* 235 */ _LoadL_memory__rule,
5836 /* 236 */ rRegI_rule,
5837 /* 237 */ rRegI_rule,
5838 /* 238 */ rRegI_rule,
5839 /* 239 */ rRegI_rule,
5840 /* 240 */ rRegI_rule,
5841 /* 241 */ rRegI_rule,
5842 /* 242 */ no_rcx_RegI_rule,
5843 /* 243 */ immI0_rule,
5844 /* 244 */ no_rcx_RegI_rule,
5845 /* 245 */ immI_32_rule,
5846 /* 246 */ no_rcx_RegI_rule,
5847 /* 247 */ rRegI_rule,
5848 /* 248 */ rRegI_rule,
5849 /* 249 */ no_rcx_RegI_rule,
5850 /* 250 */ no_rcx_RegI_rule,
5851 /* 251 */ no_rcx_RegI_rule,
5852 /* 252 */ rRegL_rule,
5853 /* 253 */ rRegL_rule,
5854 /* 254 */ rRegL_rule,
5855 /* 255 */ rRegL_rule,
5856 /* 256 */ no_rcx_RegL_rule,
5857 /* 257 */ no_rcx_RegL_rule,
5858 /* 258 */ immI_64_rule,
5859 /* 259 */ no_rcx_RegL_rule,
5860 /* 260 */ rRegL_rule,
5861 /* 261 */ rRegL_rule,
5862 /* 262 */ no_rcx_RegL_rule,
5863 /* 263 */ no_rcx_RegL_rule,
5864 /* 264 */ no_rcx_RegL_rule,
5865 /* 265 */ rRegI_rule,
5866 /* 266 */ rRegI_rule,
5867 /* 267 */ _LoadB_memory__rule,
5868 /* 268 */ rRegI_rule,
5869 /* 269 */ _LoadI_memory__rule,
5870 /* 270 */ rRegI_rule,
5871 /* 271 */ _LoadI_memory__rule,
5872 /* 272 */ rRegI_rule,
5873 /* 273 */ rRegI_rule,
5874 /* 274 */ _LoadB_memory__rule,
5875 /* 275 */ rRegI_rule,
5876 /* 276 */ _LoadI_memory__rule,
5877 /* 277 */ rRegI_rule,
5878 /* 278 */ _LoadI_memory__rule,
5879 /* 279 */ _LoadB_memory__rule,
5880 /* 280 */ rRegI_rule,
5881 /* 281 */ _LoadI_memory__rule,
5882 /* 282 */ rRegI_rule,
5883 /* 283 */ _LoadI_memory__rule,
5884 /* 284 */ _LoadL_memory__rule,
5885 /* 285 */ rRegL_rule,
5886 /* 286 */ _LoadL_memory__rule,
5887 /* 287 */ rRegL_rule,
5888 /* 288 */ immL0_rule,
5889 /* 289 */ rRegL_rule,
5890 /* 290 */ any_RegP_rule,
5891 /* 291 */ _LoadL_memory__rule,
5892 /* 292 */ rRegL_rule,
5893 /* 293 */ _LoadL_memory__rule,
5894 /* 294 */ _LoadL_memory__rule,
5895 /* 295 */ rRegL_rule,
5896 /* 296 */ _LoadL_memory__rule,
5897 /* 297 */ rRegI_rule,
5898 /* 298 */ _CmpLTMask_rRegI_rRegI_rule,
5899 /* 299 */ rRegI_rule,
5900 /* 300 */ rRegI_rule,
5901 /* 301 */ memory_rule,
5902 /* 302 */ memory_rule,
5903 /* 303 */ rdi_RegP_rule,
5904 /* 304 */ rsi_RegP_rule,
5905 /* 305 */ rdi_RegP_rule,
5906 /* 306 */ rsi_RegP_rule,
5907 /* 307 */ rsi_RegP_rule,
5908 /* 308 */ rdi_RegP_rule,
5909 /* 309 */ rRegI_rule,
5910 /* 310 */ memory_rule,
5911 /* 311 */ memory_rule,
5912 /* 312 */ memory_rule,
5913 /* 313 */ rRegL_rule,
5914 /* 314 */ _CastP2X_rRegP__rule,
5915 /* 315 */ _LoadL_memory__rule,
5916 /* 316 */ _LoadUB_memory__rule,
5917 /* 317 */ _LoadB_memory__rule,
5918 /* 318 */ rsi_RegP_rule,
5919 /* 319 */ memory_rule,
5920 /* 320 */ cmpOp_vcmppd_rule,
5921 /* 321 */ legVecY_rule,
5922 /* 322 */ vecX_rule,
5923 /* 323 */ vecX_rule,
5924 /* 324 */ vecY_rule,
5925 /* 325 */ vecY_rule,
5926 /* 326 */ vecZ_rule,
5927 /* 327 */ vecZ_rule,
5928 /* 328 */ vecD_rule,
5929 /* 329 */ vecX_rule,
5930 /* 330 */ vecY_rule,
5931 /* 331 */ vecZ_rule,
5932 /* 332 */ memory_rule,
5933 // last internally defined operand
5934 /* 333 */ rRegI_rule,
5935 /* 334 */ rRegL_rule,
5936 /* 335 */ rRegP_rule,
5937 /* 336 */ regF_rule,
5938 /* 337 */ regD_rule,
5939 /* 338 */ regF_rule,
5940 /* 339 */ regF_rule,
5941 /* 340 */ vlRegF_rule,
5942 /* 341 */ legRegF_rule,
5943 /* 342 */ regD_rule,
5944 /* 343 */ regD_rule,
5945 /* 344 */ vlRegD_rule,
5946 /* 345 */ legRegD_rule,
5947 /* 346 */ indOffset8_rule,
5948 /* 347 */ indOffset32_rule,
5949 /* 348 */ indIndexOffset_rule,
5950 /* 349 */ indIndexScale_rule,
5951 /* 350 */ indPosIndexScale_rule,
5952 /* 351 */ indIndexScaleOffset_rule,
5953 /* 352 */ indPosIndexOffset_rule,
5954 /* 353 */ indPosIndexScaleOffset_rule,
5955 /* 354 */ indCompressedOopOffset_rule,
5956 /* 355 */ indOffset8Narrow_rule,
5957 /* 356 */ indOffset32Narrow_rule,
5958 /* 357 */ indIndexOffsetNarrow_rule,
5959 /* 358 */ indIndexScaleNarrow_rule,
5960 /* 359 */ indIndexScaleOffsetNarrow_rule,
5961 /* 360 */ indPosIndexOffsetNarrow_rule,
5962 /* 361 */ indPosIndexScaleOffsetNarrow_rule,
5963 /* 362 */ immI_rule,
5964 /* 363 */ immI0_rule,
5965 /* 364 */ immL_rule,
5966 /* 365 */ immL0_rule,
5967 /* 366 */ immUL32_rule,
5968 /* 367 */ immL32_rule,
5969 /* 368 */ immP_rule,
5970 /* 369 */ immP0_rule,
5971 /* 370 */ immP31_rule,
5972 /* 371 */ immF_rule,
5973 /* 372 */ immN0_rule,
5974 /* 373 */ immN_rule,
5975 /* 374 */ immNKlass_rule,
5976 /* 375 */ immF0_rule,
5977 /* 376 */ immD_rule,
5978 /* 377 */ immD0_rule,
5979 /* 378 */ stackSlotI_rule,
5980 /* 379 */ stackSlotL_rule,
5981 /* 380 */ stackSlotP_rule,
5982 /* 381 */ stackSlotF_rule,
5983 /* 382 */ stackSlotD_rule,
5984 /* 383 */ vecS_rule,
5985 /* 384 */ legVecS_rule,
5986 /* 385 */ vecD_rule,
5987 /* 386 */ legVecD_rule,
5988 /* 387 */ vecX_rule,
5989 /* 388 */ legVecX_rule,
5990 /* 389 */ vecY_rule,
5991 /* 390 */ legVecY_rule,
5992 /* 391 */ vecZ_rule,
5993 /* 392 */ legVecZ_rule,
5994 /* 393 */ immI8_rule,
5995 /* 394 */ 0,
5996 /* 395 */ rRegL_rule,
5997 /* 396 */ rRegP_rule,
5998 /* 397 */ rRegP_rule,
5999 /* 398 */ rRegP_rule,
6000 /* 399 */ rRegI_rule,
6001 /* 400 */ memory_rule,
6002 /* 401 */ memory_rule,
6003 /* 402 */ memory_rule,
6004 /* 403 */ regF_rule,
6005 /* 404 */ regF_rule,
6006 /* 405 */ regF_rule,
6007 /* 406 */ regF_rule,
6008 /* 407 */ regF_rule,
6009 /* 408 */ regF_rule,
6010 /* 409 */ regD_rule,
6011 /* 410 */ regD_rule,
6012 /* 411 */ regD_rule,
6013 /* 412 */ regD_rule,
6014 /* 413 */ regD_rule,
6015 /* 414 */ regD_rule,
6016 /* 415 */ regF_rule,
6017 /* 416 */ regD_rule,
6018 /* 417 */ stackSlotF_rule,
6019 /* 418 */ stackSlotI_rule,
6020 /* 419 */ stackSlotD_rule,
6021 /* 420 */ stackSlotL_rule,
6022 /* 421 */ stackSlotL_rule,
6023 /* 422 */ regF_rule,
6024 /* 423 */ regD_rule,
6025 /* 424 */ rRegI_rule,
6026 /* 425 */ rRegL_rule,
6027 /* 426 */ rax_RegI_rule,
6028 /* 427 */ rax_RegI_rule,
6029 /* 428 */ rax_RegL_rule,
6030 /* 429 */ rax_RegL_rule,
6031 /* 430 */ rRegI_rule,
6032 /* 431 */ rRegI_rule,
6033 /* 432 */ rRegL_rule,
6034 /* 433 */ rRegL_rule,
6035 /* 434 */ immI0_rule,
6036 /* 435 */ immL0_rule,
6037 /* 436 */ rax_RegI_rule,
6038 /* 437 */ rRegI_rule,
6039 /* 438 */ rax_RegL_rule,
6040 /* 439 */ rRegL_rule,
6041 /* 440 */ rRegI_rule,
6042 /* 441 */ rRegI_rule,
6043 /* 442 */ rRegI_rule,
6044 /* 443 */ rRegI_rule,
6045 /* 444 */ _AndI_rRegI_immI_rule,
6046 /* 445 */ _AndI_rRegI__LoadI_memory__rule,
6047 /* 446 */ _AndI__LoadI_memory__rRegI_rule,
6048 /* 447 */ rRegI_rule,
6049 /* 448 */ rRegI_rule,
6050 /* 449 */ rRegI_rule,
6051 /* 450 */ rRegI_rule,
6052 /* 451 */ rRegP_rule,
6053 /* 452 */ rRegP_rule,
6054 /* 453 */ rRegP_rule,
6055 /* 454 */ rRegP_rule,
6056 /* 455 */ _LoadP_memory__rule,
6057 /* 456 */ _LoadP_memory__rule,
6058 /* 457 */ rRegN_rule,
6059 /* 458 */ rRegN_rule,
6060 /* 459 */ rRegN_rule,
6061 /* 460 */ immN_rule,
6062 /* 461 */ rRegN_rule,
6063 /* 462 */ immNKlass_rule,
6064 /* 463 */ rRegN_rule,
6065 /* 464 */ _LoadN_memory__rule,
6066 /* 465 */ _LoadN_memory__rule,
6067 /* 466 */ rRegL_rule,
6068 /* 467 */ rRegL_rule,
6069 /* 468 */ rRegL_rule,
6070 /* 469 */ rRegL_rule,
6071 /* 470 */ _AndL_rRegL_immL32_rule,
6072 /* 471 */ _AndL_rRegL__LoadL_memory__rule,
6073 /* 472 */ _AndL__LoadL_memory__rRegL_rule,
6074 /* 473 */ _AndL__CastP2X_rRegP___LoadL_memory__rule,
6075 /* 474 */ _AndL__LoadL_memory___CastP2X_rRegP__rule,
6076 /* 475 */ rRegL_rule,
6077 /* 476 */ rRegL_rule,
6078 /* 477 */ rRegL_rule,
6079 /* 478 */ rRegL_rule,
6080 /* 479 */ _LoadB_memory__rule,
6081 /* 480 */ _AndI__LoadUB_memory__immU8_rule,
6082 /* 481 */ _AndI__LoadB_memory__immI8_rule,
6083 /* 482 */ _PartialSubtypeCheck_rsi_RegP_rax_RegP_rule,
6084 /* 483 */ rRegP_rule,
6085 /* 484 */ rRegP_rule,
6086 /* 485 */ rRegP_rule,
6087 /* 486 */ 0,
6088 /* 487 */ 0,
6089 /* 488 */ regF_rule,
6090 /* 489 */ vlRegF_rule,
6091 /* 490 */ regD_rule,
6092 /* 491 */ vlRegD_rule,
6093 /* 492 */ regF_rule,
6094 /* 493 */ vlRegF_rule,
6095 /* 494 */ regD_rule,
6096 /* 495 */ vlRegD_rule,
6097 /* 496 */ vecX_rule,
6098 /* 497 */ _LoadVector_memory__rule,
6099 /* 498 */ vecY_rule,
6100 /* 499 */ _LoadVector_memory__rule,
6101 /* 500 */ vecZ_rule,
6102 /* 501 */ _LoadVector_memory__rule,
6103 /* 502 */ vecD_rule,
6104 /* 503 */ _LoadVector_memory__rule,
6105 /* 504 */ vecX_rule,
6106 /* 505 */ _LoadVector_memory__rule,
6107 /* 506 */ vecY_rule,
6108 /* 507 */ _LoadVector_memory__rule,
6109 /* 508 */ vecZ_rule,
6110 /* 509 */ _LoadVector_memory__rule,
6111 /* 510 */ rRegI_rule,
6112 /* 511 */ rRegI_rule,
6113 /* 512 */ vecS_rule,
6114 /* 513 */ vecD_rule,
6115 /* 514 */ vecX_rule,
6116 /* 515 */ vecY_rule,
6117 /* 516 */ vecZ_rule,
6118 /* 517 */ vecD_rule,
6119 /* 518 */ vecD_rule,
6120 /* 519 */ vecX_rule,
6121 /* 520 */ vecY_rule,
6122 /* 521 */ vecZ_rule,
6123 /* 522 */ vecD_rule,
6124 /* 523 */ vecX_rule,
6125 /* 524 */ vecY_rule,
6126 /* 525 */ vecZ_rule,
6127 /* 526 */ vecX_rule,
6128 /* 527 */ vecY_rule,
6129 /* 528 */ vecZ_rule,
6130 /* 529 */ vecD_rule,
6131 /* 530 */ vecX_rule,
6132 /* 531 */ vecY_rule,
6133 /* 532 */ vecZ_rule,
6134 /* 533 */ memory_rule,
6135 /* 534 */ _LoadB_memory__rule,
6136 /* 535 */ memory_rule,
6137 /* 536 */ _LoadUB_memory__rule,
6138 /* 537 */ _AndI__LoadUB_memory__immI_rule,
6139 /* 538 */ memory_rule,
6140 /* 539 */ _LShiftI__LoadS_memory__immI_24_rule,
6141 /* 540 */ _LoadS_memory__rule,
6142 /* 541 */ memory_rule,
6143 /* 542 */ _LShiftI__LoadUS_memory__immI_24_rule,
6144 /* 543 */ _LoadUS_memory__rule,
6145 /* 544 */ _AndI__LoadUS_memory__immI_255_rule,
6146 /* 545 */ _AndI__LoadUS_memory__immI_rule,
6147 /* 546 */ memory_rule,
6148 /* 547 */ _LShiftI__LoadI_memory__immI_24_rule,
6149 /* 548 */ _LoadI_memory__rule,
6150 /* 549 */ _LShiftI__LoadI_memory__immI_16_rule,
6151 /* 550 */ _LoadI_memory__rule,
6152 /* 551 */ _LoadI_memory__rule,
6153 /* 552 */ _AndI__LoadI_memory__immI_255_rule,
6154 /* 553 */ _AndI__LoadI_memory__immI_65535_rule,
6155 /* 554 */ _AndI__LoadI_memory__immU31_rule,
6156 /* 555 */ _ConvI2L__LoadI_memory___rule,
6157 /* 556 */ memory_rule,
6158 /* 557 */ memory_rule,
6159 /* 558 */ memory_rule,
6160 /* 559 */ memory_rule,
6161 /* 560 */ memory_rule,
6162 /* 561 */ memory_rule,
6163 /* 562 */ memory_rule,
6164 /* 563 */ memory_rule,
6165 /* 564 */ memory_rule,
6166 /* 565 */ legRegF_rule,
6167 /* 566 */ legRegF_rule,
6168 /* 567 */ legRegD_rule,
6169 /* 568 */ legRegD_rule,
6170 /* 569 */ legRegF_rule,
6171 /* 570 */ legRegF_rule,
6172 /* 571 */ legRegD_rule,
6173 /* 572 */ legRegD_rule,
6174 /* 573 */ memory_rule,
6175 /* 574 */ memory_rule,
6176 /* 575 */ memory_rule,
6177 /* 576 */ memory_rule,
6178 /* 577 */ memory_rule,
6179 /* 578 */ memory_rule,
6180 /* 579 */ memory_rule,
6181 /* 580 */ memory_rule,
6182 /* 581 */ memory_rule,
6183 /* 582 */ memory_rule,
6184 /* 583 */ memory_rule,
6185 /* 584 */ memory_rule,
6186 /* 585 */ memory_rule,
6187 /* 586 */ memory_rule,
6188 /* 587 */ memory_rule,
6189 /* 588 */ memory_rule,
6190 /* 589 */ memory_rule,
6191 /* 590 */ memory_rule,
6192 /* 591 */ memory_rule,
6193 /* 592 */ memory_rule,
6194 /* 593 */ memory_rule,
6195 /* 594 */ memory_rule,
6196 /* 595 */ memory_rule,
6197 /* 596 */ memory_rule,
6198 /* 597 */ memory_rule,
6199 /* 598 */ memory_rule,
6200 /* 599 */ memory_rule,
6201 /* 600 */ memory_rule,
6202 /* 601 */ memory_rule,
6203 /* 602 */ memory_rule,
6204 /* 603 */ memory_rule,
6205 /* 604 */ memory_rule,
6206 /* 605 */ rRegI_rule,
6207 /* 606 */ rRegL_rule,
6208 /* 607 */ rRegI_rule,
6209 /* 608 */ rRegI_rule,
6210 /* 609 */ rRegI_rule,
6211 /* 610 */ rRegI_rule,
6212 /* 611 */ rRegL_rule,
6213 /* 612 */ rRegL_rule,
6214 /* 613 */ rRegI_rule,
6215 /* 614 */ rRegI_rule,
6216 /* 615 */ rRegL_rule,
6217 /* 616 */ rRegL_rule,
6218 /* 617 */ rRegI_rule,
6219 /* 618 */ _LoadI_memory__rule,
6220 /* 619 */ rRegL_rule,
6221 /* 620 */ _LoadL_memory__rule,
6222 /* 621 */ 0,
6223 /* 622 */ 0,
6224 /* 623 */ 0,
6225 /* 624 */ 0,
6226 /* 625 */ 0,
6227 /* 626 */ 0,
6228 /* 627 */ 0,
6229 /* 628 */ 0,
6230 /* 629 */ _CastP2X_rRegP__rule,
6231 /* 630 */ _CastP2X__DecodeN_rRegN___rule,
6232 /* 631 */ rRegP_rule,
6233 /* 632 */ rRegP_rule,
6234 /* 633 */ rRegN_rule,
6235 /* 634 */ rRegN_rule,
6236 /* 635 */ rRegP_rule,
6237 /* 636 */ rRegN_rule,
6238 /* 637 */ _LShiftL_rRegL_immI2_rule,
6239 /* 638 */ _AddL__LShiftL_rRegL_immI2_immL32_rule,
6240 /* 639 */ rRegL_rule,
6241 /* 640 */ _Binary_cmpOp_rFlagsReg_rule,
6242 /* 641 */ _Binary_cmpOpU_rFlagsRegU_rule,
6243 /* 642 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6244 /* 643 */ _Binary_cmpOp_rFlagsReg_rule,
6245 /* 644 */ _Binary_cmpOpU_rFlagsRegU_rule,
6246 /* 645 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6247 /* 646 */ _Binary_cmpOp_rFlagsReg_rule,
6248 /* 647 */ _Binary_cmpOpU_rFlagsRegU_rule,
6249 /* 648 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6250 /* 649 */ _Binary_cmpOp_rFlagsReg_rule,
6251 /* 650 */ _Binary_cmpOpU_rFlagsRegU_rule,
6252 /* 651 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6253 /* 652 */ _Binary_cmpOp_rFlagsReg_rule,
6254 /* 653 */ _Binary_cmpOp_rFlagsReg_rule,
6255 /* 654 */ _Binary_cmpOpU_rFlagsRegU_rule,
6256 /* 655 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6257 /* 656 */ _Binary_cmpOpU_rFlagsRegU_rule,
6258 /* 657 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6259 /* 658 */ _Binary_cmpOp_rFlagsReg_rule,
6260 /* 659 */ _Binary_cmpOpU_rFlagsRegU_rule,
6261 /* 660 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6262 /* 661 */ _Binary_cmpOp_rFlagsReg_rule,
6263 /* 662 */ _Binary_cmpOpU_rFlagsRegU_rule,
6264 /* 663 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6265 /* 664 */ rRegI_rule,
6266 /* 665 */ rRegI_rule,
6267 /* 666 */ rRegI_rule,
6268 /* 667 */ _LoadI_memory__rule,
6269 /* 668 */ memory_rule,
6270 /* 669 */ memory_rule,
6271 /* 670 */ memory_rule,
6272 /* 671 */ rRegI_rule,
6273 /* 672 */ memory_rule,
6274 /* 673 */ rRegI_rule,
6275 /* 674 */ memory_rule,
6276 /* 675 */ rRegI_rule,
6277 /* 676 */ rRegL_rule,
6278 /* 677 */ rRegL_rule,
6279 /* 678 */ rRegL_rule,
6280 /* 679 */ _LoadL_memory__rule,
6281 /* 680 */ memory_rule,
6282 /* 681 */ memory_rule,
6283 /* 682 */ memory_rule,
6284 /* 683 */ rRegI_rule,
6285 /* 684 */ memory_rule,
6286 /* 685 */ rRegL_rule,
6287 /* 686 */ memory_rule,
6288 /* 687 */ rRegL_rule,
6289 /* 688 */ rRegP_rule,
6290 /* 689 */ rRegP_rule,
6291 /* 690 */ rRegP_rule,
6292 /* 691 */ memory_rule,
6293 /* 692 */ memory_rule,
6294 /* 693 */ memory_rule,
6295 /* 694 */ memory_rule,
6296 /* 695 */ memory_rule,
6297 /* 696 */ memory_rule,
6298 /* 697 */ memory_rule,
6299 /* 698 */ memory_rule,
6300 /* 699 */ memory_rule,
6301 /* 700 */ memory_rule,
6302 /* 701 */ memory_rule,
6303 /* 702 */ memory_rule,
6304 /* 703 */ memory_rule,
6305 /* 704 */ memory_rule,
6306 /* 705 */ memory_rule,
6307 /* 706 */ memory_rule,
6308 /* 707 */ memory_rule,
6309 /* 708 */ memory_rule,
6310 /* 709 */ memory_rule,
6311 /* 710 */ memory_rule,
6312 /* 711 */ memory_rule,
6313 /* 712 */ memory_rule,
6314 /* 713 */ memory_rule,
6315 /* 714 */ memory_rule,
6316 /* 715 */ memory_rule,
6317 /* 716 */ memory_rule,
6318 /* 717 */ memory_rule,
6319 /* 718 */ memory_rule,
6320 /* 719 */ memory_rule,
6321 /* 720 */ memory_rule,
6322 /* 721 */ memory_rule,
6323 /* 722 */ memory_rule,
6324 /* 723 */ memory_rule,
6325 /* 724 */ rRegI_rule,
6326 /* 725 */ rRegL_rule,
6327 /* 726 */ rRegI_rule,
6328 /* 727 */ rRegI_rule,
6329 /* 728 */ rRegI_rule,
6330 /* 729 */ memory_rule,
6331 /* 730 */ memory_rule,
6332 /* 731 */ rRegL_rule,
6333 /* 732 */ rRegI_rule,
6334 /* 733 */ rRegL_rule,
6335 /* 734 */ memory_rule,
6336 /* 735 */ memory_rule,
6337 /* 736 */ rRegP_rule,
6338 /* 737 */ immI0_rule,
6339 /* 738 */ memory_rule,
6340 /* 739 */ immL0_rule,
6341 /* 740 */ memory_rule,
6342 /* 741 */ rRegI_rule,
6343 /* 742 */ rRegI_rule,
6344 /* 743 */ rRegI_rule,
6345 /* 744 */ _LoadI_memory__rule,
6346 /* 745 */ _LoadI_memory__rule,
6347 /* 746 */ _Binary_rRegI_rRegI_rule,
6348 /* 747 */ rRegL_rule,
6349 /* 748 */ rRegL_rule,
6350 /* 749 */ rRegL_rule,
6351 /* 750 */ _LoadL_memory__rule,
6352 /* 751 */ _LoadL_memory__rule,
6353 /* 752 */ no_rax_RegL_rule,
6354 /* 753 */ rax_RegI_rule,
6355 /* 754 */ rax_RegL_rule,
6356 /* 755 */ rax_RegI_rule,
6357 /* 756 */ rax_RegL_rule,
6358 /* 757 */ 0,
6359 /* 758 */ 0,
6360 /* 759 */ 0,
6361 /* 760 */ 0,
6362 /* 761 */ no_rax_RegL_rule,
6363 /* 762 */ rax_RegI_rule,
6364 /* 763 */ rax_RegL_rule,
6365 /* 764 */ rRegI_rule,
6366 /* 765 */ memory_rule,
6367 /* 766 */ rRegI_rule,
6368 /* 767 */ memory_rule,
6369 /* 768 */ rRegI_rule,
6370 /* 769 */ memory_rule,
6371 /* 770 */ rRegI_rule,
6372 /* 771 */ memory_rule,
6373 /* 772 */ rRegI_rule,
6374 /* 773 */ memory_rule,
6375 /* 774 */ rRegI_rule,
6376 /* 775 */ memory_rule,
6377 /* 776 */ rRegI_rule,
6378 /* 777 */ memory_rule,
6379 /* 778 */ rRegI_rule,
6380 /* 779 */ memory_rule,
6381 /* 780 */ rRegI_rule,
6382 /* 781 */ memory_rule,
6383 /* 782 */ rRegL_rule,
6384 /* 783 */ memory_rule,
6385 /* 784 */ rRegL_rule,
6386 /* 785 */ memory_rule,
6387 /* 786 */ rRegL_rule,
6388 /* 787 */ memory_rule,
6389 /* 788 */ rRegL_rule,
6390 /* 789 */ memory_rule,
6391 /* 790 */ rRegL_rule,
6392 /* 791 */ memory_rule,
6393 /* 792 */ rRegL_rule,
6394 /* 793 */ memory_rule,
6395 /* 794 */ rRegL_rule,
6396 /* 795 */ memory_rule,
6397 /* 796 */ rRegL_rule,
6398 /* 797 */ memory_rule,
6399 /* 798 */ rRegL_rule,
6400 /* 799 */ memory_rule,
6401 /* 800 */ _LShiftI_rRegI_immI_24_rule,
6402 /* 801 */ _LShiftI_rRegI_immI_16_rule,
6403 /* 802 */ 0,
6404 /* 803 */ 0,
6405 /* 804 */ 0,
6406 /* 805 */ _LShiftI_rRegI_immI1_rule,
6407 /* 806 */ _URShiftI_rRegI_immI_M1_rule,
6408 /* 807 */ _LShiftI_rRegI_immI8_rule,
6409 /* 808 */ _URShiftI_rRegI_immI8_rule,
6410 /* 809 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule,
6411 /* 810 */ _URShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
6412 /* 811 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule,
6413 /* 812 */ _URShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
6414 /* 813 */ 0,
6415 /* 814 */ 0,
6416 /* 815 */ 0,
6417 /* 816 */ _URShiftI_rRegI_immI1_rule,
6418 /* 817 */ _LShiftI_rRegI_immI_M1_rule,
6419 /* 818 */ _URShiftI_rRegI_immI8_rule,
6420 /* 819 */ _LShiftI_rRegI_immI8_rule,
6421 /* 820 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule,
6422 /* 821 */ _LShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
6423 /* 822 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule,
6424 /* 823 */ _LShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
6425 /* 824 */ 0,
6426 /* 825 */ 0,
6427 /* 826 */ 0,
6428 /* 827 */ _LShiftL_rRegL_immI1_rule,
6429 /* 828 */ _URShiftL_rRegL_immI_M1_rule,
6430 /* 829 */ _LShiftL_rRegL_immI8_rule,
6431 /* 830 */ _URShiftL_rRegL_immI8_rule,
6432 /* 831 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule,
6433 /* 832 */ _URShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
6434 /* 833 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule,
6435 /* 834 */ _URShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
6436 /* 835 */ 0,
6437 /* 836 */ 0,
6438 /* 837 */ 0,
6439 /* 838 */ _URShiftL_rRegL_immI1_rule,
6440 /* 839 */ _LShiftL_rRegL_immI_M1_rule,
6441 /* 840 */ _URShiftL_rRegL_immI8_rule,
6442 /* 841 */ _LShiftL_rRegL_immI8_rule,
6443 /* 842 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule,
6444 /* 843 */ _LShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
6445 /* 844 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule,
6446 /* 845 */ _LShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
6447 /* 846 */ rRegI_rule,
6448 /* 847 */ rRegI_rule,
6449 /* 848 */ _AndI_rRegI_immI_255_rule,
6450 /* 849 */ rRegI_rule,
6451 /* 850 */ _AndI_rRegI_immI_65535_rule,
6452 /* 851 */ rRegI_rule,
6453 /* 852 */ rRegI_rule,
6454 /* 853 */ _LoadI_memory__rule,
6455 /* 854 */ memory_rule,
6456 /* 855 */ memory_rule,
6457 /* 856 */ memory_rule,
6458 /* 857 */ memory_rule,
6459 /* 858 */ memory_rule,
6460 /* 859 */ _XorI_rRegI_immI_M1_rule,
6461 /* 860 */ _LoadI_memory__rule,
6462 /* 861 */ _XorI_rRegI_immI_M1_rule,
6463 /* 862 */ rRegI_rule,
6464 /* 863 */ _SubI_immI0_rRegI_rule,
6465 /* 864 */ rRegI_rule,
6466 /* 865 */ _SubI_immI0__LoadI_memory__rule,
6467 /* 866 */ _LoadI_memory__rule,
6468 /* 867 */ _AddI__LoadI_memory__immI_M1_rule,
6469 /* 868 */ _LoadI_memory__rule,
6470 /* 869 */ _AddI_rRegI_immI_M1_rule,
6471 /* 870 */ rRegI_rule,
6472 /* 871 */ _AddI_rRegI_immI_M1_rule,
6473 /* 872 */ rRegI_rule,
6474 /* 873 */ _AddI__LoadI_memory__immI_M1_rule,
6475 /* 874 */ _LoadI_memory__rule,
6476 /* 875 */ rRegI_rule,
6477 /* 876 */ rRegI_rule,
6478 /* 877 */ rRegI_rule,
6479 /* 878 */ _LoadI_memory__rule,
6480 /* 879 */ memory_rule,
6481 /* 880 */ memory_rule,
6482 /* 881 */ memory_rule,
6483 /* 882 */ memory_rule,
6484 /* 883 */ memory_rule,
6485 /* 884 */ rRegI_rule,
6486 /* 885 */ rRegI_rule,
6487 /* 886 */ rRegI_rule,
6488 /* 887 */ rRegI_rule,
6489 /* 888 */ _LoadI_memory__rule,
6490 /* 889 */ memory_rule,
6491 /* 890 */ memory_rule,
6492 /* 891 */ memory_rule,
6493 /* 892 */ memory_rule,
6494 /* 893 */ memory_rule,
6495 /* 894 */ rRegL_rule,
6496 /* 895 */ rRegL_rule,
6497 /* 896 */ rRegL_rule,
6498 /* 897 */ rRegL_rule,
6499 /* 898 */ rRegL_rule,
6500 /* 899 */ _LoadL_memory__rule,
6501 /* 900 */ memory_rule,
6502 /* 901 */ memory_rule,
6503 /* 902 */ memory_rule,
6504 /* 903 */ _XorL_rRegL_immL_M1_rule,
6505 /* 904 */ _LoadL_memory__rule,
6506 /* 905 */ _XorL_rRegL_immL_M1_rule,
6507 /* 906 */ rRegL_rule,
6508 /* 907 */ _SubL_immL0_rRegL_rule,
6509 /* 908 */ rRegL_rule,
6510 /* 909 */ _SubL_immL0__LoadL_memory__rule,
6511 /* 910 */ _LoadL_memory__rule,
6512 /* 911 */ _AddL__LoadL_memory__immL_M1_rule,
6513 /* 912 */ _LoadL_memory__rule,
6514 /* 913 */ _AddL_rRegL_immL_M1_rule,
6515 /* 914 */ rRegL_rule,
6516 /* 915 */ _AddL_rRegL_immL_M1_rule,
6517 /* 916 */ rRegL_rule,
6518 /* 917 */ _AddL__LoadL_memory__immL_M1_rule,
6519 /* 918 */ _LoadL_memory__rule,
6520 /* 919 */ rRegL_rule,
6521 /* 920 */ rRegL_rule,
6522 /* 921 */ _CastP2X_any_RegP__rule,
6523 /* 922 */ rRegL_rule,
6524 /* 923 */ rRegL_rule,
6525 /* 924 */ _LoadL_memory__rule,
6526 /* 925 */ memory_rule,
6527 /* 926 */ memory_rule,
6528 /* 927 */ memory_rule,
6529 /* 928 */ rRegL_rule,
6530 /* 929 */ rRegL_rule,
6531 /* 930 */ rRegL_rule,
6532 /* 931 */ rRegL_rule,
6533 /* 932 */ _LoadL_memory__rule,
6534 /* 933 */ memory_rule,
6535 /* 934 */ memory_rule,
6536 /* 935 */ memory_rule,
6537 /* 936 */ rRegI_rule,
6538 /* 937 */ rRegP_rule,
6539 /* 938 */ rRegI_rule,
6540 /* 939 */ rRegI_rule,
6541 /* 940 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
6542 /* 941 */ _SubI_rRegI_rRegI_rule,
6543 /* 942 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
6544 /* 943 */ _SubI_rRegI_rRegI_rule,
6545 /* 944 */ _CmpLTMask_rRegI_rRegI_rule,
6546 /* 945 */ rRegI_rule,
6547 /* 946 */ regF_rule,
6548 /* 947 */ regF_rule,
6549 /* 948 */ regF_rule,
6550 /* 949 */ regD_rule,
6551 /* 950 */ regD_rule,
6552 /* 951 */ regD_rule,
6553 /* 952 */ regF_rule,
6554 /* 953 */ _LoadF_memory__rule,
6555 /* 954 */ regD_rule,
6556 /* 955 */ _LoadD_memory__rule,
6557 /* 956 */ regF_rule,
6558 /* 957 */ regF_rule,
6559 /* 958 */ regD_rule,
6560 /* 959 */ regD_rule,
6561 /* 960 */ rRegI_rule,
6562 /* 961 */ _LoadI_memory__rule,
6563 /* 962 */ rRegI_rule,
6564 /* 963 */ _LoadI_memory__rule,
6565 /* 964 */ rRegI_rule,
6566 /* 965 */ rRegI_rule,
6567 /* 966 */ rRegL_rule,
6568 /* 967 */ _LoadL_memory__rule,
6569 /* 968 */ rRegL_rule,
6570 /* 969 */ _LoadL_memory__rule,
6571 /* 970 */ rRegI_rule,
6572 /* 971 */ _ConvI2L_rRegI__rule,
6573 /* 972 */ _ConvI2L__LoadI_memory___rule,
6574 /* 973 */ rRegL_rule,
6575 /* 974 */ rRegL_rule,
6576 /* 975 */ regF_rule,
6577 /* 976 */ rRegI_rule,
6578 /* 977 */ regD_rule,
6579 /* 978 */ rRegL_rule,
6580 /* 979 */ rcx_RegL_rule,
6581 /* 980 */ rcx_RegL_rule,
6582 /* 981 */ _Binary_rdi_RegP_rcx_RegI_rule,
6583 /* 982 */ _Binary_rdi_RegP_rcx_RegI_rule,
6584 /* 983 */ _Binary_rdi_RegP_rcx_RegI_rule,
6585 /* 984 */ _Binary_rsi_RegP_rdx_RegI_rule,
6586 /* 985 */ _Binary_rdi_RegP_rdx_RegI_rule,
6587 /* 986 */ _Binary_rdi_RegP_rdx_RegI_rule,
6588 /* 987 */ _Binary_rdi_RegP_rdx_RegI_rule,
6589 /* 988 */ _Binary_rdi_RegP_rdx_RegI_rule,
6590 /* 989 */ _Binary_rdi_RegP_rdx_RegI_rule,
6591 /* 990 */ _Binary_rdi_RegP_rdx_RegI_rule,
6592 /* 991 */ _Binary_rdi_RegP_rdx_RegI_rule,
6593 /* 992 */ _Binary_rdi_RegP_rsi_RegP_rule,
6594 /* 993 */ rdi_RegP_rule,
6595 /* 994 */ rdi_RegP_rule,
6596 /* 995 */ rsi_RegP_rule,
6597 /* 996 */ rsi_RegP_rule,
6598 /* 997 */ rsi_RegP_rule,
6599 /* 998 */ rsi_RegP_rule,
6600 /* 999 */ rRegL_rule,
6601 /* 1000 */ 0,
6602 /* 1001 */ rRegI_rule,
6603 /* 1002 */ 0,
6604 /* 1003 */ rRegI_rule,
6605 /* 1004 */ 0,
6606 /* 1005 */ cmpOp_rule,
6607 /* 1006 */ cmpOp_rule,
6608 /* 1007 */ cmpOpU_rule,
6609 /* 1008 */ cmpOpUCF_rule,
6610 /* 1009 */ cmpOp_rule,
6611 /* 1010 */ cmpOpU_rule,
6612 /* 1011 */ cmpOpUCF_rule,
6613 /* 1012 */ cmpOpU_rule,
6614 /* 1013 */ cmpOpUCF_rule,
6615 /* 1014 */ cmpOpUCF2_rule,
6616 /* 1015 */ rsi_RegP_rule,
6617 /* 1016 */ 0,
6618 /* 1017 */ cmpOp_rule,
6619 /* 1018 */ cmpOp_rule,
6620 /* 1019 */ cmpOpU_rule,
6621 /* 1020 */ cmpOpUCF_rule,
6622 /* 1021 */ cmpOpU_rule,
6623 /* 1022 */ cmpOpUCF_rule,
6624 /* 1023 */ cmpOpUCF2_rule,
6625 /* 1024 */ rRegP_rule,
6626 /* 1025 */ rRegP_rule,
6627 /* 1026 */ 0,
6628 /* 1027 */ 0,
6629 /* 1028 */ 0,
6630 /* 1029 */ 0,
6631 /* 1030 */ 0,
6632 /* 1031 */ 0,
6633 /* 1032 */ no_rbp_RegP_rule,
6634 /* 1033 */ no_rbp_RegP_rule,
6635 /* 1034 */ 0,
6636 /* 1035 */ 0,
6637 /* 1036 */ 0,
6638 /* 1037 */ rRegI_rule,
6639 /* 1038 */ regF_rule,
6640 /* 1039 */ regF_rule,
6641 /* 1040 */ _LoadF_memory__rule,
6642 /* 1041 */ regF_rule,
6643 /* 1042 */ regF_rule,
6644 /* 1043 */ regF_rule,
6645 /* 1044 */ _LoadF_memory__rule,
6646 /* 1045 */ regF_rule,
6647 /* 1046 */ regD_rule,
6648 /* 1047 */ regD_rule,
6649 /* 1048 */ _LoadD_memory__rule,
6650 /* 1049 */ regD_rule,
6651 /* 1050 */ regD_rule,
6652 /* 1051 */ regD_rule,
6653 /* 1052 */ _LoadD_memory__rule,
6654 /* 1053 */ regD_rule,
6655 /* 1054 */ regF_rule,
6656 /* 1055 */ regF_rule,
6657 /* 1056 */ regF_rule,
6658 /* 1057 */ regF_rule,
6659 /* 1058 */ regF_rule,
6660 /* 1059 */ regF_rule,
6661 /* 1060 */ regD_rule,
6662 /* 1061 */ regD_rule,
6663 /* 1062 */ regD_rule,
6664 /* 1063 */ regD_rule,
6665 /* 1064 */ regD_rule,
6666 /* 1065 */ regD_rule,
6667 /* 1066 */ regF_rule,
6668 /* 1067 */ regF_rule,
6669 /* 1068 */ _LoadF_memory__rule,
6670 /* 1069 */ regF_rule,
6671 /* 1070 */ regF_rule,
6672 /* 1071 */ regF_rule,
6673 /* 1072 */ _LoadF_memory__rule,
6674 /* 1073 */ regF_rule,
6675 /* 1074 */ regD_rule,
6676 /* 1075 */ regD_rule,
6677 /* 1076 */ _LoadD_memory__rule,
6678 /* 1077 */ regD_rule,
6679 /* 1078 */ regD_rule,
6680 /* 1079 */ regD_rule,
6681 /* 1080 */ _LoadD_memory__rule,
6682 /* 1081 */ regD_rule,
6683 /* 1082 */ regF_rule,
6684 /* 1083 */ regF_rule,
6685 /* 1084 */ regF_rule,
6686 /* 1085 */ regF_rule,
6687 /* 1086 */ regF_rule,
6688 /* 1087 */ regF_rule,
6689 /* 1088 */ regD_rule,
6690 /* 1089 */ regD_rule,
6691 /* 1090 */ regD_rule,
6692 /* 1091 */ regD_rule,
6693 /* 1092 */ regD_rule,
6694 /* 1093 */ regD_rule,
6695 /* 1094 */ regF_rule,
6696 /* 1095 */ _LoadF_memory__rule,
6697 /* 1096 */ immF_rule,
6698 /* 1097 */ regD_rule,
6699 /* 1098 */ _LoadD_memory__rule,
6700 /* 1099 */ immD_rule,
6701 /* 1100 */ 0,
6702 /* 1101 */ regD_rule,
6703 /* 1102 */ regF_rule,
6704 /* 1103 */ memory_rule,
6705 /* 1104 */ memory_rule,
6706 /* 1105 */ memory_rule,
6707 /* 1106 */ memory_rule,
6708 /* 1107 */ memory_rule,
6709 /* 1108 */ memory_rule,
6710 /* 1109 */ memory_rule,
6711 /* 1110 */ memory_rule,
6712 /* 1111 */ memory_rule,
6713 /* 1112 */ memory_rule,
6714 /* 1113 */ memory_rule,
6715 /* 1114 */ memory_rule,
6716 /* 1115 */ rRegI_rule,
6717 /* 1116 */ rRegI_rule,
6718 /* 1117 */ rRegI_rule,
6719 /* 1118 */ immI_rule,
6720 /* 1119 */ immI_rule,
6721 /* 1120 */ immI_rule,
6722 /* 1121 */ rRegI_rule,
6723 /* 1122 */ _LoadS_memory__rule,
6724 /* 1123 */ rRegI_rule,
6725 /* 1124 */ _LoadS_memory__rule,
6726 /* 1125 */ immI_rule,
6727 /* 1126 */ rRegI_rule,
6728 /* 1127 */ _LoadS_memory__rule,
6729 /* 1128 */ immI_rule,
6730 /* 1129 */ rRegI_rule,
6731 /* 1130 */ _LoadS_memory__rule,
6732 /* 1131 */ immI_rule,
6733 /* 1132 */ rRegI_rule,
6734 /* 1133 */ _LoadI_memory__rule,
6735 /* 1134 */ rRegI_rule,
6736 /* 1135 */ _LoadI_memory__rule,
6737 /* 1136 */ rRegI_rule,
6738 /* 1137 */ _LoadI_memory__rule,
6739 /* 1138 */ immI_rule,
6740 /* 1139 */ immI_rule,
6741 /* 1140 */ immI_rule,
6742 /* 1141 */ _LoadL_memory__rule,
6743 /* 1142 */ rRegL_rule,
6744 /* 1143 */ rRegL_rule,
6745 /* 1144 */ immL_rule,
6746 /* 1145 */ immL_rule,
6747 /* 1146 */ _LoadL_memory__rule,
6748 /* 1147 */ _LoadL_memory__rule,
6749 /* 1148 */ _LoadF_memory__rule,
6750 /* 1149 */ _LoadF_memory__rule,
6751 /* 1150 */ vlRegF_rule,
6752 /* 1151 */ _LoadF_memory__rule,
6753 /* 1152 */ vlRegF_rule,
6754 /* 1153 */ _LoadF_memory__rule,
6755 /* 1154 */ immF0_rule,
6756 /* 1155 */ immF0_rule,
6757 /* 1156 */ immF0_rule,
6758 /* 1157 */ _LoadD_memory__rule,
6759 /* 1158 */ vlRegD_rule,
6760 /* 1159 */ _LoadD_memory__rule,
6761 /* 1160 */ vlRegD_rule,
6762 /* 1161 */ _LoadD_memory__rule,
6763 /* 1162 */ immD0_rule,
6764 /* 1163 */ immD0_rule,
6765 /* 1164 */ rRegI_rule,
6766 /* 1165 */ rRegI_rule,
6767 /* 1166 */ immI_rule,
6768 /* 1167 */ immI_rule,
6769 /* 1168 */ immI0_rule,
6770 /* 1169 */ immI0_rule,
6771 /* 1170 */ immI0_rule,
6772 /* 1171 */ immI0_rule,
6773 /* 1172 */ rRegI_rule,
6774 /* 1173 */ immI_rule,
6775 /* 1174 */ immI_rule,
6776 /* 1175 */ immI0_rule,
6777 /* 1176 */ immI0_rule,
6778 /* 1177 */ immI0_rule,
6779 /* 1178 */ immI0_rule,
6780 /* 1179 */ rRegI_rule,
6781 /* 1180 */ _LoadI_memory__rule,
6782 /* 1181 */ immI_rule,
6783 /* 1182 */ immI0_rule,
6784 /* 1183 */ immI0_rule,
6785 /* 1184 */ immI0_rule,
6786 /* 1185 */ rRegL_rule,
6787 /* 1186 */ immL_rule,
6788 /* 1187 */ immL0_rule,
6789 /* 1188 */ immL0_rule,
6790 /* 1189 */ vlRegF_rule,
6791 /* 1190 */ vlRegF_rule,
6792 /* 1191 */ vlRegD_rule,
6793 /* 1192 */ _LoadB_memory__rule,
6794 /* 1193 */ _LoadB_memory__rule,
6795 /* 1194 */ rRegI_rule,
6796 /* 1195 */ _LoadB_memory__rule,
6797 /* 1196 */ rRegI_rule,
6798 /* 1197 */ _LoadB_memory__rule,
6799 /* 1198 */ rRegI_rule,
6800 /* 1199 */ _LoadB_memory__rule,
6801 /* 1200 */ immI_rule,
6802 /* 1201 */ immI_rule,
6803 /* 1202 */ immI_rule,
6804 /* 1203 */ immI0_rule,
6805 /* 1204 */ rRegI_rule,
6806 /* 1205 */ _LoadS_memory__rule,
6807 /* 1206 */ rRegI_rule,
6808 /* 1207 */ _LoadS_memory__rule,
6809 /* 1208 */ rRegI_rule,
6810 /* 1209 */ _LoadS_memory__rule,
6811 /* 1210 */ rRegI_rule,
6812 /* 1211 */ _LoadS_memory__rule,
6813 /* 1212 */ immI_rule,
6814 /* 1213 */ immI_rule,
6815 /* 1214 */ immI_rule,
6816 /* 1215 */ immI0_rule,
6817 /* 1216 */ rRegI_rule,
6818 /* 1217 */ _LoadI_memory__rule,
6819 /* 1218 */ rRegI_rule,
6820 /* 1219 */ _LoadI_memory__rule,
6821 /* 1220 */ rRegI_rule,
6822 /* 1221 */ _LoadI_memory__rule,
6823 /* 1222 */ immI_rule,
6824 /* 1223 */ immI_rule,
6825 /* 1224 */ immI_rule,
6826 /* 1225 */ immI0_rule,
6827 /* 1226 */ rRegL_rule,
6828 /* 1227 */ rRegL_rule,
6829 /* 1228 */ immL_rule,
6830 /* 1229 */ immL_rule,
6831 /* 1230 */ _LoadL_memory__rule,
6832 /* 1231 */ _LoadL_memory__rule,
6833 /* 1232 */ _LoadL_memory__rule,
6834 /* 1233 */ immL0_rule,
6835 /* 1234 */ regF_rule,
6836 /* 1235 */ _LoadF_memory__rule,
6837 /* 1236 */ regF_rule,
6838 /* 1237 */ _LoadF_memory__rule,
6839 /* 1238 */ immF0_rule,
6840 /* 1239 */ immF0_rule,
6841 /* 1240 */ immF0_rule,
6842 /* 1241 */ immF0_rule,
6843 /* 1242 */ regD_rule,
6844 /* 1243 */ _LoadD_memory__rule,
6845 /* 1244 */ regD_rule,
6846 /* 1245 */ _LoadD_memory__rule,
6847 /* 1246 */ immD0_rule,
6848 /* 1247 */ immD0_rule,
6849 /* 1248 */ immD0_rule,
6850 /* 1249 */ rRegI_rule,
6851 /* 1250 */ rRegI_rule,
6852 /* 1251 */ rRegI_rule,
6853 /* 1252 */ rRegI_rule,
6854 /* 1253 */ rRegI_rule,
6855 /* 1254 */ rRegI_rule,
6856 /* 1255 */ rRegI_rule,
6857 /* 1256 */ rRegI_rule,
6858 /* 1257 */ rRegI_rule,
6859 /* 1258 */ rRegL_rule,
6860 /* 1259 */ rRegL_rule,
6861 /* 1260 */ rRegL_rule,
6862 /* 1261 */ regF_rule,
6863 /* 1262 */ regF_rule,
6864 /* 1263 */ regF_rule,
6865 /* 1264 */ regF_rule,
6866 /* 1265 */ regF_rule,
6867 /* 1266 */ regF_rule,
6868 /* 1267 */ regD_rule,
6869 /* 1268 */ regD_rule,
6870 /* 1269 */ regD_rule,
6871 /* 1270 */ regD_rule,
6872 /* 1271 */ rRegI_rule,
6873 /* 1272 */ rRegI_rule,
6874 /* 1273 */ rRegI_rule,
6875 /* 1274 */ rRegI_rule,
6876 /* 1275 */ rRegI_rule,
6877 /* 1276 */ rRegI_rule,
6878 /* 1277 */ rRegL_rule,
6879 /* 1278 */ rRegL_rule,
6880 /* 1279 */ rRegL_rule,
6881 /* 1280 */ regF_rule,
6882 /* 1281 */ regF_rule,
6883 /* 1282 */ regF_rule,
6884 /* 1283 */ regF_rule,
6885 /* 1284 */ regF_rule,
6886 /* 1285 */ regF_rule,
6887 /* 1286 */ regD_rule,
6888 /* 1287 */ regD_rule,
6889 /* 1288 */ regD_rule,
6890 /* 1289 */ regD_rule,
6891 /* 1290 */ vecS_rule,
6892 /* 1291 */ vecS_rule,
6893 /* 1292 */ vecS_rule,
6894 /* 1293 */ _LoadVector_memory__rule,
6895 /* 1294 */ vecD_rule,
6896 /* 1295 */ vecD_rule,
6897 /* 1296 */ vecD_rule,
6898 /* 1297 */ _LoadVector_memory__rule,
6899 /* 1298 */ vecX_rule,
6900 /* 1299 */ vecX_rule,
6901 /* 1300 */ vecX_rule,
6902 /* 1301 */ _LoadVector_memory__rule,
6903 /* 1302 */ vecY_rule,
6904 /* 1303 */ vecY_rule,
6905 /* 1304 */ _LoadVector_memory__rule,
6906 /* 1305 */ vecZ_rule,
6907 /* 1306 */ vecZ_rule,
6908 /* 1307 */ _LoadVector_memory__rule,
6909 /* 1308 */ vecS_rule,
6910 /* 1309 */ vecS_rule,
6911 /* 1310 */ vecS_rule,
6912 /* 1311 */ _LoadVector_memory__rule,
6913 /* 1312 */ vecD_rule,
6914 /* 1313 */ vecD_rule,
6915 /* 1314 */ vecD_rule,
6916 /* 1315 */ _LoadVector_memory__rule,
6917 /* 1316 */ vecX_rule,
6918 /* 1317 */ vecX_rule,
6919 /* 1318 */ vecX_rule,
6920 /* 1319 */ _LoadVector_memory__rule,
6921 /* 1320 */ vecY_rule,
6922 /* 1321 */ vecY_rule,
6923 /* 1322 */ _LoadVector_memory__rule,
6924 /* 1323 */ vecZ_rule,
6925 /* 1324 */ vecZ_rule,
6926 /* 1325 */ _LoadVector_memory__rule,
6927 /* 1326 */ vecD_rule,
6928 /* 1327 */ vecD_rule,
6929 /* 1328 */ vecD_rule,
6930 /* 1329 */ _LoadVector_memory__rule,
6931 /* 1330 */ vecX_rule,
6932 /* 1331 */ vecX_rule,
6933 /* 1332 */ vecX_rule,
6934 /* 1333 */ _LoadVector_memory__rule,
6935 /* 1334 */ vecY_rule,
6936 /* 1335 */ vecY_rule,
6937 /* 1336 */ _LoadVector_memory__rule,
6938 /* 1337 */ vecZ_rule,
6939 /* 1338 */ vecZ_rule,
6940 /* 1339 */ _LoadVector_memory__rule,
6941 /* 1340 */ vecX_rule,
6942 /* 1341 */ vecX_rule,
6943 /* 1342 */ vecX_rule,
6944 /* 1343 */ _LoadVector_memory__rule,
6945 /* 1344 */ vecY_rule,
6946 /* 1345 */ vecY_rule,
6947 /* 1346 */ _LoadVector_memory__rule,
6948 /* 1347 */ vecZ_rule,
6949 /* 1348 */ vecZ_rule,
6950 /* 1349 */ _LoadVector_memory__rule,
6951 /* 1350 */ vecD_rule,
6952 /* 1351 */ vecD_rule,
6953 /* 1352 */ vecD_rule,
6954 /* 1353 */ _LoadVector_memory__rule,
6955 /* 1354 */ vecX_rule,
6956 /* 1355 */ vecX_rule,
6957 /* 1356 */ vecX_rule,
6958 /* 1357 */ _LoadVector_memory__rule,
6959 /* 1358 */ vecY_rule,
6960 /* 1359 */ vecY_rule,
6961 /* 1360 */ _LoadVector_memory__rule,
6962 /* 1361 */ vecZ_rule,
6963 /* 1362 */ vecZ_rule,
6964 /* 1363 */ _LoadVector_memory__rule,
6965 /* 1364 */ vecX_rule,
6966 /* 1365 */ vecX_rule,
6967 /* 1366 */ vecX_rule,
6968 /* 1367 */ _LoadVector_memory__rule,
6969 /* 1368 */ vecY_rule,
6970 /* 1369 */ vecY_rule,
6971 /* 1370 */ _LoadVector_memory__rule,
6972 /* 1371 */ vecZ_rule,
6973 /* 1372 */ vecZ_rule,
6974 /* 1373 */ _LoadVector_memory__rule,
6975 /* 1374 */ vecS_rule,
6976 /* 1375 */ vecS_rule,
6977 /* 1376 */ vecS_rule,
6978 /* 1377 */ vecD_rule,
6979 /* 1378 */ vecD_rule,
6980 /* 1379 */ vecD_rule,
6981 /* 1380 */ vecX_rule,
6982 /* 1381 */ vecX_rule,
6983 /* 1382 */ vecX_rule,
6984 /* 1383 */ vecY_rule,
6985 /* 1384 */ vecY_rule,
6986 /* 1385 */ vecZ_rule,
6987 /* 1386 */ vecZ_rule,
6988 /* 1387 */ vecS_rule,
6989 /* 1388 */ vecS_rule,
6990 /* 1389 */ vecS_rule,
6991 /* 1390 */ vecD_rule,
6992 /* 1391 */ vecD_rule,
6993 /* 1392 */ vecD_rule,
6994 /* 1393 */ vecX_rule,
6995 /* 1394 */ vecX_rule,
6996 /* 1395 */ vecX_rule,
6997 /* 1396 */ vecY_rule,
6998 /* 1397 */ vecY_rule,
6999 /* 1398 */ vecZ_rule,
7000 /* 1399 */ vecZ_rule,
7001 /* 1400 */ vecD_rule,
7002 /* 1401 */ vecD_rule,
7003 /* 1402 */ vecD_rule,
7004 /* 1403 */ vecX_rule,
7005 /* 1404 */ vecX_rule,
7006 /* 1405 */ vecX_rule,
7007 /* 1406 */ vecY_rule,
7008 /* 1407 */ vecY_rule,
7009 /* 1408 */ vecZ_rule,
7010 /* 1409 */ vecZ_rule,
7011 /* 1410 */ vecX_rule,
7012 /* 1411 */ vecX_rule,
7013 /* 1412 */ vecX_rule,
7014 /* 1413 */ vecY_rule,
7015 /* 1414 */ vecY_rule,
7016 /* 1415 */ vecZ_rule,
7017 /* 1416 */ vecZ_rule,
7018 /* 1417 */ vecD_rule,
7019 /* 1418 */ vecD_rule,
7020 /* 1419 */ vecD_rule,
7021 /* 1420 */ vecX_rule,
7022 /* 1421 */ vecX_rule,
7023 /* 1422 */ vecX_rule,
7024 /* 1423 */ vecY_rule,
7025 /* 1424 */ vecY_rule,
7026 /* 1425 */ vecZ_rule,
7027 /* 1426 */ vecZ_rule,
7028 /* 1427 */ vecX_rule,
7029 /* 1428 */ vecX_rule,
7030 /* 1429 */ vecX_rule,
7031 /* 1430 */ vecY_rule,
7032 /* 1431 */ vecY_rule,
7033 /* 1432 */ vecZ_rule,
7034 /* 1433 */ vecZ_rule,
7035 /* 1434 */ vecS_rule,
7036 /* 1435 */ vecD_rule,
7037 /* 1436 */ vecX_rule,
7038 /* 1437 */ vecX_rule,
7039 /* 1438 */ vecY_rule,
7040 /* 1439 */ vecZ_rule,
7041 /* 1440 */ vecS_rule,
7042 /* 1441 */ vecS_rule,
7043 /* 1442 */ vecS_rule,
7044 /* 1443 */ _LoadVector_memory__rule,
7045 /* 1444 */ vecD_rule,
7046 /* 1445 */ vecD_rule,
7047 /* 1446 */ vecD_rule,
7048 /* 1447 */ _LoadVector_memory__rule,
7049 /* 1448 */ vecX_rule,
7050 /* 1449 */ vecX_rule,
7051 /* 1450 */ vecX_rule,
7052 /* 1451 */ _LoadVector_memory__rule,
7053 /* 1452 */ vecY_rule,
7054 /* 1453 */ vecY_rule,
7055 /* 1454 */ _LoadVector_memory__rule,
7056 /* 1455 */ vecZ_rule,
7057 /* 1456 */ vecZ_rule,
7058 /* 1457 */ _LoadVector_memory__rule,
7059 /* 1458 */ vecD_rule,
7060 /* 1459 */ vecD_rule,
7061 /* 1460 */ vecD_rule,
7062 /* 1461 */ _LoadVector_memory__rule,
7063 /* 1462 */ vecX_rule,
7064 /* 1463 */ vecX_rule,
7065 /* 1464 */ vecX_rule,
7066 /* 1465 */ _LoadVector_memory__rule,
7067 /* 1466 */ vecX_rule,
7068 /* 1467 */ vecX_rule,
7069 /* 1468 */ _LoadVector_memory__rule,
7070 /* 1469 */ vecY_rule,
7071 /* 1470 */ vecY_rule,
7072 /* 1471 */ _LoadVector_memory__rule,
7073 /* 1472 */ vecZ_rule,
7074 /* 1473 */ vecZ_rule,
7075 /* 1474 */ _LoadVector_memory__rule,
7076 /* 1475 */ vecY_rule,
7077 /* 1476 */ vecY_rule,
7078 /* 1477 */ _LoadVector_memory__rule,
7079 /* 1478 */ vecZ_rule,
7080 /* 1479 */ vecZ_rule,
7081 /* 1480 */ _LoadVector_memory__rule,
7082 /* 1481 */ vecD_rule,
7083 /* 1482 */ vecD_rule,
7084 /* 1483 */ vecD_rule,
7085 /* 1484 */ _LoadVector_memory__rule,
7086 /* 1485 */ vecX_rule,
7087 /* 1486 */ vecX_rule,
7088 /* 1487 */ vecX_rule,
7089 /* 1488 */ _LoadVector_memory__rule,
7090 /* 1489 */ vecY_rule,
7091 /* 1490 */ vecY_rule,
7092 /* 1491 */ _LoadVector_memory__rule,
7093 /* 1492 */ vecZ_rule,
7094 /* 1493 */ vecZ_rule,
7095 /* 1494 */ _LoadVector_memory__rule,
7096 /* 1495 */ vecX_rule,
7097 /* 1496 */ vecX_rule,
7098 /* 1497 */ vecX_rule,
7099 /* 1498 */ _LoadVector_memory__rule,
7100 /* 1499 */ vecY_rule,
7101 /* 1500 */ vecY_rule,
7102 /* 1501 */ _LoadVector_memory__rule,
7103 /* 1502 */ vecZ_rule,
7104 /* 1503 */ vecZ_rule,
7105 /* 1504 */ _LoadVector_memory__rule,
7106 /* 1505 */ _Binary_cmpOp_vcmppd_immI8_rule,
7107 /* 1506 */ _Binary_cmpOp_vcmppd_immI8_rule,
7108 /* 1507 */ vecD_rule,
7109 /* 1508 */ vecD_rule,
7110 /* 1509 */ vecD_rule,
7111 /* 1510 */ vecX_rule,
7112 /* 1511 */ vecX_rule,
7113 /* 1512 */ vecX_rule,
7114 /* 1513 */ vecY_rule,
7115 /* 1514 */ vecY_rule,
7116 /* 1515 */ vecZ_rule,
7117 /* 1516 */ vecZ_rule,
7118 /* 1517 */ vecX_rule,
7119 /* 1518 */ vecX_rule,
7120 /* 1519 */ vecX_rule,
7121 /* 1520 */ vecY_rule,
7122 /* 1521 */ vecY_rule,
7123 /* 1522 */ vecZ_rule,
7124 /* 1523 */ vecZ_rule,
7125 /* 1524 */ vecS_rule,
7126 /* 1525 */ vecS_rule,
7127 /* 1526 */ vecS_rule,
7128 /* 1527 */ vecD_rule,
7129 /* 1528 */ vecD_rule,
7130 /* 1529 */ vecD_rule,
7131 /* 1530 */ vecX_rule,
7132 /* 1531 */ vecX_rule,
7133 /* 1532 */ vecX_rule,
7134 /* 1533 */ vecX_rule,
7135 /* 1534 */ vecX_rule,
7136 /* 1535 */ vecX_rule,
7137 /* 1536 */ vecY_rule,
7138 /* 1537 */ vecY_rule,
7139 /* 1538 */ vecY_rule,
7140 /* 1539 */ vecZ_rule,
7141 /* 1540 */ vecZ_rule,
7142 /* 1541 */ vecZ_rule,
7143 /* 1542 */ vecS_rule,
7144 /* 1543 */ vecS_rule,
7145 /* 1544 */ vecS_rule,
7146 /* 1545 */ vecD_rule,
7147 /* 1546 */ vecD_rule,
7148 /* 1547 */ vecD_rule,
7149 /* 1548 */ vecX_rule,
7150 /* 1549 */ vecX_rule,
7151 /* 1550 */ vecX_rule,
7152 /* 1551 */ vecY_rule,
7153 /* 1552 */ vecY_rule,
7154 /* 1553 */ vecY_rule,
7155 /* 1554 */ vecZ_rule,
7156 /* 1555 */ vecZ_rule,
7157 /* 1556 */ vecZ_rule,
7158 /* 1557 */ vecD_rule,
7159 /* 1558 */ vecD_rule,
7160 /* 1559 */ vecD_rule,
7161 /* 1560 */ vecX_rule,
7162 /* 1561 */ vecX_rule,
7163 /* 1562 */ vecX_rule,
7164 /* 1563 */ vecY_rule,
7165 /* 1564 */ vecY_rule,
7166 /* 1565 */ vecY_rule,
7167 /* 1566 */ vecZ_rule,
7168 /* 1567 */ vecZ_rule,
7169 /* 1568 */ vecZ_rule,
7170 /* 1569 */ vecX_rule,
7171 /* 1570 */ vecX_rule,
7172 /* 1571 */ vecY_rule,
7173 /* 1572 */ vecY_rule,
7174 /* 1573 */ vecZ_rule,
7175 /* 1574 */ vecZ_rule,
7176 /* 1575 */ vecZ_rule,
7177 /* 1576 */ vecX_rule,
7178 /* 1577 */ vecX_rule,
7179 /* 1578 */ vecY_rule,
7180 /* 1579 */ vecY_rule,
7181 /* 1580 */ vecS_rule,
7182 /* 1581 */ vecS_rule,
7183 /* 1582 */ vecS_rule,
7184 /* 1583 */ _LoadVector_memory__rule,
7185 /* 1584 */ vecD_rule,
7186 /* 1585 */ vecD_rule,
7187 /* 1586 */ vecD_rule,
7188 /* 1587 */ _LoadVector_memory__rule,
7189 /* 1588 */ vecX_rule,
7190 /* 1589 */ vecX_rule,
7191 /* 1590 */ vecX_rule,
7192 /* 1591 */ _LoadVector_memory__rule,
7193 /* 1592 */ vecY_rule,
7194 /* 1593 */ vecY_rule,
7195 /* 1594 */ _LoadVector_memory__rule,
7196 /* 1595 */ vecZ_rule,
7197 /* 1596 */ vecZ_rule,
7198 /* 1597 */ _LoadVector_memory__rule,
7199 /* 1598 */ vecS_rule,
7200 /* 1599 */ vecS_rule,
7201 /* 1600 */ vecS_rule,
7202 /* 1601 */ _LoadVector_memory__rule,
7203 /* 1602 */ vecD_rule,
7204 /* 1603 */ vecD_rule,
7205 /* 1604 */ vecD_rule,
7206 /* 1605 */ _LoadVector_memory__rule,
7207 /* 1606 */ vecX_rule,
7208 /* 1607 */ vecX_rule,
7209 /* 1608 */ vecX_rule,
7210 /* 1609 */ _LoadVector_memory__rule,
7211 /* 1610 */ vecY_rule,
7212 /* 1611 */ vecY_rule,
7213 /* 1612 */ _LoadVector_memory__rule,
7214 /* 1613 */ vecZ_rule,
7215 /* 1614 */ vecZ_rule,
7216 /* 1615 */ _LoadVector_memory__rule,
7217 /* 1616 */ vecS_rule,
7218 /* 1617 */ vecS_rule,
7219 /* 1618 */ vecS_rule,
7220 /* 1619 */ _LoadVector_memory__rule,
7221 /* 1620 */ vecD_rule,
7222 /* 1621 */ vecD_rule,
7223 /* 1622 */ vecD_rule,
7224 /* 1623 */ _LoadVector_memory__rule,
7225 /* 1624 */ vecX_rule,
7226 /* 1625 */ vecX_rule,
7227 /* 1626 */ vecX_rule,
7228 /* 1627 */ _LoadVector_memory__rule,
7229 /* 1628 */ vecY_rule,
7230 /* 1629 */ vecY_rule,
7231 /* 1630 */ _LoadVector_memory__rule,
7232 /* 1631 */ vecZ_rule,
7233 /* 1632 */ vecZ_rule,
7234 /* 1633 */ _LoadVector_memory__rule,
7235 /* 1634 */ vecX_rule,
7236 /* 1635 */ vecX_rule,
7237 /* 1636 */ vecY_rule,
7238 /* 1637 */ vecY_rule,
7239 /* 1638 */ vecZ_rule,
7240 /* 1639 */ vecZ_rule,
7241 /* 1640 */ vecD_rule,
7242 /* 1641 */ vecD_rule,
7243 /* 1642 */ vecX_rule,
7244 /* 1643 */ vecX_rule,
7245 /* 1644 */ vecY_rule,
7246 /* 1645 */ vecY_rule,
7247 /* 1646 */ vecZ_rule,
7248 /* 1647 */ vecZ_rule,
7249 /* 1648 */ vecX_rule,
7250 /* 1649 */ vecX_rule,
7251 /* 1650 */ vecY_rule,
7252 /* 1651 */ vecY_rule,
7253 /* 1652 */ vecZ_rule,
7254 /* 1653 */ vecZ_rule,
7255 /* 1654 */ vecX_rule,
7256 /* 1655 */ vecX_rule,
7257 /* 1656 */ vecY_rule,
7258 /* 1657 */ vecY_rule,
7259 /* 1658 */ vecZ_rule,
7260 /* 1659 */ vecZ_rule,
7261 /* 1660 */ vecD_rule,
7262 /* 1661 */ vecD_rule,
7263 /* 1662 */ vecX_rule,
7264 /* 1663 */ vecX_rule,
7265 /* 1664 */ vecY_rule,
7266 /* 1665 */ vecZ_rule,
7267 /* 1666 */ _MulAddVS2VI_vecD_vecD_rule,
7268 /* 1667 */ vecD_rule,
7269 /* 1668 */ _MulAddVS2VI_vecX_vecX_rule,
7270 /* 1669 */ vecX_rule,
7271 /* 1670 */ _MulAddVS2VI_vecY_vecY_rule,
7272 /* 1671 */ vecY_rule,
7273 /* 1672 */ _MulAddVS2VI_vecZ_vecZ_rule,
7274 /* 1673 */ vecZ_rule,
7275 /* 1674 */ memory_rule,
7276 /* 1675 */ memory_rule,
7277 /* 1676 */ memory_rule,
7278 /* 1677 */ memory_rule,
7279 /* 1678 */ memory_rule,
7280 /* 1679 */ memory_rule,
7281 /* 1680 */ memory_rule,
7282 /* 1681 */ memory_rule,
7283 /* 1682 */ memory_rule,
7284 /* 1683 */ memory_rule,
7285 /* 1684 */ _Binary_memory_rRegP_rule,
7286 /* 1685 */ _Binary_memory_rRegP_rule,
7287 /* 1686 */ _Binary_memory_rRegP_rule,
7288 /* 1687 */ memory_rule,
7289 // last instruction
7290 0 // no trailing comma
7291};
7292
7293const int rightOp[] = {
7294 /* 0 */ 0,
7295 /* 1 */ 0,
7296 /* 2 */ 0,
7297 /* 3 */ 0,
7298 /* 4 */ 0,
7299 /* 5 */ 0,
7300 /* 6 */ 0,
7301 /* 7 */ 0,
7302 /* 8 */ 0,
7303 /* 9 */ 0,
7304 /* 10 */ 0,
7305 /* 11 */ 0,
7306 /* 12 */ 0,
7307 /* 13 */ 0,
7308 /* 14 */ 0,
7309 /* 15 */ 0,
7310 /* 16 */ 0,
7311 /* 17 */ 0,
7312 /* 18 */ 0,
7313 /* 19 */ 0,
7314 /* 20 */ 0,
7315 /* 21 */ 0,
7316 /* 22 */ 0,
7317 /* 23 */ 0,
7318 /* 24 */ 0,
7319 /* 25 */ 0,
7320 /* 26 */ 0,
7321 /* 27 */ 0,
7322 /* 28 */ 0,
7323 /* 29 */ 0,
7324 /* 30 */ 0,
7325 /* 31 */ 0,
7326 /* 32 */ 0,
7327 /* 33 */ 0,
7328 /* 34 */ 0,
7329 /* 35 */ 0,
7330 /* 36 */ 0,
7331 /* 37 */ 0,
7332 /* 38 */ 0,
7333 /* 39 */ 0,
7334 /* 40 */ 0,
7335 /* 41 */ 0,
7336 /* 42 */ 0,
7337 /* 43 */ 0,
7338 /* 44 */ 0,
7339 /* 45 */ 0,
7340 /* 46 */ 0,
7341 /* 47 */ 0,
7342 /* 48 */ 0,
7343 /* 49 */ 0,
7344 /* 50 */ 0,
7345 /* 51 */ 0,
7346 /* 52 */ 0,
7347 /* 53 */ 0,
7348 /* 54 */ 0,
7349 /* 55 */ 0,
7350 /* 56 */ 0,
7351 /* 57 */ 0,
7352 /* 58 */ 0,
7353 /* 59 */ 0,
7354 /* 60 */ 0,
7355 /* 61 */ 0,
7356 /* 62 */ 0,
7357 /* 63 */ 0,
7358 /* 64 */ 0,
7359 /* 65 */ 0,
7360 /* 66 */ 0,
7361 /* 67 */ 0,
7362 /* 68 */ 0,
7363 /* 69 */ 0,
7364 /* 70 */ 0,
7365 /* 71 */ 0,
7366 /* 72 */ 0,
7367 /* 73 */ 0,
7368 /* 74 */ 0,
7369 /* 75 */ 0,
7370 /* 76 */ 0,
7371 /* 77 */ 0,
7372 /* 78 */ 0,
7373 /* 79 */ 0,
7374 /* 80 */ 0,
7375 /* 81 */ 0,
7376 /* 82 */ 0,
7377 /* 83 */ 0,
7378 /* 84 */ 0,
7379 /* 85 */ 0,
7380 /* 86 */ 0,
7381 /* 87 */ 0,
7382 /* 88 */ 0,
7383 /* 89 */ 0,
7384 /* 90 */ immL8_rule,
7385 /* 91 */ immL32_rule,
7386 /* 92 */ immL32_rule,
7387 /* 93 */ rRegL_rule,
7388 /* 94 */ _LShiftL_rRegL_immI2_rule,
7389 /* 95 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7390 /* 96 */ immL32_rule,
7391 /* 97 */ immL32_rule,
7392 /* 98 */ immL32_rule,
7393 /* 99 */ immL32_rule,
7394 /* 100 */ 0,
7395 /* 101 */ immL8_rule,
7396 /* 102 */ immL32_rule,
7397 /* 103 */ immL32_rule,
7398 /* 104 */ rRegL_rule,
7399 /* 105 */ _LShiftL_rRegL_immI2_rule,
7400 /* 106 */ immL32_rule,
7401 /* 107 */ immL32_rule,
7402 /* 108 */ immL32_rule,
7403 /* 109 */ 0,
7404 /* 110 */ 0,
7405 /* 111 */ 0,
7406 /* 112 */ 0,
7407 /* 113 */ 0,
7408 /* 114 */ 0,
7409 /* 115 */ 0,
7410 /* 116 */ 0,
7411 /* 117 */ 0,
7412 /* 118 */ 0,
7413 /* 119 */ 0,
7414 /* 120 */ 0,
7415 /* 121 */ 0,
7416 /* 122 */ 0,
7417 /* 123 */ 0,
7418 /* 124 */ 0,
7419 /* 125 */ 0,
7420 /* 126 */ 0,
7421 /* 127 */ 0,
7422 /* 128 */ 0,
7423 /* 129 */ 0,
7424 /* 130 */ 0,
7425 /* 131 */ 0,
7426 /* 132 */ 0,
7427 /* 133 */ 0,
7428 /* 134 */ 0,
7429 /* 135 */ 0,
7430 /* 136 */ 0,
7431 /* 137 */ 0,
7432 /* 138 */ 0,
7433 /* 139 */ 0,
7434 /* 140 */ 0,
7435 /* 141 */ 0,
7436 /* 142 */ 0,
7437 /* 143 */ 0,
7438 /* 144 */ 0,
7439 /* 145 */ 0,
7440 /* 146 */ 0,
7441 /* 147 */ 0,
7442 /* 148 */ 0,
7443 /* 149 */ 0,
7444 /* 150 */ 0,
7445 /* 151 */ 0,
7446 /* 152 */ 0,
7447 // last operand
7448 /* 153 */ 0,
7449 // last operand class
7450 /* 154 */ rRegL_rule,
7451 /* 155 */ immI2_rule,
7452 /* 156 */ 0,
7453 /* 157 */ immI2_rule,
7454 /* 158 */ _LShiftL_rRegL_immI2_rule,
7455 /* 159 */ _ConvI2L_rRegI__rule,
7456 /* 160 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7457 /* 161 */ 0,
7458 /* 162 */ rRegL_rule,
7459 /* 163 */ _LShiftL_rRegL_immI2_rule,
7460 /* 164 */ _ConvI2L_rRegI__rule,
7461 /* 165 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7462 /* 166 */ 0,
7463 /* 167 */ 0,
7464 /* 168 */ immI_rule,
7465 /* 169 */ 0,
7466 /* 170 */ immI_24_rule,
7467 /* 171 */ 0,
7468 /* 172 */ immI_24_rule,
7469 /* 173 */ immI_255_rule,
7470 /* 174 */ immI_rule,
7471 /* 175 */ 0,
7472 /* 176 */ immI_24_rule,
7473 /* 177 */ immI_16_rule,
7474 /* 178 */ immI_255_rule,
7475 /* 179 */ immI_65535_rule,
7476 /* 180 */ immU31_rule,
7477 /* 181 */ 0,
7478 /* 182 */ 0,
7479 /* 183 */ 0,
7480 /* 184 */ 0,
7481 /* 185 */ immL32_rule,
7482 /* 186 */ rFlagsReg_rule,
7483 /* 187 */ rRegI_rule,
7484 /* 188 */ rFlagsRegU_rule,
7485 /* 189 */ rFlagsRegUCF_rule,
7486 /* 190 */ _LoadI_memory__rule,
7487 /* 191 */ rRegN_rule,
7488 /* 192 */ rRegP_rule,
7489 /* 193 */ rRegL_rule,
7490 /* 194 */ _LoadL_memory__rule,
7491 /* 195 */ regF_rule,
7492 /* 196 */ regD_rule,
7493 /* 197 */ rRegI_rule,
7494 /* 198 */ _LoadI_memory__rule,
7495 /* 199 */ immI_rule,
7496 /* 200 */ immI1_rule,
7497 /* 201 */ immI_M1_rule,
7498 /* 202 */ rRegL_rule,
7499 /* 203 */ _LoadL_memory__rule,
7500 /* 204 */ immL32_rule,
7501 /* 205 */ immL1_rule,
7502 /* 206 */ immL_M1_rule,
7503 /* 207 */ rRegP_rule,
7504 /* 208 */ rRegI_rule,
7505 /* 209 */ rRegL_rule,
7506 /* 210 */ rRegN_rule,
7507 /* 211 */ rRegI_rule,
7508 /* 212 */ immI_rule,
7509 /* 213 */ rRegL_rule,
7510 /* 214 */ immL32_rule,
7511 /* 215 */ rRegI_rule,
7512 /* 216 */ _LoadI_memory__rule,
7513 /* 217 */ _LoadL_memory__rule,
7514 /* 218 */ immI1_rule,
7515 /* 219 */ immI8_rule,
7516 /* 220 */ rcx_RegI_rule,
7517 /* 221 */ immI1_rule,
7518 /* 222 */ immI8_rule,
7519 /* 223 */ rcx_RegI_rule,
7520 /* 224 */ immI1_rule,
7521 /* 225 */ immI8_rule,
7522 /* 226 */ rcx_RegI_rule,
7523 /* 227 */ immI1_rule,
7524 /* 228 */ immI8_rule,
7525 /* 229 */ rcx_RegI_rule,
7526 /* 230 */ immI1_rule,
7527 /* 231 */ immI8_rule,
7528 /* 232 */ rcx_RegI_rule,
7529 /* 233 */ immI1_rule,
7530 /* 234 */ immI8_rule,
7531 /* 235 */ rcx_RegI_rule,
7532 /* 236 */ immI_24_rule,
7533 /* 237 */ immI_16_rule,
7534 /* 238 */ immI1_rule,
7535 /* 239 */ immI_M1_rule,
7536 /* 240 */ immI8_rule,
7537 /* 241 */ immI8_rule,
7538 /* 242 */ rcx_RegI_rule,
7539 /* 243 */ rcx_RegI_rule,
7540 /* 244 */ _SubI_immI0_rcx_RegI_rule,
7541 /* 245 */ rcx_RegI_rule,
7542 /* 246 */ _SubI_immI_32_rcx_RegI_rule,
7543 /* 247 */ immI1_rule,
7544 /* 248 */ immI_M1_rule,
7545 /* 249 */ rcx_RegI_rule,
7546 /* 250 */ _SubI_immI0_rcx_RegI_rule,
7547 /* 251 */ _SubI_immI_32_rcx_RegI_rule,
7548 /* 252 */ immI1_rule,
7549 /* 253 */ immI_M1_rule,
7550 /* 254 */ immI8_rule,
7551 /* 255 */ immI8_rule,
7552 /* 256 */ rcx_RegI_rule,
7553 /* 257 */ _SubI_immI0_rcx_RegI_rule,
7554 /* 258 */ rcx_RegI_rule,
7555 /* 259 */ _SubI_immI_64_rcx_RegI_rule,
7556 /* 260 */ immI1_rule,
7557 /* 261 */ immI_M1_rule,
7558 /* 262 */ rcx_RegI_rule,
7559 /* 263 */ _SubI_immI0_rcx_RegI_rule,
7560 /* 264 */ _SubI_immI_64_rcx_RegI_rule,
7561 /* 265 */ immI_255_rule,
7562 /* 266 */ immI_65535_rule,
7563 /* 267 */ rRegI_rule,
7564 /* 268 */ _LoadB_memory__rule,
7565 /* 269 */ rRegI_rule,
7566 /* 270 */ _LoadI_memory__rule,
7567 /* 271 */ immI_rule,
7568 /* 272 */ immI_M1_rule,
7569 /* 273 */ immI_M1_rule,
7570 /* 274 */ rRegI_rule,
7571 /* 275 */ _LoadB_memory__rule,
7572 /* 276 */ rRegI_rule,
7573 /* 277 */ _LoadI_memory__rule,
7574 /* 278 */ immI_rule,
7575 /* 279 */ rRegI_rule,
7576 /* 280 */ _LoadB_memory__rule,
7577 /* 281 */ rRegI_rule,
7578 /* 282 */ _LoadI_memory__rule,
7579 /* 283 */ immI_rule,
7580 /* 284 */ rRegL_rule,
7581 /* 285 */ _LoadL_memory__rule,
7582 /* 286 */ immL32_rule,
7583 /* 287 */ immL_M1_rule,
7584 /* 288 */ rRegL_rule,
7585 /* 289 */ immL_M1_rule,
7586 /* 290 */ 0,
7587 /* 291 */ rRegL_rule,
7588 /* 292 */ _LoadL_memory__rule,
7589 /* 293 */ immL32_rule,
7590 /* 294 */ rRegL_rule,
7591 /* 295 */ _LoadL_memory__rule,
7592 /* 296 */ immL32_rule,
7593 /* 297 */ rRegI_rule,
7594 /* 298 */ rRegI_rule,
7595 /* 299 */ rRegI_rule,
7596 /* 300 */ _CmpLTMask_rRegI_rRegI_rule,
7597 /* 301 */ 0,
7598 /* 302 */ 0,
7599 /* 303 */ rcx_RegI_rule,
7600 /* 304 */ rdx_RegI_rule,
7601 /* 305 */ rdx_RegI_rule,
7602 /* 306 */ immI_rule,
7603 /* 307 */ rax_RegI_rule,
7604 /* 308 */ rsi_RegP_rule,
7605 /* 309 */ immI_rule,
7606 /* 310 */ 0,
7607 /* 311 */ 0,
7608 /* 312 */ 0,
7609 /* 313 */ immL32_rule,
7610 /* 314 */ _LoadL_memory__rule,
7611 /* 315 */ _CastP2X_rRegP__rule,
7612 /* 316 */ immU8_rule,
7613 /* 317 */ immI8_rule,
7614 /* 318 */ rax_RegP_rule,
7615 /* 319 */ 0,
7616 /* 320 */ immI8_rule,
7617 /* 321 */ legVecY_rule,
7618 /* 322 */ vecX_rule,
7619 /* 323 */ _LoadVector_memory__rule,
7620 /* 324 */ vecY_rule,
7621 /* 325 */ _LoadVector_memory__rule,
7622 /* 326 */ vecZ_rule,
7623 /* 327 */ _LoadVector_memory__rule,
7624 /* 328 */ vecD_rule,
7625 /* 329 */ vecX_rule,
7626 /* 330 */ vecY_rule,
7627 /* 331 */ vecZ_rule,
7628 /* 332 */ rRegP_rule,
7629 // last internally defined operand
7630 /* 333 */ 0,
7631 /* 334 */ 0,
7632 /* 335 */ 0,
7633 /* 336 */ 0,
7634 /* 337 */ 0,
7635 /* 338 */ 0,
7636 /* 339 */ 0,
7637 /* 340 */ 0,
7638 /* 341 */ 0,
7639 /* 342 */ 0,
7640 /* 343 */ 0,
7641 /* 344 */ 0,
7642 /* 345 */ 0,
7643 /* 346 */ 0,
7644 /* 347 */ 0,
7645 /* 348 */ 0,
7646 /* 349 */ 0,
7647 /* 350 */ 0,
7648 /* 351 */ 0,
7649 /* 352 */ 0,
7650 /* 353 */ 0,
7651 /* 354 */ 0,
7652 /* 355 */ 0,
7653 /* 356 */ 0,
7654 /* 357 */ 0,
7655 /* 358 */ 0,
7656 /* 359 */ 0,
7657 /* 360 */ 0,
7658 /* 361 */ 0,
7659 /* 362 */ 0,
7660 /* 363 */ 0,
7661 /* 364 */ 0,
7662 /* 365 */ 0,
7663 /* 366 */ 0,
7664 /* 367 */ 0,
7665 /* 368 */ 0,
7666 /* 369 */ 0,
7667 /* 370 */ 0,
7668 /* 371 */ 0,
7669 /* 372 */ 0,
7670 /* 373 */ 0,
7671 /* 374 */ 0,
7672 /* 375 */ 0,
7673 /* 376 */ 0,
7674 /* 377 */ 0,
7675 /* 378 */ 0,
7676 /* 379 */ 0,
7677 /* 380 */ 0,
7678 /* 381 */ 0,
7679 /* 382 */ 0,
7680 /* 383 */ 0,
7681 /* 384 */ 0,
7682 /* 385 */ 0,
7683 /* 386 */ 0,
7684 /* 387 */ 0,
7685 /* 388 */ 0,
7686 /* 389 */ 0,
7687 /* 390 */ 0,
7688 /* 391 */ 0,
7689 /* 392 */ 0,
7690 /* 393 */ 0,
7691 /* 394 */ 0,
7692 /* 395 */ 0,
7693 /* 396 */ 0,
7694 /* 397 */ 0,
7695 /* 398 */ 0,
7696 /* 399 */ 0,
7697 /* 400 */ _Binary_rax_RegP_rRegP_rule,
7698 /* 401 */ _Binary_rax_RegI_rRegI_rule,
7699 /* 402 */ _Binary_rax_RegL_rRegL_rule,
7700 /* 403 */ regF_rule,
7701 /* 404 */ regF_rule,
7702 /* 405 */ _LoadF_memory__rule,
7703 /* 406 */ _LoadF_memory__rule,
7704 /* 407 */ immF_rule,
7705 /* 408 */ immF_rule,
7706 /* 409 */ regD_rule,
7707 /* 410 */ regD_rule,
7708 /* 411 */ _LoadD_memory__rule,
7709 /* 412 */ _LoadD_memory__rule,
7710 /* 413 */ immD_rule,
7711 /* 414 */ immD_rule,
7712 /* 415 */ 0,
7713 /* 416 */ 0,
7714 /* 417 */ 0,
7715 /* 418 */ 0,
7716 /* 419 */ 0,
7717 /* 420 */ 0,
7718 /* 421 */ 0,
7719 /* 422 */ 0,
7720 /* 423 */ 0,
7721 /* 424 */ 0,
7722 /* 425 */ 0,
7723 /* 426 */ rRegI_rule,
7724 /* 427 */ immI_rule,
7725 /* 428 */ rRegL_rule,
7726 /* 429 */ immL32_rule,
7727 /* 430 */ rRegI_rule,
7728 /* 431 */ immI_rule,
7729 /* 432 */ rRegL_rule,
7730 /* 433 */ immL32_rule,
7731 /* 434 */ rax_RegI_rule,
7732 /* 435 */ rax_RegL_rule,
7733 /* 436 */ rRegI_rule,
7734 /* 437 */ immI_rule,
7735 /* 438 */ rRegL_rule,
7736 /* 439 */ immL32_rule,
7737 /* 440 */ rRegI_rule,
7738 /* 441 */ immI_rule,
7739 /* 442 */ _LoadI_memory__rule,
7740 /* 443 */ immI0_rule,
7741 /* 444 */ immI0_rule,
7742 /* 445 */ immI0_rule,
7743 /* 446 */ immI0_rule,
7744 /* 447 */ rRegI_rule,
7745 /* 448 */ immI_rule,
7746 /* 449 */ _LoadI_memory__rule,
7747 /* 450 */ immI0_rule,
7748 /* 451 */ rRegP_rule,
7749 /* 452 */ _LoadP_memory__rule,
7750 /* 453 */ _LoadP_memory__rule,
7751 /* 454 */ immP0_rule,
7752 /* 455 */ immP0_rule,
7753 /* 456 */ immP0_rule,
7754 /* 457 */ rRegN_rule,
7755 /* 458 */ _LoadN_memory__rule,
7756 /* 459 */ immN_rule,
7757 /* 460 */ _LoadN_memory__rule,
7758 /* 461 */ immNKlass_rule,
7759 /* 462 */ _LoadNKlass_memory__rule,
7760 /* 463 */ immN0_rule,
7761 /* 464 */ immN0_rule,
7762 /* 465 */ immN0_rule,
7763 /* 466 */ rRegL_rule,
7764 /* 467 */ immL32_rule,
7765 /* 468 */ _LoadL_memory__rule,
7766 /* 469 */ immL0_rule,
7767 /* 470 */ immL0_rule,
7768 /* 471 */ immL0_rule,
7769 /* 472 */ immL0_rule,
7770 /* 473 */ immL0_rule,
7771 /* 474 */ immL0_rule,
7772 /* 475 */ rRegL_rule,
7773 /* 476 */ immL32_rule,
7774 /* 477 */ _LoadL_memory__rule,
7775 /* 478 */ immL0_rule,
7776 /* 479 */ immI8_rule,
7777 /* 480 */ immI0_rule,
7778 /* 481 */ immI0_rule,
7779 /* 482 */ immP0_rule,
7780 /* 483 */ rbx_RegP_rule,
7781 /* 484 */ rbx_RegP_rule,
7782 /* 485 */ rax_RegP_rule,
7783 /* 486 */ 0,
7784 /* 487 */ 0,
7785 /* 488 */ 0,
7786 /* 489 */ 0,
7787 /* 490 */ 0,
7788 /* 491 */ 0,
7789 /* 492 */ 0,
7790 /* 493 */ 0,
7791 /* 494 */ 0,
7792 /* 495 */ 0,
7793 /* 496 */ 0,
7794 /* 497 */ 0,
7795 /* 498 */ 0,
7796 /* 499 */ 0,
7797 /* 500 */ 0,
7798 /* 501 */ 0,
7799 /* 502 */ 0,
7800 /* 503 */ 0,
7801 /* 504 */ 0,
7802 /* 505 */ 0,
7803 /* 506 */ 0,
7804 /* 507 */ 0,
7805 /* 508 */ 0,
7806 /* 509 */ 0,
7807 /* 510 */ 0,
7808 /* 511 */ 0,
7809 /* 512 */ 0,
7810 /* 513 */ 0,
7811 /* 514 */ 0,
7812 /* 515 */ 0,
7813 /* 516 */ 0,
7814 /* 517 */ 0,
7815 /* 518 */ 0,
7816 /* 519 */ 0,
7817 /* 520 */ 0,
7818 /* 521 */ 0,
7819 /* 522 */ 0,
7820 /* 523 */ 0,
7821 /* 524 */ 0,
7822 /* 525 */ 0,
7823 /* 526 */ 0,
7824 /* 527 */ 0,
7825 /* 528 */ 0,
7826 /* 529 */ 0,
7827 /* 530 */ 0,
7828 /* 531 */ 0,
7829 /* 532 */ 0,
7830 /* 533 */ 0,
7831 /* 534 */ 0,
7832 /* 535 */ 0,
7833 /* 536 */ 0,
7834 /* 537 */ 0,
7835 /* 538 */ 0,
7836 /* 539 */ immI_24_rule,
7837 /* 540 */ 0,
7838 /* 541 */ 0,
7839 /* 542 */ immI_24_rule,
7840 /* 543 */ 0,
7841 /* 544 */ 0,
7842 /* 545 */ 0,
7843 /* 546 */ 0,
7844 /* 547 */ immI_24_rule,
7845 /* 548 */ immI_255_rule,
7846 /* 549 */ immI_16_rule,
7847 /* 550 */ immI_65535_rule,
7848 /* 551 */ 0,
7849 /* 552 */ 0,
7850 /* 553 */ 0,
7851 /* 554 */ 0,
7852 /* 555 */ immL_32bits_rule,
7853 /* 556 */ 0,
7854 /* 557 */ 0,
7855 /* 558 */ 0,
7856 /* 559 */ 0,
7857 /* 560 */ 0,
7858 /* 561 */ 0,
7859 /* 562 */ 0,
7860 /* 563 */ 0,
7861 /* 564 */ 0,
7862 /* 565 */ legRegF_rule,
7863 /* 566 */ legRegF_rule,
7864 /* 567 */ legRegD_rule,
7865 /* 568 */ legRegD_rule,
7866 /* 569 */ legRegF_rule,
7867 /* 570 */ legRegF_rule,
7868 /* 571 */ legRegD_rule,
7869 /* 572 */ legRegD_rule,
7870 /* 573 */ 0,
7871 /* 574 */ 0,
7872 /* 575 */ 0,
7873 /* 576 */ 0,
7874 /* 577 */ rRegI_rule,
7875 /* 578 */ rRegI_rule,
7876 /* 579 */ rRegI_rule,
7877 /* 580 */ rRegL_rule,
7878 /* 581 */ any_RegP_rule,
7879 /* 582 */ immP0_rule,
7880 /* 583 */ immP31_rule,
7881 /* 584 */ rRegN_rule,
7882 /* 585 */ rRegN_rule,
7883 /* 586 */ immN0_rule,
7884 /* 587 */ immN_rule,
7885 /* 588 */ immNKlass_rule,
7886 /* 589 */ immI0_rule,
7887 /* 590 */ immI_rule,
7888 /* 591 */ immL0_rule,
7889 /* 592 */ immL32_rule,
7890 /* 593 */ immI0_rule,
7891 /* 594 */ immI16_rule,
7892 /* 595 */ immI0_rule,
7893 /* 596 */ immI8_rule,
7894 /* 597 */ immI0_rule,
7895 /* 598 */ immI0_rule,
7896 /* 599 */ regF_rule,
7897 /* 600 */ immF0_rule,
7898 /* 601 */ immF_rule,
7899 /* 602 */ regD_rule,
7900 /* 603 */ immD0_rule,
7901 /* 604 */ immD0_rule,
7902 /* 605 */ 0,
7903 /* 606 */ 0,
7904 /* 607 */ 0,
7905 /* 608 */ 0,
7906 /* 609 */ 0,
7907 /* 610 */ 0,
7908 /* 611 */ 0,
7909 /* 612 */ 0,
7910 /* 613 */ 0,
7911 /* 614 */ 0,
7912 /* 615 */ 0,
7913 /* 616 */ 0,
7914 /* 617 */ 0,
7915 /* 618 */ 0,
7916 /* 619 */ 0,
7917 /* 620 */ 0,
7918 /* 621 */ 0,
7919 /* 622 */ 0,
7920 /* 623 */ 0,
7921 /* 624 */ 0,
7922 /* 625 */ 0,
7923 /* 626 */ 0,
7924 /* 627 */ 0,
7925 /* 628 */ 0,
7926 /* 629 */ 0,
7927 /* 630 */ 0,
7928 /* 631 */ 0,
7929 /* 632 */ 0,
7930 /* 633 */ 0,
7931 /* 634 */ 0,
7932 /* 635 */ 0,
7933 /* 636 */ 0,
7934 /* 637 */ 0,
7935 /* 638 */ 0,
7936 /* 639 */ 0,
7937 /* 640 */ _Binary_rRegI_rRegI_rule,
7938 /* 641 */ _Binary_rRegI_rRegI_rule,
7939 /* 642 */ _Binary_rRegI_rRegI_rule,
7940 /* 643 */ _Binary_rRegI__LoadI_memory__rule,
7941 /* 644 */ _Binary_rRegI__LoadI_memory__rule,
7942 /* 645 */ _Binary_rRegI__LoadI_memory__rule,
7943 /* 646 */ _Binary_rRegN_rRegN_rule,
7944 /* 647 */ _Binary_rRegN_rRegN_rule,
7945 /* 648 */ _Binary_rRegN_rRegN_rule,
7946 /* 649 */ _Binary_rRegP_rRegP_rule,
7947 /* 650 */ _Binary_rRegP_rRegP_rule,
7948 /* 651 */ _Binary_rRegP_rRegP_rule,
7949 /* 652 */ _Binary_rRegL_rRegL_rule,
7950 /* 653 */ _Binary_rRegL__LoadL_memory__rule,
7951 /* 654 */ _Binary_rRegL_rRegL_rule,
7952 /* 655 */ _Binary_rRegL_rRegL_rule,
7953 /* 656 */ _Binary_rRegL__LoadL_memory__rule,
7954 /* 657 */ _Binary_rRegL__LoadL_memory__rule,
7955 /* 658 */ _Binary_regF_regF_rule,
7956 /* 659 */ _Binary_regF_regF_rule,
7957 /* 660 */ _Binary_regF_regF_rule,
7958 /* 661 */ _Binary_regD_regD_rule,
7959 /* 662 */ _Binary_regD_regD_rule,
7960 /* 663 */ _Binary_regD_regD_rule,
7961 /* 664 */ rRegI_rule,
7962 /* 665 */ immI_rule,
7963 /* 666 */ _LoadI_memory__rule,
7964 /* 667 */ rRegI_rule,
7965 /* 668 */ _AddI__LoadI_memory__rRegI_rule,
7966 /* 669 */ _AddI_rRegI__LoadI_memory__rule,
7967 /* 670 */ _AddI__LoadI_memory__immI_rule,
7968 /* 671 */ immI1_rule,
7969 /* 672 */ _AddI__LoadI_memory__immI1_rule,
7970 /* 673 */ immI_M1_rule,
7971 /* 674 */ _AddI__LoadI_memory__immI_M1_rule,
7972 /* 675 */ immI_rule,
7973 /* 676 */ rRegL_rule,
7974 /* 677 */ immL32_rule,
7975 /* 678 */ _LoadL_memory__rule,
7976 /* 679 */ rRegL_rule,
7977 /* 680 */ _AddL__LoadL_memory__rRegL_rule,
7978 /* 681 */ _AddL_rRegL__LoadL_memory__rule,
7979 /* 682 */ _AddL__LoadL_memory__immL32_rule,
7980 /* 683 */ immL1_rule,
7981 /* 684 */ _AddL__LoadL_memory__immL1_rule,
7982 /* 685 */ immL_M1_rule,
7983 /* 686 */ _AddL__LoadL_memory__immL_M1_rule,
7984 /* 687 */ immL32_rule,
7985 /* 688 */ rRegL_rule,
7986 /* 689 */ immL32_rule,
7987 /* 690 */ immL32_rule,
7988 /* 691 */ 0,
7989 /* 692 */ _Binary_rax_RegP_rRegP_rule,
7990 /* 693 */ _Binary_rax_RegP_rRegP_rule,
7991 /* 694 */ _Binary_rax_RegL_rRegL_rule,
7992 /* 695 */ _Binary_rax_RegL_rRegL_rule,
7993 /* 696 */ _Binary_rax_RegI_rRegI_rule,
7994 /* 697 */ _Binary_rax_RegI_rRegI_rule,
7995 /* 698 */ _Binary_rax_RegI_rRegI_rule,
7996 /* 699 */ _Binary_rax_RegI_rRegI_rule,
7997 /* 700 */ _Binary_rax_RegI_rRegI_rule,
7998 /* 701 */ _Binary_rax_RegI_rRegI_rule,
7999 /* 702 */ _Binary_rax_RegN_rRegN_rule,
8000 /* 703 */ _Binary_rax_RegN_rRegN_rule,
8001 /* 704 */ _Binary_rax_RegI_rRegI_rule,
8002 /* 705 */ _Binary_rax_RegI_rRegI_rule,
8003 /* 706 */ _Binary_rax_RegI_rRegI_rule,
8004 /* 707 */ _Binary_rax_RegL_rRegL_rule,
8005 /* 708 */ _Binary_rax_RegN_rRegN_rule,
8006 /* 709 */ _Binary_rax_RegP_rRegP_rule,
8007 /* 710 */ immI_rule,
8008 /* 711 */ rRegI_rule,
8009 /* 712 */ immI_rule,
8010 /* 713 */ rRegI_rule,
8011 /* 714 */ immI_rule,
8012 /* 715 */ rRegI_rule,
8013 /* 716 */ immL32_rule,
8014 /* 717 */ rRegL_rule,
8015 /* 718 */ rRegI_rule,
8016 /* 719 */ rRegI_rule,
8017 /* 720 */ rRegI_rule,
8018 /* 721 */ rRegL_rule,
8019 /* 722 */ rRegP_rule,
8020 /* 723 */ rRegN_rule,
8021 /* 724 */ 0,
8022 /* 725 */ 0,
8023 /* 726 */ rRegI_rule,
8024 /* 727 */ immI_rule,
8025 /* 728 */ _LoadI_memory__rule,
8026 /* 729 */ _SubI__LoadI_memory__rRegI_rule,
8027 /* 730 */ _SubI__LoadI_memory__immI_rule,
8028 /* 731 */ rRegL_rule,
8029 /* 732 */ immL32_rule,
8030 /* 733 */ _LoadL_memory__rule,
8031 /* 734 */ _SubL__LoadL_memory__rRegL_rule,
8032 /* 735 */ _SubL__LoadL_memory__immL32_rule,
8033 /* 736 */ _SubI_immI0_rRegI_rule,
8034 /* 737 */ rRegI_rule,
8035 /* 738 */ _SubI_immI0__LoadI_memory__rule,
8036 /* 739 */ rRegL_rule,
8037 /* 740 */ _SubL_immL0__LoadL_memory__rule,
8038 /* 741 */ rRegI_rule,
8039 /* 742 */ immI_rule,
8040 /* 743 */ _LoadI_memory__rule,
8041 /* 744 */ rRegI_rule,
8042 /* 745 */ immI_rule,
8043 /* 746 */ _Binary_rRegI_rRegI_rule,
8044 /* 747 */ rRegL_rule,
8045 /* 748 */ immL32_rule,
8046 /* 749 */ _LoadL_memory__rule,
8047 /* 750 */ rRegL_rule,
8048 /* 751 */ immL32_rule,
8049 /* 752 */ rax_RegL_rule,
8050 /* 753 */ no_rax_rdx_RegI_rule,
8051 /* 754 */ no_rax_rdx_RegL_rule,
8052 /* 755 */ no_rax_rdx_RegI_rule,
8053 /* 756 */ no_rax_rdx_RegL_rule,
8054 /* 757 */ 0,
8055 /* 758 */ 0,
8056 /* 759 */ 0,
8057 /* 760 */ 0,
8058 /* 761 */ immL10_rule,
8059 /* 762 */ no_rax_rdx_RegI_rule,
8060 /* 763 */ no_rax_rdx_RegL_rule,
8061 /* 764 */ immI1_rule,
8062 /* 765 */ _LShiftI__LoadI_memory__immI1_rule,
8063 /* 766 */ immI8_rule,
8064 /* 767 */ _LShiftI__LoadI_memory__immI8_rule,
8065 /* 768 */ rcx_RegI_rule,
8066 /* 769 */ _LShiftI__LoadI_memory__rcx_RegI_rule,
8067 /* 770 */ immI1_rule,
8068 /* 771 */ _RShiftI__LoadI_memory__immI1_rule,
8069 /* 772 */ immI8_rule,
8070 /* 773 */ _RShiftI__LoadI_memory__immI8_rule,
8071 /* 774 */ rcx_RegI_rule,
8072 /* 775 */ _RShiftI__LoadI_memory__rcx_RegI_rule,
8073 /* 776 */ immI1_rule,
8074 /* 777 */ _URShiftI__LoadI_memory__immI1_rule,
8075 /* 778 */ immI8_rule,
8076 /* 779 */ _URShiftI__LoadI_memory__immI8_rule,
8077 /* 780 */ rcx_RegI_rule,
8078 /* 781 */ _URShiftI__LoadI_memory__rcx_RegI_rule,
8079 /* 782 */ immI1_rule,
8080 /* 783 */ _LShiftL__LoadL_memory__immI1_rule,
8081 /* 784 */ immI8_rule,
8082 /* 785 */ _LShiftL__LoadL_memory__immI8_rule,
8083 /* 786 */ rcx_RegI_rule,
8084 /* 787 */ _LShiftL__LoadL_memory__rcx_RegI_rule,
8085 /* 788 */ immI1_rule,
8086 /* 789 */ _RShiftL__LoadL_memory__immI1_rule,
8087 /* 790 */ immI8_rule,
8088 /* 791 */ _RShiftL__LoadL_memory__immI8_rule,
8089 /* 792 */ rcx_RegI_rule,
8090 /* 793 */ _RShiftL__LoadL_memory__rcx_RegI_rule,
8091 /* 794 */ immI1_rule,
8092 /* 795 */ _URShiftL__LoadL_memory__immI1_rule,
8093 /* 796 */ immI8_rule,
8094 /* 797 */ _URShiftL__LoadL_memory__immI8_rule,
8095 /* 798 */ rcx_RegI_rule,
8096 /* 799 */ _URShiftL__LoadL_memory__rcx_RegI_rule,
8097 /* 800 */ immI_24_rule,
8098 /* 801 */ immI_16_rule,
8099 /* 802 */ 0,
8100 /* 803 */ 0,
8101 /* 804 */ 0,
8102 /* 805 */ _URShiftI_rRegI_immI_M1_rule,
8103 /* 806 */ _LShiftI_rRegI_immI1_rule,
8104 /* 807 */ _URShiftI_rRegI_immI8_rule,
8105 /* 808 */ _LShiftI_rRegI_immI8_rule,
8106 /* 809 */ _URShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
8107 /* 810 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule,
8108 /* 811 */ _URShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
8109 /* 812 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule,
8110 /* 813 */ 0,
8111 /* 814 */ 0,
8112 /* 815 */ 0,
8113 /* 816 */ _LShiftI_rRegI_immI_M1_rule,
8114 /* 817 */ _URShiftI_rRegI_immI1_rule,
8115 /* 818 */ _LShiftI_rRegI_immI8_rule,
8116 /* 819 */ _URShiftI_rRegI_immI8_rule,
8117 /* 820 */ _LShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule,
8118 /* 821 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule,
8119 /* 822 */ _LShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule,
8120 /* 823 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule,
8121 /* 824 */ 0,
8122 /* 825 */ 0,
8123 /* 826 */ 0,
8124 /* 827 */ _URShiftL_rRegL_immI_M1_rule,
8125 /* 828 */ _LShiftL_rRegL_immI1_rule,
8126 /* 829 */ _URShiftL_rRegL_immI8_rule,
8127 /* 830 */ _LShiftL_rRegL_immI8_rule,
8128 /* 831 */ _URShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
8129 /* 832 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule,
8130 /* 833 */ _URShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
8131 /* 834 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule,
8132 /* 835 */ 0,
8133 /* 836 */ 0,
8134 /* 837 */ 0,
8135 /* 838 */ _LShiftL_rRegL_immI_M1_rule,
8136 /* 839 */ _URShiftL_rRegL_immI1_rule,
8137 /* 840 */ _LShiftL_rRegL_immI8_rule,
8138 /* 841 */ _URShiftL_rRegL_immI8_rule,
8139 /* 842 */ _LShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule,
8140 /* 843 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule,
8141 /* 844 */ _LShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule,
8142 /* 845 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule,
8143 /* 846 */ rRegI_rule,
8144 /* 847 */ immI_255_rule,
8145 /* 848 */ 0,
8146 /* 849 */ immI_65535_rule,
8147 /* 850 */ 0,
8148 /* 851 */ immI_rule,
8149 /* 852 */ _LoadI_memory__rule,
8150 /* 853 */ rRegI_rule,
8151 /* 854 */ _AndI__LoadB_memory__rRegI_rule,
8152 /* 855 */ _AndI_rRegI__LoadB_memory__rule,
8153 /* 856 */ _AndI__LoadI_memory__rRegI_rule,
8154 /* 857 */ _AndI_rRegI__LoadI_memory__rule,
8155 /* 858 */ _AndI__LoadI_memory__immI_rule,
8156 /* 859 */ _LoadI_memory__rule,
8157 /* 860 */ _XorI_rRegI_immI_M1_rule,
8158 /* 861 */ rRegI_rule,
8159 /* 862 */ _XorI_rRegI_immI_M1_rule,
8160 /* 863 */ rRegI_rule,
8161 /* 864 */ _SubI_immI0_rRegI_rule,
8162 /* 865 */ _LoadI_memory__rule,
8163 /* 866 */ _SubI_immI0__LoadI_memory__rule,
8164 /* 867 */ _LoadI_memory__rule,
8165 /* 868 */ _AddI__LoadI_memory__immI_M1_rule,
8166 /* 869 */ rRegI_rule,
8167 /* 870 */ _AddI_rRegI_immI_M1_rule,
8168 /* 871 */ rRegI_rule,
8169 /* 872 */ _AddI_rRegI_immI_M1_rule,
8170 /* 873 */ _LoadI_memory__rule,
8171 /* 874 */ _AddI__LoadI_memory__immI_M1_rule,
8172 /* 875 */ rRegI_rule,
8173 /* 876 */ immI_rule,
8174 /* 877 */ _LoadI_memory__rule,
8175 /* 878 */ rRegI_rule,
8176 /* 879 */ _OrI__LoadB_memory__rRegI_rule,
8177 /* 880 */ _OrI_rRegI__LoadB_memory__rule,
8178 /* 881 */ _OrI__LoadI_memory__rRegI_rule,
8179 /* 882 */ _OrI_rRegI__LoadI_memory__rule,
8180 /* 883 */ _OrI__LoadI_memory__immI_rule,
8181 /* 884 */ rRegI_rule,
8182 /* 885 */ immI_M1_rule,
8183 /* 886 */ immI_rule,
8184 /* 887 */ _LoadI_memory__rule,
8185 /* 888 */ rRegI_rule,
8186 /* 889 */ _XorI__LoadB_memory__rRegI_rule,
8187 /* 890 */ _XorI_rRegI__LoadB_memory__rule,
8188 /* 891 */ _XorI__LoadI_memory__rRegI_rule,
8189 /* 892 */ _XorI_rRegI__LoadI_memory__rule,
8190 /* 893 */ _XorI__LoadI_memory__immI_rule,
8191 /* 894 */ rRegL_rule,
8192 /* 895 */ immL_255_rule,
8193 /* 896 */ immL_65535_rule,
8194 /* 897 */ immL32_rule,
8195 /* 898 */ _LoadL_memory__rule,
8196 /* 899 */ rRegL_rule,
8197 /* 900 */ _AndL__LoadL_memory__rRegL_rule,
8198 /* 901 */ _AndL_rRegL__LoadL_memory__rule,
8199 /* 902 */ _AndL__LoadL_memory__immL32_rule,
8200 /* 903 */ _LoadL_memory__rule,
8201 /* 904 */ _XorL_rRegL_immL_M1_rule,
8202 /* 905 */ rRegL_rule,
8203 /* 906 */ _XorL_rRegL_immL_M1_rule,
8204 /* 907 */ rRegL_rule,
8205 /* 908 */ _SubL_immL0_rRegL_rule,
8206 /* 909 */ _LoadL_memory__rule,
8207 /* 910 */ _SubL_immL0__LoadL_memory__rule,
8208 /* 911 */ _LoadL_memory__rule,
8209 /* 912 */ _AddL__LoadL_memory__immL_M1_rule,
8210 /* 913 */ rRegL_rule,
8211 /* 914 */ _AddL_rRegL_immL_M1_rule,
8212 /* 915 */ rRegL_rule,
8213 /* 916 */ _AddL_rRegL_immL_M1_rule,
8214 /* 917 */ _LoadL_memory__rule,
8215 /* 918 */ _AddL__LoadL_memory__immL_M1_rule,
8216 /* 919 */ rRegL_rule,
8217 /* 920 */ _CastP2X_any_RegP__rule,
8218 /* 921 */ rRegL_rule,
8219 /* 922 */ immL32_rule,
8220 /* 923 */ _LoadL_memory__rule,
8221 /* 924 */ rRegL_rule,
8222 /* 925 */ _OrL__LoadL_memory__rRegL_rule,
8223 /* 926 */ _OrL_rRegL__LoadL_memory__rule,
8224 /* 927 */ _OrL__LoadL_memory__immL32_rule,
8225 /* 928 */ rRegL_rule,
8226 /* 929 */ immL_M1_rule,
8227 /* 930 */ immL32_rule,
8228 /* 931 */ _LoadL_memory__rule,
8229 /* 932 */ rRegL_rule,
8230 /* 933 */ _XorL__LoadL_memory__rRegL_rule,
8231 /* 934 */ _XorL_rRegL__LoadL_memory__rule,
8232 /* 935 */ _XorL__LoadL_memory__immL32_rule,
8233 /* 936 */ 0,
8234 /* 937 */ 0,
8235 /* 938 */ rRegI_rule,
8236 /* 939 */ immI0_rule,
8237 /* 940 */ _SubI_rRegI_rRegI_rule,
8238 /* 941 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
8239 /* 942 */ _SubI_rRegI_rRegI_rule,
8240 /* 943 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
8241 /* 944 */ rRegI_rule,
8242 /* 945 */ _CmpLTMask_rRegI_rRegI_rule,
8243 /* 946 */ regF_rule,
8244 /* 947 */ _LoadF_memory__rule,
8245 /* 948 */ immF_rule,
8246 /* 949 */ regD_rule,
8247 /* 950 */ _LoadD_memory__rule,
8248 /* 951 */ immD_rule,
8249 /* 952 */ 0,
8250 /* 953 */ 0,
8251 /* 954 */ 0,
8252 /* 955 */ 0,
8253 /* 956 */ 0,
8254 /* 957 */ 0,
8255 /* 958 */ 0,
8256 /* 959 */ 0,
8257 /* 960 */ 0,
8258 /* 961 */ 0,
8259 /* 962 */ 0,
8260 /* 963 */ 0,
8261 /* 964 */ 0,
8262 /* 965 */ 0,
8263 /* 966 */ 0,
8264 /* 967 */ 0,
8265 /* 968 */ 0,
8266 /* 969 */ 0,
8267 /* 970 */ 0,
8268 /* 971 */ immL_32bits_rule,
8269 /* 972 */ immL_32bits_rule,
8270 /* 973 */ immL_32bits_rule,
8271 /* 974 */ 0,
8272 /* 975 */ 0,
8273 /* 976 */ 0,
8274 /* 977 */ 0,
8275 /* 978 */ 0,
8276 /* 979 */ rdi_RegP_rule,
8277 /* 980 */ rdi_RegP_rule,
8278 /* 981 */ _Binary_rsi_RegP_rdx_RegI_rule,
8279 /* 982 */ _Binary_rsi_RegP_rdx_RegI_rule,
8280 /* 983 */ _Binary_rsi_RegP_rdx_RegI_rule,
8281 /* 984 */ _Binary_rdi_RegP_rcx_RegI_rule,
8282 /* 985 */ _Binary_rsi_RegP_immI_rule,
8283 /* 986 */ _Binary_rsi_RegP_immI_rule,
8284 /* 987 */ _Binary_rsi_RegP_immI_rule,
8285 /* 988 */ _Binary_rsi_RegP_rax_RegI_rule,
8286 /* 989 */ _Binary_rsi_RegP_rax_RegI_rule,
8287 /* 990 */ _Binary_rsi_RegP_rax_RegI_rule,
8288 /* 991 */ rax_RegI_rule,
8289 /* 992 */ rcx_RegI_rule,
8290 /* 993 */ rsi_RegP_rule,
8291 /* 994 */ rsi_RegP_rule,
8292 /* 995 */ rcx_RegI_rule,
8293 /* 996 */ _Binary_rdi_RegP_rdx_RegI_rule,
8294 /* 997 */ _Binary_rdi_RegP_rdx_RegI_rule,
8295 /* 998 */ _Binary_rdi_RegP_rdx_RegI_rule,
8296 /* 999 */ rRegL_rule,
8297 /* 1000 */ 0,
8298 /* 1001 */ rRegI_rule,
8299 /* 1002 */ 0,
8300 /* 1003 */ rRegI_rule,
8301 /* 1004 */ 0,
8302 /* 1005 */ rFlagsReg_rule,
8303 /* 1006 */ rFlagsReg_rule,
8304 /* 1007 */ rFlagsRegU_rule,
8305 /* 1008 */ rFlagsRegUCF_rule,
8306 /* 1009 */ rFlagsReg_rule,
8307 /* 1010 */ rFlagsRegU_rule,
8308 /* 1011 */ rFlagsRegUCF_rule,
8309 /* 1012 */ rFlagsRegU_rule,
8310 /* 1013 */ rFlagsRegUCF_rule,
8311 /* 1014 */ rFlagsRegUCF_rule,
8312 /* 1015 */ rax_RegP_rule,
8313 /* 1016 */ 0,
8314 /* 1017 */ rFlagsReg_rule,
8315 /* 1018 */ rFlagsReg_rule,
8316 /* 1019 */ rFlagsRegU_rule,
8317 /* 1020 */ rFlagsRegUCF_rule,
8318 /* 1021 */ rFlagsRegU_rule,
8319 /* 1022 */ rFlagsRegUCF_rule,
8320 /* 1023 */ rFlagsRegUCF_rule,
8321 /* 1024 */ 0,
8322 /* 1025 */ 0,
8323 /* 1026 */ 0,
8324 /* 1027 */ 0,
8325 /* 1028 */ 0,
8326 /* 1029 */ 0,
8327 /* 1030 */ 0,
8328 /* 1031 */ 0,
8329 /* 1032 */ rbx_RegP_rule,
8330 /* 1033 */ rax_RegP_rule,
8331 /* 1034 */ 0,
8332 /* 1035 */ 0,
8333 /* 1036 */ 0,
8334 /* 1037 */ 0,
8335 /* 1038 */ regF_rule,
8336 /* 1039 */ _LoadF_memory__rule,
8337 /* 1040 */ regF_rule,
8338 /* 1041 */ immF_rule,
8339 /* 1042 */ regF_rule,
8340 /* 1043 */ _LoadF_memory__rule,
8341 /* 1044 */ regF_rule,
8342 /* 1045 */ immF_rule,
8343 /* 1046 */ regD_rule,
8344 /* 1047 */ _LoadD_memory__rule,
8345 /* 1048 */ regD_rule,
8346 /* 1049 */ immD_rule,
8347 /* 1050 */ regD_rule,
8348 /* 1051 */ _LoadD_memory__rule,
8349 /* 1052 */ regD_rule,
8350 /* 1053 */ immD_rule,
8351 /* 1054 */ regF_rule,
8352 /* 1055 */ _LoadF_memory__rule,
8353 /* 1056 */ immF_rule,
8354 /* 1057 */ regF_rule,
8355 /* 1058 */ _LoadF_memory__rule,
8356 /* 1059 */ immF_rule,
8357 /* 1060 */ regD_rule,
8358 /* 1061 */ _LoadD_memory__rule,
8359 /* 1062 */ immD_rule,
8360 /* 1063 */ regD_rule,
8361 /* 1064 */ _LoadD_memory__rule,
8362 /* 1065 */ immD_rule,
8363 /* 1066 */ regF_rule,
8364 /* 1067 */ _LoadF_memory__rule,
8365 /* 1068 */ regF_rule,
8366 /* 1069 */ immF_rule,
8367 /* 1070 */ regF_rule,
8368 /* 1071 */ _LoadF_memory__rule,
8369 /* 1072 */ regF_rule,
8370 /* 1073 */ immF_rule,
8371 /* 1074 */ regD_rule,
8372 /* 1075 */ _LoadD_memory__rule,
8373 /* 1076 */ regD_rule,
8374 /* 1077 */ immD_rule,
8375 /* 1078 */ regD_rule,
8376 /* 1079 */ _LoadD_memory__rule,
8377 /* 1080 */ regD_rule,
8378 /* 1081 */ immD_rule,
8379 /* 1082 */ regF_rule,
8380 /* 1083 */ _LoadF_memory__rule,
8381 /* 1084 */ immF_rule,
8382 /* 1085 */ regF_rule,
8383 /* 1086 */ _LoadF_memory__rule,
8384 /* 1087 */ immF_rule,
8385 /* 1088 */ regD_rule,
8386 /* 1089 */ _LoadD_memory__rule,
8387 /* 1090 */ immD_rule,
8388 /* 1091 */ regD_rule,
8389 /* 1092 */ _LoadD_memory__rule,
8390 /* 1093 */ immD_rule,
8391 /* 1094 */ 0,
8392 /* 1095 */ 0,
8393 /* 1096 */ 0,
8394 /* 1097 */ 0,
8395 /* 1098 */ 0,
8396 /* 1099 */ 0,
8397 /* 1100 */ 0,
8398 /* 1101 */ _Binary_regD_regD_rule,
8399 /* 1102 */ _Binary_regF_regF_rule,
8400 /* 1103 */ 0,
8401 /* 1104 */ 0,
8402 /* 1105 */ 0,
8403 /* 1106 */ 0,
8404 /* 1107 */ 0,
8405 /* 1108 */ 0,
8406 /* 1109 */ vecS_rule,
8407 /* 1110 */ vecD_rule,
8408 /* 1111 */ vecX_rule,
8409 /* 1112 */ vecY_rule,
8410 /* 1113 */ vecZ_rule,
8411 /* 1114 */ vecZ_rule,
8412 /* 1115 */ 0,
8413 /* 1116 */ 0,
8414 /* 1117 */ 0,
8415 /* 1118 */ 0,
8416 /* 1119 */ 0,
8417 /* 1120 */ 0,
8418 /* 1121 */ 0,
8419 /* 1122 */ 0,
8420 /* 1123 */ 0,
8421 /* 1124 */ 0,
8422 /* 1125 */ 0,
8423 /* 1126 */ 0,
8424 /* 1127 */ 0,
8425 /* 1128 */ 0,
8426 /* 1129 */ 0,
8427 /* 1130 */ 0,
8428 /* 1131 */ 0,
8429 /* 1132 */ 0,
8430 /* 1133 */ 0,
8431 /* 1134 */ 0,
8432 /* 1135 */ 0,
8433 /* 1136 */ 0,
8434 /* 1137 */ 0,
8435 /* 1138 */ 0,
8436 /* 1139 */ 0,
8437 /* 1140 */ 0,
8438 /* 1141 */ 0,
8439 /* 1142 */ 0,
8440 /* 1143 */ 0,
8441 /* 1144 */ 0,
8442 /* 1145 */ 0,
8443 /* 1146 */ 0,
8444 /* 1147 */ 0,
8445 /* 1148 */ 0,
8446 /* 1149 */ 0,
8447 /* 1150 */ 0,
8448 /* 1151 */ 0,
8449 /* 1152 */ 0,
8450 /* 1153 */ 0,
8451 /* 1154 */ 0,
8452 /* 1155 */ 0,
8453 /* 1156 */ 0,
8454 /* 1157 */ 0,
8455 /* 1158 */ 0,
8456 /* 1159 */ 0,
8457 /* 1160 */ 0,
8458 /* 1161 */ 0,
8459 /* 1162 */ 0,
8460 /* 1163 */ 0,
8461 /* 1164 */ 0,
8462 /* 1165 */ 0,
8463 /* 1166 */ 0,
8464 /* 1167 */ 0,
8465 /* 1168 */ 0,
8466 /* 1169 */ 0,
8467 /* 1170 */ 0,
8468 /* 1171 */ 0,
8469 /* 1172 */ 0,
8470 /* 1173 */ 0,
8471 /* 1174 */ 0,
8472 /* 1175 */ 0,
8473 /* 1176 */ 0,
8474 /* 1177 */ 0,
8475 /* 1178 */ 0,
8476 /* 1179 */ 0,
8477 /* 1180 */ 0,
8478 /* 1181 */ 0,
8479 /* 1182 */ 0,
8480 /* 1183 */ 0,
8481 /* 1184 */ 0,
8482 /* 1185 */ 0,
8483 /* 1186 */ 0,
8484 /* 1187 */ 0,
8485 /* 1188 */ 0,
8486 /* 1189 */ 0,
8487 /* 1190 */ 0,
8488 /* 1191 */ 0,
8489 /* 1192 */ 0,
8490 /* 1193 */ 0,
8491 /* 1194 */ 0,
8492 /* 1195 */ 0,
8493 /* 1196 */ 0,
8494 /* 1197 */ 0,
8495 /* 1198 */ 0,
8496 /* 1199 */ 0,
8497 /* 1200 */ 0,
8498 /* 1201 */ 0,
8499 /* 1202 */ 0,
8500 /* 1203 */ 0,
8501 /* 1204 */ 0,
8502 /* 1205 */ 0,
8503 /* 1206 */ 0,
8504 /* 1207 */ 0,
8505 /* 1208 */ 0,
8506 /* 1209 */ 0,
8507 /* 1210 */ 0,
8508 /* 1211 */ 0,
8509 /* 1212 */ 0,
8510 /* 1213 */ 0,
8511 /* 1214 */ 0,
8512 /* 1215 */ 0,
8513 /* 1216 */ 0,
8514 /* 1217 */ 0,
8515 /* 1218 */ 0,
8516 /* 1219 */ 0,
8517 /* 1220 */ 0,
8518 /* 1221 */ 0,
8519 /* 1222 */ 0,
8520 /* 1223 */ 0,
8521 /* 1224 */ 0,
8522 /* 1225 */ 0,
8523 /* 1226 */ 0,
8524 /* 1227 */ 0,
8525 /* 1228 */ 0,
8526 /* 1229 */ 0,
8527 /* 1230 */ 0,
8528 /* 1231 */ 0,
8529 /* 1232 */ 0,
8530 /* 1233 */ 0,
8531 /* 1234 */ 0,
8532 /* 1235 */ 0,
8533 /* 1236 */ 0,
8534 /* 1237 */ 0,
8535 /* 1238 */ 0,
8536 /* 1239 */ 0,
8537 /* 1240 */ 0,
8538 /* 1241 */ 0,
8539 /* 1242 */ 0,
8540 /* 1243 */ 0,
8541 /* 1244 */ 0,
8542 /* 1245 */ 0,
8543 /* 1246 */ 0,
8544 /* 1247 */ 0,
8545 /* 1248 */ 0,
8546 /* 1249 */ vecD_rule,
8547 /* 1250 */ vecD_rule,
8548 /* 1251 */ vecD_rule,
8549 /* 1252 */ vecX_rule,
8550 /* 1253 */ vecX_rule,
8551 /* 1254 */ vecX_rule,
8552 /* 1255 */ vecY_rule,
8553 /* 1256 */ vecY_rule,
8554 /* 1257 */ legVecZ_rule,
8555 /* 1258 */ vecX_rule,
8556 /* 1259 */ vecY_rule,
8557 /* 1260 */ legVecZ_rule,
8558 /* 1261 */ vecD_rule,
8559 /* 1262 */ vecD_rule,
8560 /* 1263 */ vecX_rule,
8561 /* 1264 */ vecX_rule,
8562 /* 1265 */ vecY_rule,
8563 /* 1266 */ legVecZ_rule,
8564 /* 1267 */ vecX_rule,
8565 /* 1268 */ vecX_rule,
8566 /* 1269 */ vecY_rule,
8567 /* 1270 */ legVecZ_rule,
8568 /* 1271 */ vecD_rule,
8569 /* 1272 */ vecD_rule,
8570 /* 1273 */ vecX_rule,
8571 /* 1274 */ vecX_rule,
8572 /* 1275 */ vecY_rule,
8573 /* 1276 */ legVecZ_rule,
8574 /* 1277 */ vecX_rule,
8575 /* 1278 */ vecY_rule,
8576 /* 1279 */ legVecZ_rule,
8577 /* 1280 */ vecD_rule,
8578 /* 1281 */ vecD_rule,
8579 /* 1282 */ vecX_rule,
8580 /* 1283 */ vecX_rule,
8581 /* 1284 */ vecY_rule,
8582 /* 1285 */ legVecZ_rule,
8583 /* 1286 */ vecX_rule,
8584 /* 1287 */ vecX_rule,
8585 /* 1288 */ vecY_rule,
8586 /* 1289 */ legVecZ_rule,
8587 /* 1290 */ vecS_rule,
8588 /* 1291 */ vecS_rule,
8589 /* 1292 */ _LoadVector_memory__rule,
8590 /* 1293 */ vecS_rule,
8591 /* 1294 */ vecD_rule,
8592 /* 1295 */ vecD_rule,
8593 /* 1296 */ _LoadVector_memory__rule,
8594 /* 1297 */ vecD_rule,
8595 /* 1298 */ vecX_rule,
8596 /* 1299 */ vecX_rule,
8597 /* 1300 */ _LoadVector_memory__rule,
8598 /* 1301 */ vecX_rule,
8599 /* 1302 */ vecY_rule,
8600 /* 1303 */ _LoadVector_memory__rule,
8601 /* 1304 */ vecY_rule,
8602 /* 1305 */ vecZ_rule,
8603 /* 1306 */ _LoadVector_memory__rule,
8604 /* 1307 */ vecZ_rule,
8605 /* 1308 */ vecS_rule,
8606 /* 1309 */ vecS_rule,
8607 /* 1310 */ _LoadVector_memory__rule,
8608 /* 1311 */ vecS_rule,
8609 /* 1312 */ vecD_rule,
8610 /* 1313 */ vecD_rule,
8611 /* 1314 */ _LoadVector_memory__rule,
8612 /* 1315 */ vecD_rule,
8613 /* 1316 */ vecX_rule,
8614 /* 1317 */ vecX_rule,
8615 /* 1318 */ _LoadVector_memory__rule,
8616 /* 1319 */ vecX_rule,
8617 /* 1320 */ vecY_rule,
8618 /* 1321 */ _LoadVector_memory__rule,
8619 /* 1322 */ vecY_rule,
8620 /* 1323 */ vecZ_rule,
8621 /* 1324 */ _LoadVector_memory__rule,
8622 /* 1325 */ vecZ_rule,
8623 /* 1326 */ vecD_rule,
8624 /* 1327 */ vecD_rule,
8625 /* 1328 */ _LoadVector_memory__rule,
8626 /* 1329 */ vecD_rule,
8627 /* 1330 */ vecX_rule,
8628 /* 1331 */ vecX_rule,
8629 /* 1332 */ _LoadVector_memory__rule,
8630 /* 1333 */ vecX_rule,
8631 /* 1334 */ vecY_rule,
8632 /* 1335 */ _LoadVector_memory__rule,
8633 /* 1336 */ vecY_rule,
8634 /* 1337 */ vecZ_rule,
8635 /* 1338 */ _LoadVector_memory__rule,
8636 /* 1339 */ vecZ_rule,
8637 /* 1340 */ vecX_rule,
8638 /* 1341 */ vecX_rule,
8639 /* 1342 */ _LoadVector_memory__rule,
8640 /* 1343 */ vecX_rule,
8641 /* 1344 */ vecY_rule,
8642 /* 1345 */ _LoadVector_memory__rule,
8643 /* 1346 */ vecY_rule,
8644 /* 1347 */ vecZ_rule,
8645 /* 1348 */ _LoadVector_memory__rule,
8646 /* 1349 */ vecZ_rule,
8647 /* 1350 */ vecD_rule,
8648 /* 1351 */ vecD_rule,
8649 /* 1352 */ _LoadVector_memory__rule,
8650 /* 1353 */ vecD_rule,
8651 /* 1354 */ vecX_rule,
8652 /* 1355 */ vecX_rule,
8653 /* 1356 */ _LoadVector_memory__rule,
8654 /* 1357 */ vecX_rule,
8655 /* 1358 */ vecY_rule,
8656 /* 1359 */ _LoadVector_memory__rule,
8657 /* 1360 */ vecY_rule,
8658 /* 1361 */ vecZ_rule,
8659 /* 1362 */ _LoadVector_memory__rule,
8660 /* 1363 */ vecZ_rule,
8661 /* 1364 */ vecX_rule,
8662 /* 1365 */ vecX_rule,
8663 /* 1366 */ _LoadVector_memory__rule,
8664 /* 1367 */ vecX_rule,
8665 /* 1368 */ vecY_rule,
8666 /* 1369 */ _LoadVector_memory__rule,
8667 /* 1370 */ vecY_rule,
8668 /* 1371 */ vecZ_rule,
8669 /* 1372 */ _LoadVector_memory__rule,
8670 /* 1373 */ vecZ_rule,
8671 /* 1374 */ vecS_rule,
8672 /* 1375 */ vecS_rule,
8673 /* 1376 */ _LoadVector_memory__rule,
8674 /* 1377 */ vecD_rule,
8675 /* 1378 */ vecD_rule,
8676 /* 1379 */ _LoadVector_memory__rule,
8677 /* 1380 */ vecX_rule,
8678 /* 1381 */ vecX_rule,
8679 /* 1382 */ _LoadVector_memory__rule,
8680 /* 1383 */ vecY_rule,
8681 /* 1384 */ _LoadVector_memory__rule,
8682 /* 1385 */ vecZ_rule,
8683 /* 1386 */ _LoadVector_memory__rule,
8684 /* 1387 */ vecS_rule,
8685 /* 1388 */ vecS_rule,
8686 /* 1389 */ _LoadVector_memory__rule,
8687 /* 1390 */ vecD_rule,
8688 /* 1391 */ vecD_rule,
8689 /* 1392 */ _LoadVector_memory__rule,
8690 /* 1393 */ vecX_rule,
8691 /* 1394 */ vecX_rule,
8692 /* 1395 */ _LoadVector_memory__rule,
8693 /* 1396 */ vecY_rule,
8694 /* 1397 */ _LoadVector_memory__rule,
8695 /* 1398 */ vecZ_rule,
8696 /* 1399 */ _LoadVector_memory__rule,
8697 /* 1400 */ vecD_rule,
8698 /* 1401 */ vecD_rule,
8699 /* 1402 */ _LoadVector_memory__rule,
8700 /* 1403 */ vecX_rule,
8701 /* 1404 */ vecX_rule,
8702 /* 1405 */ _LoadVector_memory__rule,
8703 /* 1406 */ vecY_rule,
8704 /* 1407 */ _LoadVector_memory__rule,
8705 /* 1408 */ vecZ_rule,
8706 /* 1409 */ _LoadVector_memory__rule,
8707 /* 1410 */ vecX_rule,
8708 /* 1411 */ vecX_rule,
8709 /* 1412 */ _LoadVector_memory__rule,
8710 /* 1413 */ vecY_rule,
8711 /* 1414 */ _LoadVector_memory__rule,
8712 /* 1415 */ vecZ_rule,
8713 /* 1416 */ _LoadVector_memory__rule,
8714 /* 1417 */ vecD_rule,
8715 /* 1418 */ vecD_rule,
8716 /* 1419 */ _LoadVector_memory__rule,
8717 /* 1420 */ vecX_rule,
8718 /* 1421 */ vecX_rule,
8719 /* 1422 */ _LoadVector_memory__rule,
8720 /* 1423 */ vecY_rule,
8721 /* 1424 */ _LoadVector_memory__rule,
8722 /* 1425 */ vecZ_rule,
8723 /* 1426 */ _LoadVector_memory__rule,
8724 /* 1427 */ vecX_rule,
8725 /* 1428 */ vecX_rule,
8726 /* 1429 */ _LoadVector_memory__rule,
8727 /* 1430 */ vecY_rule,
8728 /* 1431 */ _LoadVector_memory__rule,
8729 /* 1432 */ vecZ_rule,
8730 /* 1433 */ _LoadVector_memory__rule,
8731 /* 1434 */ vecS_rule,
8732 /* 1435 */ vecD_rule,
8733 /* 1436 */ vecX_rule,
8734 /* 1437 */ vecX_rule,
8735 /* 1438 */ vecY_rule,
8736 /* 1439 */ vecZ_rule,
8737 /* 1440 */ vecS_rule,
8738 /* 1441 */ vecS_rule,
8739 /* 1442 */ _LoadVector_memory__rule,
8740 /* 1443 */ vecS_rule,
8741 /* 1444 */ vecD_rule,
8742 /* 1445 */ vecD_rule,
8743 /* 1446 */ _LoadVector_memory__rule,
8744 /* 1447 */ vecD_rule,
8745 /* 1448 */ vecX_rule,
8746 /* 1449 */ vecX_rule,
8747 /* 1450 */ _LoadVector_memory__rule,
8748 /* 1451 */ vecX_rule,
8749 /* 1452 */ vecY_rule,
8750 /* 1453 */ _LoadVector_memory__rule,
8751 /* 1454 */ vecY_rule,
8752 /* 1455 */ vecZ_rule,
8753 /* 1456 */ _LoadVector_memory__rule,
8754 /* 1457 */ vecZ_rule,
8755 /* 1458 */ vecD_rule,
8756 /* 1459 */ vecD_rule,
8757 /* 1460 */ _LoadVector_memory__rule,
8758 /* 1461 */ vecD_rule,
8759 /* 1462 */ vecX_rule,
8760 /* 1463 */ vecX_rule,
8761 /* 1464 */ _LoadVector_memory__rule,
8762 /* 1465 */ vecX_rule,
8763 /* 1466 */ vecX_rule,
8764 /* 1467 */ _LoadVector_memory__rule,
8765 /* 1468 */ vecX_rule,
8766 /* 1469 */ vecY_rule,
8767 /* 1470 */ _LoadVector_memory__rule,
8768 /* 1471 */ vecY_rule,
8769 /* 1472 */ vecZ_rule,
8770 /* 1473 */ _LoadVector_memory__rule,
8771 /* 1474 */ vecZ_rule,
8772 /* 1475 */ vecY_rule,
8773 /* 1476 */ _LoadVector_memory__rule,
8774 /* 1477 */ vecY_rule,
8775 /* 1478 */ vecZ_rule,
8776 /* 1479 */ _LoadVector_memory__rule,
8777 /* 1480 */ vecZ_rule,
8778 /* 1481 */ vecD_rule,
8779 /* 1482 */ vecD_rule,
8780 /* 1483 */ _LoadVector_memory__rule,
8781 /* 1484 */ vecD_rule,
8782 /* 1485 */ vecX_rule,
8783 /* 1486 */ vecX_rule,
8784 /* 1487 */ _LoadVector_memory__rule,
8785 /* 1488 */ vecX_rule,
8786 /* 1489 */ vecY_rule,
8787 /* 1490 */ _LoadVector_memory__rule,
8788 /* 1491 */ vecY_rule,
8789 /* 1492 */ vecZ_rule,
8790 /* 1493 */ _LoadVector_memory__rule,
8791 /* 1494 */ vecZ_rule,
8792 /* 1495 */ vecX_rule,
8793 /* 1496 */ vecX_rule,
8794 /* 1497 */ _LoadVector_memory__rule,
8795 /* 1498 */ vecX_rule,
8796 /* 1499 */ vecY_rule,
8797 /* 1500 */ _LoadVector_memory__rule,
8798 /* 1501 */ vecY_rule,
8799 /* 1502 */ vecZ_rule,
8800 /* 1503 */ _LoadVector_memory__rule,
8801 /* 1504 */ vecZ_rule,
8802 /* 1505 */ _Binary_legVecY_legVecY_rule,
8803 /* 1506 */ _Binary_legVecY_legVecY_rule,
8804 /* 1507 */ vecD_rule,
8805 /* 1508 */ vecD_rule,
8806 /* 1509 */ _LoadVector_memory__rule,
8807 /* 1510 */ vecX_rule,
8808 /* 1511 */ vecX_rule,
8809 /* 1512 */ _LoadVector_memory__rule,
8810 /* 1513 */ vecY_rule,
8811 /* 1514 */ _LoadVector_memory__rule,
8812 /* 1515 */ vecZ_rule,
8813 /* 1516 */ _LoadVector_memory__rule,
8814 /* 1517 */ vecX_rule,
8815 /* 1518 */ vecX_rule,
8816 /* 1519 */ _LoadVector_memory__rule,
8817 /* 1520 */ vecY_rule,
8818 /* 1521 */ _LoadVector_memory__rule,
8819 /* 1522 */ vecZ_rule,
8820 /* 1523 */ _LoadVector_memory__rule,
8821 /* 1524 */ vecS_rule,
8822 /* 1525 */ vecS_rule,
8823 /* 1526 */ vecS_rule,
8824 /* 1527 */ vecS_rule,
8825 /* 1528 */ vecS_rule,
8826 /* 1529 */ vecS_rule,
8827 /* 1530 */ vecS_rule,
8828 /* 1531 */ vecS_rule,
8829 /* 1532 */ vecS_rule,
8830 /* 1533 */ vecS_rule,
8831 /* 1534 */ vecS_rule,
8832 /* 1535 */ vecS_rule,
8833 /* 1536 */ vecS_rule,
8834 /* 1537 */ vecS_rule,
8835 /* 1538 */ vecS_rule,
8836 /* 1539 */ vecS_rule,
8837 /* 1540 */ vecS_rule,
8838 /* 1541 */ vecS_rule,
8839 /* 1542 */ vecS_rule,
8840 /* 1543 */ vecS_rule,
8841 /* 1544 */ vecS_rule,
8842 /* 1545 */ vecS_rule,
8843 /* 1546 */ vecS_rule,
8844 /* 1547 */ vecS_rule,
8845 /* 1548 */ vecS_rule,
8846 /* 1549 */ vecS_rule,
8847 /* 1550 */ vecS_rule,
8848 /* 1551 */ vecS_rule,
8849 /* 1552 */ vecS_rule,
8850 /* 1553 */ vecS_rule,
8851 /* 1554 */ vecS_rule,
8852 /* 1555 */ vecS_rule,
8853 /* 1556 */ vecS_rule,
8854 /* 1557 */ vecS_rule,
8855 /* 1558 */ vecS_rule,
8856 /* 1559 */ vecS_rule,
8857 /* 1560 */ vecS_rule,
8858 /* 1561 */ vecS_rule,
8859 /* 1562 */ vecS_rule,
8860 /* 1563 */ vecS_rule,
8861 /* 1564 */ vecS_rule,
8862 /* 1565 */ vecS_rule,
8863 /* 1566 */ vecS_rule,
8864 /* 1567 */ vecS_rule,
8865 /* 1568 */ vecS_rule,
8866 /* 1569 */ vecS_rule,
8867 /* 1570 */ vecS_rule,
8868 /* 1571 */ vecS_rule,
8869 /* 1572 */ vecS_rule,
8870 /* 1573 */ vecS_rule,
8871 /* 1574 */ vecS_rule,
8872 /* 1575 */ vecS_rule,
8873 /* 1576 */ vecS_rule,
8874 /* 1577 */ vecS_rule,
8875 /* 1578 */ vecS_rule,
8876 /* 1579 */ vecS_rule,
8877 /* 1580 */ vecS_rule,
8878 /* 1581 */ vecS_rule,
8879 /* 1582 */ _LoadVector_memory__rule,
8880 /* 1583 */ vecS_rule,
8881 /* 1584 */ vecD_rule,
8882 /* 1585 */ vecD_rule,
8883 /* 1586 */ _LoadVector_memory__rule,
8884 /* 1587 */ vecD_rule,
8885 /* 1588 */ vecX_rule,
8886 /* 1589 */ vecX_rule,
8887 /* 1590 */ _LoadVector_memory__rule,
8888 /* 1591 */ vecX_rule,
8889 /* 1592 */ vecY_rule,
8890 /* 1593 */ _LoadVector_memory__rule,
8891 /* 1594 */ vecY_rule,
8892 /* 1595 */ vecZ_rule,
8893 /* 1596 */ _LoadVector_memory__rule,
8894 /* 1597 */ vecZ_rule,
8895 /* 1598 */ vecS_rule,
8896 /* 1599 */ vecS_rule,
8897 /* 1600 */ _LoadVector_memory__rule,
8898 /* 1601 */ vecS_rule,
8899 /* 1602 */ vecD_rule,
8900 /* 1603 */ vecD_rule,
8901 /* 1604 */ _LoadVector_memory__rule,
8902 /* 1605 */ vecD_rule,
8903 /* 1606 */ vecX_rule,
8904 /* 1607 */ vecX_rule,
8905 /* 1608 */ _LoadVector_memory__rule,
8906 /* 1609 */ vecX_rule,
8907 /* 1610 */ vecY_rule,
8908 /* 1611 */ _LoadVector_memory__rule,
8909 /* 1612 */ vecY_rule,
8910 /* 1613 */ vecZ_rule,
8911 /* 1614 */ _LoadVector_memory__rule,
8912 /* 1615 */ vecZ_rule,
8913 /* 1616 */ vecS_rule,
8914 /* 1617 */ vecS_rule,
8915 /* 1618 */ _LoadVector_memory__rule,
8916 /* 1619 */ vecS_rule,
8917 /* 1620 */ vecD_rule,
8918 /* 1621 */ vecD_rule,
8919 /* 1622 */ _LoadVector_memory__rule,
8920 /* 1623 */ vecD_rule,
8921 /* 1624 */ vecX_rule,
8922 /* 1625 */ vecX_rule,
8923 /* 1626 */ _LoadVector_memory__rule,
8924 /* 1627 */ vecX_rule,
8925 /* 1628 */ vecY_rule,
8926 /* 1629 */ _LoadVector_memory__rule,
8927 /* 1630 */ vecY_rule,
8928 /* 1631 */ vecZ_rule,
8929 /* 1632 */ _LoadVector_memory__rule,
8930 /* 1633 */ vecZ_rule,
8931 /* 1634 */ 0,
8932 /* 1635 */ 0,
8933 /* 1636 */ 0,
8934 /* 1637 */ 0,
8935 /* 1638 */ 0,
8936 /* 1639 */ 0,
8937 /* 1640 */ 0,
8938 /* 1641 */ 0,
8939 /* 1642 */ 0,
8940 /* 1643 */ 0,
8941 /* 1644 */ 0,
8942 /* 1645 */ 0,
8943 /* 1646 */ 0,
8944 /* 1647 */ 0,
8945 /* 1648 */ _Binary_vecX_vecX_rule,
8946 /* 1649 */ _Binary_vecX__LoadVector_memory__rule,
8947 /* 1650 */ _Binary_vecY_vecY_rule,
8948 /* 1651 */ _Binary_vecY__LoadVector_memory__rule,
8949 /* 1652 */ _Binary_vecZ_vecZ_rule,
8950 /* 1653 */ _Binary_vecZ__LoadVector_memory__rule,
8951 /* 1654 */ _Binary_vecX_vecX_rule,
8952 /* 1655 */ _Binary_vecX__LoadVector_memory__rule,
8953 /* 1656 */ _Binary_vecY_vecY_rule,
8954 /* 1657 */ _Binary_vecY__LoadVector_memory__rule,
8955 /* 1658 */ _Binary_vecZ_vecZ_rule,
8956 /* 1659 */ _Binary_vecZ__LoadVector_memory__rule,
8957 /* 1660 */ vecD_rule,
8958 /* 1661 */ vecD_rule,
8959 /* 1662 */ vecX_rule,
8960 /* 1663 */ vecX_rule,
8961 /* 1664 */ vecY_rule,
8962 /* 1665 */ vecZ_rule,
8963 /* 1666 */ vecD_rule,
8964 /* 1667 */ _MulAddVS2VI_vecD_vecD_rule,
8965 /* 1668 */ vecX_rule,
8966 /* 1669 */ _MulAddVS2VI_vecX_vecX_rule,
8967 /* 1670 */ vecY_rule,
8968 /* 1671 */ _MulAddVS2VI_vecY_vecY_rule,
8969 /* 1672 */ vecZ_rule,
8970 /* 1673 */ _MulAddVS2VI_vecZ_vecZ_rule,
8971 /* 1674 */ _Binary_rax_RegP_rRegP_rule,
8972 /* 1675 */ _Binary_rax_RegP_rRegP_rule,
8973 /* 1676 */ _Binary_rax_RegN_rRegN_rule,
8974 /* 1677 */ _Binary_rax_RegN_rRegN_rule,
8975 /* 1678 */ _Binary_rax_RegN_rRegN_rule,
8976 /* 1679 */ _Binary_rax_RegP_rRegP_rule,
8977 /* 1680 */ rRegP_rule,
8978 /* 1681 */ rRegP_rule,
8979 /* 1682 */ rRegP_rule,
8980 /* 1683 */ rRegP_rule,
8981 /* 1684 */ _Binary_rax_RegP_rRegP_rule,
8982 /* 1685 */ _Binary_rax_RegP_rRegP_rule,
8983 /* 1686 */ _Binary_rax_RegP_rRegP_rule,
8984 /* 1687 */ _Binary_rRegP_rRegP_rule,
8985 // last instruction
8986 0 // no trailing comma
8987};
8988
8989const char *ruleName[] = {
8990 /* 0 */ "UNIVERSE",
8991 /* 1 */ "LABEL",
8992 /* 2 */ "SREGI",
8993 /* 3 */ "SREGP",
8994 /* 4 */ "SREGF",
8995 /* 5 */ "SREGD",
8996 /* 6 */ "SREGL",
8997 /* 7 */ "METHOD",
8998 /* 8 */ "IMMI",
8999 /* 9 */ "IMMI0",
9000 /* 10 */ "IMMI1",
9001 /* 11 */ "IMMI_M1",
9002 /* 12 */ "IMMI2",
9003 /* 13 */ "IMMI8",
9004 /* 14 */ "IMMU8",
9005 /* 15 */ "IMMI16",
9006 /* 16 */ "IMMU31",
9007 /* 17 */ "IMMI_32",
9008 /* 18 */ "IMMI_64",
9009 /* 19 */ "IMMP",
9010 /* 20 */ "IMMP0",
9011 /* 21 */ "IMMN",
9012 /* 22 */ "IMMNKLASS",
9013 /* 23 */ "IMMN0",
9014 /* 24 */ "IMMP31",
9015 /* 25 */ "IMML",
9016 /* 26 */ "IMML8",
9017 /* 27 */ "IMMUL32",
9018 /* 28 */ "IMML32",
9019 /* 29 */ "IMML0",
9020 /* 30 */ "IMML1",
9021 /* 31 */ "IMML_M1",
9022 /* 32 */ "IMML10",
9023 /* 33 */ "IMML_127",
9024 /* 34 */ "IMML_32BITS",
9025 /* 35 */ "IMMF0",
9026 /* 36 */ "IMMF",
9027 /* 37 */ "IMMD0",
9028 /* 38 */ "IMMD",
9029 /* 39 */ "IMMI_16",
9030 /* 40 */ "IMMI_24",
9031 /* 41 */ "IMMI_255",
9032 /* 42 */ "IMMI_65535",
9033 /* 43 */ "IMML_255",
9034 /* 44 */ "IMML_65535",
9035 /* 45 */ "RREGI",
9036 /* 46 */ "RAX_REGI",
9037 /* 47 */ "RBX_REGI",
9038 /* 48 */ "RCX_REGI",
9039 /* 49 */ "RDX_REGI",
9040 /* 50 */ "RDI_REGI",
9041 /* 51 */ "NO_RCX_REGI",
9042 /* 52 */ "NO_RAX_RDX_REGI",
9043 /* 53 */ "ANY_REGP",
9044 /* 54 */ "RREGP",
9045 /* 55 */ "RREGN",
9046 /* 56 */ "NO_RAX_REGP",
9047 /* 57 */ "NO_RBP_REGP",
9048 /* 58 */ "NO_RAX_RBX_REGP",
9049 /* 59 */ "RAX_REGP",
9050 /* 60 */ "RAX_REGN",
9051 /* 61 */ "RBX_REGP",
9052 /* 62 */ "RSI_REGP",
9053 /* 63 */ "RDI_REGP",
9054 /* 64 */ "R15_REGP",
9055 /* 65 */ "RREGL",
9056 /* 66 */ "NO_RAX_RDX_REGL",
9057 /* 67 */ "NO_RAX_REGL",
9058 /* 68 */ "NO_RCX_REGL",
9059 /* 69 */ "RAX_REGL",
9060 /* 70 */ "RCX_REGL",
9061 /* 71 */ "RDX_REGL",
9062 /* 72 */ "RFLAGSREG",
9063 /* 73 */ "RFLAGSREGU",
9064 /* 74 */ "RFLAGSREGUCF",
9065 /* 75 */ "REGF",
9066 /* 76 */ "LEGREGF",
9067 /* 77 */ "VLREGF",
9068 /* 78 */ "REGD",
9069 /* 79 */ "LEGREGD",
9070 /* 80 */ "VLREGD",
9071 /* 81 */ "VECS",
9072 /* 82 */ "LEGVECS",
9073 /* 83 */ "VECD",
9074 /* 84 */ "LEGVECD",
9075 /* 85 */ "VECX",
9076 /* 86 */ "LEGVECX",
9077 /* 87 */ "VECY",
9078 /* 88 */ "LEGVECY",
9079 /* 89 */ "INDIRECT",
9080 /* 90 */ "INDOFFSET8",
9081 /* 91 */ "INDOFFSET32",
9082 /* 92 */ "INDINDEXOFFSET",
9083 /* 93 */ "INDINDEX",
9084 /* 94 */ "INDINDEXSCALE",
9085 /* 95 */ "INDPOSINDEXSCALE",
9086 /* 96 */ "INDINDEXSCALEOFFSET",
9087 /* 97 */ "INDPOSINDEXOFFSET",
9088 /* 98 */ "INDPOSINDEXSCALEOFFSET",
9089 /* 99 */ "INDCOMPRESSEDOOPOFFSET",
9090 /* 100 */ "INDIRECTNARROW",
9091 /* 101 */ "INDOFFSET8NARROW",
9092 /* 102 */ "INDOFFSET32NARROW",
9093 /* 103 */ "INDINDEXOFFSETNARROW",
9094 /* 104 */ "INDINDEXNARROW",
9095 /* 105 */ "INDINDEXSCALENARROW",
9096 /* 106 */ "INDINDEXSCALEOFFSETNARROW",
9097 /* 107 */ "INDPOSINDEXOFFSETNARROW",
9098 /* 108 */ "INDPOSINDEXSCALEOFFSETNARROW",
9099 /* 109 */ "STACKSLOTP",
9100 /* 110 */ "STACKSLOTI",
9101 /* 111 */ "STACKSLOTF",
9102 /* 112 */ "STACKSLOTD",
9103 /* 113 */ "STACKSLOTL",
9104 /* 114 */ "CMPOP",
9105 /* 115 */ "CMPOPU",
9106 /* 116 */ "CMPOPUCF",
9107 /* 117 */ "CMPOPUCF2",
9108 /* 118 */ "RXMM0",
9109 /* 119 */ "RXMM1",
9110 /* 120 */ "RXMM2",
9111 /* 121 */ "RXMM3",
9112 /* 122 */ "RXMM4",
9113 /* 123 */ "RXMM5",
9114 /* 124 */ "RXMM6",
9115 /* 125 */ "RXMM7",
9116 /* 126 */ "RXMM8",
9117 /* 127 */ "RXMM9",
9118 /* 128 */ "RXMM10",
9119 /* 129 */ "RXMM11",
9120 /* 130 */ "RXMM12",
9121 /* 131 */ "RXMM13",
9122 /* 132 */ "RXMM14",
9123 /* 133 */ "RXMM15",
9124 /* 134 */ "RXMM16",
9125 /* 135 */ "RXMM17",
9126 /* 136 */ "RXMM18",
9127 /* 137 */ "RXMM19",
9128 /* 138 */ "RXMM20",
9129 /* 139 */ "RXMM21",
9130 /* 140 */ "RXMM22",
9131 /* 141 */ "RXMM23",
9132 /* 142 */ "RXMM24",
9133 /* 143 */ "RXMM25",
9134 /* 144 */ "RXMM26",
9135 /* 145 */ "RXMM27",
9136 /* 146 */ "RXMM28",
9137 /* 147 */ "RXMM29",
9138 /* 148 */ "RXMM30",
9139 /* 149 */ "RXMM31",
9140 /* 150 */ "VECZ",
9141 /* 151 */ "LEGVECZ",
9142 /* 152 */ "CMPOP_VCMPPD",
9143 // last operand
9144 /* 153 */ "MEMORY",
9145 // last operand class
9146 /* 154 */ "_AddP_any_RegP_rRegL",
9147 /* 155 */ "_LShiftL_rRegL_immI2",
9148 /* 156 */ "_ConvI2L_rRegI_",
9149 /* 157 */ "_LShiftL__ConvI2L_rRegI__immI2",
9150 /* 158 */ "_AddP_any_RegP__LShiftL_rRegL_immI2",
9151 /* 159 */ "_AddP_any_RegP__ConvI2L_rRegI_",
9152 /* 160 */ "_AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2",
9153 /* 161 */ "_DecodeN_rRegN_",
9154 /* 162 */ "_AddP__DecodeN_rRegN__rRegL",
9155 /* 163 */ "_AddP__DecodeN_rRegN___LShiftL_rRegL_immI2",
9156 /* 164 */ "_AddP__DecodeN_rRegN___ConvI2L_rRegI_",
9157 /* 165 */ "_AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2",
9158 /* 166 */ "_LoadB_memory_",
9159 /* 167 */ "_LoadUB_memory_",
9160 /* 168 */ "_AndI__LoadUB_memory__immI",
9161 /* 169 */ "_LoadS_memory_",
9162 /* 170 */ "_LShiftI__LoadS_memory__immI_24",
9163 /* 171 */ "_LoadUS_memory_",
9164 /* 172 */ "_LShiftI__LoadUS_memory__immI_24",
9165 /* 173 */ "_AndI__LoadUS_memory__immI_255",
9166 /* 174 */ "_AndI__LoadUS_memory__immI",
9167 /* 175 */ "_LoadI_memory_",
9168 /* 176 */ "_LShiftI__LoadI_memory__immI_24",
9169 /* 177 */ "_LShiftI__LoadI_memory__immI_16",
9170 /* 178 */ "_AndI__LoadI_memory__immI_255",
9171 /* 179 */ "_AndI__LoadI_memory__immI_65535",
9172 /* 180 */ "_AndI__LoadI_memory__immU31",
9173 /* 181 */ "_ConvI2L__LoadI_memory__",
9174 /* 182 */ "_LoadL_memory_",
9175 /* 183 */ "_CastP2X_rRegP_",
9176 /* 184 */ "_CastP2X__DecodeN_rRegN__",
9177 /* 185 */ "_AddL__LShiftL_rRegL_immI2_immL32",
9178 /* 186 */ "_Binary_cmpOp_rFlagsReg",
9179 /* 187 */ "_Binary_rRegI_rRegI",
9180 /* 188 */ "_Binary_cmpOpU_rFlagsRegU",
9181 /* 189 */ "_Binary_cmpOpUCF_rFlagsRegUCF",
9182 /* 190 */ "_Binary_rRegI__LoadI_memory_",
9183 /* 191 */ "_Binary_rRegN_rRegN",
9184 /* 192 */ "_Binary_rRegP_rRegP",
9185 /* 193 */ "_Binary_rRegL_rRegL",
9186 /* 194 */ "_Binary_rRegL__LoadL_memory_",
9187 /* 195 */ "_Binary_regF_regF",
9188 /* 196 */ "_Binary_regD_regD",
9189 /* 197 */ "_AddI__LoadI_memory__rRegI",
9190 /* 198 */ "_AddI_rRegI__LoadI_memory_",
9191 /* 199 */ "_AddI__LoadI_memory__immI",
9192 /* 200 */ "_AddI__LoadI_memory__immI1",
9193 /* 201 */ "_AddI__LoadI_memory__immI_M1",
9194 /* 202 */ "_AddL__LoadL_memory__rRegL",
9195 /* 203 */ "_AddL_rRegL__LoadL_memory_",
9196 /* 204 */ "_AddL__LoadL_memory__immL32",
9197 /* 205 */ "_AddL__LoadL_memory__immL1",
9198 /* 206 */ "_AddL__LoadL_memory__immL_M1",
9199 /* 207 */ "_Binary_rax_RegP_rRegP",
9200 /* 208 */ "_Binary_rax_RegI_rRegI",
9201 /* 209 */ "_Binary_rax_RegL_rRegL",
9202 /* 210 */ "_Binary_rax_RegN_rRegN",
9203 /* 211 */ "_SubI__LoadI_memory__rRegI",
9204 /* 212 */ "_SubI__LoadI_memory__immI",
9205 /* 213 */ "_SubL__LoadL_memory__rRegL",
9206 /* 214 */ "_SubL__LoadL_memory__immL32",
9207 /* 215 */ "_SubI_immI0_rRegI",
9208 /* 216 */ "_SubI_immI0__LoadI_memory_",
9209 /* 217 */ "_SubL_immL0__LoadL_memory_",
9210 /* 218 */ "_LShiftI__LoadI_memory__immI1",
9211 /* 219 */ "_LShiftI__LoadI_memory__immI8",
9212 /* 220 */ "_LShiftI__LoadI_memory__rcx_RegI",
9213 /* 221 */ "_RShiftI__LoadI_memory__immI1",
9214 /* 222 */ "_RShiftI__LoadI_memory__immI8",
9215 /* 223 */ "_RShiftI__LoadI_memory__rcx_RegI",
9216 /* 224 */ "_URShiftI__LoadI_memory__immI1",
9217 /* 225 */ "_URShiftI__LoadI_memory__immI8",
9218 /* 226 */ "_URShiftI__LoadI_memory__rcx_RegI",
9219 /* 227 */ "_LShiftL__LoadL_memory__immI1",
9220 /* 228 */ "_LShiftL__LoadL_memory__immI8",
9221 /* 229 */ "_LShiftL__LoadL_memory__rcx_RegI",
9222 /* 230 */ "_RShiftL__LoadL_memory__immI1",
9223 /* 231 */ "_RShiftL__LoadL_memory__immI8",
9224 /* 232 */ "_RShiftL__LoadL_memory__rcx_RegI",
9225 /* 233 */ "_URShiftL__LoadL_memory__immI1",
9226 /* 234 */ "_URShiftL__LoadL_memory__immI8",
9227 /* 235 */ "_URShiftL__LoadL_memory__rcx_RegI",
9228 /* 236 */ "_LShiftI_rRegI_immI_24",
9229 /* 237 */ "_LShiftI_rRegI_immI_16",
9230 /* 238 */ "_LShiftI_rRegI_immI1",
9231 /* 239 */ "_URShiftI_rRegI_immI_M1",
9232 /* 240 */ "_LShiftI_rRegI_immI8",
9233 /* 241 */ "_URShiftI_rRegI_immI8",
9234 /* 242 */ "_LShiftI_no_rcx_RegI_rcx_RegI",
9235 /* 243 */ "_SubI_immI0_rcx_RegI",
9236 /* 244 */ "_URShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI",
9237 /* 245 */ "_SubI_immI_32_rcx_RegI",
9238 /* 246 */ "_URShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI",
9239 /* 247 */ "_URShiftI_rRegI_immI1",
9240 /* 248 */ "_LShiftI_rRegI_immI_M1",
9241 /* 249 */ "_URShiftI_no_rcx_RegI_rcx_RegI",
9242 /* 250 */ "_LShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI",
9243 /* 251 */ "_LShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI",
9244 /* 252 */ "_LShiftL_rRegL_immI1",
9245 /* 253 */ "_URShiftL_rRegL_immI_M1",
9246 /* 254 */ "_LShiftL_rRegL_immI8",
9247 /* 255 */ "_URShiftL_rRegL_immI8",
9248 /* 256 */ "_LShiftL_no_rcx_RegL_rcx_RegI",
9249 /* 257 */ "_URShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI",
9250 /* 258 */ "_SubI_immI_64_rcx_RegI",
9251 /* 259 */ "_URShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI",
9252 /* 260 */ "_URShiftL_rRegL_immI1",
9253 /* 261 */ "_LShiftL_rRegL_immI_M1",
9254 /* 262 */ "_URShiftL_no_rcx_RegL_rcx_RegI",
9255 /* 263 */ "_LShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI",
9256 /* 264 */ "_LShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI",
9257 /* 265 */ "_AndI_rRegI_immI_255",
9258 /* 266 */ "_AndI_rRegI_immI_65535",
9259 /* 267 */ "_AndI__LoadB_memory__rRegI",
9260 /* 268 */ "_AndI_rRegI__LoadB_memory_",
9261 /* 269 */ "_AndI__LoadI_memory__rRegI",
9262 /* 270 */ "_AndI_rRegI__LoadI_memory_",
9263 /* 271 */ "_AndI__LoadI_memory__immI",
9264 /* 272 */ "_XorI_rRegI_immI_M1",
9265 /* 273 */ "_AddI_rRegI_immI_M1",
9266 /* 274 */ "_OrI__LoadB_memory__rRegI",
9267 /* 275 */ "_OrI_rRegI__LoadB_memory_",
9268 /* 276 */ "_OrI__LoadI_memory__rRegI",
9269 /* 277 */ "_OrI_rRegI__LoadI_memory_",
9270 /* 278 */ "_OrI__LoadI_memory__immI",
9271 /* 279 */ "_XorI__LoadB_memory__rRegI",
9272 /* 280 */ "_XorI_rRegI__LoadB_memory_",
9273 /* 281 */ "_XorI__LoadI_memory__rRegI",
9274 /* 282 */ "_XorI_rRegI__LoadI_memory_",
9275 /* 283 */ "_XorI__LoadI_memory__immI",
9276 /* 284 */ "_AndL__LoadL_memory__rRegL",
9277 /* 285 */ "_AndL_rRegL__LoadL_memory_",
9278 /* 286 */ "_AndL__LoadL_memory__immL32",
9279 /* 287 */ "_XorL_rRegL_immL_M1",
9280 /* 288 */ "_SubL_immL0_rRegL",
9281 /* 289 */ "_AddL_rRegL_immL_M1",
9282 /* 290 */ "_CastP2X_any_RegP_",
9283 /* 291 */ "_OrL__LoadL_memory__rRegL",
9284 /* 292 */ "_OrL_rRegL__LoadL_memory_",
9285 /* 293 */ "_OrL__LoadL_memory__immL32",
9286 /* 294 */ "_XorL__LoadL_memory__rRegL",
9287 /* 295 */ "_XorL_rRegL__LoadL_memory_",
9288 /* 296 */ "_XorL__LoadL_memory__immL32",
9289 /* 297 */ "_CmpLTMask_rRegI_rRegI",
9290 /* 298 */ "_AndI__CmpLTMask_rRegI_rRegI_rRegI",
9291 /* 299 */ "_SubI_rRegI_rRegI",
9292 /* 300 */ "_AndI_rRegI__CmpLTMask_rRegI_rRegI",
9293 /* 301 */ "_LoadF_memory_",
9294 /* 302 */ "_LoadD_memory_",
9295 /* 303 */ "_Binary_rdi_RegP_rcx_RegI",
9296 /* 304 */ "_Binary_rsi_RegP_rdx_RegI",
9297 /* 305 */ "_Binary_rdi_RegP_rdx_RegI",
9298 /* 306 */ "_Binary_rsi_RegP_immI",
9299 /* 307 */ "_Binary_rsi_RegP_rax_RegI",
9300 /* 308 */ "_Binary_rdi_RegP_rsi_RegP",
9301 /* 309 */ "_AndI_rRegI_immI",
9302 /* 310 */ "_LoadP_memory_",
9303 /* 311 */ "_LoadN_memory_",
9304 /* 312 */ "_LoadNKlass_memory_",
9305 /* 313 */ "_AndL_rRegL_immL32",
9306 /* 314 */ "_AndL__CastP2X_rRegP___LoadL_memory_",
9307 /* 315 */ "_AndL__LoadL_memory___CastP2X_rRegP_",
9308 /* 316 */ "_AndI__LoadUB_memory__immU8",
9309 /* 317 */ "_AndI__LoadB_memory__immI8",
9310 /* 318 */ "_PartialSubtypeCheck_rsi_RegP_rax_RegP",
9311 /* 319 */ "_LoadVector_memory_",
9312 /* 320 */ "_Binary_cmpOp_vcmppd_immI8",
9313 /* 321 */ "_Binary_legVecY_legVecY",
9314 /* 322 */ "_Binary_vecX_vecX",
9315 /* 323 */ "_Binary_vecX__LoadVector_memory_",
9316 /* 324 */ "_Binary_vecY_vecY",
9317 /* 325 */ "_Binary_vecY__LoadVector_memory_",
9318 /* 326 */ "_Binary_vecZ_vecZ",
9319 /* 327 */ "_Binary_vecZ__LoadVector_memory_",
9320 /* 328 */ "_MulAddVS2VI_vecD_vecD",
9321 /* 329 */ "_MulAddVS2VI_vecX_vecX",
9322 /* 330 */ "_MulAddVS2VI_vecY_vecY",
9323 /* 331 */ "_MulAddVS2VI_vecZ_vecZ",
9324 /* 332 */ "_Binary_memory_rRegP",
9325 // last internally defined operand
9326 /* 333 */ "storeSSI",
9327 /* 334 */ "storeSSL",
9328 /* 335 */ "storeSSP",
9329 /* 336 */ "storeSSF",
9330 /* 337 */ "storeSSD",
9331 /* 338 */ "MoveF2VL",
9332 /* 339 */ "MoveF2LEG",
9333 /* 340 */ "MoveVL2F",
9334 /* 341 */ "MoveLEG2F",
9335 /* 342 */ "MoveD2VL",
9336 /* 343 */ "MoveD2LEG",
9337 /* 344 */ "MoveVL2D",
9338 /* 345 */ "MoveLEG2D",
9339 /* 346 */ "leaP8",
9340 /* 347 */ "leaP32",
9341 /* 348 */ "leaPIdxOff",
9342 /* 349 */ "leaPIdxScale",
9343 /* 350 */ "leaPPosIdxScale",
9344 /* 351 */ "leaPIdxScaleOff",
9345 /* 352 */ "leaPPosIdxOff",
9346 /* 353 */ "leaPPosIdxScaleOff",
9347 /* 354 */ "leaPCompressedOopOffset",
9348 /* 355 */ "leaP8Narrow",
9349 /* 356 */ "leaP32Narrow",
9350 /* 357 */ "leaPIdxOffNarrow",
9351 /* 358 */ "leaPIdxScaleNarrow",
9352 /* 359 */ "leaPIdxScaleOffNarrow",
9353 /* 360 */ "leaPPosIdxOffNarrow",
9354 /* 361 */ "leaPPosIdxScaleOffNarrow",
9355 /* 362 */ "loadConI",
9356 /* 363 */ "loadConI0",
9357 /* 364 */ "loadConL",
9358 /* 365 */ "loadConL0",
9359 /* 366 */ "loadConUL32",
9360 /* 367 */ "loadConL32",
9361 /* 368 */ "loadConP",
9362 /* 369 */ "loadConP0",
9363 /* 370 */ "loadConP31",
9364 /* 371 */ "loadConF",
9365 /* 372 */ "loadConN0",
9366 /* 373 */ "loadConN",
9367 /* 374 */ "loadConNKlass",
9368 /* 375 */ "loadConF0",
9369 /* 376 */ "loadConD",
9370 /* 377 */ "loadConD0",
9371 /* 378 */ "loadSSI",
9372 /* 379 */ "loadSSL",
9373 /* 380 */ "loadSSP",
9374 /* 381 */ "loadSSF",
9375 /* 382 */ "loadSSD",
9376 /* 383 */ "MoveVecS2Leg",
9377 /* 384 */ "MoveLeg2VecS",
9378 /* 385 */ "MoveVecD2Leg",
9379 /* 386 */ "MoveLeg2VecD",
9380 /* 387 */ "MoveVecX2Leg",
9381 /* 388 */ "MoveLeg2VecX",
9382 /* 389 */ "MoveVecY2Leg",
9383 /* 390 */ "MoveLeg2VecY",
9384 /* 391 */ "MoveVecZ2Leg",
9385 /* 392 */ "MoveLeg2VecZ",
9386 /* 393 */ "vshiftcntimm",
9387 /* 394 */ "membar_volatile",
9388 /* 395 */ "castX2P",
9389 /* 396 */ "castP2X",
9390 /* 397 */ "checkCastPP",
9391 /* 398 */ "castPP",
9392 /* 399 */ "castII",
9393 /* 400 */ "storePConditional",
9394 /* 401 */ "storeIConditional",
9395 /* 402 */ "storeLConditional",
9396 /* 403 */ "cmpF_cc_reg",
9397 /* 404 */ "cmpF_cc_reg_CF",
9398 /* 405 */ "cmpF_cc_mem",
9399 /* 406 */ "cmpF_cc_memCF",
9400 /* 407 */ "cmpF_cc_imm",
9401 /* 408 */ "cmpF_cc_immCF",
9402 /* 409 */ "cmpD_cc_reg",
9403 /* 410 */ "cmpD_cc_reg_CF",
9404 /* 411 */ "cmpD_cc_mem",
9405 /* 412 */ "cmpD_cc_memCF",
9406 /* 413 */ "cmpD_cc_imm",
9407 /* 414 */ "cmpD_cc_immCF",
9408 /* 415 */ "roundFloat_nop",
9409 /* 416 */ "roundDouble_nop",
9410 /* 417 */ "MoveF2I_stack_reg",
9411 /* 418 */ "MoveI2F_stack_reg",
9412 /* 419 */ "MoveD2L_stack_reg",
9413 /* 420 */ "MoveL2D_stack_reg_partial",
9414 /* 421 */ "MoveL2D_stack_reg",
9415 /* 422 */ "MoveF2I_reg_reg",
9416 /* 423 */ "MoveD2L_reg_reg",
9417 /* 424 */ "MoveI2F_reg_reg",
9418 /* 425 */ "MoveL2D_reg_reg",
9419 /* 426 */ "overflowAddI_rReg",
9420 /* 427 */ "overflowAddI_rReg_imm",
9421 /* 428 */ "overflowAddL_rReg",
9422 /* 429 */ "overflowAddL_rReg_imm",
9423 /* 430 */ "overflowSubI_rReg",
9424 /* 431 */ "overflowSubI_rReg_imm",
9425 /* 432 */ "overflowSubL_rReg",
9426 /* 433 */ "overflowSubL_rReg_imm",
9427 /* 434 */ "overflowNegI_rReg",
9428 /* 435 */ "overflowNegL_rReg",
9429 /* 436 */ "overflowMulI_rReg",
9430 /* 437 */ "overflowMulI_rReg_imm",
9431 /* 438 */ "overflowMulL_rReg",
9432 /* 439 */ "overflowMulL_rReg_imm",
9433 /* 440 */ "compI_rReg",
9434 /* 441 */ "compI_rReg_imm",
9435 /* 442 */ "compI_rReg_mem",
9436 /* 443 */ "testI_reg",
9437 /* 444 */ "testI_reg_imm",
9438 /* 445 */ "testI_reg_mem",
9439 /* 446 */ "testI_reg_mem_0",
9440 /* 447 */ "compU_rReg",
9441 /* 448 */ "compU_rReg_imm",
9442 /* 449 */ "compU_rReg_mem",
9443 /* 450 */ "testU_reg",
9444 /* 451 */ "compP_rReg",
9445 /* 452 */ "compP_rReg_mem",
9446 /* 453 */ "compP_mem_rReg",
9447 /* 454 */ "testP_reg",
9448 /* 455 */ "testP_mem",
9449 /* 456 */ "testP_mem_reg0",
9450 /* 457 */ "compN_rReg",
9451 /* 458 */ "compN_rReg_mem",
9452 /* 459 */ "compN_rReg_imm",
9453 /* 460 */ "compN_mem_imm",
9454 /* 461 */ "compN_rReg_imm_klass",
9455 /* 462 */ "compN_mem_imm_klass",
9456 /* 463 */ "testN_reg",
9457 /* 464 */ "testN_mem",
9458 /* 465 */ "testN_mem_reg0",
9459 /* 466 */ "compL_rReg",
9460 /* 467 */ "compL_rReg_imm",
9461 /* 468 */ "compL_rReg_mem",
9462 /* 469 */ "testL_reg",
9463 /* 470 */ "testL_reg_imm",
9464 /* 471 */ "testL_reg_mem",
9465 /* 472 */ "testL_reg_mem_0",
9466 /* 473 */ "testL_reg_mem2",
9467 /* 474 */ "testL_reg_mem2_0",
9468 /* 475 */ "compUL_rReg",
9469 /* 476 */ "compUL_rReg_imm",
9470 /* 477 */ "compUL_rReg_mem",
9471 /* 478 */ "testUL_reg",
9472 /* 479 */ "compB_mem_imm",
9473 /* 480 */ "testUB_mem_imm",
9474 /* 481 */ "testB_mem_imm",
9475 /* 482 */ "partialSubtypeCheck_vs_Zero",
9476 /* 483 */ "cmpFastLockRTM",
9477 /* 484 */ "cmpFastLock",
9478 /* 485 */ "cmpFastUnlock",
9479 /* 486 */ "safePoint_poll",
9480 /* 487 */ "tlsLoadP",
9481 /* 488 */ "absF_reg",
9482 /* 489 */ "absF_reg_reg",
9483 /* 490 */ "absD_reg",
9484 /* 491 */ "absD_reg_reg",
9485 /* 492 */ "negF_reg",
9486 /* 493 */ "negF_reg_reg",
9487 /* 494 */ "negD_reg",
9488 /* 495 */ "negD_reg_reg",
9489 /* 496 */ "vsqrt2D_reg",
9490 /* 497 */ "vsqrt2D_mem",
9491 /* 498 */ "vsqrt4D_reg",
9492 /* 499 */ "vsqrt4D_mem",
9493 /* 500 */ "vsqrt8D_reg",
9494 /* 501 */ "vsqrt8D_mem",
9495 /* 502 */ "vsqrt2F_reg",
9496 /* 503 */ "vsqrt2F_mem",
9497 /* 504 */ "vsqrt4F_reg",
9498 /* 505 */ "vsqrt4F_mem",
9499 /* 506 */ "vsqrt8F_reg",
9500 /* 507 */ "vsqrt8F_mem",
9501 /* 508 */ "vsqrt16F_reg",
9502 /* 509 */ "vsqrt16F_mem",
9503 /* 510 */ "vshiftcnt",
9504 /* 511 */ "vshiftcnt_0",
9505 /* 512 */ "vabs4B_reg",
9506 /* 513 */ "vabs8B_reg",
9507 /* 514 */ "vabs16B_reg",
9508 /* 515 */ "vabs32B_reg",
9509 /* 516 */ "vabs64B_reg",
9510 /* 517 */ "vabs2S_reg",
9511 /* 518 */ "vabs4S_reg",
9512 /* 519 */ "vabs8S_reg",
9513 /* 520 */ "vabs16S_reg",
9514 /* 521 */ "vabs32S_reg",
9515 /* 522 */ "vabs2I_reg",
9516 /* 523 */ "vabs4I_reg",
9517 /* 524 */ "vabs8I_reg",
9518 /* 525 */ "vabs16I_reg",
9519 /* 526 */ "vabs2L_reg",
9520 /* 527 */ "vabs4L_reg",
9521 /* 528 */ "vabs8L_reg",
9522 /* 529 */ "vpopcount2I",
9523 /* 530 */ "vpopcount4I",
9524 /* 531 */ "vpopcount8I",
9525 /* 532 */ "vpopcount16I",
9526 /* 533 */ "loadB",
9527 /* 534 */ "loadB2L",
9528 /* 535 */ "loadUB",
9529 /* 536 */ "loadUB2L",
9530 /* 537 */ "loadUB2L_immI",
9531 /* 538 */ "loadS",
9532 /* 539 */ "loadS2B",
9533 /* 540 */ "loadS2L",
9534 /* 541 */ "loadUS",
9535 /* 542 */ "loadUS2B",
9536 /* 543 */ "loadUS2L",
9537 /* 544 */ "loadUS2L_immI_255",
9538 /* 545 */ "loadUS2L_immI",
9539 /* 546 */ "loadI",
9540 /* 547 */ "loadI2B",
9541 /* 548 */ "loadI2UB",
9542 /* 549 */ "loadI2S",
9543 /* 550 */ "loadI2US",
9544 /* 551 */ "loadI2L",
9545 /* 552 */ "loadI2L_immI_255",
9546 /* 553 */ "loadI2L_immI_65535",
9547 /* 554 */ "loadI2L_immU31",
9548 /* 555 */ "loadUI2L",
9549 /* 556 */ "loadL",
9550 /* 557 */ "loadRange",
9551 /* 558 */ "loadP",
9552 /* 559 */ "loadN",
9553 /* 560 */ "loadKlass",
9554 /* 561 */ "loadNKlass",
9555 /* 562 */ "loadF",
9556 /* 563 */ "loadD_partial",
9557 /* 564 */ "loadD",
9558 /* 565 */ "maxF_reg",
9559 /* 566 */ "maxF_reduction_reg",
9560 /* 567 */ "maxD_reg",
9561 /* 568 */ "maxD_reduction_reg",
9562 /* 569 */ "minF_reg",
9563 /* 570 */ "minF_reduction_reg",
9564 /* 571 */ "minD_reg",
9565 /* 572 */ "minD_reduction_reg",
9566 /* 573 */ "prefetchAlloc",
9567 /* 574 */ "prefetchAllocNTA",
9568 /* 575 */ "prefetchAllocT0",
9569 /* 576 */ "prefetchAllocT2",
9570 /* 577 */ "storeB",
9571 /* 578 */ "storeC",
9572 /* 579 */ "storeI",
9573 /* 580 */ "storeL",
9574 /* 581 */ "storeP",
9575 /* 582 */ "storeImmP0",
9576 /* 583 */ "storeImmP",
9577 /* 584 */ "storeN",
9578 /* 585 */ "storeNKlass",
9579 /* 586 */ "storeImmN0",
9580 /* 587 */ "storeImmN",
9581 /* 588 */ "storeImmNKlass",
9582 /* 589 */ "storeImmI0",
9583 /* 590 */ "storeImmI",
9584 /* 591 */ "storeImmL0",
9585 /* 592 */ "storeImmL",
9586 /* 593 */ "storeImmC0",
9587 /* 594 */ "storeImmI16",
9588 /* 595 */ "storeImmB0",
9589 /* 596 */ "storeImmB",
9590 /* 597 */ "storeImmCM0_reg",
9591 /* 598 */ "storeImmCM0",
9592 /* 599 */ "storeF",
9593 /* 600 */ "storeF0",
9594 /* 601 */ "storeF_imm",
9595 /* 602 */ "storeD",
9596 /* 603 */ "storeD0_imm",
9597 /* 604 */ "storeD0",
9598 /* 605 */ "bytes_reverse_int",
9599 /* 606 */ "bytes_reverse_long",
9600 /* 607 */ "bytes_reverse_unsigned_short",
9601 /* 608 */ "bytes_reverse_short",
9602 /* 609 */ "countLeadingZerosI",
9603 /* 610 */ "countLeadingZerosI_bsr",
9604 /* 611 */ "countLeadingZerosL",
9605 /* 612 */ "countLeadingZerosL_bsr",
9606 /* 613 */ "countTrailingZerosI",
9607 /* 614 */ "countTrailingZerosI_bsf",
9608 /* 615 */ "countTrailingZerosL",
9609 /* 616 */ "countTrailingZerosL_bsf",
9610 /* 617 */ "popCountI",
9611 /* 618 */ "popCountI_mem",
9612 /* 619 */ "popCountL",
9613 /* 620 */ "popCountL_mem",
9614 /* 621 */ "membar_acquire",
9615 /* 622 */ "membar_acquire_0",
9616 /* 623 */ "membar_acquire_lock",
9617 /* 624 */ "membar_release",
9618 /* 625 */ "membar_release_0",
9619 /* 626 */ "membar_release_lock",
9620 /* 627 */ "unnecessary_membar_volatile",
9621 /* 628 */ "membar_storestore",
9622 /* 629 */ "convP2I",
9623 /* 630 */ "convN2I",
9624 /* 631 */ "encodeHeapOop",
9625 /* 632 */ "encodeHeapOop_not_null",
9626 /* 633 */ "decodeHeapOop",
9627 /* 634 */ "decodeHeapOop_not_null",
9628 /* 635 */ "encodeKlass_not_null",
9629 /* 636 */ "decodeKlass_not_null",
9630 /* 637 */ "jumpXtnd_offset",
9631 /* 638 */ "jumpXtnd_addr",
9632 /* 639 */ "jumpXtnd",
9633 /* 640 */ "cmovI_reg",
9634 /* 641 */ "cmovI_regU",
9635 /* 642 */ "cmovI_regUCF",
9636 /* 643 */ "cmovI_mem",
9637 /* 644 */ "cmovI_memU",
9638 /* 645 */ "cmovI_memUCF",
9639 /* 646 */ "cmovN_reg",
9640 /* 647 */ "cmovN_regU",
9641 /* 648 */ "cmovN_regUCF",
9642 /* 649 */ "cmovP_reg",
9643 /* 650 */ "cmovP_regU",
9644 /* 651 */ "cmovP_regUCF",
9645 /* 652 */ "cmovL_reg",
9646 /* 653 */ "cmovL_mem",
9647 /* 654 */ "cmovL_regU",
9648 /* 655 */ "cmovL_regUCF",
9649 /* 656 */ "cmovL_memU",
9650 /* 657 */ "cmovL_memUCF",
9651 /* 658 */ "cmovF_reg",
9652 /* 659 */ "cmovF_regU",
9653 /* 660 */ "cmovF_regUCF",
9654 /* 661 */ "cmovD_reg",
9655 /* 662 */ "cmovD_regU",
9656 /* 663 */ "cmovD_regUCF",
9657 /* 664 */ "addI_rReg",
9658 /* 665 */ "addI_rReg_imm",
9659 /* 666 */ "addI_rReg_mem",
9660 /* 667 */ "addI_rReg_mem_0",
9661 /* 668 */ "addI_mem_rReg",
9662 /* 669 */ "addI_mem_rReg_0",
9663 /* 670 */ "addI_mem_imm",
9664 /* 671 */ "incI_rReg",
9665 /* 672 */ "incI_mem",
9666 /* 673 */ "decI_rReg",
9667 /* 674 */ "decI_mem",
9668 /* 675 */ "leaI_rReg_immI",
9669 /* 676 */ "addL_rReg",
9670 /* 677 */ "addL_rReg_imm",
9671 /* 678 */ "addL_rReg_mem",
9672 /* 679 */ "addL_rReg_mem_0",
9673 /* 680 */ "addL_mem_rReg",
9674 /* 681 */ "addL_mem_rReg_0",
9675 /* 682 */ "addL_mem_imm",
9676 /* 683 */ "incL_rReg",
9677 /* 684 */ "incL_mem",
9678 /* 685 */ "decL_rReg",
9679 /* 686 */ "decL_mem",
9680 /* 687 */ "leaL_rReg_immL",
9681 /* 688 */ "addP_rReg",
9682 /* 689 */ "addP_rReg_imm",
9683 /* 690 */ "leaP_rReg_imm",
9684 /* 691 */ "loadPLocked",
9685 /* 692 */ "compareAndSwapP",
9686 /* 693 */ "compareAndSwapP_0",
9687 /* 694 */ "compareAndSwapL",
9688 /* 695 */ "compareAndSwapL_0",
9689 /* 696 */ "compareAndSwapI",
9690 /* 697 */ "compareAndSwapI_0",
9691 /* 698 */ "compareAndSwapB",
9692 /* 699 */ "compareAndSwapB_0",
9693 /* 700 */ "compareAndSwapS",
9694 /* 701 */ "compareAndSwapS_0",
9695 /* 702 */ "compareAndSwapN",
9696 /* 703 */ "compareAndSwapN_0",
9697 /* 704 */ "compareAndExchangeB",
9698 /* 705 */ "compareAndExchangeS",
9699 /* 706 */ "compareAndExchangeI",
9700 /* 707 */ "compareAndExchangeL",
9701 /* 708 */ "compareAndExchangeN",
9702 /* 709 */ "compareAndExchangeP",
9703 /* 710 */ "xaddB_no_res",
9704 /* 711 */ "xaddB",
9705 /* 712 */ "xaddS_no_res",
9706 /* 713 */ "xaddS",
9707 /* 714 */ "xaddI_no_res",
9708 /* 715 */ "xaddI",
9709 /* 716 */ "xaddL_no_res",
9710 /* 717 */ "xaddL",
9711 /* 718 */ "xchgB",
9712 /* 719 */ "xchgS",
9713 /* 720 */ "xchgI",
9714 /* 721 */ "xchgL",
9715 /* 722 */ "xchgP",
9716 /* 723 */ "xchgN",
9717 /* 724 */ "absI_rReg",
9718 /* 725 */ "absL_rReg",
9719 /* 726 */ "subI_rReg",
9720 /* 727 */ "subI_rReg_imm",
9721 /* 728 */ "subI_rReg_mem",
9722 /* 729 */ "subI_mem_rReg",
9723 /* 730 */ "subI_mem_imm",
9724 /* 731 */ "subL_rReg",
9725 /* 732 */ "subL_rReg_imm",
9726 /* 733 */ "subL_rReg_mem",
9727 /* 734 */ "subL_mem_rReg",
9728 /* 735 */ "subL_mem_imm",
9729 /* 736 */ "subP_rReg",
9730 /* 737 */ "negI_rReg",
9731 /* 738 */ "negI_mem",
9732 /* 739 */ "negL_rReg",
9733 /* 740 */ "negL_mem",
9734 /* 741 */ "mulI_rReg",
9735 /* 742 */ "mulI_rReg_imm",
9736 /* 743 */ "mulI_mem",
9737 /* 744 */ "mulI_mem_0",
9738 /* 745 */ "mulI_mem_imm",
9739 /* 746 */ "mulAddS2I_rReg",
9740 /* 747 */ "mulL_rReg",
9741 /* 748 */ "mulL_rReg_imm",
9742 /* 749 */ "mulL_mem",
9743 /* 750 */ "mulL_mem_0",
9744 /* 751 */ "mulL_mem_imm",
9745 /* 752 */ "mulHiL_rReg",
9746 /* 753 */ "divI_rReg",
9747 /* 754 */ "divL_rReg",
9748 /* 755 */ "divModI_rReg_divmod",
9749 /* 756 */ "divModL_rReg_divmod",
9750 /* 757 */ "loadConL_0x6666666666666667",
9751 /* 758 */ "mul_hi",
9752 /* 759 */ "sarL_rReg_63",
9753 /* 760 */ "sarL_rReg_2",
9754 /* 761 */ "divL_10",
9755 /* 762 */ "modI_rReg",
9756 /* 763 */ "modL_rReg",
9757 /* 764 */ "salI_rReg_1",
9758 /* 765 */ "salI_mem_1",
9759 /* 766 */ "salI_rReg_imm",
9760 /* 767 */ "salI_mem_imm",
9761 /* 768 */ "salI_rReg_CL",
9762 /* 769 */ "salI_mem_CL",
9763 /* 770 */ "sarI_rReg_1",
9764 /* 771 */ "sarI_mem_1",
9765 /* 772 */ "sarI_rReg_imm",
9766 /* 773 */ "sarI_mem_imm",
9767 /* 774 */ "sarI_rReg_CL",
9768 /* 775 */ "sarI_mem_CL",
9769 /* 776 */ "shrI_rReg_1",
9770 /* 777 */ "shrI_mem_1",
9771 /* 778 */ "shrI_rReg_imm",
9772 /* 779 */ "shrI_mem_imm",
9773 /* 780 */ "shrI_rReg_CL",
9774 /* 781 */ "shrI_mem_CL",
9775 /* 782 */ "salL_rReg_1",
9776 /* 783 */ "salL_mem_1",
9777 /* 784 */ "salL_rReg_imm",
9778 /* 785 */ "salL_mem_imm",
9779 /* 786 */ "salL_rReg_CL",
9780 /* 787 */ "salL_mem_CL",
9781 /* 788 */ "sarL_rReg_1",
9782 /* 789 */ "sarL_mem_1",
9783 /* 790 */ "sarL_rReg_imm",
9784 /* 791 */ "sarL_mem_imm",
9785 /* 792 */ "sarL_rReg_CL",
9786 /* 793 */ "sarL_mem_CL",
9787 /* 794 */ "shrL_rReg_1",
9788 /* 795 */ "shrL_mem_1",
9789 /* 796 */ "shrL_rReg_imm",
9790 /* 797 */ "shrL_mem_imm",
9791 /* 798 */ "shrL_rReg_CL",
9792 /* 799 */ "shrL_mem_CL",
9793 /* 800 */ "i2b",
9794 /* 801 */ "i2s",
9795 /* 802 */ "rolI_rReg_imm1",
9796 /* 803 */ "rolI_rReg_imm8",
9797 /* 804 */ "rolI_rReg_CL",
9798 /* 805 */ "rolI_rReg_i1",
9799 /* 806 */ "rolI_rReg_i1_0",
9800 /* 807 */ "rolI_rReg_i8",
9801 /* 808 */ "rolI_rReg_i8_0",
9802 /* 809 */ "rolI_rReg_Var_C0",
9803 /* 810 */ "rolI_rReg_Var_C0_0",
9804 /* 811 */ "rolI_rReg_Var_C32",
9805 /* 812 */ "rolI_rReg_Var_C32_0",
9806 /* 813 */ "rorI_rReg_imm1",
9807 /* 814 */ "rorI_rReg_imm8",
9808 /* 815 */ "rorI_rReg_CL",
9809 /* 816 */ "rorI_rReg_i1",
9810 /* 817 */ "rorI_rReg_i1_0",
9811 /* 818 */ "rorI_rReg_i8",
9812 /* 819 */ "rorI_rReg_i8_0",
9813 /* 820 */ "rorI_rReg_Var_C0",
9814 /* 821 */ "rorI_rReg_Var_C0_0",
9815 /* 822 */ "rorI_rReg_Var_C32",
9816 /* 823 */ "rorI_rReg_Var_C32_0",
9817 /* 824 */ "rolL_rReg_imm1",
9818 /* 825 */ "rolL_rReg_imm8",
9819 /* 826 */ "rolL_rReg_CL",
9820 /* 827 */ "rolL_rReg_i1",
9821 /* 828 */ "rolL_rReg_i1_0",
9822 /* 829 */ "rolL_rReg_i8",
9823 /* 830 */ "rolL_rReg_i8_0",
9824 /* 831 */ "rolL_rReg_Var_C0",
9825 /* 832 */ "rolL_rReg_Var_C0_0",
9826 /* 833 */ "rolL_rReg_Var_C64",
9827 /* 834 */ "rolL_rReg_Var_C64_0",
9828 /* 835 */ "rorL_rReg_imm1",
9829 /* 836 */ "rorL_rReg_imm8",
9830 /* 837 */ "rorL_rReg_CL",
9831 /* 838 */ "rorL_rReg_i1",
9832 /* 839 */ "rorL_rReg_i1_0",
9833 /* 840 */ "rorL_rReg_i8",
9834 /* 841 */ "rorL_rReg_i8_0",
9835 /* 842 */ "rorL_rReg_Var_C0",
9836 /* 843 */ "rorL_rReg_Var_C0_0",
9837 /* 844 */ "rorL_rReg_Var_C64",
9838 /* 845 */ "rorL_rReg_Var_C64_0",
9839 /* 846 */ "andI_rReg",
9840 /* 847 */ "andI_rReg_imm255",
9841 /* 848 */ "andI2L_rReg_imm255",
9842 /* 849 */ "andI_rReg_imm65535",
9843 /* 850 */ "andI2L_rReg_imm65535",
9844 /* 851 */ "andI_rReg_imm",
9845 /* 852 */ "andI_rReg_mem",
9846 /* 853 */ "andI_rReg_mem_0",
9847 /* 854 */ "andB_mem_rReg",
9848 /* 855 */ "andB_mem_rReg_0",
9849 /* 856 */ "andI_mem_rReg",
9850 /* 857 */ "andI_mem_rReg_0",
9851 /* 858 */ "andI_mem_imm",
9852 /* 859 */ "andnI_rReg_rReg_mem",
9853 /* 860 */ "andnI_rReg_rReg_mem_0",
9854 /* 861 */ "andnI_rReg_rReg_rReg",
9855 /* 862 */ "andnI_rReg_rReg_rReg_0",
9856 /* 863 */ "blsiI_rReg_rReg",
9857 /* 864 */ "blsiI_rReg_rReg_0",
9858 /* 865 */ "blsiI_rReg_mem",
9859 /* 866 */ "blsiI_rReg_mem_0",
9860 /* 867 */ "blsmskI_rReg_mem",
9861 /* 868 */ "blsmskI_rReg_mem_0",
9862 /* 869 */ "blsmskI_rReg_rReg",
9863 /* 870 */ "blsmskI_rReg_rReg_0",
9864 /* 871 */ "blsrI_rReg_rReg",
9865 /* 872 */ "blsrI_rReg_rReg_0",
9866 /* 873 */ "blsrI_rReg_mem",
9867 /* 874 */ "blsrI_rReg_mem_0",
9868 /* 875 */ "orI_rReg",
9869 /* 876 */ "orI_rReg_imm",
9870 /* 877 */ "orI_rReg_mem",
9871 /* 878 */ "orI_rReg_mem_0",
9872 /* 879 */ "orB_mem_rReg",
9873 /* 880 */ "orB_mem_rReg_0",
9874 /* 881 */ "orI_mem_rReg",
9875 /* 882 */ "orI_mem_rReg_0",
9876 /* 883 */ "orI_mem_imm",
9877 /* 884 */ "xorI_rReg",
9878 /* 885 */ "xorI_rReg_im1",
9879 /* 886 */ "xorI_rReg_imm",
9880 /* 887 */ "xorI_rReg_mem",
9881 /* 888 */ "xorI_rReg_mem_0",
9882 /* 889 */ "xorB_mem_rReg",
9883 /* 890 */ "xorB_mem_rReg_0",
9884 /* 891 */ "xorI_mem_rReg",
9885 /* 892 */ "xorI_mem_rReg_0",
9886 /* 893 */ "xorI_mem_imm",
9887 /* 894 */ "andL_rReg",
9888 /* 895 */ "andL_rReg_imm255",
9889 /* 896 */ "andL_rReg_imm65535",
9890 /* 897 */ "andL_rReg_imm",
9891 /* 898 */ "andL_rReg_mem",
9892 /* 899 */ "andL_rReg_mem_0",
9893 /* 900 */ "andL_mem_rReg",
9894 /* 901 */ "andL_mem_rReg_0",
9895 /* 902 */ "andL_mem_imm",
9896 /* 903 */ "andnL_rReg_rReg_mem",
9897 /* 904 */ "andnL_rReg_rReg_mem_0",
9898 /* 905 */ "andnL_rReg_rReg_rReg",
9899 /* 906 */ "andnL_rReg_rReg_rReg_0",
9900 /* 907 */ "blsiL_rReg_rReg",
9901 /* 908 */ "blsiL_rReg_rReg_0",
9902 /* 909 */ "blsiL_rReg_mem",
9903 /* 910 */ "blsiL_rReg_mem_0",
9904 /* 911 */ "blsmskL_rReg_mem",
9905 /* 912 */ "blsmskL_rReg_mem_0",
9906 /* 913 */ "blsmskL_rReg_rReg",
9907 /* 914 */ "blsmskL_rReg_rReg_0",
9908 /* 915 */ "blsrL_rReg_rReg",
9909 /* 916 */ "blsrL_rReg_rReg_0",
9910 /* 917 */ "blsrL_rReg_mem",
9911 /* 918 */ "blsrL_rReg_mem_0",
9912 /* 919 */ "orL_rReg",
9913 /* 920 */ "orL_rReg_castP2X",
9914 /* 921 */ "orL_rReg_castP2X_0",
9915 /* 922 */ "orL_rReg_imm",
9916 /* 923 */ "orL_rReg_mem",
9917 /* 924 */ "orL_rReg_mem_0",
9918 /* 925 */ "orL_mem_rReg",
9919 /* 926 */ "orL_mem_rReg_0",
9920 /* 927 */ "orL_mem_imm",
9921 /* 928 */ "xorL_rReg",
9922 /* 929 */ "xorL_rReg_im1",
9923 /* 930 */ "xorL_rReg_imm",
9924 /* 931 */ "xorL_rReg_mem",
9925 /* 932 */ "xorL_rReg_mem_0",
9926 /* 933 */ "xorL_mem_rReg",
9927 /* 934 */ "xorL_mem_rReg_0",
9928 /* 935 */ "xorL_mem_imm",
9929 /* 936 */ "convI2B",
9930 /* 937 */ "convP2B",
9931 /* 938 */ "cmpLTMask",
9932 /* 939 */ "cmpLTMask0",
9933 /* 940 */ "cadd_cmpLTMask",
9934 /* 941 */ "cadd_cmpLTMask_1",
9935 /* 942 */ "cadd_cmpLTMask_0",
9936 /* 943 */ "cadd_cmpLTMask_2",
9937 /* 944 */ "and_cmpLTMask",
9938 /* 945 */ "and_cmpLTMask_0",
9939 /* 946 */ "cmpF_reg",
9940 /* 947 */ "cmpF_mem",
9941 /* 948 */ "cmpF_imm",
9942 /* 949 */ "cmpD_reg",
9943 /* 950 */ "cmpD_mem",
9944 /* 951 */ "cmpD_imm",
9945 /* 952 */ "convF2D_reg_reg",
9946 /* 953 */ "convF2D_reg_mem",
9947 /* 954 */ "convD2F_reg_reg",
9948 /* 955 */ "convD2F_reg_mem",
9949 /* 956 */ "convF2I_reg_reg",
9950 /* 957 */ "convF2L_reg_reg",
9951 /* 958 */ "convD2I_reg_reg",
9952 /* 959 */ "convD2L_reg_reg",
9953 /* 960 */ "convI2F_reg_reg",
9954 /* 961 */ "convI2F_reg_mem",
9955 /* 962 */ "convI2D_reg_reg",
9956 /* 963 */ "convI2D_reg_mem",
9957 /* 964 */ "convXI2F_reg",
9958 /* 965 */ "convXI2D_reg",
9959 /* 966 */ "convL2F_reg_reg",
9960 /* 967 */ "convL2F_reg_mem",
9961 /* 968 */ "convL2D_reg_reg",
9962 /* 969 */ "convL2D_reg_mem",
9963 /* 970 */ "convI2L_reg_reg",
9964 /* 971 */ "convI2L_reg_reg_zex",
9965 /* 972 */ "convI2L_reg_mem_zex",
9966 /* 973 */ "zerox_long_reg_reg",
9967 /* 974 */ "convL2I_reg_reg",
9968 /* 975 */ "MoveF2I_reg_stack",
9969 /* 976 */ "MoveI2F_reg_stack",
9970 /* 977 */ "MoveD2L_reg_stack",
9971 /* 978 */ "MoveL2D_reg_stack",
9972 /* 979 */ "rep_stos",
9973 /* 980 */ "rep_stos_large",
9974 /* 981 */ "string_compareL",
9975 /* 982 */ "string_compareU",
9976 /* 983 */ "string_compareLU",
9977 /* 984 */ "string_compareUL",
9978 /* 985 */ "string_indexof_conL",
9979 /* 986 */ "string_indexof_conU",
9980 /* 987 */ "string_indexof_conUL",
9981 /* 988 */ "string_indexofL",
9982 /* 989 */ "string_indexofU",
9983 /* 990 */ "string_indexofUL",
9984 /* 991 */ "string_indexofU_char",
9985 /* 992 */ "string_equals",
9986 /* 993 */ "array_equalsB",
9987 /* 994 */ "array_equalsC",
9988 /* 995 */ "has_negatives",
9989 /* 996 */ "string_compress",
9990 /* 997 */ "string_inflate",
9991 /* 998 */ "encode_iso_array",
9992 /* 999 */ "cmpL3_reg_reg",
9993 /* 1000 */ "cmovI_reg_g",
9994 /* 1001 */ "minI_rReg",
9995 /* 1002 */ "cmovI_reg_l",
9996 /* 1003 */ "maxI_rReg",
9997 /* 1004 */ "jmpDir",
9998 /* 1005 */ "jmpCon",
9999 /* 1006 */ "jmpLoopEnd",
10000 /* 1007 */ "jmpLoopEndU",
10001 /* 1008 */ "jmpLoopEndUCF",
10002 /* 1009 */ "jmpLoopEnd_and_restoreMask",
10003 /* 1010 */ "jmpLoopEndU_and_restoreMask",
10004 /* 1011 */ "jmpLoopEndUCF_and_restoreMask",
10005 /* 1012 */ "jmpConU",
10006 /* 1013 */ "jmpConUCF",
10007 /* 1014 */ "jmpConUCF2",
10008 /* 1015 */ "partialSubtypeCheck",
10009 /* 1016 */ "jmpDir_short",
10010 /* 1017 */ "jmpCon_short",
10011 /* 1018 */ "jmpLoopEnd_short",
10012 /* 1019 */ "jmpLoopEndU_short",
10013 /* 1020 */ "jmpLoopEndUCF_short",
10014 /* 1021 */ "jmpConU_short",
10015 /* 1022 */ "jmpConUCF_short",
10016 /* 1023 */ "jmpConUCF2_short",
10017 /* 1024 */ "safePoint_poll_far",
10018 /* 1025 */ "safePoint_poll_tls",
10019 /* 1026 */ "CallStaticJavaDirect",
10020 /* 1027 */ "CallDynamicJavaDirect",
10021 /* 1028 */ "CallRuntimeDirect",
10022 /* 1029 */ "CallLeafDirect",
10023 /* 1030 */ "CallLeafNoFPDirect",
10024 /* 1031 */ "Ret",
10025 /* 1032 */ "TailCalljmpInd",
10026 /* 1033 */ "tailjmpInd",
10027 /* 1034 */ "CreateException",
10028 /* 1035 */ "RethrowException",
10029 /* 1036 */ "ShouldNotReachHere",
10030 /* 1037 */ "setMask",
10031 /* 1038 */ "addF_reg",
10032 /* 1039 */ "addF_mem",
10033 /* 1040 */ "addF_mem_0",
10034 /* 1041 */ "addF_imm",
10035 /* 1042 */ "addF_reg_reg",
10036 /* 1043 */ "addF_reg_mem",
10037 /* 1044 */ "addF_reg_mem_0",
10038 /* 1045 */ "addF_reg_imm",
10039 /* 1046 */ "addD_reg",
10040 /* 1047 */ "addD_mem",
10041 /* 1048 */ "addD_mem_0",
10042 /* 1049 */ "addD_imm",
10043 /* 1050 */ "addD_reg_reg",
10044 /* 1051 */ "addD_reg_mem",
10045 /* 1052 */ "addD_reg_mem_0",
10046 /* 1053 */ "addD_reg_imm",
10047 /* 1054 */ "subF_reg",
10048 /* 1055 */ "subF_mem",
10049 /* 1056 */ "subF_imm",
10050 /* 1057 */ "subF_reg_reg",
10051 /* 1058 */ "subF_reg_mem",
10052 /* 1059 */ "subF_reg_imm",
10053 /* 1060 */ "subD_reg",
10054 /* 1061 */ "subD_mem",
10055 /* 1062 */ "subD_imm",
10056 /* 1063 */ "subD_reg_reg",
10057 /* 1064 */ "subD_reg_mem",
10058 /* 1065 */ "subD_reg_imm",
10059 /* 1066 */ "mulF_reg",
10060 /* 1067 */ "mulF_mem",
10061 /* 1068 */ "mulF_mem_0",
10062 /* 1069 */ "mulF_imm",
10063 /* 1070 */ "mulF_reg_reg",
10064 /* 1071 */ "mulF_reg_mem",
10065 /* 1072 */ "mulF_reg_mem_0",
10066 /* 1073 */ "mulF_reg_imm",
10067 /* 1074 */ "mulD_reg",
10068 /* 1075 */ "mulD_mem",
10069 /* 1076 */ "mulD_mem_0",
10070 /* 1077 */ "mulD_imm",
10071 /* 1078 */ "mulD_reg_reg",
10072 /* 1079 */ "mulD_reg_mem",
10073 /* 1080 */ "mulD_reg_mem_0",
10074 /* 1081 */ "mulD_reg_imm",
10075 /* 1082 */ "divF_reg",
10076 /* 1083 */ "divF_mem",
10077 /* 1084 */ "divF_imm",
10078 /* 1085 */ "divF_reg_reg",
10079 /* 1086 */ "divF_reg_mem",
10080 /* 1087 */ "divF_reg_imm",
10081 /* 1088 */ "divD_reg",
10082 /* 1089 */ "divD_mem",
10083 /* 1090 */ "divD_imm",
10084 /* 1091 */ "divD_reg_reg",
10085 /* 1092 */ "divD_reg_mem",
10086 /* 1093 */ "divD_reg_imm",
10087 /* 1094 */ "sqrtF_reg",
10088 /* 1095 */ "sqrtF_mem",
10089 /* 1096 */ "sqrtF_imm",
10090 /* 1097 */ "sqrtD_reg",
10091 /* 1098 */ "sqrtD_mem",
10092 /* 1099 */ "sqrtD_imm",
10093 /* 1100 */ "onspinwait",
10094 /* 1101 */ "fmaD_reg",
10095 /* 1102 */ "fmaF_reg",
10096 /* 1103 */ "loadV4",
10097 /* 1104 */ "loadV8",
10098 /* 1105 */ "loadV16",
10099 /* 1106 */ "loadV32",
10100 /* 1107 */ "loadV64_dword",
10101 /* 1108 */ "loadV64_qword",
10102 /* 1109 */ "storeV4",
10103 /* 1110 */ "storeV8",
10104 /* 1111 */ "storeV16",
10105 /* 1112 */ "storeV32",
10106 /* 1113 */ "storeV64_dword",
10107 /* 1114 */ "storeV64_qword",
10108 /* 1115 */ "Repl16B",
10109 /* 1116 */ "Repl32B",
10110 /* 1117 */ "Repl64B",
10111 /* 1118 */ "Repl16B_imm",
10112 /* 1119 */ "Repl32B_imm",
10113 /* 1120 */ "Repl64B_imm",
10114 /* 1121 */ "Repl4S",
10115 /* 1122 */ "Repl4S_mem",
10116 /* 1123 */ "Repl8S",
10117 /* 1124 */ "Repl8S_mem",
10118 /* 1125 */ "Repl8S_imm",
10119 /* 1126 */ "Repl16S",
10120 /* 1127 */ "Repl16S_mem",
10121 /* 1128 */ "Repl16S_imm",
10122 /* 1129 */ "Repl32S",
10123 /* 1130 */ "Repl32S_mem",
10124 /* 1131 */ "Repl32S_imm",
10125 /* 1132 */ "Repl4I",
10126 /* 1133 */ "Repl4I_mem",
10127 /* 1134 */ "Repl8I",
10128 /* 1135 */ "Repl8I_mem",
10129 /* 1136 */ "Repl16I",
10130 /* 1137 */ "Repl16I_mem",
10131 /* 1138 */ "Repl4I_imm",
10132 /* 1139 */ "Repl8I_imm",
10133 /* 1140 */ "Repl16I_imm",
10134 /* 1141 */ "Repl2L_mem",
10135 /* 1142 */ "Repl4L",
10136 /* 1143 */ "Repl8L",
10137 /* 1144 */ "Repl4L_imm",
10138 /* 1145 */ "Repl8L_imm",
10139 /* 1146 */ "Repl4L_mem",
10140 /* 1147 */ "Repl8L_mem",
10141 /* 1148 */ "Repl2F_mem",
10142 /* 1149 */ "Repl4F_mem",
10143 /* 1150 */ "Repl8F",
10144 /* 1151 */ "Repl8F_mem",
10145 /* 1152 */ "Repl16F",
10146 /* 1153 */ "Repl16F_mem",
10147 /* 1154 */ "Repl2F_zero",
10148 /* 1155 */ "Repl4F_zero",
10149 /* 1156 */ "Repl8F_zero",
10150 /* 1157 */ "Repl2D_mem",
10151 /* 1158 */ "Repl4D",
10152 /* 1159 */ "Repl4D_mem",
10153 /* 1160 */ "Repl8D",
10154 /* 1161 */ "Repl8D_mem",
10155 /* 1162 */ "Repl2D_zero",
10156 /* 1163 */ "Repl4D_zero",
10157 /* 1164 */ "Repl4B",
10158 /* 1165 */ "Repl8B",
10159 /* 1166 */ "Repl4B_imm",
10160 /* 1167 */ "Repl8B_imm",
10161 /* 1168 */ "Repl4B_zero",
10162 /* 1169 */ "Repl8B_zero",
10163 /* 1170 */ "Repl16B_zero",
10164 /* 1171 */ "Repl32B_zero",
10165 /* 1172 */ "Repl2S",
10166 /* 1173 */ "Repl2S_imm",
10167 /* 1174 */ "Repl4S_imm",
10168 /* 1175 */ "Repl2S_zero",
10169 /* 1176 */ "Repl4S_zero",
10170 /* 1177 */ "Repl8S_zero",
10171 /* 1178 */ "Repl16S_zero",
10172 /* 1179 */ "Repl2I",
10173 /* 1180 */ "Repl2I_mem",
10174 /* 1181 */ "Repl2I_imm",
10175 /* 1182 */ "Repl2I_zero",
10176 /* 1183 */ "Repl4I_zero",
10177 /* 1184 */ "Repl8I_zero",
10178 /* 1185 */ "Repl2L",
10179 /* 1186 */ "Repl2L_imm",
10180 /* 1187 */ "Repl2L_zero",
10181 /* 1188 */ "Repl4L_zero",
10182 /* 1189 */ "Repl2F",
10183 /* 1190 */ "Repl4F",
10184 /* 1191 */ "Repl2D",
10185 /* 1192 */ "Repl4B_mem_evex",
10186 /* 1193 */ "Repl8B_mem_evex",
10187 /* 1194 */ "Repl16B_evex",
10188 /* 1195 */ "Repl16B_mem_evex",
10189 /* 1196 */ "Repl32B_evex",
10190 /* 1197 */ "Repl32B_mem_evex",
10191 /* 1198 */ "Repl64B_evex",
10192 /* 1199 */ "Repl64B_mem_evex",
10193 /* 1200 */ "Repl16B_imm_evex",
10194 /* 1201 */ "Repl32B_imm_evex",
10195 /* 1202 */ "Repl64B_imm_evex",
10196 /* 1203 */ "Repl64B_zero_evex",
10197 /* 1204 */ "Repl4S_evex",
10198 /* 1205 */ "Repl4S_mem_evex",
10199 /* 1206 */ "Repl8S_evex",
10200 /* 1207 */ "Repl8S_mem_evex",
10201 /* 1208 */ "Repl16S_evex",
10202 /* 1209 */ "Repl16S_mem_evex",
10203 /* 1210 */ "Repl32S_evex",
10204 /* 1211 */ "Repl32S_mem_evex",
10205 /* 1212 */ "Repl8S_imm_evex",
10206 /* 1213 */ "Repl16S_imm_evex",
10207 /* 1214 */ "Repl32S_imm_evex",
10208 /* 1215 */ "Repl32S_zero_evex",
10209 /* 1216 */ "Repl4I_evex",
10210 /* 1217 */ "Repl4I_mem_evex",
10211 /* 1218 */ "Repl8I_evex",
10212 /* 1219 */ "Repl8I_mem_evex",
10213 /* 1220 */ "Repl16I_evex",
10214 /* 1221 */ "Repl16I_mem_evex",
10215 /* 1222 */ "Repl4I_imm_evex",
10216 /* 1223 */ "Repl8I_imm_evex",
10217 /* 1224 */ "Repl16I_imm_evex",
10218 /* 1225 */ "Repl16I_zero_evex",
10219 /* 1226 */ "Repl4L_evex",
10220 /* 1227 */ "Repl8L_evex",
10221 /* 1228 */ "Repl4L_imm_evex",
10222 /* 1229 */ "Repl8L_imm_evex",
10223 /* 1230 */ "Repl2L_mem_evex",
10224 /* 1231 */ "Repl4L_mem_evex",
10225 /* 1232 */ "Repl8L_mem_evex",
10226 /* 1233 */ "Repl8L_zero_evex",
10227 /* 1234 */ "Repl8F_evex",
10228 /* 1235 */ "Repl8F_mem_evex",
10229 /* 1236 */ "Repl16F_evex",
10230 /* 1237 */ "Repl16F_mem_evex",
10231 /* 1238 */ "Repl2F_zero_evex",
10232 /* 1239 */ "Repl4F_zero_evex",
10233 /* 1240 */ "Repl8F_zero_evex",
10234 /* 1241 */ "Repl16F_zero_evex",
10235 /* 1242 */ "Repl4D_evex",
10236 /* 1243 */ "Repl4D_mem_evex",
10237 /* 1244 */ "Repl8D_evex",
10238 /* 1245 */ "Repl8D_mem_evex",
10239 /* 1246 */ "Repl2D_zero_evex",
10240 /* 1247 */ "Repl4D_zero_evex",
10241 /* 1248 */ "Repl8D_zero_evex",
10242 /* 1249 */ "rsadd2I_reduction_reg",
10243 /* 1250 */ "rvadd2I_reduction_reg",
10244 /* 1251 */ "rvadd2I_reduction_reg_evex",
10245 /* 1252 */ "rsadd4I_reduction_reg",
10246 /* 1253 */ "rvadd4I_reduction_reg",
10247 /* 1254 */ "rvadd4I_reduction_reg_evex",
10248 /* 1255 */ "rvadd8I_reduction_reg",
10249 /* 1256 */ "rvadd8I_reduction_reg_evex",
10250 /* 1257 */ "rvadd16I_reduction_reg_evex",
10251 /* 1258 */ "rvadd2L_reduction_reg",
10252 /* 1259 */ "rvadd4L_reduction_reg",
10253 /* 1260 */ "rvadd8L_reduction_reg",
10254 /* 1261 */ "rsadd2F_reduction_reg",
10255 /* 1262 */ "rvadd2F_reduction_reg",
10256 /* 1263 */ "rsadd4F_reduction_reg",
10257 /* 1264 */ "rvadd4F_reduction_reg",
10258 /* 1265 */ "radd8F_reduction_reg",
10259 /* 1266 */ "radd16F_reduction_reg",
10260 /* 1267 */ "rsadd2D_reduction_reg",
10261 /* 1268 */ "rvadd2D_reduction_reg",
10262 /* 1269 */ "rvadd4D_reduction_reg",
10263 /* 1270 */ "rvadd8D_reduction_reg",
10264 /* 1271 */ "rsmul2I_reduction_reg",
10265 /* 1272 */ "rvmul2I_reduction_reg",
10266 /* 1273 */ "rsmul4I_reduction_reg",
10267 /* 1274 */ "rvmul4I_reduction_reg",
10268 /* 1275 */ "rvmul8I_reduction_reg",
10269 /* 1276 */ "rvmul16I_reduction_reg",
10270 /* 1277 */ "rvmul2L_reduction_reg",
10271 /* 1278 */ "rvmul4L_reduction_reg",
10272 /* 1279 */ "rvmul8L_reduction_reg",
10273 /* 1280 */ "rsmul2F_reduction",
10274 /* 1281 */ "rvmul2F_reduction_reg",
10275 /* 1282 */ "rsmul4F_reduction_reg",
10276 /* 1283 */ "rvmul4F_reduction_reg",
10277 /* 1284 */ "rvmul8F_reduction_reg",
10278 /* 1285 */ "rvmul16F_reduction_reg",
10279 /* 1286 */ "rsmul2D_reduction_reg",
10280 /* 1287 */ "rvmul2D_reduction_reg",
10281 /* 1288 */ "rvmul4D_reduction_reg",
10282 /* 1289 */ "rvmul8D_reduction_reg",
10283 /* 1290 */ "vadd4B",
10284 /* 1291 */ "vadd4B_reg",
10285 /* 1292 */ "vadd4B_mem",
10286 /* 1293 */ "vadd4B_mem_0",
10287 /* 1294 */ "vadd8B",
10288 /* 1295 */ "vadd8B_reg",
10289 /* 1296 */ "vadd8B_mem",
10290 /* 1297 */ "vadd8B_mem_0",
10291 /* 1298 */ "vadd16B",
10292 /* 1299 */ "vadd16B_reg",
10293 /* 1300 */ "vadd16B_mem",
10294 /* 1301 */ "vadd16B_mem_0",
10295 /* 1302 */ "vadd32B_reg",
10296 /* 1303 */ "vadd32B_mem",
10297 /* 1304 */ "vadd32B_mem_0",
10298 /* 1305 */ "vadd64B_reg",
10299 /* 1306 */ "vadd64B_mem",
10300 /* 1307 */ "vadd64B_mem_0",
10301 /* 1308 */ "vadd2S",
10302 /* 1309 */ "vadd2S_reg",
10303 /* 1310 */ "vadd2S_mem",
10304 /* 1311 */ "vadd2S_mem_0",
10305 /* 1312 */ "vadd4S",
10306 /* 1313 */ "vadd4S_reg",
10307 /* 1314 */ "vadd4S_mem",
10308 /* 1315 */ "vadd4S_mem_0",
10309 /* 1316 */ "vadd8S",
10310 /* 1317 */ "vadd8S_reg",
10311 /* 1318 */ "vadd8S_mem",
10312 /* 1319 */ "vadd8S_mem_0",
10313 /* 1320 */ "vadd16S_reg",
10314 /* 1321 */ "vadd16S_mem",
10315 /* 1322 */ "vadd16S_mem_0",
10316 /* 1323 */ "vadd32S_reg",
10317 /* 1324 */ "vadd32S_mem",
10318 /* 1325 */ "vadd32S_mem_0",
10319 /* 1326 */ "vadd2I",
10320 /* 1327 */ "vadd2I_reg",
10321 /* 1328 */ "vadd2I_mem",
10322 /* 1329 */ "vadd2I_mem_0",
10323 /* 1330 */ "vadd4I",
10324 /* 1331 */ "vadd4I_reg",
10325 /* 1332 */ "vadd4I_mem",
10326 /* 1333 */ "vadd4I_mem_0",
10327 /* 1334 */ "vadd8I_reg",
10328 /* 1335 */ "vadd8I_mem",
10329 /* 1336 */ "vadd8I_mem_0",
10330 /* 1337 */ "vadd16I_reg",
10331 /* 1338 */ "vadd16I_mem",
10332 /* 1339 */ "vadd16I_mem_0",
10333 /* 1340 */ "vadd2L",
10334 /* 1341 */ "vadd2L_reg",
10335 /* 1342 */ "vadd2L_mem",
10336 /* 1343 */ "vadd2L_mem_0",
10337 /* 1344 */ "vadd4L_reg",
10338 /* 1345 */ "vadd4L_mem",
10339 /* 1346 */ "vadd4L_mem_0",
10340 /* 1347 */ "vadd8L_reg",
10341 /* 1348 */ "vadd8L_mem",
10342 /* 1349 */ "vadd8L_mem_0",
10343 /* 1350 */ "vadd2F",
10344 /* 1351 */ "vadd2F_reg",
10345 /* 1352 */ "vadd2F_mem",
10346 /* 1353 */ "vadd2F_mem_0",
10347 /* 1354 */ "vadd4F",
10348 /* 1355 */ "vadd4F_reg",
10349 /* 1356 */ "vadd4F_mem",
10350 /* 1357 */ "vadd4F_mem_0",
10351 /* 1358 */ "vadd8F_reg",
10352 /* 1359 */ "vadd8F_mem",
10353 /* 1360 */ "vadd8F_mem_0",
10354 /* 1361 */ "vadd16F_reg",
10355 /* 1362 */ "vadd16F_mem",
10356 /* 1363 */ "vadd16F_mem_0",
10357 /* 1364 */ "vadd2D",
10358 /* 1365 */ "vadd2D_reg",
10359 /* 1366 */ "vadd2D_mem",
10360 /* 1367 */ "vadd2D_mem_0",
10361 /* 1368 */ "vadd4D_reg",
10362 /* 1369 */ "vadd4D_mem",
10363 /* 1370 */ "vadd4D_mem_0",
10364 /* 1371 */ "vadd8D_reg",
10365 /* 1372 */ "vadd8D_mem",
10366 /* 1373 */ "vadd8D_mem_0",
10367 /* 1374 */ "vsub4B",
10368 /* 1375 */ "vsub4B_reg",
10369 /* 1376 */ "vsub4B_mem",
10370 /* 1377 */ "vsub8B",
10371 /* 1378 */ "vsub8B_reg",
10372 /* 1379 */ "vsub8B_mem",
10373 /* 1380 */ "vsub16B",
10374 /* 1381 */ "vsub16B_reg",
10375 /* 1382 */ "vsub16B_mem",
10376 /* 1383 */ "vsub32B_reg",
10377 /* 1384 */ "vsub32B_mem",
10378 /* 1385 */ "vsub64B_reg",
10379 /* 1386 */ "vsub64B_mem",
10380 /* 1387 */ "vsub2S",
10381 /* 1388 */ "vsub2S_reg",
10382 /* 1389 */ "vsub2S_mem",
10383 /* 1390 */ "vsub4S",
10384 /* 1391 */ "vsub4S_reg",
10385 /* 1392 */ "vsub4S_mem",
10386 /* 1393 */ "vsub8S",
10387 /* 1394 */ "vsub8S_reg",
10388 /* 1395 */ "vsub8S_mem",
10389 /* 1396 */ "vsub16S_reg",
10390 /* 1397 */ "vsub16S_mem",
10391 /* 1398 */ "vsub32S_reg",
10392 /* 1399 */ "vsub32S_mem",
10393 /* 1400 */ "vsub2I",
10394 /* 1401 */ "vsub2I_reg",
10395 /* 1402 */ "vsub2I_mem",
10396 /* 1403 */ "vsub4I",
10397 /* 1404 */ "vsub4I_reg",
10398 /* 1405 */ "vsub4I_mem",
10399 /* 1406 */ "vsub8I_reg",
10400 /* 1407 */ "vsub8I_mem",
10401 /* 1408 */ "vsub16I_reg",
10402 /* 1409 */ "vsub16I_mem",
10403 /* 1410 */ "vsub2L",
10404 /* 1411 */ "vsub2L_reg",
10405 /* 1412 */ "vsub2L_mem",
10406 /* 1413 */ "vsub4L_reg",
10407 /* 1414 */ "vsub4L_mem",
10408 /* 1415 */ "vsub8L_reg",
10409 /* 1416 */ "vsub8L_mem",
10410 /* 1417 */ "vsub2F",
10411 /* 1418 */ "vsub2F_reg",
10412 /* 1419 */ "vsub2F_mem",
10413 /* 1420 */ "vsub4F",
10414 /* 1421 */ "vsub4F_reg",
10415 /* 1422 */ "vsub4F_mem",
10416 /* 1423 */ "vsub8F_reg",
10417 /* 1424 */ "vsub8F_mem",
10418 /* 1425 */ "vsub16F_reg",
10419 /* 1426 */ "vsub16F_mem",
10420 /* 1427 */ "vsub2D",
10421 /* 1428 */ "vsub2D_reg",
10422 /* 1429 */ "vsub2D_mem",
10423 /* 1430 */ "vsub4D_reg",
10424 /* 1431 */ "vsub4D_mem",
10425 /* 1432 */ "vsub8D_reg",
10426 /* 1433 */ "vsub8D_mem",
10427 /* 1434 */ "mul4B_reg",
10428 /* 1435 */ "mul8B_reg",
10429 /* 1436 */ "mul16B_reg",
10430 /* 1437 */ "vmul16B_reg_avx",
10431 /* 1438 */ "vmul32B_reg_avx",
10432 /* 1439 */ "vmul64B_reg_avx",
10433 /* 1440 */ "vmul2S",
10434 /* 1441 */ "vmul2S_reg",
10435 /* 1442 */ "vmul2S_mem",
10436 /* 1443 */ "vmul2S_mem_0",
10437 /* 1444 */ "vmul4S",
10438 /* 1445 */ "vmul4S_reg",
10439 /* 1446 */ "vmul4S_mem",
10440 /* 1447 */ "vmul4S_mem_0",
10441 /* 1448 */ "vmul8S",
10442 /* 1449 */ "vmul8S_reg",
10443 /* 1450 */ "vmul8S_mem",
10444 /* 1451 */ "vmul8S_mem_0",
10445 /* 1452 */ "vmul16S_reg",
10446 /* 1453 */ "vmul16S_mem",
10447 /* 1454 */ "vmul16S_mem_0",
10448 /* 1455 */ "vmul32S_reg",
10449 /* 1456 */ "vmul32S_mem",
10450 /* 1457 */ "vmul32S_mem_0",
10451 /* 1458 */ "vmul2I",
10452 /* 1459 */ "vmul2I_reg",
10453 /* 1460 */ "vmul2I_mem",
10454 /* 1461 */ "vmul2I_mem_0",
10455 /* 1462 */ "vmul4I",
10456 /* 1463 */ "vmul4I_reg",
10457 /* 1464 */ "vmul4I_mem",
10458 /* 1465 */ "vmul4I_mem_0",
10459 /* 1466 */ "vmul2L_reg",
10460 /* 1467 */ "vmul2L_mem",
10461 /* 1468 */ "vmul2L_mem_0",
10462 /* 1469 */ "vmul4L_reg",
10463 /* 1470 */ "vmul4L_mem",
10464 /* 1471 */ "vmul4L_mem_0",
10465 /* 1472 */ "vmul8L_reg",
10466 /* 1473 */ "vmul8L_mem",
10467 /* 1474 */ "vmul8L_mem_0",
10468 /* 1475 */ "vmul8I_reg",
10469 /* 1476 */ "vmul8I_mem",
10470 /* 1477 */ "vmul8I_mem_0",
10471 /* 1478 */ "vmul16I_reg",
10472 /* 1479 */ "vmul16I_mem",
10473 /* 1480 */ "vmul16I_mem_0",
10474 /* 1481 */ "vmul2F",
10475 /* 1482 */ "vmul2F_reg",
10476 /* 1483 */ "vmul2F_mem",
10477 /* 1484 */ "vmul2F_mem_0",
10478 /* 1485 */ "vmul4F",
10479 /* 1486 */ "vmul4F_reg",
10480 /* 1487 */ "vmul4F_mem",
10481 /* 1488 */ "vmul4F_mem_0",
10482 /* 1489 */ "vmul8F_reg",
10483 /* 1490 */ "vmul8F_mem",
10484 /* 1491 */ "vmul8F_mem_0",
10485 /* 1492 */ "vmul16F_reg",
10486 /* 1493 */ "vmul16F_mem",
10487 /* 1494 */ "vmul16F_mem_0",
10488 /* 1495 */ "vmul2D",
10489 /* 1496 */ "vmul2D_reg",
10490 /* 1497 */ "vmul2D_mem",
10491 /* 1498 */ "vmul2D_mem_0",
10492 /* 1499 */ "vmul4D_reg",
10493 /* 1500 */ "vmul4D_mem",
10494 /* 1501 */ "vmul4D_mem_0",
10495 /* 1502 */ "vmul8D_reg",
10496 /* 1503 */ "vmul8D_mem",
10497 /* 1504 */ "vmul8D_mem_0",
10498 /* 1505 */ "vcmov8F_reg",
10499 /* 1506 */ "vcmov4D_reg",
10500 /* 1507 */ "vdiv2F",
10501 /* 1508 */ "vdiv2F_reg",
10502 /* 1509 */ "vdiv2F_mem",
10503 /* 1510 */ "vdiv4F",
10504 /* 1511 */ "vdiv4F_reg",
10505 /* 1512 */ "vdiv4F_mem",
10506 /* 1513 */ "vdiv8F_reg",
10507 /* 1514 */ "vdiv8F_mem",
10508 /* 1515 */ "vdiv16F_reg",
10509 /* 1516 */ "vdiv16F_mem",
10510 /* 1517 */ "vdiv2D",
10511 /* 1518 */ "vdiv2D_reg",
10512 /* 1519 */ "vdiv2D_mem",
10513 /* 1520 */ "vdiv4D_reg",
10514 /* 1521 */ "vdiv4D_mem",
10515 /* 1522 */ "vdiv8D_reg",
10516 /* 1523 */ "vdiv8D_mem",
10517 /* 1524 */ "vshift4B",
10518 /* 1525 */ "vshift4B_0",
10519 /* 1526 */ "vshift4B_1",
10520 /* 1527 */ "vshift8B",
10521 /* 1528 */ "vshift8B_0",
10522 /* 1529 */ "vshift8B_1",
10523 /* 1530 */ "vshift16B",
10524 /* 1531 */ "vshift16B_0",
10525 /* 1532 */ "vshift16B_1",
10526 /* 1533 */ "vshift16B_avx",
10527 /* 1534 */ "vshift16B_avx_0",
10528 /* 1535 */ "vshift16B_avx_1",
10529 /* 1536 */ "vshift32B_avx",
10530 /* 1537 */ "vshift32B_avx_0",
10531 /* 1538 */ "vshift32B_avx_1",
10532 /* 1539 */ "vshift64B_avx",
10533 /* 1540 */ "vshift64B_avx_0",
10534 /* 1541 */ "vshift64B_avx_1",
10535 /* 1542 */ "vshist2S",
10536 /* 1543 */ "vshist2S_0",
10537 /* 1544 */ "vshist2S_1",
10538 /* 1545 */ "vshift4S",
10539 /* 1546 */ "vshift4S_0",
10540 /* 1547 */ "vshift4S_1",
10541 /* 1548 */ "vshift8S",
10542 /* 1549 */ "vshift8S_0",
10543 /* 1550 */ "vshift8S_1",
10544 /* 1551 */ "vshift16S",
10545 /* 1552 */ "vshift16S_0",
10546 /* 1553 */ "vshift16S_1",
10547 /* 1554 */ "vshift32S",
10548 /* 1555 */ "vshift32S_0",
10549 /* 1556 */ "vshift32S_1",
10550 /* 1557 */ "vshift2I",
10551 /* 1558 */ "vshift2I_0",
10552 /* 1559 */ "vshift2I_1",
10553 /* 1560 */ "vshift4I",
10554 /* 1561 */ "vshift4I_0",
10555 /* 1562 */ "vshift4I_1",
10556 /* 1563 */ "vshift8I",
10557 /* 1564 */ "vshift8I_0",
10558 /* 1565 */ "vshift8I_1",
10559 /* 1566 */ "vshift16I",
10560 /* 1567 */ "vshift16I_0",
10561 /* 1568 */ "vshift16I_1",
10562 /* 1569 */ "vshift2L",
10563 /* 1570 */ "vshift2L_0",
10564 /* 1571 */ "vshift4L",
10565 /* 1572 */ "vshift4L_0",
10566 /* 1573 */ "vshift8L",
10567 /* 1574 */ "vshift8L_0",
10568 /* 1575 */ "vshift8L_1",
10569 /* 1576 */ "vsra2L_reg",
10570 /* 1577 */ "vsra2L_reg_evex",
10571 /* 1578 */ "vsra4L_reg",
10572 /* 1579 */ "vsra4L_reg_evex",
10573 /* 1580 */ "vand4B",
10574 /* 1581 */ "vand4B_reg",
10575 /* 1582 */ "vand4B_mem",
10576 /* 1583 */ "vand4B_mem_0",
10577 /* 1584 */ "vand8B",
10578 /* 1585 */ "vand8B_reg",
10579 /* 1586 */ "vand8B_mem",
10580 /* 1587 */ "vand8B_mem_0",
10581 /* 1588 */ "vand16B",
10582 /* 1589 */ "vand16B_reg",
10583 /* 1590 */ "vand16B_mem",
10584 /* 1591 */ "vand16B_mem_0",
10585 /* 1592 */ "vand32B_reg",
10586 /* 1593 */ "vand32B_mem",
10587 /* 1594 */ "vand32B_mem_0",
10588 /* 1595 */ "vand64B_reg",
10589 /* 1596 */ "vand64B_mem",
10590 /* 1597 */ "vand64B_mem_0",
10591 /* 1598 */ "vor4B",
10592 /* 1599 */ "vor4B_reg",
10593 /* 1600 */ "vor4B_mem",
10594 /* 1601 */ "vor4B_mem_0",
10595 /* 1602 */ "vor8B",
10596 /* 1603 */ "vor8B_reg",
10597 /* 1604 */ "vor8B_mem",
10598 /* 1605 */ "vor8B_mem_0",
10599 /* 1606 */ "vor16B",
10600 /* 1607 */ "vor16B_reg",
10601 /* 1608 */ "vor16B_mem",
10602 /* 1609 */ "vor16B_mem_0",
10603 /* 1610 */ "vor32B_reg",
10604 /* 1611 */ "vor32B_mem",
10605 /* 1612 */ "vor32B_mem_0",
10606 /* 1613 */ "vor64B_reg",
10607 /* 1614 */ "vor64B_mem",
10608 /* 1615 */ "vor64B_mem_0",
10609 /* 1616 */ "vxor4B",
10610 /* 1617 */ "vxor4B_reg",
10611 /* 1618 */ "vxor4B_mem",
10612 /* 1619 */ "vxor4B_mem_0",
10613 /* 1620 */ "vxor8B",
10614 /* 1621 */ "vxor8B_reg",
10615 /* 1622 */ "vxor8B_mem",
10616 /* 1623 */ "vxor8B_mem_0",
10617 /* 1624 */ "vxor16B",
10618 /* 1625 */ "vxor16B_reg",
10619 /* 1626 */ "vxor16B_mem",
10620 /* 1627 */ "vxor16B_mem_0",
10621 /* 1628 */ "vxor32B_reg",
10622 /* 1629 */ "vxor32B_mem",
10623 /* 1630 */ "vxor32B_mem_0",
10624 /* 1631 */ "vxor64B_reg",
10625 /* 1632 */ "vxor64B_mem",
10626 /* 1633 */ "vxor64B_mem_0",
10627 /* 1634 */ "vabsneg2D",
10628 /* 1635 */ "vabsneg2D_0",
10629 /* 1636 */ "vabsneg4D",
10630 /* 1637 */ "vabsneg4D_0",
10631 /* 1638 */ "vabsneg8D",
10632 /* 1639 */ "vabsneg8D_0",
10633 /* 1640 */ "vabsneg2F",
10634 /* 1641 */ "vabsneg2F_0",
10635 /* 1642 */ "vabsneg4F",
10636 /* 1643 */ "vabsneg4F_0",
10637 /* 1644 */ "vabsneg8F",
10638 /* 1645 */ "vabsneg8F_0",
10639 /* 1646 */ "vabsneg16F",
10640 /* 1647 */ "vabsneg16F_0",
10641 /* 1648 */ "vfma2D_reg",
10642 /* 1649 */ "vfma2D_mem",
10643 /* 1650 */ "vfma4D_reg",
10644 /* 1651 */ "vfma4D_mem",
10645 /* 1652 */ "vfma8D_reg",
10646 /* 1653 */ "vfma8D_mem",
10647 /* 1654 */ "vfma4F_reg",
10648 /* 1655 */ "vfma4F_mem",
10649 /* 1656 */ "vfma8F_reg",
10650 /* 1657 */ "vfma8F_mem",
10651 /* 1658 */ "vfma16F_reg",
10652 /* 1659 */ "vfma16F_mem",
10653 /* 1660 */ "smuladd4S2I_reg",
10654 /* 1661 */ "vmuladd4S2I_reg",
10655 /* 1662 */ "smuladd8S4I_reg",
10656 /* 1663 */ "vmuladd8S4I_reg",
10657 /* 1664 */ "vmuladd16S8I_reg",
10658 /* 1665 */ "vmuladd32S16I_reg",
10659 /* 1666 */ "vmuladdadd4S2I_reg",
10660 /* 1667 */ "vmuladdadd4S2I_reg_0",
10661 /* 1668 */ "vmuladdadd8S4I_reg",
10662 /* 1669 */ "vmuladdadd8S4I_reg_0",
10663 /* 1670 */ "vmuladdadd16S8I_reg",
10664 /* 1671 */ "vmuladdadd16S8I_reg_0",
10665 /* 1672 */ "vmuladdadd32S16I_reg",
10666 /* 1673 */ "vmuladdadd32S16I_reg_0",
10667 /* 1674 */ "compareAndSwapP_shenandoah",
10668 /* 1675 */ "compareAndSwapP_shenandoah_0",
10669 /* 1676 */ "compareAndSwapN_shenandoah",
10670 /* 1677 */ "compareAndSwapN_shenandoah_0",
10671 /* 1678 */ "compareAndExchangeN_shenandoah",
10672 /* 1679 */ "compareAndExchangeP_shenandoah",
10673 /* 1680 */ "zLoadBarrierSlowRegXmmAndYmm",
10674 /* 1681 */ "zLoadBarrierSlowRegZmm",
10675 /* 1682 */ "zLoadBarrierWeakSlowRegXmmAndYmm",
10676 /* 1683 */ "zLoadBarrierWeakSlowRegZmm",
10677 /* 1684 */ "z_compareAndExchangeP",
10678 /* 1685 */ "z_compareAndSwapP",
10679 /* 1686 */ "z_compareAndSwapP_0",
10680 /* 1687 */ "z_xchgP",
10681 // last instruction
10682 "invalid rule name" // no trailing comma
10683};
10684
10685const bool swallowed[] = {
10686 /* 0 */ false,
10687 /* 1 */ false,
10688 /* 2 */ false,
10689 /* 3 */ false,
10690 /* 4 */ false,
10691 /* 5 */ false,
10692 /* 6 */ false,
10693 /* 7 */ false,
10694 /* 8 */ true,
10695 /* 9 */ true,
10696 /* 10 */ true,
10697 /* 11 */ true,
10698 /* 12 */ true,
10699 /* 13 */ true,
10700 /* 14 */ true,
10701 /* 15 */ true,
10702 /* 16 */ true,
10703 /* 17 */ true,
10704 /* 18 */ true,
10705 /* 19 */ true,
10706 /* 20 */ true,
10707 /* 21 */ true,
10708 /* 22 */ true,
10709 /* 23 */ true,
10710 /* 24 */ true,
10711 /* 25 */ true,
10712 /* 26 */ true,
10713 /* 27 */ true,
10714 /* 28 */ true,
10715 /* 29 */ true,
10716 /* 30 */ true,
10717 /* 31 */ true,
10718 /* 32 */ true,
10719 /* 33 */ true,
10720 /* 34 */ true,
10721 /* 35 */ true,
10722 /* 36 */ true,
10723 /* 37 */ true,
10724 /* 38 */ true,
10725 /* 39 */ true,
10726 /* 40 */ true,
10727 /* 41 */ true,
10728 /* 42 */ true,
10729 /* 43 */ true,
10730 /* 44 */ true,
10731 /* 45 */ false,
10732 /* 46 */ false,
10733 /* 47 */ false,
10734 /* 48 */ false,
10735 /* 49 */ false,
10736 /* 50 */ false,
10737 /* 51 */ false,
10738 /* 52 */ false,
10739 /* 53 */ false,
10740 /* 54 */ false,
10741 /* 55 */ false,
10742 /* 56 */ false,
10743 /* 57 */ false,
10744 /* 58 */ false,
10745 /* 59 */ false,
10746 /* 60 */ false,
10747 /* 61 */ false,
10748 /* 62 */ false,
10749 /* 63 */ false,
10750 /* 64 */ false,
10751 /* 65 */ false,
10752 /* 66 */ false,
10753 /* 67 */ false,
10754 /* 68 */ false,
10755 /* 69 */ false,
10756 /* 70 */ false,
10757 /* 71 */ false,
10758 /* 72 */ false,
10759 /* 73 */ false,
10760 /* 74 */ false,
10761 /* 75 */ false,
10762 /* 76 */ false,
10763 /* 77 */ false,
10764 /* 78 */ false,
10765 /* 79 */ false,
10766 /* 80 */ false,
10767 /* 81 */ false,
10768 /* 82 */ false,
10769 /* 83 */ false,
10770 /* 84 */ false,
10771 /* 85 */ false,
10772 /* 86 */ false,
10773 /* 87 */ false,
10774 /* 88 */ false,
10775 /* 89 */ false,
10776 /* 90 */ false,
10777 /* 91 */ false,
10778 /* 92 */ false,
10779 /* 93 */ false,
10780 /* 94 */ false,
10781 /* 95 */ false,
10782 /* 96 */ false,
10783 /* 97 */ false,
10784 /* 98 */ false,
10785 /* 99 */ false,
10786 /* 100 */ false,
10787 /* 101 */ false,
10788 /* 102 */ false,
10789 /* 103 */ false,
10790 /* 104 */ false,
10791 /* 105 */ false,
10792 /* 106 */ false,
10793 /* 107 */ false,
10794 /* 108 */ false,
10795 /* 109 */ false,
10796 /* 110 */ false,
10797 /* 111 */ false,
10798 /* 112 */ false,
10799 /* 113 */ false,
10800 /* 114 */ true,
10801 /* 115 */ true,
10802 /* 116 */ true,
10803 /* 117 */ true,
10804 /* 118 */ false,
10805 /* 119 */ false,
10806 /* 120 */ false,
10807 /* 121 */ false,
10808 /* 122 */ false,
10809 /* 123 */ false,
10810 /* 124 */ false,
10811 /* 125 */ false,
10812 /* 126 */ false,
10813 /* 127 */ false,
10814 /* 128 */ false,
10815 /* 129 */ false,
10816 /* 130 */ false,
10817 /* 131 */ false,
10818 /* 132 */ false,
10819 /* 133 */ false,
10820 /* 134 */ false,
10821 /* 135 */ false,
10822 /* 136 */ false,
10823 /* 137 */ false,
10824 /* 138 */ false,
10825 /* 139 */ false,
10826 /* 140 */ false,
10827 /* 141 */ false,
10828 /* 142 */ false,
10829 /* 143 */ false,
10830 /* 144 */ false,
10831 /* 145 */ false,
10832 /* 146 */ false,
10833 /* 147 */ false,
10834 /* 148 */ false,
10835 /* 149 */ false,
10836 /* 150 */ false,
10837 /* 151 */ false,
10838 /* 152 */ true,
10839 // last operand
10840 /* 153 */ false,
10841 // last operand class
10842 /* 154 */ false,
10843 /* 155 */ false,
10844 /* 156 */ false,
10845 /* 157 */ false,
10846 /* 158 */ false,
10847 /* 159 */ false,
10848 /* 160 */ false,
10849 /* 161 */ false,
10850 /* 162 */ false,
10851 /* 163 */ false,
10852 /* 164 */ false,
10853 /* 165 */ false,
10854 /* 166 */ false,
10855 /* 167 */ false,
10856 /* 168 */ false,
10857 /* 169 */ false,
10858 /* 170 */ false,
10859 /* 171 */ false,
10860 /* 172 */ false,
10861 /* 173 */ false,
10862 /* 174 */ false,
10863 /* 175 */ false,
10864 /* 176 */ false,
10865 /* 177 */ false,
10866 /* 178 */ false,
10867 /* 179 */ false,
10868 /* 180 */ false,
10869 /* 181 */ false,
10870 /* 182 */ false,
10871 /* 183 */ false,
10872 /* 184 */ false,
10873 /* 185 */ false,
10874 /* 186 */ false,
10875 /* 187 */ false,
10876 /* 188 */ false,
10877 /* 189 */ false,
10878 /* 190 */ false,
10879 /* 191 */ false,
10880 /* 192 */ false,
10881 /* 193 */ false,
10882 /* 194 */ false,
10883 /* 195 */ false,
10884 /* 196 */ false,
10885 /* 197 */ false,
10886 /* 198 */ false,
10887 /* 199 */ false,
10888 /* 200 */ false,
10889 /* 201 */ false,
10890 /* 202 */ false,
10891 /* 203 */ false,
10892 /* 204 */ false,
10893 /* 205 */ false,
10894 /* 206 */ false,
10895 /* 207 */ false,
10896 /* 208 */ false,
10897 /* 209 */ false,
10898 /* 210 */ false,
10899 /* 211 */ false,
10900 /* 212 */ false,
10901 /* 213 */ false,
10902 /* 214 */ false,
10903 /* 215 */ false,
10904 /* 216 */ false,
10905 /* 217 */ false,
10906 /* 218 */ false,
10907 /* 219 */ false,
10908 /* 220 */ false,
10909 /* 221 */ false,
10910 /* 222 */ false,
10911 /* 223 */ false,
10912 /* 224 */ false,
10913 /* 225 */ false,
10914 /* 226 */ false,
10915 /* 227 */ false,
10916 /* 228 */ false,
10917 /* 229 */ false,
10918 /* 230 */ false,
10919 /* 231 */ false,
10920 /* 232 */ false,
10921 /* 233 */ false,
10922 /* 234 */ false,
10923 /* 235 */ false,
10924 /* 236 */ false,
10925 /* 237 */ false,
10926 /* 238 */ false,
10927 /* 239 */ false,
10928 /* 240 */ false,
10929 /* 241 */ false,
10930 /* 242 */ false,
10931 /* 243 */ false,
10932 /* 244 */ false,
10933 /* 245 */ false,
10934 /* 246 */ false,
10935 /* 247 */ false,
10936 /* 248 */ false,
10937 /* 249 */ false,
10938 /* 250 */ false,
10939 /* 251 */ false,
10940 /* 252 */ false,
10941 /* 253 */ false,
10942 /* 254 */ false,
10943 /* 255 */ false,
10944 /* 256 */ false,
10945 /* 257 */ false,
10946 /* 258 */ false,
10947 /* 259 */ false,
10948 /* 260 */ false,
10949 /* 261 */ false,
10950 /* 262 */ false,
10951 /* 263 */ false,
10952 /* 264 */ false,
10953 /* 265 */ false,
10954 /* 266 */ false,
10955 /* 267 */ false,
10956 /* 268 */ false,
10957 /* 269 */ false,
10958 /* 270 */ false,
10959 /* 271 */ false,
10960 /* 272 */ false,
10961 /* 273 */ false,
10962 /* 274 */ false,
10963 /* 275 */ false,
10964 /* 276 */ false,
10965 /* 277 */ false,
10966 /* 278 */ false,
10967 /* 279 */ false,
10968 /* 280 */ false,
10969 /* 281 */ false,
10970 /* 282 */ false,
10971 /* 283 */ false,
10972 /* 284 */ false,
10973 /* 285 */ false,
10974 /* 286 */ false,
10975 /* 287 */ false,
10976 /* 288 */ false,
10977 /* 289 */ false,
10978 /* 290 */ false,
10979 /* 291 */ false,
10980 /* 292 */ false,
10981 /* 293 */ false,
10982 /* 294 */ false,
10983 /* 295 */ false,
10984 /* 296 */ false,
10985 /* 297 */ false,
10986 /* 298 */ false,
10987 /* 299 */ false,
10988 /* 300 */ false,
10989 /* 301 */ false,
10990 /* 302 */ false,
10991 /* 303 */ false,
10992 /* 304 */ false,
10993 /* 305 */ false,
10994 /* 306 */ false,
10995 /* 307 */ false,
10996 /* 308 */ false,
10997 /* 309 */ false,
10998 /* 310 */ false,
10999 /* 311 */ false,
11000 /* 312 */ false,
11001 /* 313 */ false,
11002 /* 314 */ false,
11003 /* 315 */ false,
11004 /* 316 */ false,
11005 /* 317 */ false,
11006 /* 318 */ false,
11007 /* 319 */ false,
11008 /* 320 */ false,
11009 /* 321 */ false,
11010 /* 322 */ false,
11011 /* 323 */ false,
11012 /* 324 */ false,
11013 /* 325 */ false,
11014 /* 326 */ false,
11015 /* 327 */ false,
11016 /* 328 */ false,
11017 /* 329 */ false,
11018 /* 330 */ false,
11019 /* 331 */ false,
11020 /* 332 */ false,
11021 // last internally defined operand
11022 /* 333 */ false,
11023 /* 334 */ false,
11024 /* 335 */ false,
11025 /* 336 */ false,
11026 /* 337 */ false,
11027 /* 338 */ false,
11028 /* 339 */ false,
11029 /* 340 */ false,
11030 /* 341 */ false,
11031 /* 342 */ false,
11032 /* 343 */ false,
11033 /* 344 */ false,
11034 /* 345 */ false,
11035 /* 346 */ false,
11036 /* 347 */ false,
11037 /* 348 */ false,
11038 /* 349 */ false,
11039 /* 350 */ false,
11040 /* 351 */ false,
11041 /* 352 */ false,
11042 /* 353 */ false,
11043 /* 354 */ false,
11044 /* 355 */ false,
11045 /* 356 */ false,
11046 /* 357 */ false,
11047 /* 358 */ false,
11048 /* 359 */ false,
11049 /* 360 */ false,
11050 /* 361 */ false,
11051 /* 362 */ false,
11052 /* 363 */ false,
11053 /* 364 */ false,
11054 /* 365 */ false,
11055 /* 366 */ false,
11056 /* 367 */ false,
11057 /* 368 */ false,
11058 /* 369 */ false,
11059 /* 370 */ false,
11060 /* 371 */ false,
11061 /* 372 */ false,
11062 /* 373 */ false,
11063 /* 374 */ false,
11064 /* 375 */ false,
11065 /* 376 */ false,
11066 /* 377 */ false,
11067 /* 378 */ false,
11068 /* 379 */ false,
11069 /* 380 */ false,
11070 /* 381 */ false,
11071 /* 382 */ false,
11072 /* 383 */ false,
11073 /* 384 */ false,
11074 /* 385 */ false,
11075 /* 386 */ false,
11076 /* 387 */ false,
11077 /* 388 */ false,
11078 /* 389 */ false,
11079 /* 390 */ false,
11080 /* 391 */ false,
11081 /* 392 */ false,
11082 /* 393 */ false,
11083 /* 394 */ false,
11084 /* 395 */ false,
11085 /* 396 */ false,
11086 /* 397 */ false,
11087 /* 398 */ false,
11088 /* 399 */ false,
11089 /* 400 */ false,
11090 /* 401 */ false,
11091 /* 402 */ false,
11092 /* 403 */ false,
11093 /* 404 */ false,
11094 /* 405 */ false,
11095 /* 406 */ false,
11096 /* 407 */ false,
11097 /* 408 */ false,
11098 /* 409 */ false,
11099 /* 410 */ false,
11100 /* 411 */ false,
11101 /* 412 */ false,
11102 /* 413 */ false,
11103 /* 414 */ false,
11104 /* 415 */ false,
11105 /* 416 */ false,
11106 /* 417 */ false,
11107 /* 418 */ false,
11108 /* 419 */ false,
11109 /* 420 */ false,
11110 /* 421 */ false,
11111 /* 422 */ false,
11112 /* 423 */ false,
11113 /* 424 */ false,
11114 /* 425 */ false,
11115 /* 426 */ false,
11116 /* 427 */ false,
11117 /* 428 */ false,
11118 /* 429 */ false,
11119 /* 430 */ false,
11120 /* 431 */ false,
11121 /* 432 */ false,
11122 /* 433 */ false,
11123 /* 434 */ false,
11124 /* 435 */ false,
11125 /* 436 */ false,
11126 /* 437 */ false,
11127 /* 438 */ false,
11128 /* 439 */ false,
11129 /* 440 */ false,
11130 /* 441 */ false,
11131 /* 442 */ false,
11132 /* 443 */ false,
11133 /* 444 */ false,
11134 /* 445 */ false,
11135 /* 446 */ false,
11136 /* 447 */ false,
11137 /* 448 */ false,
11138 /* 449 */ false,
11139 /* 450 */ false,
11140 /* 451 */ false,
11141 /* 452 */ false,
11142 /* 453 */ false,
11143 /* 454 */ false,
11144 /* 455 */ false,
11145 /* 456 */ false,
11146 /* 457 */ false,
11147 /* 458 */ false,
11148 /* 459 */ false,
11149 /* 460 */ false,
11150 /* 461 */ false,
11151 /* 462 */ false,
11152 /* 463 */ false,
11153 /* 464 */ false,
11154 /* 465 */ false,
11155 /* 466 */ false,
11156 /* 467 */ false,
11157 /* 468 */ false,
11158 /* 469 */ false,
11159 /* 470 */ false,
11160 /* 471 */ false,
11161 /* 472 */ false,
11162 /* 473 */ false,
11163 /* 474 */ false,
11164 /* 475 */ false,
11165 /* 476 */ false,
11166 /* 477 */ false,
11167 /* 478 */ false,
11168 /* 479 */ false,
11169 /* 480 */ false,
11170 /* 481 */ false,
11171 /* 482 */ false,
11172 /* 483 */ false,
11173 /* 484 */ false,
11174 /* 485 */ false,
11175 /* 486 */ false,
11176 /* 487 */ false,
11177 /* 488 */ false,
11178 /* 489 */ false,
11179 /* 490 */ false,
11180 /* 491 */ false,
11181 /* 492 */ false,
11182 /* 493 */ false,
11183 /* 494 */ false,
11184 /* 495 */ false,
11185 /* 496 */ false,
11186 /* 497 */ false,
11187 /* 498 */ false,
11188 /* 499 */ false,
11189 /* 500 */ false,
11190 /* 501 */ false,
11191 /* 502 */ false,
11192 /* 503 */ false,
11193 /* 504 */ false,
11194 /* 505 */ false,
11195 /* 506 */ false,
11196 /* 507 */ false,
11197 /* 508 */ false,
11198 /* 509 */ false,
11199 /* 510 */ false,
11200 /* 511 */ false,
11201 /* 512 */ false,
11202 /* 513 */ false,
11203 /* 514 */ false,
11204 /* 515 */ false,
11205 /* 516 */ false,
11206 /* 517 */ false,
11207 /* 518 */ false,
11208 /* 519 */ false,
11209 /* 520 */ false,
11210 /* 521 */ false,
11211 /* 522 */ false,
11212 /* 523 */ false,
11213 /* 524 */ false,
11214 /* 525 */ false,
11215 /* 526 */ false,
11216 /* 527 */ false,
11217 /* 528 */ false,
11218 /* 529 */ false,
11219 /* 530 */ false,
11220 /* 531 */ false,
11221 /* 532 */ false,
11222 /* 533 */ false,
11223 /* 534 */ false,
11224 /* 535 */ false,
11225 /* 536 */ false,
11226 /* 537 */ false,
11227 /* 538 */ false,
11228 /* 539 */ false,
11229 /* 540 */ false,
11230 /* 541 */ false,
11231 /* 542 */ false,
11232 /* 543 */ false,
11233 /* 544 */ false,
11234 /* 545 */ false,
11235 /* 546 */ false,
11236 /* 547 */ false,
11237 /* 548 */ false,
11238 /* 549 */ false,
11239 /* 550 */ false,
11240 /* 551 */ false,
11241 /* 552 */ false,
11242 /* 553 */ false,
11243 /* 554 */ false,
11244 /* 555 */ false,
11245 /* 556 */ false,
11246 /* 557 */ false,
11247 /* 558 */ false,
11248 /* 559 */ false,
11249 /* 560 */ false,
11250 /* 561 */ false,
11251 /* 562 */ false,
11252 /* 563 */ false,
11253 /* 564 */ false,
11254 /* 565 */ false,
11255 /* 566 */ false,
11256 /* 567 */ false,
11257 /* 568 */ false,
11258 /* 569 */ false,
11259 /* 570 */ false,
11260 /* 571 */ false,
11261 /* 572 */ false,
11262 /* 573 */ false,
11263 /* 574 */ false,
11264 /* 575 */ false,
11265 /* 576 */ false,
11266 /* 577 */ false,
11267 /* 578 */ false,
11268 /* 579 */ false,
11269 /* 580 */ false,
11270 /* 581 */ false,
11271 /* 582 */ false,
11272 /* 583 */ false,
11273 /* 584 */ false,
11274 /* 585 */ false,
11275 /* 586 */ false,
11276 /* 587 */ false,
11277 /* 588 */ false,
11278 /* 589 */ false,
11279 /* 590 */ false,
11280 /* 591 */ false,
11281 /* 592 */ false,
11282 /* 593 */ false,
11283 /* 594 */ false,
11284 /* 595 */ false,
11285 /* 596 */ false,
11286 /* 597 */ false,
11287 /* 598 */ false,
11288 /* 599 */ false,
11289 /* 600 */ false,
11290 /* 601 */ false,
11291 /* 602 */ false,
11292 /* 603 */ false,
11293 /* 604 */ false,
11294 /* 605 */ false,
11295 /* 606 */ false,
11296 /* 607 */ false,
11297 /* 608 */ false,
11298 /* 609 */ false,
11299 /* 610 */ false,
11300 /* 611 */ false,
11301 /* 612 */ false,
11302 /* 613 */ false,
11303 /* 614 */ false,
11304 /* 615 */ false,
11305 /* 616 */ false,
11306 /* 617 */ false,
11307 /* 618 */ false,
11308 /* 619 */ false,
11309 /* 620 */ false,
11310 /* 621 */ false,
11311 /* 622 */ false,
11312 /* 623 */ false,
11313 /* 624 */ false,
11314 /* 625 */ false,
11315 /* 626 */ false,
11316 /* 627 */ false,
11317 /* 628 */ false,
11318 /* 629 */ false,
11319 /* 630 */ false,
11320 /* 631 */ false,
11321 /* 632 */ false,
11322 /* 633 */ false,
11323 /* 634 */ false,
11324 /* 635 */ false,
11325 /* 636 */ false,
11326 /* 637 */ false,
11327 /* 638 */ false,
11328 /* 639 */ false,
11329 /* 640 */ false,
11330 /* 641 */ false,
11331 /* 642 */ false,
11332 /* 643 */ false,
11333 /* 644 */ false,
11334 /* 645 */ false,
11335 /* 646 */ false,
11336 /* 647 */ false,
11337 /* 648 */ false,
11338 /* 649 */ false,
11339 /* 650 */ false,
11340 /* 651 */ false,
11341 /* 652 */ false,
11342 /* 653 */ false,
11343 /* 654 */ false,
11344 /* 655 */ false,
11345 /* 656 */ false,
11346 /* 657 */ false,
11347 /* 658 */ false,
11348 /* 659 */ false,
11349 /* 660 */ false,
11350 /* 661 */ false,
11351 /* 662 */ false,
11352 /* 663 */ false,
11353 /* 664 */ false,
11354 /* 665 */ false,
11355 /* 666 */ false,
11356 /* 667 */ false,
11357 /* 668 */ false,
11358 /* 669 */ false,
11359 /* 670 */ false,
11360 /* 671 */ false,
11361 /* 672 */ false,
11362 /* 673 */ false,
11363 /* 674 */ false,
11364 /* 675 */ false,
11365 /* 676 */ false,
11366 /* 677 */ false,
11367 /* 678 */ false,
11368 /* 679 */ false,
11369 /* 680 */ false,
11370 /* 681 */ false,
11371 /* 682 */ false,
11372 /* 683 */ false,
11373 /* 684 */ false,
11374 /* 685 */ false,
11375 /* 686 */ false,
11376 /* 687 */ false,
11377 /* 688 */ false,
11378 /* 689 */ false,
11379 /* 690 */ false,
11380 /* 691 */ false,
11381 /* 692 */ false,
11382 /* 693 */ false,
11383 /* 694 */ false,
11384 /* 695 */ false,
11385 /* 696 */ false,
11386 /* 697 */ false,
11387 /* 698 */ false,
11388 /* 699 */ false,
11389 /* 700 */ false,
11390 /* 701 */ false,
11391 /* 702 */ false,
11392 /* 703 */ false,
11393 /* 704 */ false,
11394 /* 705 */ false,
11395 /* 706 */ false,
11396 /* 707 */ false,
11397 /* 708 */ false,
11398 /* 709 */ false,
11399 /* 710 */ false,
11400 /* 711 */ false,
11401 /* 712 */ false,
11402 /* 713 */ false,
11403 /* 714 */ false,
11404 /* 715 */ false,
11405 /* 716 */ false,
11406 /* 717 */ false,
11407 /* 718 */ false,
11408 /* 719 */ false,
11409 /* 720 */ false,
11410 /* 721 */ false,
11411 /* 722 */ false,
11412 /* 723 */ false,
11413 /* 724 */ false,
11414 /* 725 */ false,
11415 /* 726 */ false,
11416 /* 727 */ false,
11417 /* 728 */ false,
11418 /* 729 */ false,
11419 /* 730 */ false,
11420 /* 731 */ false,
11421 /* 732 */ false,
11422 /* 733 */ false,
11423 /* 734 */ false,
11424 /* 735 */ false,
11425 /* 736 */ false,
11426 /* 737 */ false,
11427 /* 738 */ false,
11428 /* 739 */ false,
11429 /* 740 */ false,
11430 /* 741 */ false,
11431 /* 742 */ false,
11432 /* 743 */ false,
11433 /* 744 */ false,
11434 /* 745 */ false,
11435 /* 746 */ false,
11436 /* 747 */ false,
11437 /* 748 */ false,
11438 /* 749 */ false,
11439 /* 750 */ false,
11440 /* 751 */ false,
11441 /* 752 */ false,
11442 /* 753 */ false,
11443 /* 754 */ false,
11444 /* 755 */ false,
11445 /* 756 */ false,
11446 /* 757 */ false,
11447 /* 758 */ false,
11448 /* 759 */ false,
11449 /* 760 */ false,
11450 /* 761 */ false,
11451 /* 762 */ false,
11452 /* 763 */ false,
11453 /* 764 */ false,
11454 /* 765 */ false,
11455 /* 766 */ false,
11456 /* 767 */ false,
11457 /* 768 */ false,
11458 /* 769 */ false,
11459 /* 770 */ false,
11460 /* 771 */ false,
11461 /* 772 */ false,
11462 /* 773 */ false,
11463 /* 774 */ false,
11464 /* 775 */ false,
11465 /* 776 */ false,
11466 /* 777 */ false,
11467 /* 778 */ false,
11468 /* 779 */ false,
11469 /* 780 */ false,
11470 /* 781 */ false,
11471 /* 782 */ false,
11472 /* 783 */ false,
11473 /* 784 */ false,
11474 /* 785 */ false,
11475 /* 786 */ false,
11476 /* 787 */ false,
11477 /* 788 */ false,
11478 /* 789 */ false,
11479 /* 790 */ false,
11480 /* 791 */ false,
11481 /* 792 */ false,
11482 /* 793 */ false,
11483 /* 794 */ false,
11484 /* 795 */ false,
11485 /* 796 */ false,
11486 /* 797 */ false,
11487 /* 798 */ false,
11488 /* 799 */ false,
11489 /* 800 */ false,
11490 /* 801 */ false,
11491 /* 802 */ false,
11492 /* 803 */ false,
11493 /* 804 */ false,
11494 /* 805 */ false,
11495 /* 806 */ false,
11496 /* 807 */ false,
11497 /* 808 */ false,
11498 /* 809 */ false,
11499 /* 810 */ false,
11500 /* 811 */ false,
11501 /* 812 */ false,
11502 /* 813 */ false,
11503 /* 814 */ false,
11504 /* 815 */ false,
11505 /* 816 */ false,
11506 /* 817 */ false,
11507 /* 818 */ false,
11508 /* 819 */ false,
11509 /* 820 */ false,
11510 /* 821 */ false,
11511 /* 822 */ false,
11512 /* 823 */ false,
11513 /* 824 */ false,
11514 /* 825 */ false,
11515 /* 826 */ false,
11516 /* 827 */ false,
11517 /* 828 */ false,
11518 /* 829 */ false,
11519 /* 830 */ false,
11520 /* 831 */ false,
11521 /* 832 */ false,
11522 /* 833 */ false,
11523 /* 834 */ false,
11524 /* 835 */ false,
11525 /* 836 */ false,
11526 /* 837 */ false,
11527 /* 838 */ false,
11528 /* 839 */ false,
11529 /* 840 */ false,
11530 /* 841 */ false,
11531 /* 842 */ false,
11532 /* 843 */ false,
11533 /* 844 */ false,
11534 /* 845 */ false,
11535 /* 846 */ false,
11536 /* 847 */ false,
11537 /* 848 */ false,
11538 /* 849 */ false,
11539 /* 850 */ false,
11540 /* 851 */ false,
11541 /* 852 */ false,
11542 /* 853 */ false,
11543 /* 854 */ false,
11544 /* 855 */ false,
11545 /* 856 */ false,
11546 /* 857 */ false,
11547 /* 858 */ false,
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12364 /* 1675 */ false,
12365 /* 1676 */ false,
12366 /* 1677 */ false,
12367 /* 1678 */ false,
12368 /* 1679 */ false,
12369 /* 1680 */ false,
12370 /* 1681 */ false,
12371 /* 1682 */ false,
12372 /* 1683 */ false,
12373 /* 1684 */ false,
12374 /* 1685 */ false,
12375 /* 1686 */ false,
12376 /* 1687 */ false,
12377 // last instruction
12378 false // no trailing comma
12379};
12380
12381// Mapping from machine-independent opcode to boolean
12382const char must_clone[] = {
12383 0, // Node: 0
12384 0, // Set: 1
12385 0, // RegN: 2
12386 0, // RegI: 3
12387 0, // RegP: 4
12388 0, // RegF: 5
12389 0, // RegD: 6
12390 0, // RegL: 7
12391 0, // RegFlags: 8
12392 0, // VecS: 9
12393 0, // VecD: 10
12394 0, // VecX: 11
12395 0, // VecY: 12
12396 0, // VecZ: 13
12397 0, // _last_machine_leaf: 14
12398 0, // AbsD: 15
12399 0, // AbsF: 16
12400 0, // AbsI: 17
12401 0, // AbsL: 18
12402 0, // AddD: 19
12403 0, // AddF: 20
12404 0, // AddI: 21
12405 0, // AddL: 22
12406 0, // AddP: 23
12407 0, // Allocate: 24
12408 0, // AllocateArray: 25
12409 0, // AndI: 26
12410 0, // AndL: 27
12411 0, // ArrayCopy: 28
12412 0, // AryEq: 29
12413 0, // AtanD: 30
12414 1, // Binary: 31
12415 1, // Bool: 32
12416 0, // BoxLock: 33
12417 0, // ReverseBytesI: 34
12418 0, // ReverseBytesL: 35
12419 0, // ReverseBytesUS: 36
12420 0, // ReverseBytesS: 37
12421 0, // CProj: 38
12422 0, // CallDynamicJava: 39
12423 0, // CallJava: 40
12424 0, // CallLeaf: 41
12425 0, // CallLeafNoFP: 42
12426 0, // CallRuntime: 43
12427 0, // CallStaticJava: 44
12428 0, // CastII: 45
12429 0, // CastX2P: 46
12430 0, // CastP2X: 47
12431 0, // CastPP: 48
12432 0, // Catch: 49
12433 0, // CatchProj: 50
12434 0, // CheckCastPP: 51
12435 0, // ClearArray: 52
12436 0, // ConstraintCast: 53
12437 0, // CMoveD: 54
12438 0, // CMoveVD: 55
12439 0, // CMoveF: 56
12440 0, // CMoveVF: 57
12441 0, // CMoveI: 58
12442 0, // CMoveL: 59
12443 0, // CMoveP: 60
12444 0, // CMoveN: 61
12445 1, // CmpN: 62
12446 1, // CmpD: 63
12447 0, // CmpD3: 64
12448 1, // CmpF: 65
12449 0, // CmpF3: 66
12450 1, // CmpI: 67
12451 1, // CmpL: 68
12452 0, // CmpL3: 69
12453 0, // CmpLTMask: 70
12454 1, // CmpP: 71
12455 1, // CmpU: 72
12456 1, // CmpUL: 73
12457 0, // CompareAndSwapB: 74
12458 0, // CompareAndSwapS: 75
12459 0, // CompareAndSwapI: 76
12460 0, // CompareAndSwapL: 77
12461 0, // CompareAndSwapP: 78
12462 0, // CompareAndSwapN: 79
12463 0, // WeakCompareAndSwapB: 80
12464 0, // WeakCompareAndSwapS: 81
12465 0, // WeakCompareAndSwapI: 82
12466 0, // WeakCompareAndSwapL: 83
12467 0, // WeakCompareAndSwapP: 84
12468 0, // WeakCompareAndSwapN: 85
12469 0, // CompareAndExchangeB: 86
12470 0, // CompareAndExchangeS: 87
12471 0, // CompareAndExchangeI: 88
12472 0, // CompareAndExchangeL: 89
12473 0, // CompareAndExchangeP: 90
12474 0, // CompareAndExchangeN: 91
12475 0, // GetAndAddB: 92
12476 0, // GetAndAddS: 93
12477 0, // GetAndAddI: 94
12478 0, // GetAndAddL: 95
12479 0, // GetAndSetB: 96
12480 0, // GetAndSetS: 97
12481 0, // GetAndSetI: 98
12482 0, // GetAndSetL: 99
12483 0, // GetAndSetP: 100
12484 0, // GetAndSetN: 101
12485 0, // Con: 102
12486 0, // ConN: 103
12487 0, // ConNKlass: 104
12488 0, // ConD: 105
12489 0, // ConF: 106
12490 0, // ConI: 107
12491 0, // ConL: 108
12492 0, // ConP: 109
12493 0, // Conv2B: 110
12494 0, // ConvD2F: 111
12495 0, // ConvD2I: 112
12496 0, // ConvD2L: 113
12497 0, // ConvF2D: 114
12498 0, // ConvF2I: 115
12499 0, // ConvF2L: 116
12500 0, // ConvI2D: 117
12501 0, // ConvI2F: 118
12502 0, // ConvI2L: 119
12503 0, // ConvL2D: 120
12504 0, // ConvL2F: 121
12505 0, // ConvL2I: 122
12506 0, // CountedLoop: 123
12507 0, // CountedLoopEnd: 124
12508 0, // OuterStripMinedLoop: 125
12509 0, // OuterStripMinedLoopEnd: 126
12510 0, // CountLeadingZerosI: 127
12511 0, // CountLeadingZerosL: 128
12512 0, // CountTrailingZerosI: 129
12513 0, // CountTrailingZerosL: 130
12514 0, // CreateEx: 131
12515 0, // DecodeN: 132
12516 0, // DecodeNKlass: 133
12517 0, // DivD: 134
12518 0, // DivF: 135
12519 0, // DivI: 136
12520 0, // DivL: 137
12521 0, // DivMod: 138
12522 0, // DivModI: 139
12523 0, // DivModL: 140
12524 0, // EncodeISOArray: 141
12525 0, // EncodeP: 142
12526 0, // EncodePKlass: 143
12527 1, // FastLock: 144
12528 1, // FastUnlock: 145
12529 0, // FmaD: 146
12530 0, // FmaF: 147
12531 0, // Goto: 148
12532 0, // Halt: 149
12533 0, // HasNegatives: 150
12534 0, // If: 151
12535 0, // RangeCheck: 152
12536 0, // IfFalse: 153
12537 0, // IfTrue: 154
12538 0, // Initialize: 155
12539 0, // JProj: 156
12540 0, // Jump: 157
12541 0, // JumpProj: 158
12542 0, // LShiftI: 159
12543 0, // LShiftL: 160
12544 0, // LoadB: 161
12545 0, // LoadUB: 162
12546 0, // LoadUS: 163
12547 0, // LoadD: 164
12548 0, // LoadD_unaligned: 165
12549 0, // LoadF: 166
12550 0, // LoadI: 167
12551 0, // LoadKlass: 168
12552 0, // LoadNKlass: 169
12553 0, // LoadL: 170
12554 0, // LoadL_unaligned: 171
12555 0, // LoadPLocked: 172
12556 0, // LoadP: 173
12557 0, // LoadN: 174
12558 0, // LoadRange: 175
12559 0, // LoadS: 176
12560 0, // LoadBarrier: 177
12561 0, // LoadBarrierSlowReg: 178
12562 0, // ZCompareAndSwapP: 179
12563 0, // ZWeakCompareAndSwapP: 180
12564 0, // ZCompareAndExchangeP: 181
12565 0, // ZGetAndSetP: 182
12566 0, // Lock: 183
12567 0, // Loop: 184
12568 0, // LoopLimit: 185
12569 0, // Mach: 186
12570 0, // MachProj: 187
12571 0, // MulAddS2I: 188
12572 0, // MaxD: 189
12573 0, // MaxF: 190
12574 0, // MaxI: 191
12575 0, // MemBarAcquire: 192
12576 0, // LoadFence: 193
12577 0, // SetVectMaskI: 194
12578 0, // MemBarAcquireLock: 195
12579 0, // MemBarCPUOrder: 196
12580 0, // MemBarRelease: 197
12581 0, // StoreFence: 198
12582 0, // MemBarReleaseLock: 199
12583 0, // MemBarVolatile: 200
12584 0, // MemBarStoreStore: 201
12585 0, // MergeMem: 202
12586 0, // MinD: 203
12587 0, // MinF: 204
12588 0, // MinI: 205
12589 0, // ModD: 206
12590 0, // ModF: 207
12591 0, // ModI: 208
12592 0, // ModL: 209
12593 0, // MoveI2F: 210
12594 0, // MoveF2I: 211
12595 0, // MoveL2D: 212
12596 0, // MoveD2L: 213
12597 0, // MulD: 214
12598 0, // MulF: 215
12599 0, // MulHiL: 216
12600 0, // MulI: 217
12601 0, // MulL: 218
12602 0, // Multi: 219
12603 0, // NegD: 220
12604 0, // NegF: 221
12605 0, // NeverBranch: 222
12606 0, // OnSpinWait: 223
12607 0, // Opaque1: 224
12608 0, // Opaque2: 225
12609 0, // Opaque3: 226
12610 0, // Opaque4: 227
12611 0, // ProfileBoolean: 228
12612 0, // OrI: 229
12613 0, // OrL: 230
12614 1, // OverflowAddI: 231
12615 1, // OverflowSubI: 232
12616 1, // OverflowMulI: 233
12617 1, // OverflowAddL: 234
12618 1, // OverflowSubL: 235
12619 1, // OverflowMulL: 236
12620 0, // PCTable: 237
12621 0, // Parm: 238
12622 0, // PartialSubtypeCheck: 239
12623 0, // Phi: 240
12624 0, // PopCountI: 241
12625 0, // PopCountL: 242
12626 0, // PopCountVI: 243
12627 0, // PrefetchAllocation: 244
12628 0, // Proj: 245
12629 0, // RShiftI: 246
12630 0, // RShiftL: 247
12631 0, // Region: 248
12632 0, // Rethrow: 249
12633 0, // Return: 250
12634 0, // Root: 251
12635 0, // RoundDouble: 252
12636 0, // RoundFloat: 253
12637 0, // SafePoint: 254
12638 0, // SafePointScalarObject: 255
12639 0, // ShenandoahCompareAndExchangeP: 256
12640 0, // ShenandoahCompareAndExchangeN: 257
12641 0, // ShenandoahCompareAndSwapN: 258
12642 0, // ShenandoahCompareAndSwapP: 259
12643 0, // ShenandoahWeakCompareAndSwapN: 260
12644 0, // ShenandoahWeakCompareAndSwapP: 261
12645 0, // ShenandoahEnqueueBarrier: 262
12646 0, // ShenandoahLoadReferenceBarrier: 263
12647 0, // SCMemProj: 264
12648 0, // SqrtD: 265
12649 0, // SqrtF: 266
12650 0, // Start: 267
12651 0, // StartOSR: 268
12652 0, // StoreB: 269
12653 0, // StoreC: 270
12654 0, // StoreCM: 271
12655 0, // StorePConditional: 272
12656 0, // StoreIConditional: 273
12657 0, // StoreLConditional: 274
12658 0, // StoreD: 275
12659 0, // StoreF: 276
12660 0, // StoreI: 277
12661 0, // StoreL: 278
12662 0, // StoreP: 279
12663 0, // StoreN: 280
12664 0, // StoreNKlass: 281
12665 0, // StrComp: 282
12666 0, // StrCompressedCopy: 283
12667 0, // StrEquals: 284
12668 0, // StrIndexOf: 285
12669 0, // StrIndexOfChar: 286
12670 0, // StrInflatedCopy: 287
12671 0, // SubD: 288
12672 0, // SubF: 289
12673 0, // SubI: 290
12674 0, // SubL: 291
12675 0, // TailCall: 292
12676 0, // TailJump: 293
12677 0, // ThreadLocal: 294
12678 0, // Unlock: 295
12679 0, // URShiftI: 296
12680 0, // URShiftL: 297
12681 0, // XorI: 298
12682 0, // XorL: 299
12683 0, // Vector: 300
12684 0, // AddVB: 301
12685 0, // AddVS: 302
12686 0, // AddVI: 303
12687 0, // AddReductionVI: 304
12688 0, // AddVL: 305
12689 0, // AddReductionVL: 306
12690 0, // AddVF: 307
12691 0, // AddReductionVF: 308
12692 0, // AddVD: 309
12693 0, // AddReductionVD: 310
12694 0, // SubVB: 311
12695 0, // SubVS: 312
12696 0, // SubVI: 313
12697 0, // SubVL: 314
12698 0, // SubVF: 315
12699 0, // SubVD: 316
12700 0, // MulVB: 317
12701 0, // MulVS: 318
12702 0, // MulVI: 319
12703 0, // MulReductionVI: 320
12704 0, // MulVL: 321
12705 0, // MulReductionVL: 322
12706 0, // MulVF: 323
12707 0, // MulReductionVF: 324
12708 0, // MulVD: 325
12709 0, // MulReductionVD: 326
12710 0, // MulAddVS2VI: 327
12711 0, // FmaVD: 328
12712 0, // FmaVF: 329
12713 0, // DivVF: 330
12714 0, // DivVD: 331
12715 0, // AbsVB: 332
12716 0, // AbsVS: 333
12717 0, // AbsVI: 334
12718 0, // AbsVL: 335
12719 0, // AbsVF: 336
12720 0, // AbsVD: 337
12721 0, // NegVF: 338
12722 0, // NegVD: 339
12723 0, // SqrtVD: 340
12724 0, // SqrtVF: 341
12725 0, // LShiftCntV: 342
12726 0, // RShiftCntV: 343
12727 0, // LShiftVB: 344
12728 0, // LShiftVS: 345
12729 0, // LShiftVI: 346
12730 0, // LShiftVL: 347
12731 0, // RShiftVB: 348
12732 0, // RShiftVS: 349
12733 0, // RShiftVI: 350
12734 0, // RShiftVL: 351
12735 0, // URShiftVB: 352
12736 0, // URShiftVS: 353
12737 0, // URShiftVI: 354
12738 0, // URShiftVL: 355
12739 0, // AndV: 356
12740 0, // OrV: 357
12741 0, // XorV: 358
12742 0, // MinV: 359
12743 0, // MaxV: 360
12744 0, // MinReductionV: 361
12745 0, // MaxReductionV: 362
12746 0, // LoadVector: 363
12747 0, // StoreVector: 364
12748 0, // Pack: 365
12749 0, // PackB: 366
12750 0, // PackS: 367
12751 0, // PackI: 368
12752 0, // PackL: 369
12753 0, // PackF: 370
12754 0, // PackD: 371
12755 0, // Pack2L: 372
12756 0, // Pack2D: 373
12757 0, // ReplicateB: 374
12758 0, // ReplicateS: 375
12759 0, // ReplicateI: 376
12760 0, // ReplicateL: 377
12761 0, // ReplicateF: 378
12762 0, // ReplicateD: 379
12763 0, // Extract: 380
12764 0, // ExtractB: 381
12765 0, // ExtractUB: 382
12766 0, // ExtractC: 383
12767 0, // ExtractS: 384
12768 0, // ExtractI: 385
12769 0, // ExtractL: 386
12770 0, // ExtractF: 387
12771 0, // ExtractD: 388
12772 0, // Digit: 389
12773 0, // LowerCase: 390
12774 0, // UpperCase: 391
12775 0 // no trailing comma // Whitespace: 392
12776};
12777// The following instructions can cisc-spill
12778// MoveVL2F can cisc-spill operand 1 to loadF
12779// MoveLEG2F can cisc-spill operand 1 to loadF
12780// MoveVL2D can cisc-spill operand 1 to loadSSD
12781// MoveLEG2D can cisc-spill operand 1 to loadSSD
12782// popCountI can cisc-spill operand 1 to popCountI_mem
12783// popCountL can cisc-spill operand 1 to popCountL_mem
12784// cmovI_reg can cisc-spill operand 4 to cmovI_mem
12785// cmovI_regU can cisc-spill operand 4 to cmovI_memU
12786// cmovI_regUCF can cisc-spill operand 4 to cmovI_memUCF
12787// cmovL_reg can cisc-spill operand 4 to cmovL_mem
12788// cmovL_regU can cisc-spill operand 4 to cmovL_memU
12789// cmovL_regUCF can cisc-spill operand 4 to cmovL_memUCF
12790// addI_rReg can cisc-spill operand 2 to addI_rReg_mem
12791// addL_rReg can cisc-spill operand 2 to addL_rReg_mem
12792// subI_rReg can cisc-spill operand 2 to subI_rReg_mem
12793// subL_rReg can cisc-spill operand 2 to subL_rReg_mem
12794// mulI_rReg can cisc-spill operand 2 to mulI_mem
12795// mulI_rReg_imm can cisc-spill operand 1 to mulI_mem_imm
12796// mulL_rReg can cisc-spill operand 2 to mulL_mem
12797// mulL_rReg_imm can cisc-spill operand 1 to mulL_mem_imm
12798// i2b can cisc-spill operand 1 to loadI2B
12799// i2s can cisc-spill operand 1 to loadI2S
12800// andI_rReg can cisc-spill operand 2 to andI_rReg_mem
12801// andI2L_rReg_imm255 can cisc-spill operand 1 to loadI2L_immI_255
12802// andI2L_rReg_imm65535 can cisc-spill operand 1 to loadI2L_immI_65535
12803// andnI_rReg_rReg_rReg can cisc-spill operand 3 to andnI_rReg_rReg_mem
12804// andnI_rReg_rReg_rReg_0 can cisc-spill operand 1 to andnI_rReg_rReg_mem_0
12805// orI_rReg can cisc-spill operand 2 to orI_rReg_mem
12806// xorI_rReg can cisc-spill operand 2 to xorI_rReg_mem
12807// andL_rReg can cisc-spill operand 2 to andL_rReg_mem
12808// andnL_rReg_rReg_rReg can cisc-spill operand 3 to andnL_rReg_rReg_mem
12809// andnL_rReg_rReg_rReg_0 can cisc-spill operand 1 to andnL_rReg_rReg_mem_0
12810// orL_rReg can cisc-spill operand 2 to orL_rReg_mem
12811// xorL_rReg can cisc-spill operand 2 to xorL_rReg_mem
12812// cmpF_cc_reg can cisc-spill operand 2 to cmpF_cc_mem
12813// cmpF_cc_reg_CF can cisc-spill operand 2 to cmpF_cc_memCF
12814// cmpD_cc_reg can cisc-spill operand 2 to cmpD_cc_mem
12815// cmpD_cc_reg_CF can cisc-spill operand 2 to cmpD_cc_memCF
12816// cmpF_reg can cisc-spill operand 2 to cmpF_mem
12817// cmpD_reg can cisc-spill operand 2 to cmpD_mem
12818// convF2D_reg_reg can cisc-spill operand 1 to convF2D_reg_mem
12819// convD2F_reg_reg can cisc-spill operand 1 to convD2F_reg_mem
12820// convL2F_reg_reg can cisc-spill operand 1 to convL2F_reg_mem
12821// convL2D_reg_reg can cisc-spill operand 1 to convL2D_reg_mem
12822// convI2L_reg_reg can cisc-spill operand 1 to loadI2L
12823// convI2L_reg_reg_zex can cisc-spill operand 1 to loadUI2L
12824// MoveF2I_reg_reg can cisc-spill operand 1 to MoveF2I_stack_reg
12825// MoveD2L_reg_reg can cisc-spill operand 1 to MoveD2L_stack_reg
12826// MoveI2F_reg_reg can cisc-spill operand 1 to MoveI2F_stack_reg
12827// compI_rReg can cisc-spill operand 2 to compI_rReg_mem
12828// compU_rReg can cisc-spill operand 2 to compU_rReg_mem
12829// compP_rReg can cisc-spill operand 2 to compP_rReg_mem
12830// compL_rReg can cisc-spill operand 2 to compL_rReg_mem
12831// compUL_rReg can cisc-spill operand 2 to compUL_rReg_mem
12832// addF_reg can cisc-spill operand 2 to addF_mem
12833// addF_reg_reg can cisc-spill operand 2 to addF_reg_mem
12834// addD_reg can cisc-spill operand 2 to addD_mem
12835// addD_reg_reg can cisc-spill operand 2 to addD_reg_mem
12836// subF_reg can cisc-spill operand 2 to subF_mem
12837// subF_reg_reg can cisc-spill operand 2 to subF_reg_mem
12838// subD_reg can cisc-spill operand 2 to subD_mem
12839// subD_reg_reg can cisc-spill operand 2 to subD_reg_mem
12840// mulF_reg can cisc-spill operand 2 to mulF_mem
12841// mulF_reg_reg can cisc-spill operand 2 to mulF_reg_mem
12842// mulD_reg can cisc-spill operand 2 to mulD_mem
12843// mulD_reg_reg can cisc-spill operand 2 to mulD_reg_mem
12844// divF_reg can cisc-spill operand 2 to divF_mem
12845// divF_reg_reg can cisc-spill operand 2 to divF_reg_mem
12846// divD_reg can cisc-spill operand 2 to divD_mem
12847// divD_reg_reg can cisc-spill operand 2 to divD_reg_mem
12848// sqrtF_reg can cisc-spill operand 1 to sqrtF_mem
12849// sqrtD_reg can cisc-spill operand 1 to sqrtD_mem
12850// Repl8I can cisc-spill operand 1 to Repl8I_mem
12851// Repl16I can cisc-spill operand 1 to Repl16I_mem
12852// Repl4L can cisc-spill operand 1 to Repl4L_mem
12853// Repl8L can cisc-spill operand 1 to Repl8L_mem
12854// Repl2I can cisc-spill operand 1 to Repl2I_mem
12855// Repl4I_evex can cisc-spill operand 1 to Repl4I_mem_evex
12856// Repl8I_evex can cisc-spill operand 1 to Repl8I_mem_evex
12857// Repl16I_evex can cisc-spill operand 1 to Repl16I_mem_evex
12858// Repl4L_evex can cisc-spill operand 1 to Repl4L_mem_evex
12859// Repl8L_evex can cisc-spill operand 1 to Repl8L_mem_evex
12860// Repl8F_evex can cisc-spill operand 1 to Repl8F_mem_evex
12861// Repl16F_evex can cisc-spill operand 1 to Repl16F_mem_evex
12862// Repl4D_evex can cisc-spill operand 1 to Repl4D_mem_evex
12863// Repl8D_evex can cisc-spill operand 1 to Repl8D_mem_evex
12864
12865
12866
12867// An array of character pointers to machine register names.
12868const char *Matcher::regName[REG_COUNT] = {
12869 "R10",
12870 "R10_H",
12871 "R11",
12872 "R11_H",
12873 "R8",
12874 "R8_H",
12875 "R9",
12876 "R9_H",
12877 "R12",
12878 "R12_H",
12879 "RCX",
12880 "RCX_H",
12881 "RBX",
12882 "RBX_H",
12883 "RDI",
12884 "RDI_H",
12885 "RDX",
12886 "RDX_H",
12887 "RSI",
12888 "RSI_H",
12889 "RAX",
12890 "RAX_H",
12891 "RBP",
12892 "RBP_H",
12893 "R13",
12894 "R13_H",
12895 "R14",
12896 "R14_H",
12897 "R15",
12898 "R15_H",
12899 "RSP",
12900 "RSP_H",
12901 "XMM0",
12902 "XMM0b",
12903 "XMM0c",
12904 "XMM0d",
12905 "XMM0e",
12906 "XMM0f",
12907 "XMM0g",
12908 "XMM0h",
12909 "XMM0i",
12910 "XMM0j",
12911 "XMM0k",
12912 "XMM0l",
12913 "XMM0m",
12914 "XMM0n",
12915 "XMM0o",
12916 "XMM0p",
12917 "XMM1",
12918 "XMM1b",
12919 "XMM1c",
12920 "XMM1d",
12921 "XMM1e",
12922 "XMM1f",
12923 "XMM1g",
12924 "XMM1h",
12925 "XMM1i",
12926 "XMM1j",
12927 "XMM1k",
12928 "XMM1l",
12929 "XMM1m",
12930 "XMM1n",
12931 "XMM1o",
12932 "XMM1p",
12933 "XMM2",
12934 "XMM2b",
12935 "XMM2c",
12936 "XMM2d",
12937 "XMM2e",
12938 "XMM2f",
12939 "XMM2g",
12940 "XMM2h",
12941 "XMM2i",
12942 "XMM2j",
12943 "XMM2k",
12944 "XMM2l",
12945 "XMM2m",
12946 "XMM2n",
12947 "XMM2o",
12948 "XMM2p",
12949 "XMM3",
12950 "XMM3b",
12951 "XMM3c",
12952 "XMM3d",
12953 "XMM3e",
12954 "XMM3f",
12955 "XMM3g",
12956 "XMM3h",
12957 "XMM3i",
12958 "XMM3j",
12959 "XMM3k",
12960 "XMM3l",
12961 "XMM3m",
12962 "XMM3n",
12963 "XMM3o",
12964 "XMM3p",
12965 "XMM4",
12966 "XMM4b",
12967 "XMM4c",
12968 "XMM4d",
12969 "XMM4e",
12970 "XMM4f",
12971 "XMM4g",
12972 "XMM4h",
12973 "XMM4i",
12974 "XMM4j",
12975 "XMM4k",
12976 "XMM4l",
12977 "XMM4m",
12978 "XMM4n",
12979 "XMM4o",
12980 "XMM4p",
12981 "XMM5",
12982 "XMM5b",
12983 "XMM5c",
12984 "XMM5d",
12985 "XMM5e",
12986 "XMM5f",
12987 "XMM5g",
12988 "XMM5h",
12989 "XMM5i",
12990 "XMM5j",
12991 "XMM5k",
12992 "XMM5l",
12993 "XMM5m",
12994 "XMM5n",
12995 "XMM5o",
12996 "XMM5p",
12997 "XMM6",
12998 "XMM6b",
12999 "XMM6c",
13000 "XMM6d",
13001 "XMM6e",
13002 "XMM6f",
13003 "XMM6g",
13004 "XMM6h",
13005 "XMM6i",
13006 "XMM6j",
13007 "XMM6k",
13008 "XMM6l",
13009 "XMM6m",
13010 "XMM6n",
13011 "XMM6o",
13012 "XMM6p",
13013 "XMM7",
13014 "XMM7b",
13015 "XMM7c",
13016 "XMM7d",
13017 "XMM7e",
13018 "XMM7f",
13019 "XMM7g",
13020 "XMM7h",
13021 "XMM7i",
13022 "XMM7j",
13023 "XMM7k",
13024 "XMM7l",
13025 "XMM7m",
13026 "XMM7n",
13027 "XMM7o",
13028 "XMM7p",
13029 "XMM8",
13030 "XMM8b",
13031 "XMM8c",
13032 "XMM8d",
13033 "XMM8e",
13034 "XMM8f",
13035 "XMM8g",
13036 "XMM8h",
13037 "XMM8i",
13038 "XMM8j",
13039 "XMM8k",
13040 "XMM8l",
13041 "XMM8m",
13042 "XMM8n",
13043 "XMM8o",
13044 "XMM8p",
13045 "XMM9",
13046 "XMM9b",
13047 "XMM9c",
13048 "XMM9d",
13049 "XMM9e",
13050 "XMM9f",
13051 "XMM9g",
13052 "XMM9h",
13053 "XMM9i",
13054 "XMM9j",
13055 "XMM9k",
13056 "XMM9l",
13057 "XMM9m",
13058 "XMM9n",
13059 "XMM9o",
13060 "XMM9p",
13061 "XMM10",
13062 "XMM10b",
13063 "XMM10c",
13064 "XMM10d",
13065 "XMM10e",
13066 "XMM10f",
13067 "XMM10g",
13068 "XMM10h",
13069 "XMM10i",
13070 "XMM10j",
13071 "XMM10k",
13072 "XMM10l",
13073 "XMM10m",
13074 "XMM10n",
13075 "XMM10o",
13076 "XMM10p",
13077 "XMM11",
13078 "XMM11b",
13079 "XMM11c",
13080 "XMM11d",
13081 "XMM11e",
13082 "XMM11f",
13083 "XMM11g",
13084 "XMM11h",
13085 "XMM11i",
13086 "XMM11j",
13087 "XMM11k",
13088 "XMM11l",
13089 "XMM11m",
13090 "XMM11n",
13091 "XMM11o",
13092 "XMM11p",
13093 "XMM12",
13094 "XMM12b",
13095 "XMM12c",
13096 "XMM12d",
13097 "XMM12e",
13098 "XMM12f",
13099 "XMM12g",
13100 "XMM12h",
13101 "XMM12i",
13102 "XMM12j",
13103 "XMM12k",
13104 "XMM12l",
13105 "XMM12m",
13106 "XMM12n",
13107 "XMM12o",
13108 "XMM12p",
13109 "XMM13",
13110 "XMM13b",
13111 "XMM13c",
13112 "XMM13d",
13113 "XMM13e",
13114 "XMM13f",
13115 "XMM13g",
13116 "XMM13h",
13117 "XMM13i",
13118 "XMM13j",
13119 "XMM13k",
13120 "XMM13l",
13121 "XMM13m",
13122 "XMM13n",
13123 "XMM13o",
13124 "XMM13p",
13125 "XMM14",
13126 "XMM14b",
13127 "XMM14c",
13128 "XMM14d",
13129 "XMM14e",
13130 "XMM14f",
13131 "XMM14g",
13132 "XMM14h",
13133 "XMM14i",
13134 "XMM14j",
13135 "XMM14k",
13136 "XMM14l",
13137 "XMM14m",
13138 "XMM14n",
13139 "XMM14o",
13140 "XMM14p",
13141 "XMM15",
13142 "XMM15b",
13143 "XMM15c",
13144 "XMM15d",
13145 "XMM15e",
13146 "XMM15f",
13147 "XMM15g",
13148 "XMM15h",
13149 "XMM15i",
13150 "XMM15j",
13151 "XMM15k",
13152 "XMM15l",
13153 "XMM15m",
13154 "XMM15n",
13155 "XMM15o",
13156 "XMM15p",
13157 "XMM16",
13158 "XMM16b",
13159 "XMM16c",
13160 "XMM16d",
13161 "XMM16e",
13162 "XMM16f",
13163 "XMM16g",
13164 "XMM16h",
13165 "XMM16i",
13166 "XMM16j",
13167 "XMM16k",
13168 "XMM16l",
13169 "XMM16m",
13170 "XMM16n",
13171 "XMM16o",
13172 "XMM16p",
13173 "XMM17",
13174 "XMM17b",
13175 "XMM17c",
13176 "XMM17d",
13177 "XMM17e",
13178 "XMM17f",
13179 "XMM17g",
13180 "XMM17h",
13181 "XMM17i",
13182 "XMM17j",
13183 "XMM17k",
13184 "XMM17l",
13185 "XMM17m",
13186 "XMM17n",
13187 "XMM17o",
13188 "XMM17p",
13189 "XMM18",
13190 "XMM18b",
13191 "XMM18c",
13192 "XMM18d",
13193 "XMM18e",
13194 "XMM18f",
13195 "XMM18g",
13196 "XMM18h",
13197 "XMM18i",
13198 "XMM18j",
13199 "XMM18k",
13200 "XMM18l",
13201 "XMM18m",
13202 "XMM18n",
13203 "XMM18o",
13204 "XMM18p",
13205 "XMM19",
13206 "XMM19b",
13207 "XMM19c",
13208 "XMM19d",
13209 "XMM19e",
13210 "XMM19f",
13211 "XMM19g",
13212 "XMM19h",
13213 "XMM19i",
13214 "XMM19j",
13215 "XMM19k",
13216 "XMM19l",
13217 "XMM19m",
13218 "XMM19n",
13219 "XMM19o",
13220 "XMM19p",
13221 "XMM20",
13222 "XMM20b",
13223 "XMM20c",
13224 "XMM20d",
13225 "XMM20e",
13226 "XMM20f",
13227 "XMM20g",
13228 "XMM20h",
13229 "XMM20i",
13230 "XMM20j",
13231 "XMM20k",
13232 "XMM20l",
13233 "XMM20m",
13234 "XMM20n",
13235 "XMM20o",
13236 "XMM20p",
13237 "XMM21",
13238 "XMM21b",
13239 "XMM21c",
13240 "XMM21d",
13241 "XMM21e",
13242 "XMM21f",
13243 "XMM21g",
13244 "XMM21h",
13245 "XMM21i",
13246 "XMM21j",
13247 "XMM21k",
13248 "XMM21l",
13249 "XMM21m",
13250 "XMM21n",
13251 "XMM21o",
13252 "XMM21p",
13253 "XMM22",
13254 "XMM22b",
13255 "XMM22c",
13256 "XMM22d",
13257 "XMM22e",
13258 "XMM22f",
13259 "XMM22g",
13260 "XMM22h",
13261 "XMM22i",
13262 "XMM22j",
13263 "XMM22k",
13264 "XMM22l",
13265 "XMM22m",
13266 "XMM22n",
13267 "XMM22o",
13268 "XMM22p",
13269 "XMM23",
13270 "XMM23b",
13271 "XMM23c",
13272 "XMM23d",
13273 "XMM23e",
13274 "XMM23f",
13275 "XMM23g",
13276 "XMM23h",
13277 "XMM23i",
13278 "XMM23j",
13279 "XMM23k",
13280 "XMM23l",
13281 "XMM23m",
13282 "XMM23n",
13283 "XMM23o",
13284 "XMM23p",
13285 "XMM24",
13286 "XMM24b",
13287 "XMM24c",
13288 "XMM24d",
13289 "XMM24e",
13290 "XMM24f",
13291 "XMM24g",
13292 "XMM24h",
13293 "XMM24i",
13294 "XMM24j",
13295 "XMM24k",
13296 "XMM24l",
13297 "XMM24m",
13298 "XMM24n",
13299 "XMM24o",
13300 "XMM24p",
13301 "XMM25",
13302 "XMM25b",
13303 "XMM25c",
13304 "XMM25d",
13305 "XMM25e",
13306 "XMM25f",
13307 "XMM25g",
13308 "XMM25h",
13309 "XMM25i",
13310 "XMM25j",
13311 "XMM25k",
13312 "XMM25l",
13313 "XMM25m",
13314 "XMM25n",
13315 "XMM25o",
13316 "XMM25p",
13317 "XMM26",
13318 "XMM26b",
13319 "XMM26c",
13320 "XMM26d",
13321 "XMM26e",
13322 "XMM26f",
13323 "XMM26g",
13324 "XMM26h",
13325 "XMM26i",
13326 "XMM26j",
13327 "XMM26k",
13328 "XMM26l",
13329 "XMM26m",
13330 "XMM26n",
13331 "XMM26o",
13332 "XMM26p",
13333 "XMM27",
13334 "XMM27b",
13335 "XMM27c",
13336 "XMM27d",
13337 "XMM27e",
13338 "XMM27f",
13339 "XMM27g",
13340 "XMM27h",
13341 "XMM27i",
13342 "XMM27j",
13343 "XMM27k",
13344 "XMM27l",
13345 "XMM27m",
13346 "XMM27n",
13347 "XMM27o",
13348 "XMM27p",
13349 "XMM28",
13350 "XMM28b",
13351 "XMM28c",
13352 "XMM28d",
13353 "XMM28e",
13354 "XMM28f",
13355 "XMM28g",
13356 "XMM28h",
13357 "XMM28i",
13358 "XMM28j",
13359 "XMM28k",
13360 "XMM28l",
13361 "XMM28m",
13362 "XMM28n",
13363 "XMM28o",
13364 "XMM28p",
13365 "XMM29",
13366 "XMM29b",
13367 "XMM29c",
13368 "XMM29d",
13369 "XMM29e",
13370 "XMM29f",
13371 "XMM29g",
13372 "XMM29h",
13373 "XMM29i",
13374 "XMM29j",
13375 "XMM29k",
13376 "XMM29l",
13377 "XMM29m",
13378 "XMM29n",
13379 "XMM29o",
13380 "XMM29p",
13381 "XMM30",
13382 "XMM30b",
13383 "XMM30c",
13384 "XMM30d",
13385 "XMM30e",
13386 "XMM30f",
13387 "XMM30g",
13388 "XMM30h",
13389 "XMM30i",
13390 "XMM30j",
13391 "XMM30k",
13392 "XMM30l",
13393 "XMM30m",
13394 "XMM30n",
13395 "XMM30o",
13396 "XMM30p",
13397 "XMM31",
13398 "XMM31b",
13399 "XMM31c",
13400 "XMM31d",
13401 "XMM31e",
13402 "XMM31f",
13403 "XMM31g",
13404 "XMM31h",
13405 "XMM31i",
13406 "XMM31j",
13407 "XMM31k",
13408 "XMM31l",
13409 "XMM31m",
13410 "XMM31n",
13411 "XMM31o",
13412 "XMM31p",
13413 "RFLAGS" // no trailing comma
13414};
13415
13416// An array of character pointers to machine register names.
13417const VMReg OptoReg::opto2vm[REG_COUNT] = {
13418 r10->as_VMReg(),
13419 r10->as_VMReg()->next(),
13420 r11->as_VMReg(),
13421 r11->as_VMReg()->next(),
13422 r8->as_VMReg(),
13423 r8->as_VMReg()->next(),
13424 r9->as_VMReg(),
13425 r9->as_VMReg()->next(),
13426 r12->as_VMReg(),
13427 r12->as_VMReg()->next(),
13428 rcx->as_VMReg(),
13429 rcx->as_VMReg()->next(),
13430 rbx->as_VMReg(),
13431 rbx->as_VMReg()->next(),
13432 rdi->as_VMReg(),
13433 rdi->as_VMReg()->next(),
13434 rdx->as_VMReg(),
13435 rdx->as_VMReg()->next(),
13436 rsi->as_VMReg(),
13437 rsi->as_VMReg()->next(),
13438 rax->as_VMReg(),
13439 rax->as_VMReg()->next(),
13440 rbp->as_VMReg(),
13441 rbp->as_VMReg()->next(),
13442 r13->as_VMReg(),
13443 r13->as_VMReg()->next(),
13444 r14->as_VMReg(),
13445 r14->as_VMReg()->next(),
13446 r15->as_VMReg(),
13447 r15->as_VMReg()->next(),
13448 rsp->as_VMReg(),
13449 rsp->as_VMReg()->next(),
13450 xmm0->as_VMReg(),
13451 xmm0->as_VMReg()->next(1),
13452 xmm0->as_VMReg()->next(2),
13453 xmm0->as_VMReg()->next(3),
13454 xmm0->as_VMReg()->next(4),
13455 xmm0->as_VMReg()->next(5),
13456 xmm0->as_VMReg()->next(6),
13457 xmm0->as_VMReg()->next(7),
13458 xmm0->as_VMReg()->next(8),
13459 xmm0->as_VMReg()->next(9),
13460 xmm0->as_VMReg()->next(10),
13461 xmm0->as_VMReg()->next(11),
13462 xmm0->as_VMReg()->next(12),
13463 xmm0->as_VMReg()->next(13),
13464 xmm0->as_VMReg()->next(14),
13465 xmm0->as_VMReg()->next(15),
13466 xmm1->as_VMReg(),
13467 xmm1->as_VMReg()->next(1),
13468 xmm1->as_VMReg()->next(2),
13469 xmm1->as_VMReg()->next(3),
13470 xmm1->as_VMReg()->next(4),
13471 xmm1->as_VMReg()->next(5),
13472 xmm1->as_VMReg()->next(6),
13473 xmm1->as_VMReg()->next(7),
13474 xmm1->as_VMReg()->next(8),
13475 xmm1->as_VMReg()->next(9),
13476 xmm1->as_VMReg()->next(10),
13477 xmm1->as_VMReg()->next(11),
13478 xmm1->as_VMReg()->next(12),
13479 xmm1->as_VMReg()->next(13),
13480 xmm1->as_VMReg()->next(14),
13481 xmm1->as_VMReg()->next(15),
13482 xmm2->as_VMReg(),
13483 xmm2->as_VMReg()->next(1),
13484 xmm2->as_VMReg()->next(2),
13485 xmm2->as_VMReg()->next(3),
13486 xmm2->as_VMReg()->next(4),
13487 xmm2->as_VMReg()->next(5),
13488 xmm2->as_VMReg()->next(6),
13489 xmm2->as_VMReg()->next(7),
13490 xmm2->as_VMReg()->next(8),
13491 xmm2->as_VMReg()->next(9),
13492 xmm2->as_VMReg()->next(10),
13493 xmm2->as_VMReg()->next(11),
13494 xmm2->as_VMReg()->next(12),
13495 xmm2->as_VMReg()->next(13),
13496 xmm2->as_VMReg()->next(14),
13497 xmm2->as_VMReg()->next(15),
13498 xmm3->as_VMReg(),
13499 xmm3->as_VMReg()->next(1),
13500 xmm3->as_VMReg()->next(2),
13501 xmm3->as_VMReg()->next(3),
13502 xmm3->as_VMReg()->next(4),
13503 xmm3->as_VMReg()->next(5),
13504 xmm3->as_VMReg()->next(6),
13505 xmm3->as_VMReg()->next(7),
13506 xmm3->as_VMReg()->next(8),
13507 xmm3->as_VMReg()->next(9),
13508 xmm3->as_VMReg()->next(10),
13509 xmm3->as_VMReg()->next(11),
13510 xmm3->as_VMReg()->next(12),
13511 xmm3->as_VMReg()->next(13),
13512 xmm3->as_VMReg()->next(14),
13513 xmm3->as_VMReg()->next(15),
13514 xmm4->as_VMReg(),
13515 xmm4->as_VMReg()->next(1),
13516 xmm4->as_VMReg()->next(2),
13517 xmm4->as_VMReg()->next(3),
13518 xmm4->as_VMReg()->next(4),
13519 xmm4->as_VMReg()->next(5),
13520 xmm4->as_VMReg()->next(6),
13521 xmm4->as_VMReg()->next(7),
13522 xmm4->as_VMReg()->next(8),
13523 xmm4->as_VMReg()->next(9),
13524 xmm4->as_VMReg()->next(10),
13525 xmm4->as_VMReg()->next(11),
13526 xmm4->as_VMReg()->next(12),
13527 xmm4->as_VMReg()->next(13),
13528 xmm4->as_VMReg()->next(14),
13529 xmm4->as_VMReg()->next(15),
13530 xmm5->as_VMReg(),
13531 xmm5->as_VMReg()->next(1),
13532 xmm5->as_VMReg()->next(2),
13533 xmm5->as_VMReg()->next(3),
13534 xmm5->as_VMReg()->next(4),
13535 xmm5->as_VMReg()->next(5),
13536 xmm5->as_VMReg()->next(6),
13537 xmm5->as_VMReg()->next(7),
13538 xmm5->as_VMReg()->next(8),
13539 xmm5->as_VMReg()->next(9),
13540 xmm5->as_VMReg()->next(10),
13541 xmm5->as_VMReg()->next(11),
13542 xmm5->as_VMReg()->next(12),
13543 xmm5->as_VMReg()->next(13),
13544 xmm5->as_VMReg()->next(14),
13545 xmm5->as_VMReg()->next(15),
13546 xmm6->as_VMReg(),
13547 xmm6->as_VMReg()->next(1),
13548 xmm6->as_VMReg()->next(2),
13549 xmm6->as_VMReg()->next(3),
13550 xmm6->as_VMReg()->next(4),
13551 xmm6->as_VMReg()->next(5),
13552 xmm6->as_VMReg()->next(6),
13553 xmm6->as_VMReg()->next(7),
13554 xmm6->as_VMReg()->next(8),
13555 xmm6->as_VMReg()->next(9),
13556 xmm6->as_VMReg()->next(10),
13557 xmm6->as_VMReg()->next(11),
13558 xmm6->as_VMReg()->next(12),
13559 xmm6->as_VMReg()->next(13),
13560 xmm6->as_VMReg()->next(14),
13561 xmm6->as_VMReg()->next(15),
13562 xmm7->as_VMReg(),
13563 xmm7->as_VMReg()->next(1),
13564 xmm7->as_VMReg()->next(2),
13565 xmm7->as_VMReg()->next(3),
13566 xmm7->as_VMReg()->next(4),
13567 xmm7->as_VMReg()->next(5),
13568 xmm7->as_VMReg()->next(6),
13569 xmm7->as_VMReg()->next(7),
13570 xmm7->as_VMReg()->next(8),
13571 xmm7->as_VMReg()->next(9),
13572 xmm7->as_VMReg()->next(10),
13573 xmm7->as_VMReg()->next(11),
13574 xmm7->as_VMReg()->next(12),
13575 xmm7->as_VMReg()->next(13),
13576 xmm7->as_VMReg()->next(14),
13577 xmm7->as_VMReg()->next(15),
13578 xmm8->as_VMReg(),
13579 xmm8->as_VMReg()->next(1),
13580 xmm8->as_VMReg()->next(2),
13581 xmm8->as_VMReg()->next(3),
13582 xmm8->as_VMReg()->next(4),
13583 xmm8->as_VMReg()->next(5),
13584 xmm8->as_VMReg()->next(6),
13585 xmm8->as_VMReg()->next(7),
13586 xmm8->as_VMReg()->next(8),
13587 xmm8->as_VMReg()->next(9),
13588 xmm8->as_VMReg()->next(10),
13589 xmm8->as_VMReg()->next(11),
13590 xmm8->as_VMReg()->next(12),
13591 xmm8->as_VMReg()->next(13),
13592 xmm8->as_VMReg()->next(14),
13593 xmm8->as_VMReg()->next(15),
13594 xmm9->as_VMReg(),
13595 xmm9->as_VMReg()->next(1),
13596 xmm9->as_VMReg()->next(2),
13597 xmm9->as_VMReg()->next(3),
13598 xmm9->as_VMReg()->next(4),
13599 xmm9->as_VMReg()->next(5),
13600 xmm9->as_VMReg()->next(6),
13601 xmm9->as_VMReg()->next(7),
13602 xmm9->as_VMReg()->next(8),
13603 xmm9->as_VMReg()->next(9),
13604 xmm9->as_VMReg()->next(10),
13605 xmm9->as_VMReg()->next(11),
13606 xmm9->as_VMReg()->next(12),
13607 xmm9->as_VMReg()->next(13),
13608 xmm9->as_VMReg()->next(14),
13609 xmm9->as_VMReg()->next(15),
13610 xmm10->as_VMReg(),
13611 xmm10->as_VMReg()->next(1),
13612 xmm10->as_VMReg()->next(2),
13613 xmm10->as_VMReg()->next(3),
13614 xmm10->as_VMReg()->next(4),
13615 xmm10->as_VMReg()->next(5),
13616 xmm10->as_VMReg()->next(6),
13617 xmm10->as_VMReg()->next(7),
13618 xmm10->as_VMReg()->next(8),
13619 xmm10->as_VMReg()->next(9),
13620 xmm10->as_VMReg()->next(10),
13621 xmm10->as_VMReg()->next(11),
13622 xmm10->as_VMReg()->next(12),
13623 xmm10->as_VMReg()->next(13),
13624 xmm10->as_VMReg()->next(14),
13625 xmm10->as_VMReg()->next(15),
13626 xmm11->as_VMReg(),
13627 xmm11->as_VMReg()->next(1),
13628 xmm11->as_VMReg()->next(2),
13629 xmm11->as_VMReg()->next(3),
13630 xmm11->as_VMReg()->next(4),
13631 xmm11->as_VMReg()->next(5),
13632 xmm11->as_VMReg()->next(6),
13633 xmm11->as_VMReg()->next(7),
13634 xmm11->as_VMReg()->next(8),
13635 xmm11->as_VMReg()->next(9),
13636 xmm11->as_VMReg()->next(10),
13637 xmm11->as_VMReg()->next(11),
13638 xmm11->as_VMReg()->next(12),
13639 xmm11->as_VMReg()->next(13),
13640 xmm11->as_VMReg()->next(14),
13641 xmm11->as_VMReg()->next(15),
13642 xmm12->as_VMReg(),
13643 xmm12->as_VMReg()->next(1),
13644 xmm12->as_VMReg()->next(2),
13645 xmm12->as_VMReg()->next(3),
13646 xmm12->as_VMReg()->next(4),
13647 xmm12->as_VMReg()->next(5),
13648 xmm12->as_VMReg()->next(6),
13649 xmm12->as_VMReg()->next(7),
13650 xmm12->as_VMReg()->next(8),
13651 xmm12->as_VMReg()->next(9),
13652 xmm12->as_VMReg()->next(10),
13653 xmm12->as_VMReg()->next(11),
13654 xmm12->as_VMReg()->next(12),
13655 xmm12->as_VMReg()->next(13),
13656 xmm12->as_VMReg()->next(14),
13657 xmm12->as_VMReg()->next(15),
13658 xmm13->as_VMReg(),
13659 xmm13->as_VMReg()->next(1),
13660 xmm13->as_VMReg()->next(2),
13661 xmm13->as_VMReg()->next(3),
13662 xmm13->as_VMReg()->next(4),
13663 xmm13->as_VMReg()->next(5),
13664 xmm13->as_VMReg()->next(6),
13665 xmm13->as_VMReg()->next(7),
13666 xmm13->as_VMReg()->next(8),
13667 xmm13->as_VMReg()->next(9),
13668 xmm13->as_VMReg()->next(10),
13669 xmm13->as_VMReg()->next(11),
13670 xmm13->as_VMReg()->next(12),
13671 xmm13->as_VMReg()->next(13),
13672 xmm13->as_VMReg()->next(14),
13673 xmm13->as_VMReg()->next(15),
13674 xmm14->as_VMReg(),
13675 xmm14->as_VMReg()->next(1),
13676 xmm14->as_VMReg()->next(2),
13677 xmm14->as_VMReg()->next(3),
13678 xmm14->as_VMReg()->next(4),
13679 xmm14->as_VMReg()->next(5),
13680 xmm14->as_VMReg()->next(6),
13681 xmm14->as_VMReg()->next(7),
13682 xmm14->as_VMReg()->next(8),
13683 xmm14->as_VMReg()->next(9),
13684 xmm14->as_VMReg()->next(10),
13685 xmm14->as_VMReg()->next(11),
13686 xmm14->as_VMReg()->next(12),
13687 xmm14->as_VMReg()->next(13),
13688 xmm14->as_VMReg()->next(14),
13689 xmm14->as_VMReg()->next(15),
13690 xmm15->as_VMReg(),
13691 xmm15->as_VMReg()->next(1),
13692 xmm15->as_VMReg()->next(2),
13693 xmm15->as_VMReg()->next(3),
13694 xmm15->as_VMReg()->next(4),
13695 xmm15->as_VMReg()->next(5),
13696 xmm15->as_VMReg()->next(6),
13697 xmm15->as_VMReg()->next(7),
13698 xmm15->as_VMReg()->next(8),
13699 xmm15->as_VMReg()->next(9),
13700 xmm15->as_VMReg()->next(10),
13701 xmm15->as_VMReg()->next(11),
13702 xmm15->as_VMReg()->next(12),
13703 xmm15->as_VMReg()->next(13),
13704 xmm15->as_VMReg()->next(14),
13705 xmm15->as_VMReg()->next(15),
13706 xmm16->as_VMReg(),
13707 xmm16->as_VMReg()->next(1),
13708 xmm16->as_VMReg()->next(2),
13709 xmm16->as_VMReg()->next(3),
13710 xmm16->as_VMReg()->next(4),
13711 xmm16->as_VMReg()->next(5),
13712 xmm16->as_VMReg()->next(6),
13713 xmm16->as_VMReg()->next(7),
13714 xmm16->as_VMReg()->next(8),
13715 xmm16->as_VMReg()->next(9),
13716 xmm16->as_VMReg()->next(10),
13717 xmm16->as_VMReg()->next(11),
13718 xmm16->as_VMReg()->next(12),
13719 xmm16->as_VMReg()->next(13),
13720 xmm16->as_VMReg()->next(14),
13721 xmm16->as_VMReg()->next(15),
13722 xmm17->as_VMReg(),
13723 xmm17->as_VMReg()->next(1),
13724 xmm17->as_VMReg()->next(2),
13725 xmm17->as_VMReg()->next(3),
13726 xmm17->as_VMReg()->next(4),
13727 xmm17->as_VMReg()->next(5),
13728 xmm17->as_VMReg()->next(6),
13729 xmm17->as_VMReg()->next(7),
13730 xmm17->as_VMReg()->next(8),
13731 xmm17->as_VMReg()->next(9),
13732 xmm17->as_VMReg()->next(10),
13733 xmm17->as_VMReg()->next(11),
13734 xmm17->as_VMReg()->next(12),
13735 xmm17->as_VMReg()->next(13),
13736 xmm17->as_VMReg()->next(14),
13737 xmm17->as_VMReg()->next(15),
13738 xmm18->as_VMReg(),
13739 xmm18->as_VMReg()->next(1),
13740 xmm18->as_VMReg()->next(2),
13741 xmm18->as_VMReg()->next(3),
13742 xmm18->as_VMReg()->next(4),
13743 xmm18->as_VMReg()->next(5),
13744 xmm18->as_VMReg()->next(6),
13745 xmm18->as_VMReg()->next(7),
13746 xmm18->as_VMReg()->next(8),
13747 xmm18->as_VMReg()->next(9),
13748 xmm18->as_VMReg()->next(10),
13749 xmm18->as_VMReg()->next(11),
13750 xmm18->as_VMReg()->next(12),
13751 xmm18->as_VMReg()->next(13),
13752 xmm18->as_VMReg()->next(14),
13753 xmm18->as_VMReg()->next(15),
13754 xmm19->as_VMReg(),
13755 xmm19->as_VMReg()->next(1),
13756 xmm19->as_VMReg()->next(2),
13757 xmm19->as_VMReg()->next(3),
13758 xmm19->as_VMReg()->next(4),
13759 xmm19->as_VMReg()->next(5),
13760 xmm19->as_VMReg()->next(6),
13761 xmm19->as_VMReg()->next(7),
13762 xmm19->as_VMReg()->next(8),
13763 xmm19->as_VMReg()->next(9),
13764 xmm19->as_VMReg()->next(10),
13765 xmm19->as_VMReg()->next(11),
13766 xmm19->as_VMReg()->next(12),
13767 xmm19->as_VMReg()->next(13),
13768 xmm19->as_VMReg()->next(14),
13769 xmm19->as_VMReg()->next(15),
13770 xmm20->as_VMReg(),
13771 xmm20->as_VMReg()->next(1),
13772 xmm20->as_VMReg()->next(2),
13773 xmm20->as_VMReg()->next(3),
13774 xmm20->as_VMReg()->next(4),
13775 xmm20->as_VMReg()->next(5),
13776 xmm20->as_VMReg()->next(6),
13777 xmm20->as_VMReg()->next(7),
13778 xmm20->as_VMReg()->next(8),
13779 xmm20->as_VMReg()->next(9),
13780 xmm20->as_VMReg()->next(10),
13781 xmm20->as_VMReg()->next(11),
13782 xmm20->as_VMReg()->next(12),
13783 xmm20->as_VMReg()->next(13),
13784 xmm20->as_VMReg()->next(14),
13785 xmm20->as_VMReg()->next(15),
13786 xmm21->as_VMReg(),
13787 xmm21->as_VMReg()->next(1),
13788 xmm21->as_VMReg()->next(2),
13789 xmm21->as_VMReg()->next(3),
13790 xmm21->as_VMReg()->next(4),
13791 xmm21->as_VMReg()->next(5),
13792 xmm21->as_VMReg()->next(6),
13793 xmm21->as_VMReg()->next(7),
13794 xmm21->as_VMReg()->next(8),
13795 xmm21->as_VMReg()->next(9),
13796 xmm21->as_VMReg()->next(10),
13797 xmm21->as_VMReg()->next(11),
13798 xmm21->as_VMReg()->next(12),
13799 xmm21->as_VMReg()->next(13),
13800 xmm21->as_VMReg()->next(14),
13801 xmm21->as_VMReg()->next(15),
13802 xmm22->as_VMReg(),
13803 xmm22->as_VMReg()->next(1),
13804 xmm22->as_VMReg()->next(2),
13805 xmm22->as_VMReg()->next(3),
13806 xmm22->as_VMReg()->next(4),
13807 xmm22->as_VMReg()->next(5),
13808 xmm22->as_VMReg()->next(6),
13809 xmm22->as_VMReg()->next(7),
13810 xmm22->as_VMReg()->next(8),
13811 xmm22->as_VMReg()->next(9),
13812 xmm22->as_VMReg()->next(10),
13813 xmm22->as_VMReg()->next(11),
13814 xmm22->as_VMReg()->next(12),
13815 xmm22->as_VMReg()->next(13),
13816 xmm22->as_VMReg()->next(14),
13817 xmm22->as_VMReg()->next(15),
13818 xmm23->as_VMReg(),
13819 xmm23->as_VMReg()->next(1),
13820 xmm23->as_VMReg()->next(2),
13821 xmm23->as_VMReg()->next(3),
13822 xmm23->as_VMReg()->next(4),
13823 xmm23->as_VMReg()->next(5),
13824 xmm23->as_VMReg()->next(6),
13825 xmm23->as_VMReg()->next(7),
13826 xmm23->as_VMReg()->next(8),
13827 xmm23->as_VMReg()->next(9),
13828 xmm23->as_VMReg()->next(10),
13829 xmm23->as_VMReg()->next(11),
13830 xmm23->as_VMReg()->next(12),
13831 xmm23->as_VMReg()->next(13),
13832 xmm23->as_VMReg()->next(14),
13833 xmm23->as_VMReg()->next(15),
13834 xmm24->as_VMReg(),
13835 xmm24->as_VMReg()->next(1),
13836 xmm24->as_VMReg()->next(2),
13837 xmm24->as_VMReg()->next(3),
13838 xmm24->as_VMReg()->next(4),
13839 xmm24->as_VMReg()->next(5),
13840 xmm24->as_VMReg()->next(6),
13841 xmm24->as_VMReg()->next(7),
13842 xmm24->as_VMReg()->next(8),
13843 xmm24->as_VMReg()->next(9),
13844 xmm24->as_VMReg()->next(10),
13845 xmm24->as_VMReg()->next(11),
13846 xmm24->as_VMReg()->next(12),
13847 xmm24->as_VMReg()->next(13),
13848 xmm24->as_VMReg()->next(14),
13849 xmm24->as_VMReg()->next(15),
13850 xmm25->as_VMReg(),
13851 xmm25->as_VMReg()->next(1),
13852 xmm25->as_VMReg()->next(2),
13853 xmm25->as_VMReg()->next(3),
13854 xmm25->as_VMReg()->next(4),
13855 xmm25->as_VMReg()->next(5),
13856 xmm25->as_VMReg()->next(6),
13857 xmm25->as_VMReg()->next(7),
13858 xmm25->as_VMReg()->next(8),
13859 xmm25->as_VMReg()->next(9),
13860 xmm25->as_VMReg()->next(10),
13861 xmm25->as_VMReg()->next(11),
13862 xmm25->as_VMReg()->next(12),
13863 xmm25->as_VMReg()->next(13),
13864 xmm25->as_VMReg()->next(14),
13865 xmm25->as_VMReg()->next(15),
13866 xmm26->as_VMReg(),
13867 xmm26->as_VMReg()->next(1),
13868 xmm26->as_VMReg()->next(2),
13869 xmm26->as_VMReg()->next(3),
13870 xmm26->as_VMReg()->next(4),
13871 xmm26->as_VMReg()->next(5),
13872 xmm26->as_VMReg()->next(6),
13873 xmm26->as_VMReg()->next(7),
13874 xmm26->as_VMReg()->next(8),
13875 xmm26->as_VMReg()->next(9),
13876 xmm26->as_VMReg()->next(10),
13877 xmm26->as_VMReg()->next(11),
13878 xmm26->as_VMReg()->next(12),
13879 xmm26->as_VMReg()->next(13),
13880 xmm26->as_VMReg()->next(14),
13881 xmm26->as_VMReg()->next(15),
13882 xmm27->as_VMReg(),
13883 xmm27->as_VMReg()->next(1),
13884 xmm27->as_VMReg()->next(2),
13885 xmm27->as_VMReg()->next(3),
13886 xmm27->as_VMReg()->next(4),
13887 xmm27->as_VMReg()->next(5),
13888 xmm27->as_VMReg()->next(6),
13889 xmm27->as_VMReg()->next(7),
13890 xmm27->as_VMReg()->next(8),
13891 xmm27->as_VMReg()->next(9),
13892 xmm27->as_VMReg()->next(10),
13893 xmm27->as_VMReg()->next(11),
13894 xmm27->as_VMReg()->next(12),
13895 xmm27->as_VMReg()->next(13),
13896 xmm27->as_VMReg()->next(14),
13897 xmm27->as_VMReg()->next(15),
13898 xmm28->as_VMReg(),
13899 xmm28->as_VMReg()->next(1),
13900 xmm28->as_VMReg()->next(2),
13901 xmm28->as_VMReg()->next(3),
13902 xmm28->as_VMReg()->next(4),
13903 xmm28->as_VMReg()->next(5),
13904 xmm28->as_VMReg()->next(6),
13905 xmm28->as_VMReg()->next(7),
13906 xmm28->as_VMReg()->next(8),
13907 xmm28->as_VMReg()->next(9),
13908 xmm28->as_VMReg()->next(10),
13909 xmm28->as_VMReg()->next(11),
13910 xmm28->as_VMReg()->next(12),
13911 xmm28->as_VMReg()->next(13),
13912 xmm28->as_VMReg()->next(14),
13913 xmm28->as_VMReg()->next(15),
13914 xmm29->as_VMReg(),
13915 xmm29->as_VMReg()->next(1),
13916 xmm29->as_VMReg()->next(2),
13917 xmm29->as_VMReg()->next(3),
13918 xmm29->as_VMReg()->next(4),
13919 xmm29->as_VMReg()->next(5),
13920 xmm29->as_VMReg()->next(6),
13921 xmm29->as_VMReg()->next(7),
13922 xmm29->as_VMReg()->next(8),
13923 xmm29->as_VMReg()->next(9),
13924 xmm29->as_VMReg()->next(10),
13925 xmm29->as_VMReg()->next(11),
13926 xmm29->as_VMReg()->next(12),
13927 xmm29->as_VMReg()->next(13),
13928 xmm29->as_VMReg()->next(14),
13929 xmm29->as_VMReg()->next(15),
13930 xmm30->as_VMReg(),
13931 xmm30->as_VMReg()->next(1),
13932 xmm30->as_VMReg()->next(2),
13933 xmm30->as_VMReg()->next(3),
13934 xmm30->as_VMReg()->next(4),
13935 xmm30->as_VMReg()->next(5),
13936 xmm30->as_VMReg()->next(6),
13937 xmm30->as_VMReg()->next(7),
13938 xmm30->as_VMReg()->next(8),
13939 xmm30->as_VMReg()->next(9),
13940 xmm30->as_VMReg()->next(10),
13941 xmm30->as_VMReg()->next(11),
13942 xmm30->as_VMReg()->next(12),
13943 xmm30->as_VMReg()->next(13),
13944 xmm30->as_VMReg()->next(14),
13945 xmm30->as_VMReg()->next(15),
13946 xmm31->as_VMReg(),
13947 xmm31->as_VMReg()->next(1),
13948 xmm31->as_VMReg()->next(2),
13949 xmm31->as_VMReg()->next(3),
13950 xmm31->as_VMReg()->next(4),
13951 xmm31->as_VMReg()->next(5),
13952 xmm31->as_VMReg()->next(6),
13953 xmm31->as_VMReg()->next(7),
13954 xmm31->as_VMReg()->next(8),
13955 xmm31->as_VMReg()->next(9),
13956 xmm31->as_VMReg()->next(10),
13957 xmm31->as_VMReg()->next(11),
13958 xmm31->as_VMReg()->next(12),
13959 xmm31->as_VMReg()->next(13),
13960 xmm31->as_VMReg()->next(14),
13961 xmm31->as_VMReg()->next(15),
13962 VMRegImpl::Bad() // no trailing comma
13963 };
13964
13965 OptoReg::Name OptoReg::vm2opto[ConcreteRegisterImpl::number_of_registers];
13966
13967// An array of the machine register encode values
13968const unsigned char Matcher::_regEncode[REG_COUNT] = {
13969 (unsigned char)'\xA', // R10
13970 (unsigned char)'\xA', // R10_H
13971 (unsigned char)'\xB', // R11
13972 (unsigned char)'\xB', // R11_H
13973 (unsigned char)'\x8', // R8
13974 (unsigned char)'\x8', // R8_H
13975 (unsigned char)'\x9', // R9
13976 (unsigned char)'\x9', // R9_H
13977 (unsigned char)'\xC', // R12
13978 (unsigned char)'\xC', // R12_H
13979 (unsigned char)'\x1', // RCX
13980 (unsigned char)'\x1', // RCX_H
13981 (unsigned char)'\x3', // RBX
13982 (unsigned char)'\x3', // RBX_H
13983 (unsigned char)'\x7', // RDI
13984 (unsigned char)'\x7', // RDI_H
13985 (unsigned char)'\x2', // RDX
13986 (unsigned char)'\x2', // RDX_H
13987 (unsigned char)'\x6', // RSI
13988 (unsigned char)'\x6', // RSI_H
13989 (unsigned char)'\x0', // RAX
13990 (unsigned char)'\x0', // RAX_H
13991 (unsigned char)'\x5', // RBP
13992 (unsigned char)'\x5', // RBP_H
13993 (unsigned char)'\xD', // R13
13994 (unsigned char)'\xD', // R13_H
13995 (unsigned char)'\xE', // R14
13996 (unsigned char)'\xE', // R14_H
13997 (unsigned char)'\xF', // R15
13998 (unsigned char)'\xF', // R15_H
13999 (unsigned char)'\x4', // RSP
14000 (unsigned char)'\x4', // RSP_H
14001 (unsigned char)'\x0', // XMM0
14002 (unsigned char)'\x0', // XMM0b
14003 (unsigned char)'\x0', // XMM0c
14004 (unsigned char)'\x0', // XMM0d
14005 (unsigned char)'\x0', // XMM0e
14006 (unsigned char)'\x0', // XMM0f
14007 (unsigned char)'\x0', // XMM0g
14008 (unsigned char)'\x0', // XMM0h
14009 (unsigned char)'\x0', // XMM0i
14010 (unsigned char)'\x0', // XMM0j
14011 (unsigned char)'\x0', // XMM0k
14012 (unsigned char)'\x0', // XMM0l
14013 (unsigned char)'\x0', // XMM0m
14014 (unsigned char)'\x0', // XMM0n
14015 (unsigned char)'\x0', // XMM0o
14016 (unsigned char)'\x0', // XMM0p
14017 (unsigned char)'\x1', // XMM1
14018 (unsigned char)'\x1', // XMM1b
14019 (unsigned char)'\x1', // XMM1c
14020 (unsigned char)'\x1', // XMM1d
14021 (unsigned char)'\x1', // XMM1e
14022 (unsigned char)'\x1', // XMM1f
14023 (unsigned char)'\x1', // XMM1g
14024 (unsigned char)'\x1', // XMM1h
14025 (unsigned char)'\x1', // XMM1i
14026 (unsigned char)'\x1', // XMM1j
14027 (unsigned char)'\x1', // XMM1k
14028 (unsigned char)'\x1', // XMM1l
14029 (unsigned char)'\x1', // XMM1m
14030 (unsigned char)'\x1', // XMM1n
14031 (unsigned char)'\x1', // XMM1o
14032 (unsigned char)'\x1', // XMM1p
14033 (unsigned char)'\x2', // XMM2
14034 (unsigned char)'\x2', // XMM2b
14035 (unsigned char)'\x2', // XMM2c
14036 (unsigned char)'\x2', // XMM2d
14037 (unsigned char)'\x2', // XMM2e
14038 (unsigned char)'\x2', // XMM2f
14039 (unsigned char)'\x2', // XMM2g
14040 (unsigned char)'\x2', // XMM2h
14041 (unsigned char)'\x2', // XMM2i
14042 (unsigned char)'\x2', // XMM2j
14043 (unsigned char)'\x2', // XMM2k
14044 (unsigned char)'\x2', // XMM2l
14045 (unsigned char)'\x2', // XMM2m
14046 (unsigned char)'\x2', // XMM2n
14047 (unsigned char)'\x2', // XMM2o
14048 (unsigned char)'\x2', // XMM2p
14049 (unsigned char)'\x3', // XMM3
14050 (unsigned char)'\x3', // XMM3b
14051 (unsigned char)'\x3', // XMM3c
14052 (unsigned char)'\x3', // XMM3d
14053 (unsigned char)'\x3', // XMM3e
14054 (unsigned char)'\x3', // XMM3f
14055 (unsigned char)'\x3', // XMM3g
14056 (unsigned char)'\x3', // XMM3h
14057 (unsigned char)'\x3', // XMM3i
14058 (unsigned char)'\x3', // XMM3j
14059 (unsigned char)'\x3', // XMM3k
14060 (unsigned char)'\x3', // XMM3l
14061 (unsigned char)'\x3', // XMM3m
14062 (unsigned char)'\x3', // XMM3n
14063 (unsigned char)'\x3', // XMM3o
14064 (unsigned char)'\x3', // XMM3p
14065 (unsigned char)'\x4', // XMM4
14066 (unsigned char)'\x4', // XMM4b
14067 (unsigned char)'\x4', // XMM4c
14068 (unsigned char)'\x4', // XMM4d
14069 (unsigned char)'\x4', // XMM4e
14070 (unsigned char)'\x4', // XMM4f
14071 (unsigned char)'\x4', // XMM4g
14072 (unsigned char)'\x4', // XMM4h
14073 (unsigned char)'\x4', // XMM4i
14074 (unsigned char)'\x4', // XMM4j
14075 (unsigned char)'\x4', // XMM4k
14076 (unsigned char)'\x4', // XMM4l
14077 (unsigned char)'\x4', // XMM4m
14078 (unsigned char)'\x4', // XMM4n
14079 (unsigned char)'\x4', // XMM4o
14080 (unsigned char)'\x4', // XMM4p
14081 (unsigned char)'\x5', // XMM5
14082 (unsigned char)'\x5', // XMM5b
14083 (unsigned char)'\x5', // XMM5c
14084 (unsigned char)'\x5', // XMM5d
14085 (unsigned char)'\x5', // XMM5e
14086 (unsigned char)'\x5', // XMM5f
14087 (unsigned char)'\x5', // XMM5g
14088 (unsigned char)'\x5', // XMM5h
14089 (unsigned char)'\x5', // XMM5i
14090 (unsigned char)'\x5', // XMM5j
14091 (unsigned char)'\x5', // XMM5k
14092 (unsigned char)'\x5', // XMM5l
14093 (unsigned char)'\x5', // XMM5m
14094 (unsigned char)'\x5', // XMM5n
14095 (unsigned char)'\x5', // XMM5o
14096 (unsigned char)'\x5', // XMM5p
14097 (unsigned char)'\x6', // XMM6
14098 (unsigned char)'\x6', // XMM6b
14099 (unsigned char)'\x6', // XMM6c
14100 (unsigned char)'\x6', // XMM6d
14101 (unsigned char)'\x6', // XMM6e
14102 (unsigned char)'\x6', // XMM6f
14103 (unsigned char)'\x6', // XMM6g
14104 (unsigned char)'\x6', // XMM6h
14105 (unsigned char)'\x6', // XMM6i
14106 (unsigned char)'\x6', // XMM6j
14107 (unsigned char)'\x6', // XMM6k
14108 (unsigned char)'\x6', // XMM6l
14109 (unsigned char)'\x6', // XMM6m
14110 (unsigned char)'\x6', // XMM6n
14111 (unsigned char)'\x6', // XMM6o
14112 (unsigned char)'\x6', // XMM6p
14113 (unsigned char)'\x7', // XMM7
14114 (unsigned char)'\x7', // XMM7b
14115 (unsigned char)'\x7', // XMM7c
14116 (unsigned char)'\x7', // XMM7d
14117 (unsigned char)'\x7', // XMM7e
14118 (unsigned char)'\x7', // XMM7f
14119 (unsigned char)'\x7', // XMM7g
14120 (unsigned char)'\x7', // XMM7h
14121 (unsigned char)'\x7', // XMM7i
14122 (unsigned char)'\x7', // XMM7j
14123 (unsigned char)'\x7', // XMM7k
14124 (unsigned char)'\x7', // XMM7l
14125 (unsigned char)'\x7', // XMM7m
14126 (unsigned char)'\x7', // XMM7n
14127 (unsigned char)'\x7', // XMM7o
14128 (unsigned char)'\x7', // XMM7p
14129 (unsigned char)'\x8', // XMM8
14130 (unsigned char)'\x8', // XMM8b
14131 (unsigned char)'\x8', // XMM8c
14132 (unsigned char)'\x8', // XMM8d
14133 (unsigned char)'\x8', // XMM8e
14134 (unsigned char)'\x8', // XMM8f
14135 (unsigned char)'\x8', // XMM8g
14136 (unsigned char)'\x8', // XMM8h
14137 (unsigned char)'\x8', // XMM8i
14138 (unsigned char)'\x8', // XMM8j
14139 (unsigned char)'\x8', // XMM8k
14140 (unsigned char)'\x8', // XMM8l
14141 (unsigned char)'\x8', // XMM8m
14142 (unsigned char)'\x8', // XMM8n
14143 (unsigned char)'\x8', // XMM8o
14144 (unsigned char)'\x8', // XMM8p
14145 (unsigned char)'\x9', // XMM9
14146 (unsigned char)'\x9', // XMM9b
14147 (unsigned char)'\x9', // XMM9c
14148 (unsigned char)'\x9', // XMM9d
14149 (unsigned char)'\x9', // XMM9e
14150 (unsigned char)'\x9', // XMM9f
14151 (unsigned char)'\x9', // XMM9g
14152 (unsigned char)'\x9', // XMM9h
14153 (unsigned char)'\x9', // XMM9i
14154 (unsigned char)'\x9', // XMM9j
14155 (unsigned char)'\x9', // XMM9k
14156 (unsigned char)'\x9', // XMM9l
14157 (unsigned char)'\x9', // XMM9m
14158 (unsigned char)'\x9', // XMM9n
14159 (unsigned char)'\x9', // XMM9o
14160 (unsigned char)'\x9', // XMM9p
14161 (unsigned char)'\xA', // XMM10
14162 (unsigned char)'\xA', // XMM10b
14163 (unsigned char)'\xA', // XMM10c
14164 (unsigned char)'\xA', // XMM10d
14165 (unsigned char)'\xA', // XMM10e
14166 (unsigned char)'\xA', // XMM10f
14167 (unsigned char)'\xA', // XMM10g
14168 (unsigned char)'\xA', // XMM10h
14169 (unsigned char)'\xA', // XMM10i
14170 (unsigned char)'\xA', // XMM10j
14171 (unsigned char)'\xA', // XMM10k
14172 (unsigned char)'\xA', // XMM10l
14173 (unsigned char)'\xA', // XMM10m
14174 (unsigned char)'\xA', // XMM10n
14175 (unsigned char)'\xA', // XMM10o
14176 (unsigned char)'\xA', // XMM10p
14177 (unsigned char)'\xB', // XMM11
14178 (unsigned char)'\xB', // XMM11b
14179 (unsigned char)'\xB', // XMM11c
14180 (unsigned char)'\xB', // XMM11d
14181 (unsigned char)'\xB', // XMM11e
14182 (unsigned char)'\xB', // XMM11f
14183 (unsigned char)'\xB', // XMM11g
14184 (unsigned char)'\xB', // XMM11h
14185 (unsigned char)'\xB', // XMM11i
14186 (unsigned char)'\xB', // XMM11j
14187 (unsigned char)'\xB', // XMM11k
14188 (unsigned char)'\xB', // XMM11l
14189 (unsigned char)'\xB', // XMM11m
14190 (unsigned char)'\xB', // XMM11n
14191 (unsigned char)'\xB', // XMM11o
14192 (unsigned char)'\xB', // XMM11p
14193 (unsigned char)'\xC', // XMM12
14194 (unsigned char)'\xC', // XMM12b
14195 (unsigned char)'\xC', // XMM12c
14196 (unsigned char)'\xC', // XMM12d
14197 (unsigned char)'\xC', // XMM12e
14198 (unsigned char)'\xC', // XMM12f
14199 (unsigned char)'\xC', // XMM12g
14200 (unsigned char)'\xC', // XMM12h
14201 (unsigned char)'\xC', // XMM12i
14202 (unsigned char)'\xC', // XMM12j
14203 (unsigned char)'\xC', // XMM12k
14204 (unsigned char)'\xC', // XMM12l
14205 (unsigned char)'\xC', // XMM12m
14206 (unsigned char)'\xC', // XMM12n
14207 (unsigned char)'\xC', // XMM12o
14208 (unsigned char)'\xC', // XMM12p
14209 (unsigned char)'\xD', // XMM13
14210 (unsigned char)'\xD', // XMM13b
14211 (unsigned char)'\xD', // XMM13c
14212 (unsigned char)'\xD', // XMM13d
14213 (unsigned char)'\xD', // XMM13e
14214 (unsigned char)'\xD', // XMM13f
14215 (unsigned char)'\xD', // XMM13g
14216 (unsigned char)'\xD', // XMM13h
14217 (unsigned char)'\xD', // XMM13i
14218 (unsigned char)'\xD', // XMM13j
14219 (unsigned char)'\xD', // XMM13k
14220 (unsigned char)'\xD', // XMM13l
14221 (unsigned char)'\xD', // XMM13m
14222 (unsigned char)'\xD', // XMM13n
14223 (unsigned char)'\xD', // XMM13o
14224 (unsigned char)'\xD', // XMM13p
14225 (unsigned char)'\xE', // XMM14
14226 (unsigned char)'\xE', // XMM14b
14227 (unsigned char)'\xE', // XMM14c
14228 (unsigned char)'\xE', // XMM14d
14229 (unsigned char)'\xE', // XMM14e
14230 (unsigned char)'\xE', // XMM14f
14231 (unsigned char)'\xE', // XMM14g
14232 (unsigned char)'\xE', // XMM14h
14233 (unsigned char)'\xE', // XMM14i
14234 (unsigned char)'\xE', // XMM14j
14235 (unsigned char)'\xE', // XMM14k
14236 (unsigned char)'\xE', // XMM14l
14237 (unsigned char)'\xE', // XMM14m
14238 (unsigned char)'\xE', // XMM14n
14239 (unsigned char)'\xE', // XMM14o
14240 (unsigned char)'\xE', // XMM14p
14241 (unsigned char)'\xF', // XMM15
14242 (unsigned char)'\xF', // XMM15b
14243 (unsigned char)'\xF', // XMM15c
14244 (unsigned char)'\xF', // XMM15d
14245 (unsigned char)'\xF', // XMM15e
14246 (unsigned char)'\xF', // XMM15f
14247 (unsigned char)'\xF', // XMM15g
14248 (unsigned char)'\xF', // XMM15h
14249 (unsigned char)'\xF', // XMM15i
14250 (unsigned char)'\xF', // XMM15j
14251 (unsigned char)'\xF', // XMM15k
14252 (unsigned char)'\xF', // XMM15l
14253 (unsigned char)'\xF', // XMM15m
14254 (unsigned char)'\xF', // XMM15n
14255 (unsigned char)'\xF', // XMM15o
14256 (unsigned char)'\xF', // XMM15p
14257 (unsigned char)'\x10', // XMM16
14258 (unsigned char)'\x10', // XMM16b
14259 (unsigned char)'\x10', // XMM16c
14260 (unsigned char)'\x10', // XMM16d
14261 (unsigned char)'\x10', // XMM16e
14262 (unsigned char)'\x10', // XMM16f
14263 (unsigned char)'\x10', // XMM16g
14264 (unsigned char)'\x10', // XMM16h
14265 (unsigned char)'\x10', // XMM16i
14266 (unsigned char)'\x10', // XMM16j
14267 (unsigned char)'\x10', // XMM16k
14268 (unsigned char)'\x10', // XMM16l
14269 (unsigned char)'\x10', // XMM16m
14270 (unsigned char)'\x10', // XMM16n
14271 (unsigned char)'\x10', // XMM16o
14272 (unsigned char)'\x10', // XMM16p
14273 (unsigned char)'\x11', // XMM17
14274 (unsigned char)'\x11', // XMM17b
14275 (unsigned char)'\x11', // XMM17c
14276 (unsigned char)'\x11', // XMM17d
14277 (unsigned char)'\x11', // XMM17e
14278 (unsigned char)'\x11', // XMM17f
14279 (unsigned char)'\x11', // XMM17g
14280 (unsigned char)'\x11', // XMM17h
14281 (unsigned char)'\x11', // XMM17i
14282 (unsigned char)'\x11', // XMM17j
14283 (unsigned char)'\x11', // XMM17k
14284 (unsigned char)'\x11', // XMM17l
14285 (unsigned char)'\x11', // XMM17m
14286 (unsigned char)'\x11', // XMM17n
14287 (unsigned char)'\x11', // XMM17o
14288 (unsigned char)'\x11', // XMM17p
14289 (unsigned char)'\x12', // XMM18
14290 (unsigned char)'\x12', // XMM18b
14291 (unsigned char)'\x12', // XMM18c
14292 (unsigned char)'\x12', // XMM18d
14293 (unsigned char)'\x12', // XMM18e
14294 (unsigned char)'\x12', // XMM18f
14295 (unsigned char)'\x12', // XMM18g
14296 (unsigned char)'\x12', // XMM18h
14297 (unsigned char)'\x12', // XMM18i
14298 (unsigned char)'\x12', // XMM18j
14299 (unsigned char)'\x12', // XMM18k
14300 (unsigned char)'\x12', // XMM18l
14301 (unsigned char)'\x12', // XMM18m
14302 (unsigned char)'\x12', // XMM18n
14303 (unsigned char)'\x12', // XMM18o
14304 (unsigned char)'\x12', // XMM18p
14305 (unsigned char)'\x13', // XMM19
14306 (unsigned char)'\x13', // XMM19b
14307 (unsigned char)'\x13', // XMM19c
14308 (unsigned char)'\x13', // XMM19d
14309 (unsigned char)'\x13', // XMM19e
14310 (unsigned char)'\x13', // XMM19f
14311 (unsigned char)'\x13', // XMM19g
14312 (unsigned char)'\x13', // XMM19h
14313 (unsigned char)'\x13', // XMM19i
14314 (unsigned char)'\x13', // XMM19j
14315 (unsigned char)'\x13', // XMM19k
14316 (unsigned char)'\x13', // XMM19l
14317 (unsigned char)'\x13', // XMM19m
14318 (unsigned char)'\x13', // XMM19n
14319 (unsigned char)'\x13', // XMM19o
14320 (unsigned char)'\x13', // XMM19p
14321 (unsigned char)'\x14', // XMM20
14322 (unsigned char)'\x14', // XMM20b
14323 (unsigned char)'\x14', // XMM20c
14324 (unsigned char)'\x14', // XMM20d
14325 (unsigned char)'\x14', // XMM20e
14326 (unsigned char)'\x14', // XMM20f
14327 (unsigned char)'\x14', // XMM20g
14328 (unsigned char)'\x14', // XMM20h
14329 (unsigned char)'\x14', // XMM20i
14330 (unsigned char)'\x14', // XMM20j
14331 (unsigned char)'\x14', // XMM20k
14332 (unsigned char)'\x14', // XMM20l
14333 (unsigned char)'\x14', // XMM20m
14334 (unsigned char)'\x14', // XMM20n
14335 (unsigned char)'\x14', // XMM20o
14336 (unsigned char)'\x14', // XMM20p
14337 (unsigned char)'\x15', // XMM21
14338 (unsigned char)'\x15', // XMM21b
14339 (unsigned char)'\x15', // XMM21c
14340 (unsigned char)'\x15', // XMM21d
14341 (unsigned char)'\x15', // XMM21e
14342 (unsigned char)'\x15', // XMM21f
14343 (unsigned char)'\x15', // XMM21g
14344 (unsigned char)'\x15', // XMM21h
14345 (unsigned char)'\x15', // XMM21i
14346 (unsigned char)'\x15', // XMM21j
14347 (unsigned char)'\x15', // XMM21k
14348 (unsigned char)'\x15', // XMM21l
14349 (unsigned char)'\x15', // XMM21m
14350 (unsigned char)'\x15', // XMM21n
14351 (unsigned char)'\x15', // XMM21o
14352 (unsigned char)'\x15', // XMM21p
14353 (unsigned char)'\x16', // XMM22
14354 (unsigned char)'\x16', // XMM22b
14355 (unsigned char)'\x16', // XMM22c
14356 (unsigned char)'\x16', // XMM22d
14357 (unsigned char)'\x16', // XMM22e
14358 (unsigned char)'\x16', // XMM22f
14359 (unsigned char)'\x16', // XMM22g
14360 (unsigned char)'\x16', // XMM22h
14361 (unsigned char)'\x16', // XMM22i
14362 (unsigned char)'\x16', // XMM22j
14363 (unsigned char)'\x16', // XMM22k
14364 (unsigned char)'\x16', // XMM22l
14365 (unsigned char)'\x16', // XMM22m
14366 (unsigned char)'\x16', // XMM22n
14367 (unsigned char)'\x16', // XMM22o
14368 (unsigned char)'\x16', // XMM22p
14369 (unsigned char)'\x17', // XMM23
14370 (unsigned char)'\x17', // XMM23b
14371 (unsigned char)'\x17', // XMM23c
14372 (unsigned char)'\x17', // XMM23d
14373 (unsigned char)'\x17', // XMM23e
14374 (unsigned char)'\x17', // XMM23f
14375 (unsigned char)'\x17', // XMM23g
14376 (unsigned char)'\x17', // XMM23h
14377 (unsigned char)'\x17', // XMM23i
14378 (unsigned char)'\x17', // XMM23j
14379 (unsigned char)'\x17', // XMM23k
14380 (unsigned char)'\x17', // XMM23l
14381 (unsigned char)'\x17', // XMM23m
14382 (unsigned char)'\x17', // XMM23n
14383 (unsigned char)'\x17', // XMM23o
14384 (unsigned char)'\x17', // XMM23p
14385 (unsigned char)'\x18', // XMM24
14386 (unsigned char)'\x18', // XMM24b
14387 (unsigned char)'\x18', // XMM24c
14388 (unsigned char)'\x18', // XMM24d
14389 (unsigned char)'\x18', // XMM24e
14390 (unsigned char)'\x18', // XMM24f
14391 (unsigned char)'\x18', // XMM24g
14392 (unsigned char)'\x18', // XMM24h
14393 (unsigned char)'\x18', // XMM24i
14394 (unsigned char)'\x18', // XMM24j
14395 (unsigned char)'\x18', // XMM24k
14396 (unsigned char)'\x18', // XMM24l
14397 (unsigned char)'\x18', // XMM24m
14398 (unsigned char)'\x18', // XMM24n
14399 (unsigned char)'\x18', // XMM24o
14400 (unsigned char)'\x18', // XMM24p
14401 (unsigned char)'\x19', // XMM25
14402 (unsigned char)'\x19', // XMM25b
14403 (unsigned char)'\x19', // XMM25c
14404 (unsigned char)'\x19', // XMM25d
14405 (unsigned char)'\x19', // XMM25e
14406 (unsigned char)'\x19', // XMM25f
14407 (unsigned char)'\x19', // XMM25g
14408 (unsigned char)'\x19', // XMM25h
14409 (unsigned char)'\x19', // XMM25i
14410 (unsigned char)'\x19', // XMM25j
14411 (unsigned char)'\x19', // XMM25k
14412 (unsigned char)'\x19', // XMM25l
14413 (unsigned char)'\x19', // XMM25m
14414 (unsigned char)'\x19', // XMM25n
14415 (unsigned char)'\x19', // XMM25o
14416 (unsigned char)'\x19', // XMM25p
14417 (unsigned char)'\x1A', // XMM26
14418 (unsigned char)'\x1A', // XMM26b
14419 (unsigned char)'\x1A', // XMM26c
14420 (unsigned char)'\x1A', // XMM26d
14421 (unsigned char)'\x1A', // XMM26e
14422 (unsigned char)'\x1A', // XMM26f
14423 (unsigned char)'\x1A', // XMM26g
14424 (unsigned char)'\x1A', // XMM26h
14425 (unsigned char)'\x1A', // XMM26i
14426 (unsigned char)'\x1A', // XMM26j
14427 (unsigned char)'\x1A', // XMM26k
14428 (unsigned char)'\x1A', // XMM26l
14429 (unsigned char)'\x1A', // XMM26m
14430 (unsigned char)'\x1A', // XMM26n
14431 (unsigned char)'\x1A', // XMM26o
14432 (unsigned char)'\x1A', // XMM26p
14433 (unsigned char)'\x1B', // XMM27
14434 (unsigned char)'\x1B', // XMM27b
14435 (unsigned char)'\x1B', // XMM27c
14436 (unsigned char)'\x1B', // XMM27d
14437 (unsigned char)'\x1B', // XMM27e
14438 (unsigned char)'\x1B', // XMM27f
14439 (unsigned char)'\x1B', // XMM27g
14440 (unsigned char)'\x1B', // XMM27h
14441 (unsigned char)'\x1B', // XMM27i
14442 (unsigned char)'\x1B', // XMM27j
14443 (unsigned char)'\x1B', // XMM27k
14444 (unsigned char)'\x1B', // XMM27l
14445 (unsigned char)'\x1B', // XMM27m
14446 (unsigned char)'\x1B', // XMM27n
14447 (unsigned char)'\x1B', // XMM27o
14448 (unsigned char)'\x1B', // XMM27p
14449 (unsigned char)'\x1C', // XMM28
14450 (unsigned char)'\x1C', // XMM28b
14451 (unsigned char)'\x1C', // XMM28c
14452 (unsigned char)'\x1C', // XMM28d
14453 (unsigned char)'\x1C', // XMM28e
14454 (unsigned char)'\x1C', // XMM28f
14455 (unsigned char)'\x1C', // XMM28g
14456 (unsigned char)'\x1C', // XMM28h
14457 (unsigned char)'\x1C', // XMM28i
14458 (unsigned char)'\x1C', // XMM28j
14459 (unsigned char)'\x1C', // XMM28k
14460 (unsigned char)'\x1C', // XMM28l
14461 (unsigned char)'\x1C', // XMM28m
14462 (unsigned char)'\x1C', // XMM28n
14463 (unsigned char)'\x1C', // XMM28o
14464 (unsigned char)'\x1C', // XMM28p
14465 (unsigned char)'\x1D', // XMM29
14466 (unsigned char)'\x1D', // XMM29b
14467 (unsigned char)'\x1D', // XMM29c
14468 (unsigned char)'\x1D', // XMM29d
14469 (unsigned char)'\x1D', // XMM29e
14470 (unsigned char)'\x1D', // XMM29f
14471 (unsigned char)'\x1D', // XMM29g
14472 (unsigned char)'\x1D', // XMM29h
14473 (unsigned char)'\x1D', // XMM29i
14474 (unsigned char)'\x1D', // XMM29j
14475 (unsigned char)'\x1D', // XMM29k
14476 (unsigned char)'\x1D', // XMM29l
14477 (unsigned char)'\x1D', // XMM29m
14478 (unsigned char)'\x1D', // XMM29n
14479 (unsigned char)'\x1D', // XMM29o
14480 (unsigned char)'\x1D', // XMM29p
14481 (unsigned char)'\x1E', // XMM30
14482 (unsigned char)'\x1E', // XMM30b
14483 (unsigned char)'\x1E', // XMM30c
14484 (unsigned char)'\x1E', // XMM30d
14485 (unsigned char)'\x1E', // XMM30e
14486 (unsigned char)'\x1E', // XMM30f
14487 (unsigned char)'\x1E', // XMM30g
14488 (unsigned char)'\x1E', // XMM30h
14489 (unsigned char)'\x1E', // XMM30i
14490 (unsigned char)'\x1E', // XMM30j
14491 (unsigned char)'\x1E', // XMM30k
14492 (unsigned char)'\x1E', // XMM30l
14493 (unsigned char)'\x1E', // XMM30m
14494 (unsigned char)'\x1E', // XMM30n
14495 (unsigned char)'\x1E', // XMM30o
14496 (unsigned char)'\x1E', // XMM30p
14497 (unsigned char)'\x1F', // XMM31
14498 (unsigned char)'\x1F', // XMM31b
14499 (unsigned char)'\x1F', // XMM31c
14500 (unsigned char)'\x1F', // XMM31d
14501 (unsigned char)'\x1F', // XMM31e
14502 (unsigned char)'\x1F', // XMM31f
14503 (unsigned char)'\x1F', // XMM31g
14504 (unsigned char)'\x1F', // XMM31h
14505 (unsigned char)'\x1F', // XMM31i
14506 (unsigned char)'\x1F', // XMM31j
14507 (unsigned char)'\x1F', // XMM31k
14508 (unsigned char)'\x1F', // XMM31l
14509 (unsigned char)'\x1F', // XMM31m
14510 (unsigned char)'\x1F', // XMM31n
14511 (unsigned char)'\x1F', // XMM31o
14512 (unsigned char)'\x1F', // XMM31p
14513 (unsigned char)'\x10' // no trailing comma // RFLAGS
14514};
14515
14516
14517//------------------Define classes derived from MachOper---------------------
14518MachOper *labelOper::clone() const {
14519 return new labelOper(_label, _block_num);
14520}
14521uint labelOper::opcode() const { return LABEL; }
14522
14523const RegMask *sRegIOper::in_RegMask(int index) const {
14524 assert(0 <= index && index < 1, "index out of range");
14525 return &(Compile::current()->FIRST_STACK_mask());
14526}
14527
14528const RegMask *sRegPOper::in_RegMask(int index) const {
14529 assert(0 <= index && index < 1, "index out of range");
14530 return &(Compile::current()->FIRST_STACK_mask());
14531}
14532
14533const RegMask *sRegFOper::in_RegMask(int index) const {
14534 assert(0 <= index && index < 1, "index out of range");
14535 return &(Compile::current()->FIRST_STACK_mask());
14536}
14537
14538const RegMask *sRegDOper::in_RegMask(int index) const {
14539 assert(0 <= index && index < 1, "index out of range");
14540 return &(Compile::current()->FIRST_STACK_mask());
14541}
14542
14543const RegMask *sRegLOper::in_RegMask(int index) const {
14544 assert(0 <= index && index < 1, "index out of range");
14545 return &(Compile::current()->FIRST_STACK_mask());
14546}
14547
14548MachOper *methodOper::clone() const {
14549 return new methodOper(_method);
14550}
14551uint methodOper::opcode() const { return METHOD; }
14552
14553const RegMask *rRegIOper::in_RegMask(int index) const {
14554 assert(0 <= index && index < 1, "index out of range");
14555 return &INT_REG_mask();
14556}
14557
14558const RegMask *rax_RegIOper::in_RegMask(int index) const {
14559 assert(0 <= index && index < 1, "index out of range");
14560 return &INT_RAX_REG_mask();
14561}
14562
14563const RegMask *rbx_RegIOper::in_RegMask(int index) const {
14564 assert(0 <= index && index < 1, "index out of range");
14565 return &INT_RBX_REG_mask();
14566}
14567
14568const RegMask *rcx_RegIOper::in_RegMask(int index) const {
14569 assert(0 <= index && index < 1, "index out of range");
14570 return &INT_RCX_REG_mask();
14571}
14572
14573const RegMask *rdx_RegIOper::in_RegMask(int index) const {
14574 assert(0 <= index && index < 1, "index out of range");
14575 return &INT_RDX_REG_mask();
14576}
14577
14578const RegMask *rdi_RegIOper::in_RegMask(int index) const {
14579 assert(0 <= index && index < 1, "index out of range");
14580 return &INT_RDI_REG_mask();
14581}
14582
14583const RegMask *no_rcx_RegIOper::in_RegMask(int index) const {
14584 assert(0 <= index && index < 1, "index out of range");
14585 return &INT_NO_RCX_REG_mask();
14586}
14587
14588const RegMask *no_rax_rdx_RegIOper::in_RegMask(int index) const {
14589 assert(0 <= index && index < 1, "index out of range");
14590 return &INT_NO_RAX_RDX_REG_mask();
14591}
14592
14593const RegMask *any_RegPOper::in_RegMask(int index) const {
14594 assert(0 <= index && index < 1, "index out of range");
14595 return &ANY_REG_mask();
14596}
14597
14598const RegMask *rRegPOper::in_RegMask(int index) const {
14599 assert(0 <= index && index < 1, "index out of range");
14600 return &PTR_REG_mask();
14601}
14602
14603const RegMask *rRegNOper::in_RegMask(int index) const {
14604 assert(0 <= index && index < 1, "index out of range");
14605 return &INT_REG_mask();
14606}
14607
14608const RegMask *no_rax_RegPOper::in_RegMask(int index) const {
14609 assert(0 <= index && index < 1, "index out of range");
14610 return &PTR_NO_RAX_REG_mask();
14611}
14612
14613const RegMask *no_rbp_RegPOper::in_RegMask(int index) const {
14614 assert(0 <= index && index < 1, "index out of range");
14615 return &PTR_REG_NO_RBP_mask();
14616}
14617
14618const RegMask *no_rax_rbx_RegPOper::in_RegMask(int index) const {
14619 assert(0 <= index && index < 1, "index out of range");
14620 return &PTR_NO_RAX_RBX_REG_mask();
14621}
14622
14623const RegMask *rax_RegPOper::in_RegMask(int index) const {
14624 assert(0 <= index && index < 1, "index out of range");
14625 return &PTR_RAX_REG_mask();
14626}
14627
14628const RegMask *rax_RegNOper::in_RegMask(int index) const {
14629 assert(0 <= index && index < 1, "index out of range");
14630 return &INT_RAX_REG_mask();
14631}
14632
14633const RegMask *rbx_RegPOper::in_RegMask(int index) const {
14634 assert(0 <= index && index < 1, "index out of range");
14635 return &PTR_RBX_REG_mask();
14636}
14637
14638const RegMask *rsi_RegPOper::in_RegMask(int index) const {
14639 assert(0 <= index && index < 1, "index out of range");
14640 return &PTR_RSI_REG_mask();
14641}
14642
14643const RegMask *rdi_RegPOper::in_RegMask(int index) const {
14644 assert(0 <= index && index < 1, "index out of range");
14645 return &PTR_RDI_REG_mask();
14646}
14647
14648const RegMask *r15_RegPOper::in_RegMask(int index) const {
14649 assert(0 <= index && index < 1, "index out of range");
14650 return &PTR_R15_REG_mask();
14651}
14652
14653const RegMask *rRegLOper::in_RegMask(int index) const {
14654 assert(0 <= index && index < 1, "index out of range");
14655 return &LONG_REG_mask();
14656}
14657
14658const RegMask *no_rax_rdx_RegLOper::in_RegMask(int index) const {
14659 assert(0 <= index && index < 1, "index out of range");
14660 return &LONG_NO_RAX_RDX_REG_mask();
14661}
14662
14663const RegMask *no_rax_RegLOper::in_RegMask(int index) const {
14664 assert(0 <= index && index < 1, "index out of range");
14665 return &LONG_NO_RAX_RDX_REG_mask();
14666}
14667
14668const RegMask *no_rcx_RegLOper::in_RegMask(int index) const {
14669 assert(0 <= index && index < 1, "index out of range");
14670 return &LONG_NO_RCX_REG_mask();
14671}
14672
14673const RegMask *rax_RegLOper::in_RegMask(int index) const {
14674 assert(0 <= index && index < 1, "index out of range");
14675 return &LONG_RAX_REG_mask();
14676}
14677
14678const RegMask *rcx_RegLOper::in_RegMask(int index) const {
14679 assert(0 <= index && index < 1, "index out of range");
14680 return &LONG_RCX_REG_mask();
14681}
14682
14683const RegMask *rdx_RegLOper::in_RegMask(int index) const {
14684 assert(0 <= index && index < 1, "index out of range");
14685 return &LONG_RDX_REG_mask();
14686}
14687
14688const RegMask *rFlagsRegOper::in_RegMask(int index) const {
14689 assert(0 <= index && index < 1, "index out of range");
14690 return &INT_FLAGS_mask();
14691}
14692
14693const RegMask *rFlagsRegUOper::in_RegMask(int index) const {
14694 assert(0 <= index && index < 1, "index out of range");
14695 return &INT_FLAGS_mask();
14696}
14697
14698const RegMask *rFlagsRegUCFOper::in_RegMask(int index) const {
14699 assert(0 <= index && index < 1, "index out of range");
14700 return &INT_FLAGS_mask();
14701}
14702
14703const RegMask *regFOper::in_RegMask(int index) const {
14704 assert(0 <= index && index < 1, "index out of range");
14705 return &FLOAT_REG_mask();
14706}
14707
14708const RegMask *legRegFOper::in_RegMask(int index) const {
14709 assert(0 <= index && index < 1, "index out of range");
14710 return &FLOAT_REG_LEGACY_mask();
14711}
14712
14713const RegMask *vlRegFOper::in_RegMask(int index) const {
14714 assert(0 <= index && index < 1, "index out of range");
14715 return &FLOAT_REG_VL_mask();
14716}
14717
14718const RegMask *regDOper::in_RegMask(int index) const {
14719 assert(0 <= index && index < 1, "index out of range");
14720 return &DOUBLE_REG_mask();
14721}
14722
14723const RegMask *legRegDOper::in_RegMask(int index) const {
14724 assert(0 <= index && index < 1, "index out of range");
14725 return &DOUBLE_REG_LEGACY_mask();
14726}
14727
14728const RegMask *vlRegDOper::in_RegMask(int index) const {
14729 assert(0 <= index && index < 1, "index out of range");
14730 return &DOUBLE_REG_VL_mask();
14731}
14732
14733const RegMask *vecSOper::in_RegMask(int index) const {
14734 assert(0 <= index && index < 1, "index out of range");
14735 return &VECTORS_REG_VLBWDQ_mask();
14736}
14737
14738const RegMask *legVecSOper::in_RegMask(int index) const {
14739 assert(0 <= index && index < 1, "index out of range");
14740 return &VECTORS_REG_LEGACY_mask();
14741}
14742
14743const RegMask *vecDOper::in_RegMask(int index) const {
14744 assert(0 <= index && index < 1, "index out of range");
14745 return &VECTORD_REG_VLBWDQ_mask();
14746}
14747
14748const RegMask *legVecDOper::in_RegMask(int index) const {
14749 assert(0 <= index && index < 1, "index out of range");
14750 return &VECTORD_REG_LEGACY_mask();
14751}
14752
14753const RegMask *vecXOper::in_RegMask(int index) const {
14754 assert(0 <= index && index < 1, "index out of range");
14755 return &VECTORX_REG_VLBWDQ_mask();
14756}
14757
14758const RegMask *legVecXOper::in_RegMask(int index) const {
14759 assert(0 <= index && index < 1, "index out of range");
14760 return &VECTORX_REG_LEGACY_mask();
14761}
14762
14763const RegMask *vecYOper::in_RegMask(int index) const {
14764 assert(0 <= index && index < 1, "index out of range");
14765 return &VECTORY_REG_VLBWDQ_mask();
14766}
14767
14768const RegMask *legVecYOper::in_RegMask(int index) const {
14769 assert(0 <= index && index < 1, "index out of range");
14770 return &VECTORY_REG_LEGACY_mask();
14771}
14772
14773const RegMask *indirectOper::in_RegMask(int index) const {
14774 assert(0 <= index && index < 1, "index out of range");
14775 return &PTR_REG_mask();
14776}
14777
14778const RegMask *indOffset8Oper::in_RegMask(int index) const {
14779 assert(0 <= index && index < 1, "index out of range");
14780 return &ANY_REG_mask();
14781}
14782
14783const RegMask *indOffset32Oper::in_RegMask(int index) const {
14784 assert(0 <= index && index < 1, "index out of range");
14785 return &ANY_REG_mask();
14786}
14787
14788const RegMask *indIndexOffsetOper::in_RegMask(int index) const {
14789 assert(0 <= index && index < 2, "index out of range");
14790 switch (index) {
14791 case 0: return &ANY_REG_mask();
14792 case 1: return &LONG_REG_mask();
14793 }
14794 ShouldNotReachHere();
14795 return NULL;
14796}
14797
14798const RegMask *indIndexOper::in_RegMask(int index) const {
14799 assert(0 <= index && index < 2, "index out of range");
14800 switch (index) {
14801 case 0: return &ANY_REG_mask();
14802 case 1: return &LONG_REG_mask();
14803 }
14804 ShouldNotReachHere();
14805 return NULL;
14806}
14807
14808const RegMask *indIndexScaleOper::in_RegMask(int index) const {
14809 assert(0 <= index && index < 2, "index out of range");
14810 switch (index) {
14811 case 0: return &ANY_REG_mask();
14812 case 1: return &LONG_REG_mask();
14813 }
14814 ShouldNotReachHere();
14815 return NULL;
14816}
14817
14818const RegMask *indPosIndexScaleOper::in_RegMask(int index) const {
14819 assert(0 <= index && index < 2, "index out of range");
14820 switch (index) {
14821 case 0: return &ANY_REG_mask();
14822 case 1: return &INT_REG_mask();
14823 }
14824 ShouldNotReachHere();
14825 return NULL;
14826}
14827
14828const RegMask *indIndexScaleOffsetOper::in_RegMask(int index) const {
14829 assert(0 <= index && index < 2, "index out of range");
14830 switch (index) {
14831 case 0: return &ANY_REG_mask();
14832 case 1: return &LONG_REG_mask();
14833 }
14834 ShouldNotReachHere();
14835 return NULL;
14836}
14837
14838const RegMask *indPosIndexOffsetOper::in_RegMask(int index) const {
14839 assert(0 <= index && index < 2, "index out of range");
14840 switch (index) {
14841 case 0: return &ANY_REG_mask();
14842 case 1: return &INT_REG_mask();
14843 }
14844 ShouldNotReachHere();
14845 return NULL;
14846}
14847
14848const RegMask *indPosIndexScaleOffsetOper::in_RegMask(int index) const {
14849 assert(0 <= index && index < 2, "index out of range");
14850 switch (index) {
14851 case 0: return &ANY_REG_mask();
14852 case 1: return &INT_REG_mask();
14853 }
14854 ShouldNotReachHere();
14855 return NULL;
14856}
14857
14858const RegMask *indCompressedOopOffsetOper::in_RegMask(int index) const {
14859 assert(0 <= index && index < 1, "index out of range");
14860 return &INT_REG_mask();
14861}
14862
14863const RegMask *indirectNarrowOper::in_RegMask(int index) const {
14864 assert(0 <= index && index < 1, "index out of range");
14865 return &INT_REG_mask();
14866}
14867
14868const RegMask *indOffset8NarrowOper::in_RegMask(int index) const {
14869 assert(0 <= index && index < 1, "index out of range");
14870 return &INT_REG_mask();
14871}
14872
14873const RegMask *indOffset32NarrowOper::in_RegMask(int index) const {
14874 assert(0 <= index && index < 1, "index out of range");
14875 return &INT_REG_mask();
14876}
14877
14878const RegMask *indIndexOffsetNarrowOper::in_RegMask(int index) const {
14879 assert(0 <= index && index < 2, "index out of range");
14880 switch (index) {
14881 case 0: return &INT_REG_mask();
14882 case 1: return &LONG_REG_mask();
14883 }
14884 ShouldNotReachHere();
14885 return NULL;
14886}
14887
14888const RegMask *indIndexNarrowOper::in_RegMask(int index) const {
14889 assert(0 <= index && index < 2, "index out of range");
14890 switch (index) {
14891 case 0: return &INT_REG_mask();
14892 case 1: return &LONG_REG_mask();
14893 }
14894 ShouldNotReachHere();
14895 return NULL;
14896}
14897
14898const RegMask *indIndexScaleNarrowOper::in_RegMask(int index) const {
14899 assert(0 <= index && index < 2, "index out of range");
14900 switch (index) {
14901 case 0: return &INT_REG_mask();
14902 case 1: return &LONG_REG_mask();
14903 }
14904 ShouldNotReachHere();
14905 return NULL;
14906}
14907
14908const RegMask *indIndexScaleOffsetNarrowOper::in_RegMask(int index) const {
14909 assert(0 <= index && index < 2, "index out of range");
14910 switch (index) {
14911 case 0: return &INT_REG_mask();
14912 case 1: return &LONG_REG_mask();
14913 }
14914 ShouldNotReachHere();
14915 return NULL;
14916}
14917
14918const RegMask *indPosIndexOffsetNarrowOper::in_RegMask(int index) const {
14919 assert(0 <= index && index < 2, "index out of range");
14920 return &INT_REG_mask();
14921}
14922
14923const RegMask *indPosIndexScaleOffsetNarrowOper::in_RegMask(int index) const {
14924 assert(0 <= index && index < 2, "index out of range");
14925 return &INT_REG_mask();
14926}
14927
14928const RegMask *stackSlotPOper::in_RegMask(int index) const {
14929 assert(0 <= index && index < 1, "index out of range");
14930 return &(Compile::current()->FIRST_STACK_mask());
14931}
14932
14933const RegMask *stackSlotIOper::in_RegMask(int index) const {
14934 assert(0 <= index && index < 1, "index out of range");
14935 return &(Compile::current()->FIRST_STACK_mask());
14936}
14937
14938const RegMask *stackSlotFOper::in_RegMask(int index) const {
14939 assert(0 <= index && index < 1, "index out of range");
14940 return &(Compile::current()->FIRST_STACK_mask());
14941}
14942
14943const RegMask *stackSlotDOper::in_RegMask(int index) const {
14944 assert(0 <= index && index < 1, "index out of range");
14945 return &(Compile::current()->FIRST_STACK_mask());
14946}
14947
14948const RegMask *stackSlotLOper::in_RegMask(int index) const {
14949 assert(0 <= index && index < 1, "index out of range");
14950 return &(Compile::current()->FIRST_STACK_mask());
14951}
14952
14953const RegMask *rxmm0Oper::in_RegMask(int index) const {
14954 assert(0 <= index && index < 1, "index out of range");
14955 return &XMM0_REG_mask();
14956}
14957
14958const RegMask *rxmm1Oper::in_RegMask(int index) const {
14959 assert(0 <= index && index < 1, "index out of range");
14960 return &XMM1_REG_mask();
14961}
14962
14963const RegMask *rxmm2Oper::in_RegMask(int index) const {
14964 assert(0 <= index && index < 1, "index out of range");
14965 return &XMM2_REG_mask();
14966}
14967
14968const RegMask *rxmm3Oper::in_RegMask(int index) const {
14969 assert(0 <= index && index < 1, "index out of range");
14970 return &XMM3_REG_mask();
14971}
14972
14973const RegMask *rxmm4Oper::in_RegMask(int index) const {
14974 assert(0 <= index && index < 1, "index out of range");
14975 return &XMM4_REG_mask();
14976}
14977
14978const RegMask *rxmm5Oper::in_RegMask(int index) const {
14979 assert(0 <= index && index < 1, "index out of range");
14980 return &XMM5_REG_mask();
14981}
14982
14983const RegMask *rxmm6Oper::in_RegMask(int index) const {
14984 assert(0 <= index && index < 1, "index out of range");
14985 return &XMM6_REG_mask();
14986}
14987
14988const RegMask *rxmm7Oper::in_RegMask(int index) const {
14989 assert(0 <= index && index < 1, "index out of range");
14990 return &XMM7_REG_mask();
14991}
14992
14993const RegMask *rxmm8Oper::in_RegMask(int index) const {
14994 assert(0 <= index && index < 1, "index out of range");
14995 return &XMM8_REG_mask();
14996}
14997
14998const RegMask *rxmm9Oper::in_RegMask(int index) const {
14999 assert(0 <= index && index < 1, "index out of range");
15000 return &XMM9_REG_mask();
15001}
15002
15003const RegMask *rxmm10Oper::in_RegMask(int index) const {
15004 assert(0 <= index && index < 1, "index out of range");
15005 return &XMM10_REG_mask();
15006}
15007
15008const RegMask *rxmm11Oper::in_RegMask(int index) const {
15009 assert(0 <= index && index < 1, "index out of range");
15010 return &XMM11_REG_mask();
15011}
15012
15013const RegMask *rxmm12Oper::in_RegMask(int index) const {
15014 assert(0 <= index && index < 1, "index out of range");
15015 return &XMM12_REG_mask();
15016}
15017
15018const RegMask *rxmm13Oper::in_RegMask(int index) const {
15019 assert(0 <= index && index < 1, "index out of range");
15020 return &XMM13_REG_mask();
15021}
15022
15023const RegMask *rxmm14Oper::in_RegMask(int index) const {
15024 assert(0 <= index && index < 1, "index out of range");
15025 return &XMM14_REG_mask();
15026}
15027
15028const RegMask *rxmm15Oper::in_RegMask(int index) const {
15029 assert(0 <= index && index < 1, "index out of range");
15030 return &XMM15_REG_mask();
15031}
15032
15033const RegMask *rxmm16Oper::in_RegMask(int index) const {
15034 assert(0 <= index && index < 1, "index out of range");
15035 return &XMM16_REG_mask();
15036}
15037
15038const RegMask *rxmm17Oper::in_RegMask(int index) const {
15039 assert(0 <= index && index < 1, "index out of range");
15040 return &XMM17_REG_mask();
15041}
15042
15043const RegMask *rxmm18Oper::in_RegMask(int index) const {
15044 assert(0 <= index && index < 1, "index out of range");
15045 return &XMM18_REG_mask();
15046}
15047
15048const RegMask *rxmm19Oper::in_RegMask(int index) const {
15049 assert(0 <= index && index < 1, "index out of range");
15050 return &XMM19_REG_mask();
15051}
15052
15053const RegMask *rxmm20Oper::in_RegMask(int index) const {
15054 assert(0 <= index && index < 1, "index out of range");
15055 return &XMM20_REG_mask();
15056}
15057
15058const RegMask *rxmm21Oper::in_RegMask(int index) const {
15059 assert(0 <= index && index < 1, "index out of range");
15060 return &XMM21_REG_mask();
15061}
15062
15063const RegMask *rxmm22Oper::in_RegMask(int index) const {
15064 assert(0 <= index && index < 1, "index out of range");
15065 return &XMM22_REG_mask();
15066}
15067
15068const RegMask *rxmm23Oper::in_RegMask(int index) const {
15069 assert(0 <= index && index < 1, "index out of range");
15070 return &XMM23_REG_mask();
15071}
15072
15073const RegMask *rxmm24Oper::in_RegMask(int index) const {
15074 assert(0 <= index && index < 1, "index out of range");
15075 return &XMM24_REG_mask();
15076}
15077
15078const RegMask *rxmm25Oper::in_RegMask(int index) const {
15079 assert(0 <= index && index < 1, "index out of range");
15080 return &XMM25_REG_mask();
15081}
15082
15083const RegMask *rxmm26Oper::in_RegMask(int index) const {
15084 assert(0 <= index && index < 1, "index out of range");
15085 return &XMM26_REG_mask();
15086}
15087
15088const RegMask *rxmm27Oper::in_RegMask(int index) const {
15089 assert(0 <= index && index < 1, "index out of range");
15090 return &XMM27_REG_mask();
15091}
15092
15093const RegMask *rxmm28Oper::in_RegMask(int index) const {
15094 assert(0 <= index && index < 1, "index out of range");
15095 return &XMM28_REG_mask();
15096}
15097
15098const RegMask *rxmm29Oper::in_RegMask(int index) const {
15099 assert(0 <= index && index < 1, "index out of range");
15100 return &XMM29_REG_mask();
15101}
15102
15103const RegMask *rxmm30Oper::in_RegMask(int index) const {
15104 assert(0 <= index && index < 1, "index out of range");
15105 return &XMM30_REG_mask();
15106}
15107
15108const RegMask *rxmm31Oper::in_RegMask(int index) const {
15109 assert(0 <= index && index < 1, "index out of range");
15110 return &XMM31_REG_mask();
15111}
15112
15113const RegMask *vecZOper::in_RegMask(int index) const {
15114 assert(0 <= index && index < 1, "index out of range");
15115 return &VECTORZ_REG_mask();
15116}
15117
15118const RegMask *legVecZOper::in_RegMask(int index) const {
15119 assert(0 <= index && index < 1, "index out of range");
15120 return &VECTORZ_REG_VL_mask();
15121}
15122
15123//------------------Define members for classes derived from MachNode----------
15124
15125void MoveVL2FNode::use_cisc_RegMask() {
15126 _cisc_RegMask = &STACK_OR_FLOAT_REG_VL_mask();
15127}
15128
15129// Build CISC version of this instruction
15130MachNode *MoveVL2FNode::cisc_version(int offset) {
15131 loadFNode *node = new loadFNode();
15132
15133 // Copy _idx, inputs and operands to new node
15134 fill_new_machnode(node);
15135 // Construct operand to access [stack_pointer + offset]
15136 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15137
15138 return node;
15139}
15140
15141
15142void MoveLEG2FNode::use_cisc_RegMask() {
15143 _cisc_RegMask = &STACK_OR_FLOAT_REG_LEGACY_mask();
15144}
15145
15146// Build CISC version of this instruction
15147MachNode *MoveLEG2FNode::cisc_version(int offset) {
15148 loadFNode *node = new loadFNode();
15149
15150 // Copy _idx, inputs and operands to new node
15151 fill_new_machnode(node);
15152 // Construct operand to access [stack_pointer + offset]
15153 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15154
15155 return node;
15156}
15157
15158
15159void MoveVL2DNode::use_cisc_RegMask() {
15160 _cisc_RegMask = &STACK_OR_DOUBLE_REG_VL_mask();
15161}
15162
15163// Build CISC version of this instruction
15164MachNode *MoveVL2DNode::cisc_version(int offset) {
15165 loadSSDNode *node = new loadSSDNode();
15166
15167 // Copy _idx, inputs and operands to new node
15168 fill_new_machnode(node);
15169 // Construct operand to access [stack_pointer + offset]
15170 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15171
15172 return node;
15173}
15174
15175
15176void MoveLEG2DNode::use_cisc_RegMask() {
15177 _cisc_RegMask = &STACK_OR_DOUBLE_REG_LEGACY_mask();
15178}
15179
15180// Build CISC version of this instruction
15181MachNode *MoveLEG2DNode::cisc_version(int offset) {
15182 loadSSDNode *node = new loadSSDNode();
15183
15184 // Copy _idx, inputs and operands to new node
15185 fill_new_machnode(node);
15186 // Construct operand to access [stack_pointer + offset]
15187 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15188
15189 return node;
15190}
15191
15192
15193void popCountINode::use_cisc_RegMask() {
15194 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15195}
15196
15197// Build CISC version of this instruction
15198MachNode *popCountINode::cisc_version(int offset) {
15199 popCountI_memNode *node = new popCountI_memNode();
15200
15201 // Copy _idx, inputs and operands to new node
15202 fill_new_machnode(node);
15203 // Construct operand to access [stack_pointer + offset]
15204 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15205
15206 return node;
15207}
15208
15209
15210void popCountLNode::use_cisc_RegMask() {
15211 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15212}
15213
15214// Build CISC version of this instruction
15215MachNode *popCountLNode::cisc_version(int offset) {
15216 popCountL_memNode *node = new popCountL_memNode();
15217
15218 // Copy _idx, inputs and operands to new node
15219 fill_new_machnode(node);
15220 // Construct operand to access [stack_pointer + offset]
15221 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15222
15223 return node;
15224}
15225
15226
15227void cmovI_regNode::use_cisc_RegMask() {
15228 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15229}
15230
15231// Build CISC version of this instruction
15232MachNode *cmovI_regNode::cisc_version(int offset) {
15233 cmovI_memNode *node = new cmovI_memNode();
15234
15235 // Copy _idx, inputs and operands to new node
15236 fill_new_machnode(node);
15237 // Construct operand to access [stack_pointer + offset]
15238 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15239
15240 return node;
15241}
15242
15243
15244void cmovI_regUNode::use_cisc_RegMask() {
15245 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15246}
15247
15248// Build CISC version of this instruction
15249MachNode *cmovI_regUNode::cisc_version(int offset) {
15250 cmovI_memUNode *node = new cmovI_memUNode();
15251
15252 // Copy _idx, inputs and operands to new node
15253 fill_new_machnode(node);
15254 // Construct operand to access [stack_pointer + offset]
15255 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15256
15257 return node;
15258}
15259
15260
15261void cmovI_regUCFNode::use_cisc_RegMask() {
15262 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15263}
15264
15265// Build CISC version of this instruction
15266MachNode *cmovI_regUCFNode::cisc_version(int offset) {
15267 cmovI_memUCFNode *node = new cmovI_memUCFNode();
15268
15269 // Copy _idx, inputs and operands to new node
15270 fill_new_machnode(node);
15271 // Construct operand to access [stack_pointer + offset]
15272 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15273
15274 return node;
15275}
15276
15277
15278void cmovL_regNode::use_cisc_RegMask() {
15279 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15280}
15281
15282// Build CISC version of this instruction
15283MachNode *cmovL_regNode::cisc_version(int offset) {
15284 cmovL_memNode *node = new cmovL_memNode();
15285
15286 // Copy _idx, inputs and operands to new node
15287 fill_new_machnode(node);
15288 // Construct operand to access [stack_pointer + offset]
15289 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15290
15291 return node;
15292}
15293
15294
15295void cmovL_regUNode::use_cisc_RegMask() {
15296 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15297}
15298
15299// Build CISC version of this instruction
15300MachNode *cmovL_regUNode::cisc_version(int offset) {
15301 cmovL_memUNode *node = new cmovL_memUNode();
15302
15303 // Copy _idx, inputs and operands to new node
15304 fill_new_machnode(node);
15305 // Construct operand to access [stack_pointer + offset]
15306 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15307
15308 return node;
15309}
15310
15311
15312void cmovL_regUCFNode::use_cisc_RegMask() {
15313 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15314}
15315
15316// Build CISC version of this instruction
15317MachNode *cmovL_regUCFNode::cisc_version(int offset) {
15318 cmovL_memUCFNode *node = new cmovL_memUCFNode();
15319
15320 // Copy _idx, inputs and operands to new node
15321 fill_new_machnode(node);
15322 // Construct operand to access [stack_pointer + offset]
15323 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15324
15325 return node;
15326}
15327
15328
15329void addI_rRegNode::use_cisc_RegMask() {
15330 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15331}
15332
15333// Build CISC version of this instruction
15334MachNode *addI_rRegNode::cisc_version(int offset) {
15335 addI_rReg_memNode *node = new addI_rReg_memNode();
15336
15337 // Copy _idx, inputs and operands to new node
15338 fill_new_machnode(node);
15339 // Construct operand to access [stack_pointer + offset]
15340 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15341
15342 return node;
15343}
15344
15345
15346void addL_rRegNode::use_cisc_RegMask() {
15347 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15348}
15349
15350// Build CISC version of this instruction
15351MachNode *addL_rRegNode::cisc_version(int offset) {
15352 addL_rReg_memNode *node = new addL_rReg_memNode();
15353
15354 // Copy _idx, inputs and operands to new node
15355 fill_new_machnode(node);
15356 // Construct operand to access [stack_pointer + offset]
15357 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15358
15359 return node;
15360}
15361
15362
15363void subI_rRegNode::use_cisc_RegMask() {
15364 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15365}
15366
15367// Build CISC version of this instruction
15368MachNode *subI_rRegNode::cisc_version(int offset) {
15369 subI_rReg_memNode *node = new subI_rReg_memNode();
15370
15371 // Copy _idx, inputs and operands to new node
15372 fill_new_machnode(node);
15373 // Construct operand to access [stack_pointer + offset]
15374 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15375
15376 return node;
15377}
15378
15379
15380void subL_rRegNode::use_cisc_RegMask() {
15381 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15382}
15383
15384// Build CISC version of this instruction
15385MachNode *subL_rRegNode::cisc_version(int offset) {
15386 subL_rReg_memNode *node = new subL_rReg_memNode();
15387
15388 // Copy _idx, inputs and operands to new node
15389 fill_new_machnode(node);
15390 // Construct operand to access [stack_pointer + offset]
15391 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15392
15393 return node;
15394}
15395
15396
15397void mulI_rRegNode::use_cisc_RegMask() {
15398 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15399}
15400
15401// Build CISC version of this instruction
15402MachNode *mulI_rRegNode::cisc_version(int offset) {
15403 mulI_memNode *node = new mulI_memNode();
15404
15405 // Copy _idx, inputs and operands to new node
15406 fill_new_machnode(node);
15407 // Construct operand to access [stack_pointer + offset]
15408 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15409
15410 return node;
15411}
15412
15413
15414void mulI_rReg_immNode::use_cisc_RegMask() {
15415 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15416}
15417
15418// Build CISC version of this instruction
15419MachNode *mulI_rReg_immNode::cisc_version(int offset) {
15420 mulI_mem_immNode *node = new mulI_mem_immNode();
15421
15422 // Copy _idx, inputs and operands to new node
15423 fill_new_machnode(node);
15424 // Construct operand to access [stack_pointer + offset]
15425 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15426
15427 return node;
15428}
15429
15430
15431void mulL_rRegNode::use_cisc_RegMask() {
15432 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15433}
15434
15435// Build CISC version of this instruction
15436MachNode *mulL_rRegNode::cisc_version(int offset) {
15437 mulL_memNode *node = new mulL_memNode();
15438
15439 // Copy _idx, inputs and operands to new node
15440 fill_new_machnode(node);
15441 // Construct operand to access [stack_pointer + offset]
15442 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15443
15444 return node;
15445}
15446
15447
15448void mulL_rReg_immNode::use_cisc_RegMask() {
15449 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15450}
15451
15452// Build CISC version of this instruction
15453MachNode *mulL_rReg_immNode::cisc_version(int offset) {
15454 mulL_mem_immNode *node = new mulL_mem_immNode();
15455
15456 // Copy _idx, inputs and operands to new node
15457 fill_new_machnode(node);
15458 // Construct operand to access [stack_pointer + offset]
15459 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15460
15461 return node;
15462}
15463
15464
15465void i2bNode::use_cisc_RegMask() {
15466 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15467}
15468
15469// Build CISC version of this instruction
15470MachNode *i2bNode::cisc_version(int offset) {
15471 loadI2BNode *node = new loadI2BNode();
15472 node->_num_opnds = 3;
15473
15474 // Copy _idx, inputs and operands to new node
15475 fill_new_machnode(node);
15476 // Construct operand to access [stack_pointer + offset]
15477 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15478
15479 return node;
15480}
15481
15482
15483void i2sNode::use_cisc_RegMask() {
15484 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15485}
15486
15487// Build CISC version of this instruction
15488MachNode *i2sNode::cisc_version(int offset) {
15489 loadI2SNode *node = new loadI2SNode();
15490 node->_num_opnds = 3;
15491
15492 // Copy _idx, inputs and operands to new node
15493 fill_new_machnode(node);
15494 // Construct operand to access [stack_pointer + offset]
15495 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15496
15497 return node;
15498}
15499
15500
15501void andI_rRegNode::use_cisc_RegMask() {
15502 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15503}
15504
15505// Build CISC version of this instruction
15506MachNode *andI_rRegNode::cisc_version(int offset) {
15507 andI_rReg_memNode *node = new andI_rReg_memNode();
15508
15509 // Copy _idx, inputs and operands to new node
15510 fill_new_machnode(node);
15511 // Construct operand to access [stack_pointer + offset]
15512 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15513
15514 return node;
15515}
15516
15517
15518void andI2L_rReg_imm255Node::use_cisc_RegMask() {
15519 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15520}
15521
15522// Build CISC version of this instruction
15523MachNode *andI2L_rReg_imm255Node::cisc_version(int offset) {
15524 loadI2L_immI_255Node *node = new loadI2L_immI_255Node();
15525
15526 // Copy _idx, inputs and operands to new node
15527 fill_new_machnode(node);
15528 // Construct operand to access [stack_pointer + offset]
15529 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15530
15531 return node;
15532}
15533
15534
15535void andI2L_rReg_imm65535Node::use_cisc_RegMask() {
15536 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15537}
15538
15539// Build CISC version of this instruction
15540MachNode *andI2L_rReg_imm65535Node::cisc_version(int offset) {
15541 loadI2L_immI_65535Node *node = new loadI2L_immI_65535Node();
15542
15543 // Copy _idx, inputs and operands to new node
15544 fill_new_machnode(node);
15545 // Construct operand to access [stack_pointer + offset]
15546 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15547
15548 return node;
15549}
15550
15551
15552void andnI_rReg_rReg_rRegNode::use_cisc_RegMask() {
15553 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15554}
15555
15556// Build CISC version of this instruction
15557MachNode *andnI_rReg_rReg_rRegNode::cisc_version(int offset) {
15558 andnI_rReg_rReg_memNode *node = new andnI_rReg_rReg_memNode();
15559
15560 // Copy _idx, inputs and operands to new node
15561 fill_new_machnode(node);
15562 // Construct operand to access [stack_pointer + offset]
15563 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15564
15565 return node;
15566}
15567
15568
15569void andnI_rReg_rReg_rReg_0Node::use_cisc_RegMask() {
15570 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15571}
15572
15573// Build CISC version of this instruction
15574MachNode *andnI_rReg_rReg_rReg_0Node::cisc_version(int offset) {
15575 andnI_rReg_rReg_mem_0Node *node = new andnI_rReg_rReg_mem_0Node();
15576
15577 // Copy _idx, inputs and operands to new node
15578 fill_new_machnode(node);
15579 // Construct operand to access [stack_pointer + offset]
15580 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15581
15582 return node;
15583}
15584
15585
15586void orI_rRegNode::use_cisc_RegMask() {
15587 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15588}
15589
15590// Build CISC version of this instruction
15591MachNode *orI_rRegNode::cisc_version(int offset) {
15592 orI_rReg_memNode *node = new orI_rReg_memNode();
15593
15594 // Copy _idx, inputs and operands to new node
15595 fill_new_machnode(node);
15596 // Construct operand to access [stack_pointer + offset]
15597 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15598
15599 return node;
15600}
15601
15602
15603void xorI_rRegNode::use_cisc_RegMask() {
15604 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15605}
15606
15607// Build CISC version of this instruction
15608MachNode *xorI_rRegNode::cisc_version(int offset) {
15609 xorI_rReg_memNode *node = new xorI_rReg_memNode();
15610
15611 // Copy _idx, inputs and operands to new node
15612 fill_new_machnode(node);
15613 // Construct operand to access [stack_pointer + offset]
15614 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15615
15616 return node;
15617}
15618
15619
15620void andL_rRegNode::use_cisc_RegMask() {
15621 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15622}
15623
15624// Build CISC version of this instruction
15625MachNode *andL_rRegNode::cisc_version(int offset) {
15626 andL_rReg_memNode *node = new andL_rReg_memNode();
15627
15628 // Copy _idx, inputs and operands to new node
15629 fill_new_machnode(node);
15630 // Construct operand to access [stack_pointer + offset]
15631 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15632
15633 return node;
15634}
15635
15636
15637void andnL_rReg_rReg_rRegNode::use_cisc_RegMask() {
15638 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15639}
15640
15641// Build CISC version of this instruction
15642MachNode *andnL_rReg_rReg_rRegNode::cisc_version(int offset) {
15643 andnL_rReg_rReg_memNode *node = new andnL_rReg_rReg_memNode();
15644
15645 // Copy _idx, inputs and operands to new node
15646 fill_new_machnode(node);
15647 // Construct operand to access [stack_pointer + offset]
15648 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15649
15650 return node;
15651}
15652
15653
15654void andnL_rReg_rReg_rReg_0Node::use_cisc_RegMask() {
15655 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15656}
15657
15658// Build CISC version of this instruction
15659MachNode *andnL_rReg_rReg_rReg_0Node::cisc_version(int offset) {
15660 andnL_rReg_rReg_mem_0Node *node = new andnL_rReg_rReg_mem_0Node();
15661
15662 // Copy _idx, inputs and operands to new node
15663 fill_new_machnode(node);
15664 // Construct operand to access [stack_pointer + offset]
15665 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15666
15667 return node;
15668}
15669
15670
15671void orL_rRegNode::use_cisc_RegMask() {
15672 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15673}
15674
15675// Build CISC version of this instruction
15676MachNode *orL_rRegNode::cisc_version(int offset) {
15677 orL_rReg_memNode *node = new orL_rReg_memNode();
15678
15679 // Copy _idx, inputs and operands to new node
15680 fill_new_machnode(node);
15681 // Construct operand to access [stack_pointer + offset]
15682 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15683
15684 return node;
15685}
15686
15687
15688void xorL_rRegNode::use_cisc_RegMask() {
15689 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15690}
15691
15692// Build CISC version of this instruction
15693MachNode *xorL_rRegNode::cisc_version(int offset) {
15694 xorL_rReg_memNode *node = new xorL_rReg_memNode();
15695
15696 // Copy _idx, inputs and operands to new node
15697 fill_new_machnode(node);
15698 // Construct operand to access [stack_pointer + offset]
15699 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15700
15701 return node;
15702}
15703
15704
15705void cmpF_cc_regNode::use_cisc_RegMask() {
15706 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15707}
15708
15709// Build CISC version of this instruction
15710MachNode *cmpF_cc_regNode::cisc_version(int offset) {
15711 cmpF_cc_memNode *node = new cmpF_cc_memNode();
15712
15713 // Copy _idx, inputs and operands to new node
15714 fill_new_machnode(node);
15715 // Construct operand to access [stack_pointer + offset]
15716 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15717
15718 return node;
15719}
15720
15721
15722void cmpF_cc_reg_CFNode::use_cisc_RegMask() {
15723 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15724}
15725
15726// Build CISC version of this instruction
15727MachNode *cmpF_cc_reg_CFNode::cisc_version(int offset) {
15728 cmpF_cc_memCFNode *node = new cmpF_cc_memCFNode();
15729
15730 // Copy _idx, inputs and operands to new node
15731 fill_new_machnode(node);
15732 // Construct operand to access [stack_pointer + offset]
15733 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15734
15735 return node;
15736}
15737
15738
15739void cmpD_cc_regNode::use_cisc_RegMask() {
15740 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15741}
15742
15743// Build CISC version of this instruction
15744MachNode *cmpD_cc_regNode::cisc_version(int offset) {
15745 cmpD_cc_memNode *node = new cmpD_cc_memNode();
15746
15747 // Copy _idx, inputs and operands to new node
15748 fill_new_machnode(node);
15749 // Construct operand to access [stack_pointer + offset]
15750 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15751
15752 return node;
15753}
15754
15755
15756void cmpD_cc_reg_CFNode::use_cisc_RegMask() {
15757 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15758}
15759
15760// Build CISC version of this instruction
15761MachNode *cmpD_cc_reg_CFNode::cisc_version(int offset) {
15762 cmpD_cc_memCFNode *node = new cmpD_cc_memCFNode();
15763
15764 // Copy _idx, inputs and operands to new node
15765 fill_new_machnode(node);
15766 // Construct operand to access [stack_pointer + offset]
15767 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15768
15769 return node;
15770}
15771
15772
15773void cmpF_regNode::use_cisc_RegMask() {
15774 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15775}
15776
15777// Build CISC version of this instruction
15778MachNode *cmpF_regNode::cisc_version(int offset) {
15779 cmpF_memNode *node = new cmpF_memNode();
15780
15781 // Copy _idx, inputs and operands to new node
15782 fill_new_machnode(node);
15783 // Construct operand to access [stack_pointer + offset]
15784 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15785
15786 return node;
15787}
15788
15789
15790void cmpD_regNode::use_cisc_RegMask() {
15791 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15792}
15793
15794// Build CISC version of this instruction
15795MachNode *cmpD_regNode::cisc_version(int offset) {
15796 cmpD_memNode *node = new cmpD_memNode();
15797
15798 // Copy _idx, inputs and operands to new node
15799 fill_new_machnode(node);
15800 // Construct operand to access [stack_pointer + offset]
15801 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15802
15803 return node;
15804}
15805
15806
15807void convF2D_reg_regNode::use_cisc_RegMask() {
15808 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15809}
15810
15811// Build CISC version of this instruction
15812MachNode *convF2D_reg_regNode::cisc_version(int offset) {
15813 convF2D_reg_memNode *node = new convF2D_reg_memNode();
15814
15815 // Copy _idx, inputs and operands to new node
15816 fill_new_machnode(node);
15817 // Construct operand to access [stack_pointer + offset]
15818 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15819
15820 return node;
15821}
15822
15823
15824void convD2F_reg_regNode::use_cisc_RegMask() {
15825 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15826}
15827
15828// Build CISC version of this instruction
15829MachNode *convD2F_reg_regNode::cisc_version(int offset) {
15830 convD2F_reg_memNode *node = new convD2F_reg_memNode();
15831
15832 // Copy _idx, inputs and operands to new node
15833 fill_new_machnode(node);
15834 // Construct operand to access [stack_pointer + offset]
15835 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15836
15837 return node;
15838}
15839
15840
15841void convL2F_reg_regNode::use_cisc_RegMask() {
15842 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15843}
15844
15845// Build CISC version of this instruction
15846MachNode *convL2F_reg_regNode::cisc_version(int offset) {
15847 convL2F_reg_memNode *node = new convL2F_reg_memNode();
15848
15849 // Copy _idx, inputs and operands to new node
15850 fill_new_machnode(node);
15851 // Construct operand to access [stack_pointer + offset]
15852 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15853
15854 return node;
15855}
15856
15857
15858void convL2D_reg_regNode::use_cisc_RegMask() {
15859 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15860}
15861
15862// Build CISC version of this instruction
15863MachNode *convL2D_reg_regNode::cisc_version(int offset) {
15864 convL2D_reg_memNode *node = new convL2D_reg_memNode();
15865
15866 // Copy _idx, inputs and operands to new node
15867 fill_new_machnode(node);
15868 // Construct operand to access [stack_pointer + offset]
15869 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15870
15871 return node;
15872}
15873
15874
15875void convI2L_reg_regNode::use_cisc_RegMask() {
15876 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15877}
15878
15879// Build CISC version of this instruction
15880MachNode *convI2L_reg_regNode::cisc_version(int offset) {
15881 loadI2LNode *node = new loadI2LNode();
15882
15883 // Copy _idx, inputs and operands to new node
15884 fill_new_machnode(node);
15885 // Construct operand to access [stack_pointer + offset]
15886 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15887
15888 return node;
15889}
15890
15891
15892void convI2L_reg_reg_zexNode::use_cisc_RegMask() {
15893 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15894}
15895
15896// Build CISC version of this instruction
15897MachNode *convI2L_reg_reg_zexNode::cisc_version(int offset) {
15898 loadUI2LNode *node = new loadUI2LNode();
15899
15900 // Copy _idx, inputs and operands to new node
15901 fill_new_machnode(node);
15902 // Construct operand to access [stack_pointer + offset]
15903 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15904
15905 return node;
15906}
15907
15908
15909void MoveF2I_reg_regNode::use_cisc_RegMask() {
15910 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15911}
15912
15913// Build CISC version of this instruction
15914MachNode *MoveF2I_reg_regNode::cisc_version(int offset) {
15915 MoveF2I_stack_regNode *node = new MoveF2I_stack_regNode();
15916
15917 // Copy _idx, inputs and operands to new node
15918 fill_new_machnode(node);
15919 // Construct operand to access [stack_pointer + offset]
15920 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15921
15922 return node;
15923}
15924
15925
15926void MoveD2L_reg_regNode::use_cisc_RegMask() {
15927 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15928}
15929
15930// Build CISC version of this instruction
15931MachNode *MoveD2L_reg_regNode::cisc_version(int offset) {
15932 MoveD2L_stack_regNode *node = new MoveD2L_stack_regNode();
15933
15934 // Copy _idx, inputs and operands to new node
15935 fill_new_machnode(node);
15936 // Construct operand to access [stack_pointer + offset]
15937 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15938
15939 return node;
15940}
15941
15942
15943void MoveI2F_reg_regNode::use_cisc_RegMask() {
15944 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15945}
15946
15947// Build CISC version of this instruction
15948MachNode *MoveI2F_reg_regNode::cisc_version(int offset) {
15949 MoveI2F_stack_regNode *node = new MoveI2F_stack_regNode();
15950
15951 // Copy _idx, inputs and operands to new node
15952 fill_new_machnode(node);
15953 // Construct operand to access [stack_pointer + offset]
15954 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15955
15956 return node;
15957}
15958
15959
15960void compI_rRegNode::use_cisc_RegMask() {
15961 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15962}
15963
15964// Build CISC version of this instruction
15965MachNode *compI_rRegNode::cisc_version(int offset) {
15966 compI_rReg_memNode *node = new compI_rReg_memNode();
15967
15968 // Copy _idx, inputs and operands to new node
15969 fill_new_machnode(node);
15970 // Construct operand to access [stack_pointer + offset]
15971 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15972
15973 return node;
15974}
15975
15976
15977void compU_rRegNode::use_cisc_RegMask() {
15978 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15979}
15980
15981// Build CISC version of this instruction
15982MachNode *compU_rRegNode::cisc_version(int offset) {
15983 compU_rReg_memNode *node = new compU_rReg_memNode();
15984
15985 // Copy _idx, inputs and operands to new node
15986 fill_new_machnode(node);
15987 // Construct operand to access [stack_pointer + offset]
15988 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15989
15990 return node;
15991}
15992
15993
15994void compP_rRegNode::use_cisc_RegMask() {
15995 _cisc_RegMask = &STACK_OR_PTR_REG_mask();
15996}
15997
15998// Build CISC version of this instruction
15999MachNode *compP_rRegNode::cisc_version(int offset) {
16000 compP_rReg_memNode *node = new compP_rReg_memNode();
16001
16002 // Copy _idx, inputs and operands to new node
16003 fill_new_machnode(node);
16004 // Construct operand to access [stack_pointer + offset]
16005 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16006
16007 return node;
16008}
16009
16010
16011void compL_rRegNode::use_cisc_RegMask() {
16012 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16013}
16014
16015// Build CISC version of this instruction
16016MachNode *compL_rRegNode::cisc_version(int offset) {
16017 compL_rReg_memNode *node = new compL_rReg_memNode();
16018
16019 // Copy _idx, inputs and operands to new node
16020 fill_new_machnode(node);
16021 // Construct operand to access [stack_pointer + offset]
16022 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16023
16024 return node;
16025}
16026
16027
16028void compUL_rRegNode::use_cisc_RegMask() {
16029 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16030}
16031
16032// Build CISC version of this instruction
16033MachNode *compUL_rRegNode::cisc_version(int offset) {
16034 compUL_rReg_memNode *node = new compUL_rReg_memNode();
16035
16036 // Copy _idx, inputs and operands to new node
16037 fill_new_machnode(node);
16038 // Construct operand to access [stack_pointer + offset]
16039 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16040
16041 return node;
16042}
16043
16044// Build short branch version of this instruction
16045MachNode *jmpDirNode::short_branch_version() {
16046 jmpDir_shortNode *node = new jmpDir_shortNode();
16047
16048 // Copy _idx, inputs and operands to new node
16049 fill_new_machnode(node);
16050 return node;
16051}
16052
16053// Build short branch version of this instruction
16054MachNode *jmpConNode::short_branch_version() {
16055 jmpCon_shortNode *node = new jmpCon_shortNode();
16056 node->_prob = _prob;
16057 node->_fcnt = _fcnt;
16058
16059 // Copy _idx, inputs and operands to new node
16060 fill_new_machnode(node);
16061 return node;
16062}
16063
16064// Build short branch version of this instruction
16065MachNode *jmpLoopEndNode::short_branch_version() {
16066 jmpLoopEnd_shortNode *node = new jmpLoopEnd_shortNode();
16067 node->_prob = _prob;
16068 node->_fcnt = _fcnt;
16069
16070 // Copy _idx, inputs and operands to new node
16071 fill_new_machnode(node);
16072 return node;
16073}
16074
16075// Build short branch version of this instruction
16076MachNode *jmpLoopEndUNode::short_branch_version() {
16077 jmpLoopEndU_shortNode *node = new jmpLoopEndU_shortNode();
16078 node->_prob = _prob;
16079 node->_fcnt = _fcnt;
16080
16081 // Copy _idx, inputs and operands to new node
16082 fill_new_machnode(node);
16083 return node;
16084}
16085
16086// Build short branch version of this instruction
16087MachNode *jmpLoopEndUCFNode::short_branch_version() {
16088 jmpLoopEndUCF_shortNode *node = new jmpLoopEndUCF_shortNode();
16089 node->_prob = _prob;
16090 node->_fcnt = _fcnt;
16091
16092 // Copy _idx, inputs and operands to new node
16093 fill_new_machnode(node);
16094 return node;
16095}
16096
16097// Build short branch version of this instruction
16098MachNode *jmpConUNode::short_branch_version() {
16099 jmpConU_shortNode *node = new jmpConU_shortNode();
16100 node->_prob = _prob;
16101 node->_fcnt = _fcnt;
16102
16103 // Copy _idx, inputs and operands to new node
16104 fill_new_machnode(node);
16105 return node;
16106}
16107
16108// Build short branch version of this instruction
16109MachNode *jmpConUCFNode::short_branch_version() {
16110 jmpConUCF_shortNode *node = new jmpConUCF_shortNode();
16111 node->_prob = _prob;
16112 node->_fcnt = _fcnt;
16113
16114 // Copy _idx, inputs and operands to new node
16115 fill_new_machnode(node);
16116 return node;
16117}
16118
16119// Build short branch version of this instruction
16120MachNode *jmpConUCF2Node::short_branch_version() {
16121 jmpConUCF2_shortNode *node = new jmpConUCF2_shortNode();
16122 node->_prob = _prob;
16123 node->_fcnt = _fcnt;
16124
16125 // Copy _idx, inputs and operands to new node
16126 fill_new_machnode(node);
16127 return node;
16128}
16129
16130
16131void addF_regNode::use_cisc_RegMask() {
16132 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16133}
16134
16135// Build CISC version of this instruction
16136MachNode *addF_regNode::cisc_version(int offset) {
16137 addF_memNode *node = new addF_memNode();
16138
16139 // Copy _idx, inputs and operands to new node
16140 fill_new_machnode(node);
16141 // Construct operand to access [stack_pointer + offset]
16142 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16143
16144 return node;
16145}
16146
16147
16148void addF_reg_regNode::use_cisc_RegMask() {
16149 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16150}
16151
16152// Build CISC version of this instruction
16153MachNode *addF_reg_regNode::cisc_version(int offset) {
16154 addF_reg_memNode *node = new addF_reg_memNode();
16155
16156 // Copy _idx, inputs and operands to new node
16157 fill_new_machnode(node);
16158 // Construct operand to access [stack_pointer + offset]
16159 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16160
16161 return node;
16162}
16163
16164
16165void addD_regNode::use_cisc_RegMask() {
16166 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16167}
16168
16169// Build CISC version of this instruction
16170MachNode *addD_regNode::cisc_version(int offset) {
16171 addD_memNode *node = new addD_memNode();
16172
16173 // Copy _idx, inputs and operands to new node
16174 fill_new_machnode(node);
16175 // Construct operand to access [stack_pointer + offset]
16176 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16177
16178 return node;
16179}
16180
16181
16182void addD_reg_regNode::use_cisc_RegMask() {
16183 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16184}
16185
16186// Build CISC version of this instruction
16187MachNode *addD_reg_regNode::cisc_version(int offset) {
16188 addD_reg_memNode *node = new addD_reg_memNode();
16189
16190 // Copy _idx, inputs and operands to new node
16191 fill_new_machnode(node);
16192 // Construct operand to access [stack_pointer + offset]
16193 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16194
16195 return node;
16196}
16197
16198
16199void subF_regNode::use_cisc_RegMask() {
16200 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16201}
16202
16203// Build CISC version of this instruction
16204MachNode *subF_regNode::cisc_version(int offset) {
16205 subF_memNode *node = new subF_memNode();
16206
16207 // Copy _idx, inputs and operands to new node
16208 fill_new_machnode(node);
16209 // Construct operand to access [stack_pointer + offset]
16210 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16211
16212 return node;
16213}
16214
16215
16216void subF_reg_regNode::use_cisc_RegMask() {
16217 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16218}
16219
16220// Build CISC version of this instruction
16221MachNode *subF_reg_regNode::cisc_version(int offset) {
16222 subF_reg_memNode *node = new subF_reg_memNode();
16223
16224 // Copy _idx, inputs and operands to new node
16225 fill_new_machnode(node);
16226 // Construct operand to access [stack_pointer + offset]
16227 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16228
16229 return node;
16230}
16231
16232
16233void subD_regNode::use_cisc_RegMask() {
16234 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16235}
16236
16237// Build CISC version of this instruction
16238MachNode *subD_regNode::cisc_version(int offset) {
16239 subD_memNode *node = new subD_memNode();
16240
16241 // Copy _idx, inputs and operands to new node
16242 fill_new_machnode(node);
16243 // Construct operand to access [stack_pointer + offset]
16244 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16245
16246 return node;
16247}
16248
16249
16250void subD_reg_regNode::use_cisc_RegMask() {
16251 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16252}
16253
16254// Build CISC version of this instruction
16255MachNode *subD_reg_regNode::cisc_version(int offset) {
16256 subD_reg_memNode *node = new subD_reg_memNode();
16257
16258 // Copy _idx, inputs and operands to new node
16259 fill_new_machnode(node);
16260 // Construct operand to access [stack_pointer + offset]
16261 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16262
16263 return node;
16264}
16265
16266
16267void mulF_regNode::use_cisc_RegMask() {
16268 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16269}
16270
16271// Build CISC version of this instruction
16272MachNode *mulF_regNode::cisc_version(int offset) {
16273 mulF_memNode *node = new mulF_memNode();
16274
16275 // Copy _idx, inputs and operands to new node
16276 fill_new_machnode(node);
16277 // Construct operand to access [stack_pointer + offset]
16278 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16279
16280 return node;
16281}
16282
16283
16284void mulF_reg_regNode::use_cisc_RegMask() {
16285 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16286}
16287
16288// Build CISC version of this instruction
16289MachNode *mulF_reg_regNode::cisc_version(int offset) {
16290 mulF_reg_memNode *node = new mulF_reg_memNode();
16291
16292 // Copy _idx, inputs and operands to new node
16293 fill_new_machnode(node);
16294 // Construct operand to access [stack_pointer + offset]
16295 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16296
16297 return node;
16298}
16299
16300
16301void mulD_regNode::use_cisc_RegMask() {
16302 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16303}
16304
16305// Build CISC version of this instruction
16306MachNode *mulD_regNode::cisc_version(int offset) {
16307 mulD_memNode *node = new mulD_memNode();
16308
16309 // Copy _idx, inputs and operands to new node
16310 fill_new_machnode(node);
16311 // Construct operand to access [stack_pointer + offset]
16312 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16313
16314 return node;
16315}
16316
16317
16318void mulD_reg_regNode::use_cisc_RegMask() {
16319 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16320}
16321
16322// Build CISC version of this instruction
16323MachNode *mulD_reg_regNode::cisc_version(int offset) {
16324 mulD_reg_memNode *node = new mulD_reg_memNode();
16325
16326 // Copy _idx, inputs and operands to new node
16327 fill_new_machnode(node);
16328 // Construct operand to access [stack_pointer + offset]
16329 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16330
16331 return node;
16332}
16333
16334
16335void divF_regNode::use_cisc_RegMask() {
16336 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16337}
16338
16339// Build CISC version of this instruction
16340MachNode *divF_regNode::cisc_version(int offset) {
16341 divF_memNode *node = new divF_memNode();
16342
16343 // Copy _idx, inputs and operands to new node
16344 fill_new_machnode(node);
16345 // Construct operand to access [stack_pointer + offset]
16346 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16347
16348 return node;
16349}
16350
16351
16352void divF_reg_regNode::use_cisc_RegMask() {
16353 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16354}
16355
16356// Build CISC version of this instruction
16357MachNode *divF_reg_regNode::cisc_version(int offset) {
16358 divF_reg_memNode *node = new divF_reg_memNode();
16359
16360 // Copy _idx, inputs and operands to new node
16361 fill_new_machnode(node);
16362 // Construct operand to access [stack_pointer + offset]
16363 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16364
16365 return node;
16366}
16367
16368
16369void divD_regNode::use_cisc_RegMask() {
16370 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16371}
16372
16373// Build CISC version of this instruction
16374MachNode *divD_regNode::cisc_version(int offset) {
16375 divD_memNode *node = new divD_memNode();
16376
16377 // Copy _idx, inputs and operands to new node
16378 fill_new_machnode(node);
16379 // Construct operand to access [stack_pointer + offset]
16380 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16381
16382 return node;
16383}
16384
16385
16386void divD_reg_regNode::use_cisc_RegMask() {
16387 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16388}
16389
16390// Build CISC version of this instruction
16391MachNode *divD_reg_regNode::cisc_version(int offset) {
16392 divD_reg_memNode *node = new divD_reg_memNode();
16393
16394 // Copy _idx, inputs and operands to new node
16395 fill_new_machnode(node);
16396 // Construct operand to access [stack_pointer + offset]
16397 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16398
16399 return node;
16400}
16401
16402
16403void sqrtF_regNode::use_cisc_RegMask() {
16404 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16405}
16406
16407// Build CISC version of this instruction
16408MachNode *sqrtF_regNode::cisc_version(int offset) {
16409 sqrtF_memNode *node = new sqrtF_memNode();
16410
16411 // Copy _idx, inputs and operands to new node
16412 fill_new_machnode(node);
16413 // Construct operand to access [stack_pointer + offset]
16414 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16415
16416 return node;
16417}
16418
16419
16420void sqrtD_regNode::use_cisc_RegMask() {
16421 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16422}
16423
16424// Build CISC version of this instruction
16425MachNode *sqrtD_regNode::cisc_version(int offset) {
16426 sqrtD_memNode *node = new sqrtD_memNode();
16427
16428 // Copy _idx, inputs and operands to new node
16429 fill_new_machnode(node);
16430 // Construct operand to access [stack_pointer + offset]
16431 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16432
16433 return node;
16434}
16435
16436
16437void Repl8INode::use_cisc_RegMask() {
16438 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16439}
16440
16441// Build CISC version of this instruction
16442MachNode *Repl8INode::cisc_version(int offset) {
16443 Repl8I_memNode *node = new Repl8I_memNode();
16444 node->_bottom_type = bottom_type();
16445
16446 // Copy _idx, inputs and operands to new node
16447 fill_new_machnode(node);
16448 // Construct operand to access [stack_pointer + offset]
16449 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16450
16451 return node;
16452}
16453
16454
16455void Repl16INode::use_cisc_RegMask() {
16456 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16457}
16458
16459// Build CISC version of this instruction
16460MachNode *Repl16INode::cisc_version(int offset) {
16461 Repl16I_memNode *node = new Repl16I_memNode();
16462 node->_bottom_type = bottom_type();
16463
16464 // Copy _idx, inputs and operands to new node
16465 fill_new_machnode(node);
16466 // Construct operand to access [stack_pointer + offset]
16467 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16468
16469 return node;
16470}
16471
16472
16473void Repl4LNode::use_cisc_RegMask() {
16474 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16475}
16476
16477// Build CISC version of this instruction
16478MachNode *Repl4LNode::cisc_version(int offset) {
16479 Repl4L_memNode *node = new Repl4L_memNode();
16480 node->_bottom_type = bottom_type();
16481
16482 // Copy _idx, inputs and operands to new node
16483 fill_new_machnode(node);
16484 // Construct operand to access [stack_pointer + offset]
16485 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16486
16487 return node;
16488}
16489
16490
16491void Repl8LNode::use_cisc_RegMask() {
16492 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16493}
16494
16495// Build CISC version of this instruction
16496MachNode *Repl8LNode::cisc_version(int offset) {
16497 Repl8L_memNode *node = new Repl8L_memNode();
16498 node->_bottom_type = bottom_type();
16499
16500 // Copy _idx, inputs and operands to new node
16501 fill_new_machnode(node);
16502 // Construct operand to access [stack_pointer + offset]
16503 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16504
16505 return node;
16506}
16507
16508
16509void Repl2INode::use_cisc_RegMask() {
16510 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16511}
16512
16513// Build CISC version of this instruction
16514MachNode *Repl2INode::cisc_version(int offset) {
16515 Repl2I_memNode *node = new Repl2I_memNode();
16516 node->_bottom_type = bottom_type();
16517
16518 // Copy _idx, inputs and operands to new node
16519 fill_new_machnode(node);
16520 // Construct operand to access [stack_pointer + offset]
16521 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16522
16523 return node;
16524}
16525
16526
16527void Repl4I_evexNode::use_cisc_RegMask() {
16528 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16529}
16530
16531// Build CISC version of this instruction
16532MachNode *Repl4I_evexNode::cisc_version(int offset) {
16533 Repl4I_mem_evexNode *node = new Repl4I_mem_evexNode();
16534 node->_bottom_type = bottom_type();
16535
16536 // Copy _idx, inputs and operands to new node
16537 fill_new_machnode(node);
16538 // Construct operand to access [stack_pointer + offset]
16539 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16540
16541 return node;
16542}
16543
16544
16545void Repl8I_evexNode::use_cisc_RegMask() {
16546 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16547}
16548
16549// Build CISC version of this instruction
16550MachNode *Repl8I_evexNode::cisc_version(int offset) {
16551 Repl8I_mem_evexNode *node = new Repl8I_mem_evexNode();
16552 node->_bottom_type = bottom_type();
16553
16554 // Copy _idx, inputs and operands to new node
16555 fill_new_machnode(node);
16556 // Construct operand to access [stack_pointer + offset]
16557 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16558
16559 return node;
16560}
16561
16562
16563void Repl16I_evexNode::use_cisc_RegMask() {
16564 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16565}
16566
16567// Build CISC version of this instruction
16568MachNode *Repl16I_evexNode::cisc_version(int offset) {
16569 Repl16I_mem_evexNode *node = new Repl16I_mem_evexNode();
16570 node->_bottom_type = bottom_type();
16571
16572 // Copy _idx, inputs and operands to new node
16573 fill_new_machnode(node);
16574 // Construct operand to access [stack_pointer + offset]
16575 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16576
16577 return node;
16578}
16579
16580
16581void Repl4L_evexNode::use_cisc_RegMask() {
16582 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16583}
16584
16585// Build CISC version of this instruction
16586MachNode *Repl4L_evexNode::cisc_version(int offset) {
16587 Repl4L_mem_evexNode *node = new Repl4L_mem_evexNode();
16588 node->_bottom_type = bottom_type();
16589
16590 // Copy _idx, inputs and operands to new node
16591 fill_new_machnode(node);
16592 // Construct operand to access [stack_pointer + offset]
16593 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16594
16595 return node;
16596}
16597
16598
16599void Repl8L_evexNode::use_cisc_RegMask() {
16600 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16601}
16602
16603// Build CISC version of this instruction
16604MachNode *Repl8L_evexNode::cisc_version(int offset) {
16605 Repl8L_mem_evexNode *node = new Repl8L_mem_evexNode();
16606 node->_bottom_type = bottom_type();
16607
16608 // Copy _idx, inputs and operands to new node
16609 fill_new_machnode(node);
16610 // Construct operand to access [stack_pointer + offset]
16611 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16612
16613 return node;
16614}
16615
16616
16617void Repl8F_evexNode::use_cisc_RegMask() {
16618 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16619}
16620
16621// Build CISC version of this instruction
16622MachNode *Repl8F_evexNode::cisc_version(int offset) {
16623 Repl8F_mem_evexNode *node = new Repl8F_mem_evexNode();
16624 node->_bottom_type = bottom_type();
16625
16626 // Copy _idx, inputs and operands to new node
16627 fill_new_machnode(node);
16628 // Construct operand to access [stack_pointer + offset]
16629 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16630
16631 return node;
16632}
16633
16634
16635void Repl16F_evexNode::use_cisc_RegMask() {
16636 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16637}
16638
16639// Build CISC version of this instruction
16640MachNode *Repl16F_evexNode::cisc_version(int offset) {
16641 Repl16F_mem_evexNode *node = new Repl16F_mem_evexNode();
16642 node->_bottom_type = bottom_type();
16643
16644 // Copy _idx, inputs and operands to new node
16645 fill_new_machnode(node);
16646 // Construct operand to access [stack_pointer + offset]
16647 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16648
16649 return node;
16650}
16651
16652
16653void Repl4D_evexNode::use_cisc_RegMask() {
16654 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16655}
16656
16657// Build CISC version of this instruction
16658MachNode *Repl4D_evexNode::cisc_version(int offset) {
16659 Repl4D_mem_evexNode *node = new Repl4D_mem_evexNode();
16660 node->_bottom_type = bottom_type();
16661
16662 // Copy _idx, inputs and operands to new node
16663 fill_new_machnode(node);
16664 // Construct operand to access [stack_pointer + offset]
16665 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16666
16667 return node;
16668}
16669
16670
16671void Repl8D_evexNode::use_cisc_RegMask() {
16672 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16673}
16674
16675// Build CISC version of this instruction
16676MachNode *Repl8D_evexNode::cisc_version(int offset) {
16677 Repl8D_mem_evexNode *node = new Repl8D_mem_evexNode();
16678 node->_bottom_type = bottom_type();
16679
16680 // Copy _idx, inputs and operands to new node
16681 fill_new_machnode(node);
16682 // Construct operand to access [stack_pointer + offset]
16683 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16684
16685 return node;
16686}
16687
16688
16689// Copy _idx, inputs and operands to new node
16690void MachNode::fill_new_machnode(MachNode* node) const {
16691 // New node must use same node index
16692 node->set_idx( _idx );
16693 // Copy machine-independent inputs
16694 for( uint j = 0; j < req(); j++ ) {
16695 node->add_req(in(j));
16696 }
16697 // Copy my operands, except for cisc position
16698 int nopnds = num_opnds();
16699 assert( node->num_opnds() == (uint)nopnds, "Must have same number of operands");
16700 MachOper **to = node->_opnds;
16701 for( int i = 0; i < nopnds; i++ ) {
16702 if( i != cisc_operand() )
16703 to[i] = _opnds[i]->clone();
16704 }
16705}
16706
16707void jmpDirNode::label_set( Label* label, uint block_num ) {
16708 labelOper* oper = (labelOper*)(opnd_array(1));
16709 oper->_label = label;
16710 oper->_block_num = block_num;
16711}
16712void jmpDirNode::save_label( Label** label, uint* block_num ) {
16713 labelOper* oper = (labelOper*)(opnd_array(1));
16714 *label = oper->_label;
16715 *block_num = oper->_block_num;
16716}
16717void jmpConNode::label_set( Label* label, uint block_num ) {
16718 labelOper* oper = (labelOper*)(opnd_array(3));
16719 oper->_label = label;
16720 oper->_block_num = block_num;
16721}
16722void jmpConNode::save_label( Label** label, uint* block_num ) {
16723 labelOper* oper = (labelOper*)(opnd_array(3));
16724 *label = oper->_label;
16725 *block_num = oper->_block_num;
16726}
16727void jmpLoopEndNode::label_set( Label* label, uint block_num ) {
16728 labelOper* oper = (labelOper*)(opnd_array(3));
16729 oper->_label = label;
16730 oper->_block_num = block_num;
16731}
16732void jmpLoopEndNode::save_label( Label** label, uint* block_num ) {
16733 labelOper* oper = (labelOper*)(opnd_array(3));
16734 *label = oper->_label;
16735 *block_num = oper->_block_num;
16736}
16737void jmpLoopEndUNode::label_set( Label* label, uint block_num ) {
16738 labelOper* oper = (labelOper*)(opnd_array(3));
16739 oper->_label = label;
16740 oper->_block_num = block_num;
16741}
16742void jmpLoopEndUNode::save_label( Label** label, uint* block_num ) {
16743 labelOper* oper = (labelOper*)(opnd_array(3));
16744 *label = oper->_label;
16745 *block_num = oper->_block_num;
16746}
16747void jmpLoopEndUCFNode::label_set( Label* label, uint block_num ) {
16748 labelOper* oper = (labelOper*)(opnd_array(3));
16749 oper->_label = label;
16750 oper->_block_num = block_num;
16751}
16752void jmpLoopEndUCFNode::save_label( Label** label, uint* block_num ) {
16753 labelOper* oper = (labelOper*)(opnd_array(3));
16754 *label = oper->_label;
16755 *block_num = oper->_block_num;
16756}
16757void jmpLoopEnd_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16758 labelOper* oper = (labelOper*)(opnd_array(3));
16759 oper->_label = label;
16760 oper->_block_num = block_num;
16761}
16762void jmpLoopEnd_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16763 labelOper* oper = (labelOper*)(opnd_array(3));
16764 *label = oper->_label;
16765 *block_num = oper->_block_num;
16766}
16767void jmpLoopEndU_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16768 labelOper* oper = (labelOper*)(opnd_array(3));
16769 oper->_label = label;
16770 oper->_block_num = block_num;
16771}
16772void jmpLoopEndU_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16773 labelOper* oper = (labelOper*)(opnd_array(3));
16774 *label = oper->_label;
16775 *block_num = oper->_block_num;
16776}
16777void jmpLoopEndUCF_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16778 labelOper* oper = (labelOper*)(opnd_array(3));
16779 oper->_label = label;
16780 oper->_block_num = block_num;
16781}
16782void jmpLoopEndUCF_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16783 labelOper* oper = (labelOper*)(opnd_array(3));
16784 *label = oper->_label;
16785 *block_num = oper->_block_num;
16786}
16787void jmpConUNode::label_set( Label* label, uint block_num ) {
16788 labelOper* oper = (labelOper*)(opnd_array(3));
16789 oper->_label = label;
16790 oper->_block_num = block_num;
16791}
16792void jmpConUNode::save_label( Label** label, uint* block_num ) {
16793 labelOper* oper = (labelOper*)(opnd_array(3));
16794 *label = oper->_label;
16795 *block_num = oper->_block_num;
16796}
16797void jmpConUCFNode::label_set( Label* label, uint block_num ) {
16798 labelOper* oper = (labelOper*)(opnd_array(3));
16799 oper->_label = label;
16800 oper->_block_num = block_num;
16801}
16802void jmpConUCFNode::save_label( Label** label, uint* block_num ) {
16803 labelOper* oper = (labelOper*)(opnd_array(3));
16804 *label = oper->_label;
16805 *block_num = oper->_block_num;
16806}
16807void jmpConUCF2Node::label_set( Label* label, uint block_num ) {
16808 labelOper* oper = (labelOper*)(opnd_array(3));
16809 oper->_label = label;
16810 oper->_block_num = block_num;
16811}
16812void jmpConUCF2Node::save_label( Label** label, uint* block_num ) {
16813 labelOper* oper = (labelOper*)(opnd_array(3));
16814 *label = oper->_label;
16815 *block_num = oper->_block_num;
16816}
16817void jmpDir_shortNode::label_set( Label* label, uint block_num ) {
16818 labelOper* oper = (labelOper*)(opnd_array(1));
16819 oper->_label = label;
16820 oper->_block_num = block_num;
16821}
16822void jmpDir_shortNode::save_label( Label** label, uint* block_num ) {
16823 labelOper* oper = (labelOper*)(opnd_array(1));
16824 *label = oper->_label;
16825 *block_num = oper->_block_num;
16826}
16827void jmpCon_shortNode::label_set( Label* label, uint block_num ) {
16828 labelOper* oper = (labelOper*)(opnd_array(3));
16829 oper->_label = label;
16830 oper->_block_num = block_num;
16831}
16832void jmpCon_shortNode::save_label( Label** label, uint* block_num ) {
16833 labelOper* oper = (labelOper*)(opnd_array(3));
16834 *label = oper->_label;
16835 *block_num = oper->_block_num;
16836}
16837void jmpLoopEnd_shortNode::label_set( Label* label, uint block_num ) {
16838 labelOper* oper = (labelOper*)(opnd_array(3));
16839 oper->_label = label;
16840 oper->_block_num = block_num;
16841}
16842void jmpLoopEnd_shortNode::save_label( Label** label, uint* block_num ) {
16843 labelOper* oper = (labelOper*)(opnd_array(3));
16844 *label = oper->_label;
16845 *block_num = oper->_block_num;
16846}
16847void jmpLoopEndU_shortNode::label_set( Label* label, uint block_num ) {
16848 labelOper* oper = (labelOper*)(opnd_array(3));
16849 oper->_label = label;
16850 oper->_block_num = block_num;
16851}
16852void jmpLoopEndU_shortNode::save_label( Label** label, uint* block_num ) {
16853 labelOper* oper = (labelOper*)(opnd_array(3));
16854 *label = oper->_label;
16855 *block_num = oper->_block_num;
16856}
16857void jmpLoopEndUCF_shortNode::label_set( Label* label, uint block_num ) {
16858 labelOper* oper = (labelOper*)(opnd_array(3));
16859 oper->_label = label;
16860 oper->_block_num = block_num;
16861}
16862void jmpLoopEndUCF_shortNode::save_label( Label** label, uint* block_num ) {
16863 labelOper* oper = (labelOper*)(opnd_array(3));
16864 *label = oper->_label;
16865 *block_num = oper->_block_num;
16866}
16867void jmpConU_shortNode::label_set( Label* label, uint block_num ) {
16868 labelOper* oper = (labelOper*)(opnd_array(3));
16869 oper->_label = label;
16870 oper->_block_num = block_num;
16871}
16872void jmpConU_shortNode::save_label( Label** label, uint* block_num ) {
16873 labelOper* oper = (labelOper*)(opnd_array(3));
16874 *label = oper->_label;
16875 *block_num = oper->_block_num;
16876}
16877void jmpConUCF_shortNode::label_set( Label* label, uint block_num ) {
16878 labelOper* oper = (labelOper*)(opnd_array(3));
16879 oper->_label = label;
16880 oper->_block_num = block_num;
16881}
16882void jmpConUCF_shortNode::save_label( Label** label, uint* block_num ) {
16883 labelOper* oper = (labelOper*)(opnd_array(3));
16884 *label = oper->_label;
16885 *block_num = oper->_block_num;
16886}
16887void jmpConUCF2_shortNode::label_set( Label* label, uint block_num ) {
16888 labelOper* oper = (labelOper*)(opnd_array(3));
16889 oper->_label = label;
16890 oper->_block_num = block_num;
16891}
16892void jmpConUCF2_shortNode::save_label( Label** label, uint* block_num ) {
16893 labelOper* oper = (labelOper*)(opnd_array(3));
16894 *label = oper->_label;
16895 *block_num = oper->_block_num;
16896}
16897void CallStaticJavaDirectNode::method_set( intptr_t method ) {
16898 ((methodOper*)opnd_array(1))->_method = method;
16899}
16900
16901void CallDynamicJavaDirectNode::method_set( intptr_t method ) {
16902 ((methodOper*)opnd_array(1))->_method = method;
16903}
16904
16905void CallRuntimeDirectNode::method_set( intptr_t method ) {
16906 ((methodOper*)opnd_array(1))->_method = method;
16907}
16908
16909void CallLeafDirectNode::method_set( intptr_t method ) {
16910 ((methodOper*)opnd_array(1))->_method = method;
16911}
16912
16913void CallLeafNoFPDirectNode::method_set( intptr_t method ) {
16914 ((methodOper*)opnd_array(1))->_method = method;
16915}
16916
16917int loadBNode::reloc() const {
16918 return 1;
16919}
16920
16921int loadB2LNode::reloc() const {
16922 return 1;
16923}
16924
16925int loadUBNode::reloc() const {
16926 return 1;
16927}
16928
16929int loadUB2LNode::reloc() const {
16930 return 1;
16931}
16932
16933int loadUB2L_immINode::reloc() const {
16934 return 1;
16935}
16936
16937int loadSNode::reloc() const {
16938 return 1;
16939}
16940
16941int loadS2BNode::reloc() const {
16942 return 1;
16943}
16944
16945int loadS2LNode::reloc() const {
16946 return 1;
16947}
16948
16949int loadUSNode::reloc() const {
16950 return 1;
16951}
16952
16953int loadUS2BNode::reloc() const {
16954 return 1;
16955}
16956
16957int loadUS2LNode::reloc() const {
16958 return 1;
16959}
16960
16961int loadUS2L_immI_255Node::reloc() const {
16962 return 1;
16963}
16964
16965int loadUS2L_immINode::reloc() const {
16966 return 1;
16967}
16968
16969int loadINode::reloc() const {
16970 return 1;
16971}
16972
16973int loadI2BNode::reloc() const {
16974 return 1;
16975}
16976
16977int loadI2UBNode::reloc() const {
16978 return 1;
16979}
16980
16981int loadI2SNode::reloc() const {
16982 return 1;
16983}
16984
16985int loadI2USNode::reloc() const {
16986 return 1;
16987}
16988
16989int loadI2LNode::reloc() const {
16990 return 1;
16991}
16992
16993int loadI2L_immI_255Node::reloc() const {
16994 return 1;
16995}
16996
16997int loadI2L_immI_65535Node::reloc() const {
16998 return 1;
16999}
17000
17001int loadI2L_immU31Node::reloc() const {
17002 return 1;
17003}
17004
17005int loadUI2LNode::reloc() const {
17006 return 1;
17007}
17008
17009int loadLNode::reloc() const {
17010 return 1;
17011}
17012
17013int loadRangeNode::reloc() const {
17014 return 1;
17015}
17016
17017int loadPNode::reloc() const {
17018 return 1;
17019}
17020
17021int loadNNode::reloc() const {
17022 return 1;
17023}
17024
17025int loadKlassNode::reloc() const {
17026 return 1;
17027}
17028
17029int loadNKlassNode::reloc() const {
17030 return 1;
17031}
17032
17033int loadFNode::reloc() const {
17034 return 1;
17035}
17036
17037int loadD_partialNode::reloc() const {
17038 return 1;
17039}
17040
17041int loadDNode::reloc() const {
17042 return 1;
17043}
17044
17045int loadConPNode::reloc() const {
17046 return 1;
17047}
17048
17049int loadConP0Node::reloc() const {
17050 return 1;
17051}
17052
17053int loadConP31Node::reloc() const {
17054 return 1;
17055}
17056
17057int loadConFNode::reloc() const {
17058 return 2;
17059}
17060
17061int loadConF0Node::reloc() const {
17062 return 2;
17063}
17064
17065int loadConDNode::reloc() const {
17066 return 2;
17067}
17068
17069int loadConD0Node::reloc() const {
17070 return 2;
17071}
17072
17073int prefetchAllocNode::reloc() const {
17074 return 1;
17075}
17076
17077int prefetchAllocNTANode::reloc() const {
17078 return 1;
17079}
17080
17081int prefetchAllocT0Node::reloc() const {
17082 return 1;
17083}
17084
17085int prefetchAllocT2Node::reloc() const {
17086 return 1;
17087}
17088
17089int storeBNode::reloc() const {
17090 return 2;
17091}
17092
17093int storeCNode::reloc() const {
17094 return 2;
17095}
17096
17097int storeINode::reloc() const {
17098 return 2;
17099}
17100
17101int storeLNode::reloc() const {
17102 return 2;
17103}
17104
17105int storePNode::reloc() const {
17106 return 2;
17107}
17108
17109int storeImmP0Node::reloc() const {
17110 return 3;
17111}
17112
17113int storeImmPNode::reloc() const {
17114 return 3;
17115}
17116
17117int storeNNode::reloc() const {
17118 return 2;
17119}
17120
17121int storeNKlassNode::reloc() const {
17122 return 2;
17123}
17124
17125int storeImmN0Node::reloc() const {
17126 return 2;
17127}
17128
17129int storeImmNNode::reloc() const {
17130 return 2;
17131}
17132
17133int storeImmNKlassNode::reloc() const {
17134 return 2;
17135}
17136
17137int storeImmI0Node::reloc() const {
17138 return 2;
17139}
17140
17141int storeImmINode::reloc() const {
17142 return 2;
17143}
17144
17145int storeImmL0Node::reloc() const {
17146 return 2;
17147}
17148
17149int storeImmLNode::reloc() const {
17150 return 2;
17151}
17152
17153int storeImmC0Node::reloc() const {
17154 return 2;
17155}
17156
17157int storeImmI16Node::reloc() const {
17158 return 2;
17159}
17160
17161int storeImmB0Node::reloc() const {
17162 return 2;
17163}
17164
17165int storeImmBNode::reloc() const {
17166 return 2;
17167}
17168
17169int storeImmCM0_regNode::reloc() const {
17170 return 2;
17171}
17172
17173int storeImmCM0Node::reloc() const {
17174 return 2;
17175}
17176
17177int storeFNode::reloc() const {
17178 return 2;
17179}
17180
17181int storeF0Node::reloc() const {
17182 return 3;
17183}
17184
17185int storeF_immNode::reloc() const {
17186 return 3;
17187}
17188
17189int storeDNode::reloc() const {
17190 return 2;
17191}
17192
17193int storeD0_immNode::reloc() const {
17194 return 3;
17195}
17196
17197int storeD0Node::reloc() const {
17198 return 3;
17199}
17200
17201int popCountI_memNode::reloc() const {
17202 return 1;
17203}
17204
17205int popCountL_memNode::reloc() const {
17206 return 1;
17207}
17208
17209int cmovI_memNode::reloc() const {
17210 return 1;
17211}
17212
17213int cmovI_memUNode::reloc() const {
17214 return 1;
17215}
17216
17217int cmovI_memUCFNode::reloc() const {
17218 return 1;
17219}
17220
17221int cmovL_memNode::reloc() const {
17222 return 1;
17223}
17224
17225int cmovL_memUNode::reloc() const {
17226 return 1;
17227}
17228
17229int cmovL_memUCFNode::reloc() const {
17230 return 1;
17231}
17232
17233int addI_rReg_memNode::reloc() const {
17234 return 1;
17235}
17236
17237int addI_rReg_mem_0Node::reloc() const {
17238 return 1;
17239}
17240
17241int addI_mem_rRegNode::reloc() const {
17242 return 3;
17243}
17244
17245int addI_mem_rReg_0Node::reloc() const {
17246 return 3;
17247}
17248
17249int addI_mem_immNode::reloc() const {
17250 return 3;
17251}
17252
17253int incI_memNode::reloc() const {
17254 return 3;
17255}
17256
17257int decI_memNode::reloc() const {
17258 return 3;
17259}
17260
17261int addL_rReg_memNode::reloc() const {
17262 return 1;
17263}
17264
17265int addL_rReg_mem_0Node::reloc() const {
17266 return 1;
17267}
17268
17269int addL_mem_rRegNode::reloc() const {
17270 return 3;
17271}
17272
17273int addL_mem_rReg_0Node::reloc() const {
17274 return 3;
17275}
17276
17277int addL_mem_immNode::reloc() const {
17278 return 3;
17279}
17280
17281int incL_memNode::reloc() const {
17282 return 3;
17283}
17284
17285int decL_memNode::reloc() const {
17286 return 3;
17287}
17288
17289int loadPLockedNode::reloc() const {
17290 return 1;
17291}
17292
17293int storePConditionalNode::reloc() const {
17294 return 1;
17295}
17296
17297int storeIConditionalNode::reloc() const {
17298 return 1;
17299}
17300
17301int storeLConditionalNode::reloc() const {
17302 return 1;
17303}
17304
17305int compareAndSwapPNode::reloc() const {
17306 return 1;
17307}
17308
17309int compareAndSwapP_0Node::reloc() const {
17310 return 1;
17311}
17312
17313int compareAndSwapLNode::reloc() const {
17314 return 1;
17315}
17316
17317int compareAndSwapL_0Node::reloc() const {
17318 return 1;
17319}
17320
17321int compareAndSwapINode::reloc() const {
17322 return 1;
17323}
17324
17325int compareAndSwapI_0Node::reloc() const {
17326 return 1;
17327}
17328
17329int compareAndSwapBNode::reloc() const {
17330 return 1;
17331}
17332
17333int compareAndSwapB_0Node::reloc() const {
17334 return 1;
17335}
17336
17337int compareAndSwapSNode::reloc() const {
17338 return 1;
17339}
17340
17341int compareAndSwapS_0Node::reloc() const {
17342 return 1;
17343}
17344
17345int compareAndSwapNNode::reloc() const {
17346 return 1;
17347}
17348
17349int compareAndSwapN_0Node::reloc() const {
17350 return 1;
17351}
17352
17353int compareAndExchangeBNode::reloc() const {
17354 return 1;
17355}
17356
17357int compareAndExchangeSNode::reloc() const {
17358 return 1;
17359}
17360
17361int compareAndExchangeINode::reloc() const {
17362 return 1;
17363}
17364
17365int compareAndExchangeLNode::reloc() const {
17366 return 1;
17367}
17368
17369int compareAndExchangeNNode::reloc() const {
17370 return 1;
17371}
17372
17373int compareAndExchangePNode::reloc() const {
17374 return 1;
17375}
17376
17377int xaddB_no_resNode::reloc() const {
17378 return 1;
17379}
17380
17381int xaddBNode::reloc() const {
17382 return 1;
17383}
17384
17385int xaddS_no_resNode::reloc() const {
17386 return 1;
17387}
17388
17389int xaddSNode::reloc() const {
17390 return 1;
17391}
17392
17393int xaddI_no_resNode::reloc() const {
17394 return 1;
17395}
17396
17397int xaddINode::reloc() const {
17398 return 1;
17399}
17400
17401int xaddL_no_resNode::reloc() const {
17402 return 1;
17403}
17404
17405int xaddLNode::reloc() const {
17406 return 1;
17407}
17408
17409int xchgBNode::reloc() const {
17410 return 1;
17411}
17412
17413int xchgSNode::reloc() const {
17414 return 1;
17415}
17416
17417int xchgINode::reloc() const {
17418 return 1;
17419}
17420
17421int xchgLNode::reloc() const {
17422 return 1;
17423}
17424
17425int xchgPNode::reloc() const {
17426 return 1;
17427}
17428
17429int xchgNNode::reloc() const {
17430 return 1;
17431}
17432
17433int subI_rReg_memNode::reloc() const {
17434 return 1;
17435}
17436
17437int subI_mem_rRegNode::reloc() const {
17438 return 3;
17439}
17440
17441int subI_mem_immNode::reloc() const {
17442 return 3;
17443}
17444
17445int subL_rReg_memNode::reloc() const {
17446 return 1;
17447}
17448
17449int subL_mem_rRegNode::reloc() const {
17450 return 3;
17451}
17452
17453int subL_mem_immNode::reloc() const {
17454 return 3;
17455}
17456
17457int negI_memNode::reloc() const {
17458 return 3;
17459}
17460
17461int negL_memNode::reloc() const {
17462 return 3;
17463}
17464
17465int mulI_memNode::reloc() const {
17466 return 1;
17467}
17468
17469int mulI_mem_0Node::reloc() const {
17470 return 1;
17471}
17472
17473int mulI_mem_immNode::reloc() const {
17474 return 1;
17475}
17476
17477int mulL_memNode::reloc() const {
17478 return 1;
17479}
17480
17481int mulL_mem_0Node::reloc() const {
17482 return 1;
17483}
17484
17485int mulL_mem_immNode::reloc() const {
17486 return 1;
17487}
17488
17489int salI_mem_1Node::reloc() const {
17490 return 3;
17491}
17492
17493int salI_mem_immNode::reloc() const {
17494 return 3;
17495}
17496
17497int salI_mem_CLNode::reloc() const {
17498 return 3;
17499}
17500
17501int sarI_mem_1Node::reloc() const {
17502 return 3;
17503}
17504
17505int sarI_mem_immNode::reloc() const {
17506 return 3;
17507}
17508
17509int sarI_mem_CLNode::reloc() const {
17510 return 3;
17511}
17512
17513int shrI_mem_1Node::reloc() const {
17514 return 3;
17515}
17516
17517int shrI_mem_immNode::reloc() const {
17518 return 3;
17519}
17520
17521int shrI_mem_CLNode::reloc() const {
17522 return 3;
17523}
17524
17525int salL_mem_1Node::reloc() const {
17526 return 3;
17527}
17528
17529int salL_mem_immNode::reloc() const {
17530 return 3;
17531}
17532
17533int salL_mem_CLNode::reloc() const {
17534 return 3;
17535}
17536
17537int sarL_mem_1Node::reloc() const {
17538 return 3;
17539}
17540
17541int sarL_mem_immNode::reloc() const {
17542 return 3;
17543}
17544
17545int sarL_mem_CLNode::reloc() const {
17546 return 3;
17547}
17548
17549int shrL_mem_1Node::reloc() const {
17550 return 3;
17551}
17552
17553int shrL_mem_immNode::reloc() const {
17554 return 3;
17555}
17556
17557int shrL_mem_CLNode::reloc() const {
17558 return 3;
17559}
17560
17561int andI_rReg_memNode::reloc() const {
17562 return 1;
17563}
17564
17565int andI_rReg_mem_0Node::reloc() const {
17566 return 1;
17567}
17568
17569int andB_mem_rRegNode::reloc() const {
17570 return 3;
17571}
17572
17573int andB_mem_rReg_0Node::reloc() const {
17574 return 3;
17575}
17576
17577int andI_mem_rRegNode::reloc() const {
17578 return 3;
17579}
17580
17581int andI_mem_rReg_0Node::reloc() const {
17582 return 3;
17583}
17584
17585int andI_mem_immNode::reloc() const {
17586 return 3;
17587}
17588
17589int andnI_rReg_rReg_memNode::reloc() const {
17590 return 1;
17591}
17592
17593int andnI_rReg_rReg_mem_0Node::reloc() const {
17594 return 1;
17595}
17596
17597int blsiI_rReg_memNode::reloc() const {
17598 return 2;
17599}
17600
17601int blsiI_rReg_mem_0Node::reloc() const {
17602 return 2;
17603}
17604
17605int blsmskI_rReg_memNode::reloc() const {
17606 return 2;
17607}
17608
17609int blsmskI_rReg_mem_0Node::reloc() const {
17610 return 2;
17611}
17612
17613int blsrI_rReg_memNode::reloc() const {
17614 return 2;
17615}
17616
17617int blsrI_rReg_mem_0Node::reloc() const {
17618 return 2;
17619}
17620
17621int orI_rReg_memNode::reloc() const {
17622 return 1;
17623}
17624
17625int orI_rReg_mem_0Node::reloc() const {
17626 return 1;
17627}
17628
17629int orB_mem_rRegNode::reloc() const {
17630 return 3;
17631}
17632
17633int orB_mem_rReg_0Node::reloc() const {
17634 return 3;
17635}
17636
17637int orI_mem_rRegNode::reloc() const {
17638 return 3;
17639}
17640
17641int orI_mem_rReg_0Node::reloc() const {
17642 return 3;
17643}
17644
17645int orI_mem_immNode::reloc() const {
17646 return 3;
17647}
17648
17649int xorI_rReg_memNode::reloc() const {
17650 return 1;
17651}
17652
17653int xorI_rReg_mem_0Node::reloc() const {
17654 return 1;
17655}
17656
17657int xorB_mem_rRegNode::reloc() const {
17658 return 3;
17659}
17660
17661int xorB_mem_rReg_0Node::reloc() const {
17662 return 3;
17663}
17664
17665int xorI_mem_rRegNode::reloc() const {
17666 return 3;
17667}
17668
17669int xorI_mem_rReg_0Node::reloc() const {
17670 return 3;
17671}
17672
17673int xorI_mem_immNode::reloc() const {
17674 return 3;
17675}
17676
17677int andL_rReg_memNode::reloc() const {
17678 return 1;
17679}
17680
17681int andL_rReg_mem_0Node::reloc() const {
17682 return 1;
17683}
17684
17685int andL_mem_rRegNode::reloc() const {
17686 return 3;
17687}
17688
17689int andL_mem_rReg_0Node::reloc() const {
17690 return 3;
17691}
17692
17693int andL_mem_immNode::reloc() const {
17694 return 3;
17695}
17696
17697int andnL_rReg_rReg_memNode::reloc() const {
17698 return 1;
17699}
17700
17701int andnL_rReg_rReg_mem_0Node::reloc() const {
17702 return 1;
17703}
17704
17705int blsiL_rReg_memNode::reloc() const {
17706 return 2;
17707}
17708
17709int blsiL_rReg_mem_0Node::reloc() const {
17710 return 2;
17711}
17712
17713int blsmskL_rReg_memNode::reloc() const {
17714 return 2;
17715}
17716
17717int blsmskL_rReg_mem_0Node::reloc() const {
17718 return 2;
17719}
17720
17721int blsrL_rReg_memNode::reloc() const {
17722 return 2;
17723}
17724
17725int blsrL_rReg_mem_0Node::reloc() const {
17726 return 2;
17727}
17728
17729int orL_rReg_memNode::reloc() const {
17730 return 1;
17731}
17732
17733int orL_rReg_mem_0Node::reloc() const {
17734 return 1;
17735}
17736
17737int orL_mem_rRegNode::reloc() const {
17738 return 3;
17739}
17740
17741int orL_mem_rReg_0Node::reloc() const {
17742 return 3;
17743}
17744
17745int orL_mem_immNode::reloc() const {
17746 return 3;
17747}
17748
17749int xorL_rReg_memNode::reloc() const {
17750 return 1;
17751}
17752
17753int xorL_rReg_mem_0Node::reloc() const {
17754 return 1;
17755}
17756
17757int xorL_mem_rRegNode::reloc() const {
17758 return 3;
17759}
17760
17761int xorL_mem_rReg_0Node::reloc() const {
17762 return 3;
17763}
17764
17765int xorL_mem_immNode::reloc() const {
17766 return 3;
17767}
17768
17769int cmpF_cc_memNode::reloc() const {
17770 return 1;
17771}
17772
17773int cmpF_cc_memCFNode::reloc() const {
17774 return 1;
17775}
17776
17777int cmpF_cc_immNode::reloc() const {
17778 return 1;
17779}
17780
17781int cmpF_cc_immCFNode::reloc() const {
17782 return 1;
17783}
17784
17785int cmpD_cc_memNode::reloc() const {
17786 return 1;
17787}
17788
17789int cmpD_cc_memCFNode::reloc() const {
17790 return 1;
17791}
17792
17793int cmpD_cc_immNode::reloc() const {
17794 return 1;
17795}
17796
17797int cmpD_cc_immCFNode::reloc() const {
17798 return 1;
17799}
17800
17801int cmpF_memNode::reloc() const {
17802 return 1;
17803}
17804
17805int cmpF_immNode::reloc() const {
17806 return 1;
17807}
17808
17809int cmpD_memNode::reloc() const {
17810 return 1;
17811}
17812
17813int cmpD_immNode::reloc() const {
17814 return 1;
17815}
17816
17817int convF2D_reg_memNode::reloc() const {
17818 return 1;
17819}
17820
17821int convD2F_reg_memNode::reloc() const {
17822 return 1;
17823}
17824
17825int convI2F_reg_memNode::reloc() const {
17826 return 1;
17827}
17828
17829int convI2D_reg_memNode::reloc() const {
17830 return 1;
17831}
17832
17833int convL2F_reg_memNode::reloc() const {
17834 return 1;
17835}
17836
17837int convL2D_reg_memNode::reloc() const {
17838 return 1;
17839}
17840
17841int convI2L_reg_mem_zexNode::reloc() const {
17842 return 1;
17843}
17844
17845int compI_rReg_memNode::reloc() const {
17846 return 1;
17847}
17848
17849int testI_reg_memNode::reloc() const {
17850 return 1;
17851}
17852
17853int testI_reg_mem_0Node::reloc() const {
17854 return 1;
17855}
17856
17857int compU_rReg_memNode::reloc() const {
17858 return 1;
17859}
17860
17861int compP_rReg_memNode::reloc() const {
17862 return 1;
17863}
17864
17865int compP_mem_rRegNode::reloc() const {
17866 return 1;
17867}
17868
17869int testP_regNode::reloc() const {
17870 return 1;
17871}
17872
17873int testP_memNode::reloc() const {
17874 return 2;
17875}
17876
17877int testP_mem_reg0Node::reloc() const {
17878 return 2;
17879}
17880
17881int compN_rReg_memNode::reloc() const {
17882 return 1;
17883}
17884
17885int compN_mem_immNode::reloc() const {
17886 return 1;
17887}
17888
17889int compN_mem_imm_klassNode::reloc() const {
17890 return 1;
17891}
17892
17893int testN_memNode::reloc() const {
17894 return 1;
17895}
17896
17897int testN_mem_reg0Node::reloc() const {
17898 return 1;
17899}
17900
17901int compL_rReg_memNode::reloc() const {
17902 return 1;
17903}
17904
17905int testL_reg_memNode::reloc() const {
17906 return 1;
17907}
17908
17909int testL_reg_mem_0Node::reloc() const {
17910 return 1;
17911}
17912
17913int testL_reg_mem2Node::reloc() const {
17914 return 1;
17915}
17916
17917int testL_reg_mem2_0Node::reloc() const {
17918 return 1;
17919}
17920
17921int compUL_rReg_memNode::reloc() const {
17922 return 1;
17923}
17924
17925int compB_mem_immNode::reloc() const {
17926 return 1;
17927}
17928
17929int testUB_mem_immNode::reloc() const {
17930 return 1;
17931}
17932
17933int testB_mem_immNode::reloc() const {
17934 return 1;
17935}
17936
17937int partialSubtypeCheck_vs_ZeroNode::reloc() const {
17938 return 1;
17939}
17940
17941int safePoint_pollNode::reloc() const {
17942 return 1;
17943}
17944
17945int safePoint_poll_farNode::reloc() const {
17946 return 1;
17947}
17948
17949int safePoint_poll_tlsNode::reloc() const {
17950 return 1;
17951}
17952
17953int CallStaticJavaDirectNode::reloc() const {
17954 return 1;
17955}
17956
17957int CallDynamicJavaDirectNode::reloc() const {
17958 return 1;
17959}
17960
17961int CallRuntimeDirectNode::reloc() const {
17962 return 1;
17963}
17964
17965int CallLeafDirectNode::reloc() const {
17966 return 1;
17967}
17968
17969int CallLeafNoFPDirectNode::reloc() const {
17970 return 1;
17971}
17972
17973int RetNode::reloc() const {
17974 return 1;
17975}
17976
17977int TailCalljmpIndNode::reloc() const {
17978 return 1;
17979}
17980
17981int tailjmpIndNode::reloc() const {
17982 return 1;
17983}
17984
17985int RethrowExceptionNode::reloc() const {
17986 return 1;
17987}
17988
17989int addF_memNode::reloc() const {
17990 return 1;
17991}
17992
17993int addF_mem_0Node::reloc() const {
17994 return 1;
17995}
17996
17997int addF_immNode::reloc() const {
17998 return 1;
17999}
18000
18001int addF_reg_memNode::reloc() const {
18002 return 1;
18003}
18004
18005int addF_reg_mem_0Node::reloc() const {
18006 return 1;
18007}
18008
18009int addF_reg_immNode::reloc() const {
18010 return 1;
18011}
18012
18013int addD_memNode::reloc() const {
18014 return 1;
18015}
18016
18017int addD_mem_0Node::reloc() const {
18018 return 1;
18019}
18020
18021int addD_immNode::reloc() const {
18022 return 1;
18023}
18024
18025int addD_reg_memNode::reloc() const {
18026 return 1;
18027}
18028
18029int addD_reg_mem_0Node::reloc() const {
18030 return 1;
18031}
18032
18033int addD_reg_immNode::reloc() const {
18034 return 1;
18035}
18036
18037int subF_memNode::reloc() const {
18038 return 1;
18039}
18040
18041int subF_immNode::reloc() const {
18042 return 1;
18043}
18044
18045int subF_reg_memNode::reloc() const {
18046 return 1;
18047}
18048
18049int subF_reg_immNode::reloc() const {
18050 return 1;
18051}
18052
18053int subD_memNode::reloc() const {
18054 return 1;
18055}
18056
18057int subD_immNode::reloc() const {
18058 return 1;
18059}
18060
18061int subD_reg_memNode::reloc() const {
18062 return 1;
18063}
18064
18065int subD_reg_immNode::reloc() const {
18066 return 1;
18067}
18068
18069int mulF_memNode::reloc() const {
18070 return 1;
18071}
18072
18073int mulF_mem_0Node::reloc() const {
18074 return 1;
18075}
18076
18077int mulF_immNode::reloc() const {
18078 return 1;
18079}
18080
18081int mulF_reg_memNode::reloc() const {
18082 return 1;
18083}
18084
18085int mulF_reg_mem_0Node::reloc() const {
18086 return 1;
18087}
18088
18089int mulF_reg_immNode::reloc() const {
18090 return 1;
18091}
18092
18093int mulD_memNode::reloc() const {
18094 return 1;
18095}
18096
18097int mulD_mem_0Node::reloc() const {
18098 return 1;
18099}
18100
18101int mulD_immNode::reloc() const {
18102 return 1;
18103}
18104
18105int mulD_reg_memNode::reloc() const {
18106 return 1;
18107}
18108
18109int mulD_reg_mem_0Node::reloc() const {
18110 return 1;
18111}
18112
18113int mulD_reg_immNode::reloc() const {
18114 return 1;
18115}
18116
18117int divF_memNode::reloc() const {
18118 return 1;
18119}
18120
18121int divF_immNode::reloc() const {
18122 return 1;
18123}
18124
18125int divF_reg_memNode::reloc() const {
18126 return 1;
18127}
18128
18129int divF_reg_immNode::reloc() const {
18130 return 1;
18131}
18132
18133int divD_memNode::reloc() const {
18134 return 1;
18135}
18136
18137int divD_immNode::reloc() const {
18138 return 1;
18139}
18140
18141int divD_reg_memNode::reloc() const {
18142 return 1;
18143}
18144
18145int divD_reg_immNode::reloc() const {
18146 return 1;
18147}
18148
18149int sqrtF_memNode::reloc() const {
18150 return 1;
18151}
18152
18153int sqrtF_immNode::reloc() const {
18154 return 1;
18155}
18156
18157int sqrtD_memNode::reloc() const {
18158 return 1;
18159}
18160
18161int sqrtD_immNode::reloc() const {
18162 return 1;
18163}
18164
18165int loadV4Node::reloc() const {
18166 return 1;
18167}
18168
18169int loadV8Node::reloc() const {
18170 return 1;
18171}
18172
18173int loadV16Node::reloc() const {
18174 return 1;
18175}
18176
18177int loadV32Node::reloc() const {
18178 return 1;
18179}
18180
18181int loadV64_dwordNode::reloc() const {
18182 return 1;
18183}
18184
18185int loadV64_qwordNode::reloc() const {
18186 return 1;
18187}
18188
18189int storeV4Node::reloc() const {
18190 return 2;
18191}
18192
18193int storeV8Node::reloc() const {
18194 return 2;
18195}
18196
18197int storeV16Node::reloc() const {
18198 return 2;
18199}
18200
18201int storeV32Node::reloc() const {
18202 return 2;
18203}
18204
18205int storeV64_dwordNode::reloc() const {
18206 return 2;
18207}
18208
18209int storeV64_qwordNode::reloc() const {
18210 return 2;
18211}
18212
18213int Repl4S_memNode::reloc() const {
18214 return 1;
18215}
18216
18217int Repl8S_memNode::reloc() const {
18218 return 1;
18219}
18220
18221int Repl16S_memNode::reloc() const {
18222 return 1;
18223}
18224
18225int Repl32S_memNode::reloc() const {
18226 return 1;
18227}
18228
18229int Repl4I_memNode::reloc() const {
18230 return 1;
18231}
18232
18233int Repl8I_memNode::reloc() const {
18234 return 1;
18235}
18236
18237int Repl16I_memNode::reloc() const {
18238 return 1;
18239}
18240
18241int Repl2L_memNode::reloc() const {
18242 return 1;
18243}
18244
18245int Repl4L_memNode::reloc() const {
18246 return 1;
18247}
18248
18249int Repl8L_memNode::reloc() const {
18250 return 1;
18251}
18252
18253int Repl2F_memNode::reloc() const {
18254 return 1;
18255}
18256
18257int Repl4F_memNode::reloc() const {
18258 return 1;
18259}
18260
18261int Repl8F_memNode::reloc() const {
18262 return 1;
18263}
18264
18265int Repl16F_memNode::reloc() const {
18266 return 1;
18267}
18268
18269int Repl2F_zeroNode::reloc() const {
18270 return 1;
18271}
18272
18273int Repl4F_zeroNode::reloc() const {
18274 return 1;
18275}
18276
18277int Repl8F_zeroNode::reloc() const {
18278 return 1;
18279}
18280
18281int Repl2D_memNode::reloc() const {
18282 return 1;
18283}
18284
18285int Repl4D_memNode::reloc() const {
18286 return 1;
18287}
18288
18289int Repl8D_memNode::reloc() const {
18290 return 1;
18291}
18292
18293int Repl2D_zeroNode::reloc() const {
18294 return 1;
18295}
18296
18297int Repl4D_zeroNode::reloc() const {
18298 return 1;
18299}
18300
18301int Repl2I_memNode::reloc() const {
18302 return 1;
18303}
18304
18305int Repl4B_mem_evexNode::reloc() const {
18306 return 1;
18307}
18308
18309int Repl8B_mem_evexNode::reloc() const {
18310 return 1;
18311}
18312
18313int Repl16B_mem_evexNode::reloc() const {
18314 return 1;
18315}
18316
18317int Repl32B_mem_evexNode::reloc() const {
18318 return 1;
18319}
18320
18321int Repl64B_mem_evexNode::reloc() const {
18322 return 1;
18323}
18324
18325int Repl4S_mem_evexNode::reloc() const {
18326 return 1;
18327}
18328
18329int Repl8S_mem_evexNode::reloc() const {
18330 return 1;
18331}
18332
18333int Repl16S_mem_evexNode::reloc() const {
18334 return 1;
18335}
18336
18337int Repl32S_mem_evexNode::reloc() const {
18338 return 1;
18339}
18340
18341int Repl4I_mem_evexNode::reloc() const {
18342 return 1;
18343}
18344
18345int Repl8I_mem_evexNode::reloc() const {
18346 return 1;
18347}
18348
18349int Repl16I_mem_evexNode::reloc() const {
18350 return 1;
18351}
18352
18353int Repl2L_mem_evexNode::reloc() const {
18354 return 1;
18355}
18356
18357int Repl4L_mem_evexNode::reloc() const {
18358 return 1;
18359}
18360
18361int Repl8L_mem_evexNode::reloc() const {
18362 return 1;
18363}
18364
18365int Repl8F_mem_evexNode::reloc() const {
18366 return 1;
18367}
18368
18369int Repl16F_mem_evexNode::reloc() const {
18370 return 1;
18371}
18372
18373int Repl2F_zero_evexNode::reloc() const {
18374 return 1;
18375}
18376
18377int Repl4F_zero_evexNode::reloc() const {
18378 return 1;
18379}
18380
18381int Repl8F_zero_evexNode::reloc() const {
18382 return 1;
18383}
18384
18385int Repl16F_zero_evexNode::reloc() const {
18386 return 1;
18387}
18388
18389int Repl4D_mem_evexNode::reloc() const {
18390 return 1;
18391}
18392
18393int Repl8D_mem_evexNode::reloc() const {
18394 return 1;
18395}
18396
18397int Repl2D_zero_evexNode::reloc() const {
18398 return 1;
18399}
18400
18401int Repl4D_zero_evexNode::reloc() const {
18402 return 1;
18403}
18404
18405int Repl8D_zero_evexNode::reloc() const {
18406 return 1;
18407}
18408
18409int vadd4B_memNode::reloc() const {
18410 return 1;
18411}
18412
18413int vadd4B_mem_0Node::reloc() const {
18414 return 1;
18415}
18416
18417int vadd8B_memNode::reloc() const {
18418 return 1;
18419}
18420
18421int vadd8B_mem_0Node::reloc() const {
18422 return 1;
18423}
18424
18425int vadd16B_memNode::reloc() const {
18426 return 1;
18427}
18428
18429int vadd16B_mem_0Node::reloc() const {
18430 return 1;
18431}
18432
18433int vadd32B_memNode::reloc() const {
18434 return 1;
18435}
18436
18437int vadd32B_mem_0Node::reloc() const {
18438 return 1;
18439}
18440
18441int vadd64B_memNode::reloc() const {
18442 return 1;
18443}
18444
18445int vadd64B_mem_0Node::reloc() const {
18446 return 1;
18447}
18448
18449int vadd2S_memNode::reloc() const {
18450 return 1;
18451}
18452
18453int vadd2S_mem_0Node::reloc() const {
18454 return 1;
18455}
18456
18457int vadd4S_memNode::reloc() const {
18458 return 1;
18459}
18460
18461int vadd4S_mem_0Node::reloc() const {
18462 return 1;
18463}
18464
18465int vadd8S_memNode::reloc() const {
18466 return 1;
18467}
18468
18469int vadd8S_mem_0Node::reloc() const {
18470 return 1;
18471}
18472
18473int vadd16S_memNode::reloc() const {
18474 return 1;
18475}
18476
18477int vadd16S_mem_0Node::reloc() const {
18478 return 1;
18479}
18480
18481int vadd32S_memNode::reloc() const {
18482 return 1;
18483}
18484
18485int vadd32S_mem_0Node::reloc() const {
18486 return 1;
18487}
18488
18489int vadd2I_memNode::reloc() const {
18490 return 1;
18491}
18492
18493int vadd2I_mem_0Node::reloc() const {
18494 return 1;
18495}
18496
18497int vadd4I_memNode::reloc() const {
18498 return 1;
18499}
18500
18501int vadd4I_mem_0Node::reloc() const {
18502 return 1;
18503}
18504
18505int vadd8I_memNode::reloc() const {
18506 return 1;
18507}
18508
18509int vadd8I_mem_0Node::reloc() const {
18510 return 1;
18511}
18512
18513int vadd16I_memNode::reloc() const {
18514 return 1;
18515}
18516
18517int vadd16I_mem_0Node::reloc() const {
18518 return 1;
18519}
18520
18521int vadd2L_memNode::reloc() const {
18522 return 1;
18523}
18524
18525int vadd2L_mem_0Node::reloc() const {
18526 return 1;
18527}
18528
18529int vadd4L_memNode::reloc() const {
18530 return 1;
18531}
18532
18533int vadd4L_mem_0Node::reloc() const {
18534 return 1;
18535}
18536
18537int vadd8L_memNode::reloc() const {
18538 return 1;
18539}
18540
18541int vadd8L_mem_0Node::reloc() const {
18542 return 1;
18543}
18544
18545int vadd2F_memNode::reloc() const {
18546 return 1;
18547}
18548
18549int vadd2F_mem_0Node::reloc() const {
18550 return 1;
18551}
18552
18553int vadd4F_memNode::reloc() const {
18554 return 1;
18555}
18556
18557int vadd4F_mem_0Node::reloc() const {
18558 return 1;
18559}
18560
18561int vadd8F_memNode::reloc() const {
18562 return 1;
18563}
18564
18565int vadd8F_mem_0Node::reloc() const {
18566 return 1;
18567}
18568
18569int vadd16F_memNode::reloc() const {
18570 return 1;
18571}
18572
18573int vadd16F_mem_0Node::reloc() const {
18574 return 1;
18575}
18576
18577int vadd2D_memNode::reloc() const {
18578 return 1;
18579}
18580
18581int vadd2D_mem_0Node::reloc() const {
18582 return 1;
18583}
18584
18585int vadd4D_memNode::reloc() const {
18586 return 1;
18587}
18588
18589int vadd4D_mem_0Node::reloc() const {
18590 return 1;
18591}
18592
18593int vadd8D_memNode::reloc() const {
18594 return 1;
18595}
18596
18597int vadd8D_mem_0Node::reloc() const {
18598 return 1;
18599}
18600
18601int vsub4B_memNode::reloc() const {
18602 return 1;
18603}
18604
18605int vsub8B_memNode::reloc() const {
18606 return 1;
18607}
18608
18609int vsub16B_memNode::reloc() const {
18610 return 1;
18611}
18612
18613int vsub32B_memNode::reloc() const {
18614 return 1;
18615}
18616
18617int vsub64B_memNode::reloc() const {
18618 return 1;
18619}
18620
18621int vsub2S_memNode::reloc() const {
18622 return 1;
18623}
18624
18625int vsub4S_memNode::reloc() const {
18626 return 1;
18627}
18628
18629int vsub8S_memNode::reloc() const {
18630 return 1;
18631}
18632
18633int vsub16S_memNode::reloc() const {
18634 return 1;
18635}
18636
18637int vsub32S_memNode::reloc() const {
18638 return 1;
18639}
18640
18641int vsub2I_memNode::reloc() const {
18642 return 1;
18643}
18644
18645int vsub4I_memNode::reloc() const {
18646 return 1;
18647}
18648
18649int vsub8I_memNode::reloc() const {
18650 return 1;
18651}
18652
18653int vsub16I_memNode::reloc() const {
18654 return 1;
18655}
18656
18657int vsub2L_memNode::reloc() const {
18658 return 1;
18659}
18660
18661int vsub4L_memNode::reloc() const {
18662 return 1;
18663}
18664
18665int vsub8L_memNode::reloc() const {
18666 return 1;
18667}
18668
18669int vsub2F_memNode::reloc() const {
18670 return 1;
18671}
18672
18673int vsub4F_memNode::reloc() const {
18674 return 1;
18675}
18676
18677int vsub8F_memNode::reloc() const {
18678 return 1;
18679}
18680
18681int vsub16F_memNode::reloc() const {
18682 return 1;
18683}
18684
18685int vsub2D_memNode::reloc() const {
18686 return 1;
18687}
18688
18689int vsub4D_memNode::reloc() const {
18690 return 1;
18691}
18692
18693int vsub8D_memNode::reloc() const {
18694 return 1;
18695}
18696
18697int vmul2S_memNode::reloc() const {
18698 return 1;
18699}
18700
18701int vmul2S_mem_0Node::reloc() const {
18702 return 1;
18703}
18704
18705int vmul4S_memNode::reloc() const {
18706 return 1;
18707}
18708
18709int vmul4S_mem_0Node::reloc() const {
18710 return 1;
18711}
18712
18713int vmul8S_memNode::reloc() const {
18714 return 1;
18715}
18716
18717int vmul8S_mem_0Node::reloc() const {
18718 return 1;
18719}
18720
18721int vmul16S_memNode::reloc() const {
18722 return 1;
18723}
18724
18725int vmul16S_mem_0Node::reloc() const {
18726 return 1;
18727}
18728
18729int vmul32S_memNode::reloc() const {
18730 return 1;
18731}
18732
18733int vmul32S_mem_0Node::reloc() const {
18734 return 1;
18735}
18736
18737int vmul2I_memNode::reloc() const {
18738 return 1;
18739}
18740
18741int vmul2I_mem_0Node::reloc() const {
18742 return 1;
18743}
18744
18745int vmul4I_memNode::reloc() const {
18746 return 1;
18747}
18748
18749int vmul4I_mem_0Node::reloc() const {
18750 return 1;
18751}
18752
18753int vmul2L_memNode::reloc() const {
18754 return 1;
18755}
18756
18757int vmul2L_mem_0Node::reloc() const {
18758 return 1;
18759}
18760
18761int vmul4L_memNode::reloc() const {
18762 return 1;
18763}
18764
18765int vmul4L_mem_0Node::reloc() const {
18766 return 1;
18767}
18768
18769int vmul8L_memNode::reloc() const {
18770 return 1;
18771}
18772
18773int vmul8L_mem_0Node::reloc() const {
18774 return 1;
18775}
18776
18777int vmul8I_memNode::reloc() const {
18778 return 1;
18779}
18780
18781int vmul8I_mem_0Node::reloc() const {
18782 return 1;
18783}
18784
18785int vmul16I_memNode::reloc() const {
18786 return 1;
18787}
18788
18789int vmul16I_mem_0Node::reloc() const {
18790 return 1;
18791}
18792
18793int vmul2F_memNode::reloc() const {
18794 return 1;
18795}
18796
18797int vmul2F_mem_0Node::reloc() const {
18798 return 1;
18799}
18800
18801int vmul4F_memNode::reloc() const {
18802 return 1;
18803}
18804
18805int vmul4F_mem_0Node::reloc() const {
18806 return 1;
18807}
18808
18809int vmul8F_memNode::reloc() const {
18810 return 1;
18811}
18812
18813int vmul8F_mem_0Node::reloc() const {
18814 return 1;
18815}
18816
18817int vmul16F_memNode::reloc() const {
18818 return 1;
18819}
18820
18821int vmul16F_mem_0Node::reloc() const {
18822 return 1;
18823}
18824
18825int vmul2D_memNode::reloc() const {
18826 return 1;
18827}
18828
18829int vmul2D_mem_0Node::reloc() const {
18830 return 1;
18831}
18832
18833int vmul4D_memNode::reloc() const {
18834 return 1;
18835}
18836
18837int vmul4D_mem_0Node::reloc() const {
18838 return 1;
18839}
18840
18841int vmul8D_memNode::reloc() const {
18842 return 1;
18843}
18844
18845int vmul8D_mem_0Node::reloc() const {
18846 return 1;
18847}
18848
18849int vdiv2F_memNode::reloc() const {
18850 return 1;
18851}
18852
18853int vdiv4F_memNode::reloc() const {
18854 return 1;
18855}
18856
18857int vdiv8F_memNode::reloc() const {
18858 return 1;
18859}
18860
18861int vdiv16F_memNode::reloc() const {
18862 return 1;
18863}
18864
18865int vdiv2D_memNode::reloc() const {
18866 return 1;
18867}
18868
18869int vdiv4D_memNode::reloc() const {
18870 return 1;
18871}
18872
18873int vdiv8D_memNode::reloc() const {
18874 return 1;
18875}
18876
18877int vsqrt2D_memNode::reloc() const {
18878 return 1;
18879}
18880
18881int vsqrt4D_memNode::reloc() const {
18882 return 1;
18883}
18884
18885int vsqrt8D_memNode::reloc() const {
18886 return 1;
18887}
18888
18889int vsqrt2F_memNode::reloc() const {
18890 return 1;
18891}
18892
18893int vsqrt4F_memNode::reloc() const {
18894 return 1;
18895}
18896
18897int vsqrt8F_memNode::reloc() const {
18898 return 1;
18899}
18900
18901int vsqrt16F_memNode::reloc() const {
18902 return 1;
18903}
18904
18905int vand4B_memNode::reloc() const {
18906 return 1;
18907}
18908
18909int vand4B_mem_0Node::reloc() const {
18910 return 1;
18911}
18912
18913int vand8B_memNode::reloc() const {
18914 return 1;
18915}
18916
18917int vand8B_mem_0Node::reloc() const {
18918 return 1;
18919}
18920
18921int vand16B_memNode::reloc() const {
18922 return 1;
18923}
18924
18925int vand16B_mem_0Node::reloc() const {
18926 return 1;
18927}
18928
18929int vand32B_memNode::reloc() const {
18930 return 1;
18931}
18932
18933int vand32B_mem_0Node::reloc() const {
18934 return 1;
18935}
18936
18937int vand64B_memNode::reloc() const {
18938 return 1;
18939}
18940
18941int vand64B_mem_0Node::reloc() const {
18942 return 1;
18943}
18944
18945int vor4B_memNode::reloc() const {
18946 return 1;
18947}
18948
18949int vor4B_mem_0Node::reloc() const {
18950 return 1;
18951}
18952
18953int vor8B_memNode::reloc() const {
18954 return 1;
18955}
18956
18957int vor8B_mem_0Node::reloc() const {
18958 return 1;
18959}
18960
18961int vor16B_memNode::reloc() const {
18962 return 1;
18963}
18964
18965int vor16B_mem_0Node::reloc() const {
18966 return 1;
18967}
18968
18969int vor32B_memNode::reloc() const {
18970 return 1;
18971}
18972
18973int vor32B_mem_0Node::reloc() const {
18974 return 1;
18975}
18976
18977int vor64B_memNode::reloc() const {
18978 return 1;
18979}
18980
18981int vor64B_mem_0Node::reloc() const {
18982 return 1;
18983}
18984
18985int vxor4B_memNode::reloc() const {
18986 return 1;
18987}
18988
18989int vxor4B_mem_0Node::reloc() const {
18990 return 1;
18991}
18992
18993int vxor8B_memNode::reloc() const {
18994 return 1;
18995}
18996
18997int vxor8B_mem_0Node::reloc() const {
18998 return 1;
18999}
19000
19001int vxor16B_memNode::reloc() const {
19002 return 1;
19003}
19004
19005int vxor16B_mem_0Node::reloc() const {
19006 return 1;
19007}
19008
19009int vxor32B_memNode::reloc() const {
19010 return 1;
19011}
19012
19013int vxor32B_mem_0Node::reloc() const {
19014 return 1;
19015}
19016
19017int vxor64B_memNode::reloc() const {
19018 return 1;
19019}
19020
19021int vxor64B_mem_0Node::reloc() const {
19022 return 1;
19023}
19024
19025int vfma2D_memNode::reloc() const {
19026 return 1;
19027}
19028
19029int vfma4D_memNode::reloc() const {
19030 return 1;
19031}
19032
19033int vfma8D_memNode::reloc() const {
19034 return 1;
19035}
19036
19037int vfma4F_memNode::reloc() const {
19038 return 1;
19039}
19040
19041int vfma8F_memNode::reloc() const {
19042 return 1;
19043}
19044
19045int vfma16F_memNode::reloc() const {
19046 return 1;
19047}
19048
19049int compareAndSwapP_shenandoahNode::reloc() const {
19050 return 1;
19051}
19052
19053int compareAndSwapP_shenandoah_0Node::reloc() const {
19054 return 1;
19055}
19056
19057int compareAndSwapN_shenandoahNode::reloc() const {
19058 return 1;
19059}
19060
19061int compareAndSwapN_shenandoah_0Node::reloc() const {
19062 return 1;
19063}
19064
19065int compareAndExchangeN_shenandoahNode::reloc() const {
19066 return 1;
19067}
19068
19069int compareAndExchangeP_shenandoahNode::reloc() const {
19070 return 1;
19071}
19072
19073int zLoadBarrierSlowRegXmmAndYmmNode::reloc() const {
19074 return 1;
19075}
19076
19077int zLoadBarrierSlowRegZmmNode::reloc() const {
19078 return 1;
19079}
19080
19081int zLoadBarrierWeakSlowRegXmmAndYmmNode::reloc() const {
19082 return 1;
19083}
19084
19085int zLoadBarrierWeakSlowRegZmmNode::reloc() const {
19086 return 1;
19087}
19088
19089int z_compareAndExchangePNode::reloc() const {
19090 return 1;
19091}
19092
19093int z_compareAndSwapPNode::reloc() const {
19094 return 1;
19095}
19096
19097int z_compareAndSwapP_0Node::reloc() const {
19098 return 1;
19099}
19100
19101int z_xchgPNode::reloc() const {
19102 return 1;
19103}
19104
19105
19106void loadBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19107 cbuf.set_insts_mark();
19108 // Start at oper_input_base() and count operands
19109 unsigned idx0 = 2;
19110 unsigned idx1 = 2; // mem
19111 {
19112 MacroAssembler _masm(&cbuf);
19113
19114#line 5011 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19115
19116 __ movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19117
19118#line 19118 "ad_x86.cpp"
19119 }
19120}
19121
19122void loadB2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19123 cbuf.set_insts_mark();
19124 // Start at oper_input_base() and count operands
19125 unsigned idx0 = 2;
19126 unsigned idx1 = 2; // mem
19127 {
19128 MacroAssembler _masm(&cbuf);
19129
19130#line 5026 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19131
19132 __ movsbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19133
19134#line 19134 "ad_x86.cpp"
19135 }
19136}
19137
19138void loadUBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19139 cbuf.set_insts_mark();
19140 // Start at oper_input_base() and count operands
19141 unsigned idx0 = 2;
19142 unsigned idx1 = 2; // mem
19143 {
19144 MacroAssembler _masm(&cbuf);
19145
19146#line 5041 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19147
19148 __ movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19149
19150#line 19150 "ad_x86.cpp"
19151 }
19152}
19153
19154void loadUB2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19155 cbuf.set_insts_mark();
19156 // Start at oper_input_base() and count operands
19157 unsigned idx0 = 2;
19158 unsigned idx1 = 2; // mem
19159 {
19160 MacroAssembler _masm(&cbuf);
19161
19162#line 5056 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19163
19164 __ movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19165
19166#line 19166 "ad_x86.cpp"
19167 }
19168}
19169
19170void loadUB2L_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19171 cbuf.set_insts_mark();
19172 // Start at oper_input_base() and count operands
19173 unsigned idx0 = 2;
19174 unsigned idx1 = 2; // mem
19175 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19176 {
19177 MacroAssembler _masm(&cbuf);
19178
19179#line 5070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19180
19181 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
19182 __ movzbq(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19183 __ andl(Rdst, opnd_array(2)->constant()& right_n_bits(8));
19184
19185#line 19185 "ad_x86.cpp"
19186 }
19187}
19188
19189void loadSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19190 cbuf.set_insts_mark();
19191 // Start at oper_input_base() and count operands
19192 unsigned idx0 = 2;
19193 unsigned idx1 = 2; // mem
19194 {
19195 MacroAssembler _masm(&cbuf);
19196
19197#line 5086 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19198
19199 __ movswl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19200
19201#line 19201 "ad_x86.cpp"
19202 }
19203}
19204
19205void loadS2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19206 cbuf.set_insts_mark();
19207 // Start at oper_input_base() and count operands
19208 unsigned idx0 = 2;
19209 unsigned idx1 = 2; // mem
19210 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
19211 {
19212 MacroAssembler _masm(&cbuf);
19213
19214#line 5099 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19215
19216 __ movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19217
19218#line 19218 "ad_x86.cpp"
19219 }
19220}
19221
19222void loadS2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19223 cbuf.set_insts_mark();
19224 // Start at oper_input_base() and count operands
19225 unsigned idx0 = 2;
19226 unsigned idx1 = 2; // mem
19227 {
19228 MacroAssembler _masm(&cbuf);
19229
19230#line 5113 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19231
19232 __ movswq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19233
19234#line 19234 "ad_x86.cpp"
19235 }
19236}
19237
19238void loadUSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19239 cbuf.set_insts_mark();
19240 // Start at oper_input_base() and count operands
19241 unsigned idx0 = 2;
19242 unsigned idx1 = 2; // mem
19243 {
19244 MacroAssembler _masm(&cbuf);
19245
19246#line 5128 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19247
19248 __ movzwl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19249
19250#line 19250 "ad_x86.cpp"
19251 }
19252}
19253
19254void loadUS2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19255 cbuf.set_insts_mark();
19256 // Start at oper_input_base() and count operands
19257 unsigned idx0 = 2;
19258 unsigned idx1 = 2; // mem
19259 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
19260 {
19261 MacroAssembler _masm(&cbuf);
19262
19263#line 5141 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19264
19265 __ movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19266
19267#line 19267 "ad_x86.cpp"
19268 }
19269}
19270
19271void loadUS2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19272 cbuf.set_insts_mark();
19273 // Start at oper_input_base() and count operands
19274 unsigned idx0 = 2;
19275 unsigned idx1 = 2; // mem
19276 {
19277 MacroAssembler _masm(&cbuf);
19278
19279#line 5155 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19280
19281 __ movzwq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19282
19283#line 19283 "ad_x86.cpp"
19284 }
19285}
19286
19287void loadUS2L_immI_255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19288 cbuf.set_insts_mark();
19289 // Start at oper_input_base() and count operands
19290 unsigned idx0 = 2;
19291 unsigned idx1 = 2; // mem
19292 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19293 {
19294 MacroAssembler _masm(&cbuf);
19295
19296#line 5167 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19297
19298 __ movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19299
19300#line 19300 "ad_x86.cpp"
19301 }
19302}
19303
19304void loadUS2L_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19305 cbuf.set_insts_mark();
19306 // Start at oper_input_base() and count operands
19307 unsigned idx0 = 2;
19308 unsigned idx1 = 2; // mem
19309 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19310 {
19311 MacroAssembler _masm(&cbuf);
19312
19313#line 5180 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19314
19315 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
19316 __ movzwq(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19317 __ andl(Rdst, opnd_array(2)->constant()& right_n_bits(16));
19318
19319#line 19319 "ad_x86.cpp"
19320 }
19321}
19322
19323void loadINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19324 cbuf.set_insts_mark();
19325 // Start at oper_input_base() and count operands
19326 unsigned idx0 = 2;
19327 unsigned idx1 = 2; // mem
19328 {
19329 MacroAssembler _masm(&cbuf);
19330
19331#line 5196 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19332
19333 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19334
19335#line 19335 "ad_x86.cpp"
19336 }
19337}
19338
19339void loadI2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19340 cbuf.set_insts_mark();
19341 // Start at oper_input_base() and count operands
19342 unsigned idx0 = 2;
19343 unsigned idx1 = 2; // mem
19344 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
19345 {
19346 MacroAssembler _masm(&cbuf);
19347
19348#line 5209 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19349
19350 __ movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19351
19352#line 19352 "ad_x86.cpp"
19353 }
19354}
19355
19356void loadI2UBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19357 cbuf.set_insts_mark();
19358 // Start at oper_input_base() and count operands
19359 unsigned idx0 = 2;
19360 unsigned idx1 = 2; // mem
19361 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19362 {
19363 MacroAssembler _masm(&cbuf);
19364
19365#line 5221 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19366
19367 __ movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19368
19369#line 19369 "ad_x86.cpp"
19370 }
19371}
19372
19373void loadI2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19374 cbuf.set_insts_mark();
19375 // Start at oper_input_base() and count operands
19376 unsigned idx0 = 2;
19377 unsigned idx1 = 2; // mem
19378 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
19379 {
19380 MacroAssembler _masm(&cbuf);
19381
19382#line 5233 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19383
19384 __ movswl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19385
19386#line 19386 "ad_x86.cpp"
19387 }
19388}
19389
19390void loadI2USNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19391 cbuf.set_insts_mark();
19392 // Start at oper_input_base() and count operands
19393 unsigned idx0 = 2;
19394 unsigned idx1 = 2; // mem
19395 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19396 {
19397 MacroAssembler _masm(&cbuf);
19398
19399#line 5245 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19400
19401 __ movzwl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19402
19403#line 19403 "ad_x86.cpp"
19404 }
19405}
19406
19407void loadI2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19408 cbuf.set_insts_mark();
19409 // Start at oper_input_base() and count operands
19410 unsigned idx0 = 2;
19411 unsigned idx1 = 2; // mem
19412 {
19413 MacroAssembler _masm(&cbuf);
19414
19415#line 5259 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19416
19417 __ movslq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19418
19419#line 19419 "ad_x86.cpp"
19420 }
19421}
19422
19423void loadI2L_immI_255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19424 cbuf.set_insts_mark();
19425 // Start at oper_input_base() and count operands
19426 unsigned idx0 = 2;
19427 unsigned idx1 = 2; // mem
19428 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19429 {
19430 MacroAssembler _masm(&cbuf);
19431
19432#line 5271 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19433
19434 __ movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19435
19436#line 19436 "ad_x86.cpp"
19437 }
19438}
19439
19440void loadI2L_immI_65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19441 cbuf.set_insts_mark();
19442 // Start at oper_input_base() and count operands
19443 unsigned idx0 = 2;
19444 unsigned idx1 = 2; // mem
19445 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19446 {
19447 MacroAssembler _masm(&cbuf);
19448
19449#line 5282 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19450
19451 __ movzwq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19452
19453#line 19453 "ad_x86.cpp"
19454 }
19455}
19456
19457void loadI2L_immU31Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19458 cbuf.set_insts_mark();
19459 // Start at oper_input_base() and count operands
19460 unsigned idx0 = 2;
19461 unsigned idx1 = 2; // mem
19462 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19463 {
19464 MacroAssembler _masm(&cbuf);
19465
19466#line 5295 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19467
19468 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
19469 __ movl(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19470 __ andl(Rdst, opnd_array(2)->constant());
19471
19472#line 19472 "ad_x86.cpp"
19473 }
19474}
19475
19476void loadUI2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19477 cbuf.set_insts_mark();
19478 // Start at oper_input_base() and count operands
19479 unsigned idx0 = 2;
19480 unsigned idx1 = 2; // mem
19481 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19482 {
19483 MacroAssembler _masm(&cbuf);
19484
19485#line 5311 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19486
19487 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19488
19489#line 19489 "ad_x86.cpp"
19490 }
19491}
19492
19493void loadLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19494 cbuf.set_insts_mark();
19495 // Start at oper_input_base() and count operands
19496 unsigned idx0 = 2;
19497 unsigned idx1 = 2; // mem
19498 {
19499 MacroAssembler _masm(&cbuf);
19500
19501#line 5326 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19502
19503 __ movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19504
19505#line 19505 "ad_x86.cpp"
19506 }
19507}
19508
19509void loadRangeNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19510 cbuf.set_insts_mark();
19511 // Start at oper_input_base() and count operands
19512 unsigned idx0 = 2;
19513 unsigned idx1 = 2; // mem
19514 {
19515
19516#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19517
19518 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
19519 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19520 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
19521 emit_opcode(cbuf, Assembler::REX_X);
19522 }
19523 } else {
19524 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19525 emit_opcode(cbuf, Assembler::REX_B);
19526 } else {
19527 emit_opcode(cbuf, Assembler::REX_XB);
19528 }
19529 }
19530 } else {
19531 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19532 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19533 emit_opcode(cbuf, Assembler::REX_R);
19534 } else {
19535 emit_opcode(cbuf, Assembler::REX_RX);
19536 }
19537 } else {
19538 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19539 emit_opcode(cbuf, Assembler::REX_RB);
19540 } else {
19541 emit_opcode(cbuf, Assembler::REX_RXB);
19542 }
19543 }
19544 }
19545
19546#line 19546 "ad_x86.cpp"
19547 }
19548 {
19549
19550#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19551
19552 emit_opcode(cbuf, (0x8B /*primary()*/));
19553
19554#line 19554 "ad_x86.cpp"
19555 }
19556 {
19557
19558#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19559
19560 // High registers handle in encode_RegMem
19561 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
19562 int base = opnd_array(1)->base(ra_,this,idx1);
19563 int index = opnd_array(1)->index(ra_,this,idx1);
19564 int scale = opnd_array(1)->scale();
19565 int disp = opnd_array(1)->disp(ra_,this,idx1);
19566 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
19567
19568 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
19569
19570#line 19570 "ad_x86.cpp"
19571 }
19572}
19573
19574void loadPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19575 cbuf.set_insts_mark();
19576 // Start at oper_input_base() and count operands
19577 unsigned idx0 = 2;
19578 unsigned idx1 = 2; // mem
19579 {
19580
19581#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19582
19583 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
19584 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19585 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19586 emit_opcode(cbuf, Assembler::REX_W);
19587 } else {
19588 emit_opcode(cbuf, Assembler::REX_WX);
19589 }
19590 } else {
19591 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19592 emit_opcode(cbuf, Assembler::REX_WB);
19593 } else {
19594 emit_opcode(cbuf, Assembler::REX_WXB);
19595 }
19596 }
19597 } else {
19598 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19599 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19600 emit_opcode(cbuf, Assembler::REX_WR);
19601 } else {
19602 emit_opcode(cbuf, Assembler::REX_WRX);
19603 }
19604 } else {
19605 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19606 emit_opcode(cbuf, Assembler::REX_WRB);
19607 } else {
19608 emit_opcode(cbuf, Assembler::REX_WRXB);
19609 }
19610 }
19611 }
19612
19613#line 19613 "ad_x86.cpp"
19614 }
19615 {
19616
19617#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19618
19619 emit_opcode(cbuf, (0x8B /*primary()*/));
19620
19621#line 19621 "ad_x86.cpp"
19622 }
19623 {
19624
19625#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19626
19627 // High registers handle in encode_RegMem
19628 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
19629 int base = opnd_array(1)->base(ra_,this,idx1);
19630 int index = opnd_array(1)->index(ra_,this,idx1);
19631 int scale = opnd_array(1)->scale();
19632 int disp = opnd_array(1)->disp(ra_,this,idx1);
19633 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
19634
19635 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
19636
19637#line 19637 "ad_x86.cpp"
19638 }
19639}
19640
19641void loadNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19642 cbuf.set_insts_mark();
19643 // Start at oper_input_base() and count operands
19644 unsigned idx0 = 2;
19645 unsigned idx1 = 2; // mem
19646 {
19647 MacroAssembler _masm(&cbuf);
19648
19649#line 5364 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19650
19651 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19652
19653#line 19653 "ad_x86.cpp"
19654 }
19655}
19656
19657void loadKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19658 cbuf.set_insts_mark();
19659 // Start at oper_input_base() and count operands
19660 unsigned idx0 = 2;
19661 unsigned idx1 = 2; // mem
19662 {
19663
19664#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19665
19666 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
19667 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19668 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19669 emit_opcode(cbuf, Assembler::REX_W);
19670 } else {
19671 emit_opcode(cbuf, Assembler::REX_WX);
19672 }
19673 } else {
19674 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19675 emit_opcode(cbuf, Assembler::REX_WB);
19676 } else {
19677 emit_opcode(cbuf, Assembler::REX_WXB);
19678 }
19679 }
19680 } else {
19681 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19682 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19683 emit_opcode(cbuf, Assembler::REX_WR);
19684 } else {
19685 emit_opcode(cbuf, Assembler::REX_WRX);
19686 }
19687 } else {
19688 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19689 emit_opcode(cbuf, Assembler::REX_WRB);
19690 } else {
19691 emit_opcode(cbuf, Assembler::REX_WRXB);
19692 }
19693 }
19694 }
19695
19696#line 19696 "ad_x86.cpp"
19697 }
19698 {
19699
19700#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19701
19702 emit_opcode(cbuf, (0x8B /*primary()*/));
19703
19704#line 19704 "ad_x86.cpp"
19705 }
19706 {
19707
19708#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19709
19710 // High registers handle in encode_RegMem
19711 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
19712 int base = opnd_array(1)->base(ra_,this,idx1);
19713 int index = opnd_array(1)->index(ra_,this,idx1);
19714 int scale = opnd_array(1)->scale();
19715 int disp = opnd_array(1)->disp(ra_,this,idx1);
19716 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
19717
19718 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
19719
19720#line 19720 "ad_x86.cpp"
19721 }
19722}
19723
19724void loadNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19725 cbuf.set_insts_mark();
19726 // Start at oper_input_base() and count operands
19727 unsigned idx0 = 2;
19728 unsigned idx1 = 2; // mem
19729 {
19730 MacroAssembler _masm(&cbuf);
19731
19732#line 5390 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19733
19734 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19735
19736#line 19736 "ad_x86.cpp"
19737 }
19738}
19739
19740void loadFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19741 cbuf.set_insts_mark();
19742 // Start at oper_input_base() and count operands
19743 unsigned idx0 = 2;
19744 unsigned idx1 = 2; // mem
19745 {
19746 MacroAssembler _masm(&cbuf);
19747
19748#line 5403 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19749
19750 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19751
19752#line 19752 "ad_x86.cpp"
19753 }
19754}
19755
19756void MoveF2VLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19757 cbuf.set_insts_mark();
19758 // Start at oper_input_base() and count operands
19759 unsigned idx0 = 1;
19760 unsigned idx1 = 1; // src
19761 {
19762 MacroAssembler _masm(&cbuf);
19763
19764#line 5413 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19765
19766 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19767
19768#line 19768 "ad_x86.cpp"
19769 }
19770}
19771
19772void MoveF2LEGNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19773 cbuf.set_insts_mark();
19774 // Start at oper_input_base() and count operands
19775 unsigned idx0 = 1;
19776 unsigned idx1 = 1; // src
19777 {
19778 MacroAssembler _masm(&cbuf);
19779
19780#line 5423 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19781
19782 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19783
19784#line 19784 "ad_x86.cpp"
19785 }
19786}
19787
19788void MoveVL2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19789 cbuf.set_insts_mark();
19790 // Start at oper_input_base() and count operands
19791 unsigned idx0 = 1;
19792 unsigned idx1 = 1; // src
19793 {
19794 MacroAssembler _masm(&cbuf);
19795
19796#line 5433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19797
19798 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19799
19800#line 19800 "ad_x86.cpp"
19801 }
19802}
19803
19804void MoveLEG2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19805 cbuf.set_insts_mark();
19806 // Start at oper_input_base() and count operands
19807 unsigned idx0 = 1;
19808 unsigned idx1 = 1; // src
19809 {
19810 MacroAssembler _masm(&cbuf);
19811
19812#line 5443 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19813
19814 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19815
19816#line 19816 "ad_x86.cpp"
19817 }
19818}
19819
19820void loadD_partialNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19821 cbuf.set_insts_mark();
19822 // Start at oper_input_base() and count operands
19823 unsigned idx0 = 2;
19824 unsigned idx1 = 2; // mem
19825 {
19826 MacroAssembler _masm(&cbuf);
19827
19828#line 5457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19829
19830 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19831
19832#line 19832 "ad_x86.cpp"
19833 }
19834}
19835
19836void loadDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19837 cbuf.set_insts_mark();
19838 // Start at oper_input_base() and count operands
19839 unsigned idx0 = 2;
19840 unsigned idx1 = 2; // mem
19841 {
19842 MacroAssembler _masm(&cbuf);
19843
19844#line 5470 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19845
19846 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19847
19848#line 19848 "ad_x86.cpp"
19849 }
19850}
19851
19852void MoveD2VLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19853 cbuf.set_insts_mark();
19854 // Start at oper_input_base() and count operands
19855 unsigned idx0 = 1;
19856 unsigned idx1 = 1; // src
19857 {
19858 MacroAssembler _masm(&cbuf);
19859
19860#line 5480 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19861
19862 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19863
19864#line 19864 "ad_x86.cpp"
19865 }
19866}
19867
19868void MoveD2LEGNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19869 cbuf.set_insts_mark();
19870 // Start at oper_input_base() and count operands
19871 unsigned idx0 = 1;
19872 unsigned idx1 = 1; // src
19873 {
19874 MacroAssembler _masm(&cbuf);
19875
19876#line 5490 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19877
19878 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19879
19880#line 19880 "ad_x86.cpp"
19881 }
19882}
19883
19884void MoveVL2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19885 cbuf.set_insts_mark();
19886 // Start at oper_input_base() and count operands
19887 unsigned idx0 = 1;
19888 unsigned idx1 = 1; // src
19889 {
19890 MacroAssembler _masm(&cbuf);
19891
19892#line 5500 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19893
19894 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19895
19896#line 19896 "ad_x86.cpp"
19897 }
19898}
19899
19900void MoveLEG2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19901 cbuf.set_insts_mark();
19902 // Start at oper_input_base() and count operands
19903 unsigned idx0 = 1;
19904 unsigned idx1 = 1; // src
19905 {
19906 MacroAssembler _masm(&cbuf);
19907
19908#line 5510 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19909
19910 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
19911
19912#line 19912 "ad_x86.cpp"
19913 }
19914}
19915
19916void maxF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19917 cbuf.set_insts_mark();
19918 // Start at oper_input_base() and count operands
19919 unsigned idx0 = 1;
19920 unsigned idx1 = 1; // a
19921 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19922 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19923 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19924 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19925 {
19926 MacroAssembler _masm(&cbuf);
19927
19928#line 5535 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19929
19930 int vector_len = Assembler::AVX_128bit;
19931 __ blendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19932 __ blendvps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19933 __ vmaxss(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19934 __ cmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19935 __ blendvps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19936
19937#line 19937 "ad_x86.cpp"
19938 }
19939}
19940
19941void maxF_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19942 cbuf.set_insts_mark();
19943 // Start at oper_input_base() and count operands
19944 unsigned idx0 = 1;
19945 unsigned idx1 = 1; // a
19946 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19947 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19948 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19949 {
19950 MacroAssembler _masm(&cbuf);
19951
19952#line 5552 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19953
19954 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
19955 false /*min*/, true /*single*/);
19956
19957#line 19957 "ad_x86.cpp"
19958 }
19959}
19960
19961void maxD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19962 cbuf.set_insts_mark();
19963 // Start at oper_input_base() and count operands
19964 unsigned idx0 = 1;
19965 unsigned idx1 = 1; // a
19966 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19967 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19968 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19969 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19970 {
19971 MacroAssembler _masm(&cbuf);
19972
19973#line 5571 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19974
19975 int vector_len = Assembler::AVX_128bit;
19976 __ blendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19977 __ blendvpd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19978 __ vmaxsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19979 __ cmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19980 __ blendvpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19981
19982#line 19982 "ad_x86.cpp"
19983 }
19984}
19985
19986void maxD_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19987 cbuf.set_insts_mark();
19988 // Start at oper_input_base() and count operands
19989 unsigned idx0 = 1;
19990 unsigned idx1 = 1; // a
19991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19992 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19993 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19994 {
19995 MacroAssembler _masm(&cbuf);
19996
19997#line 5588 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
19998
19999 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
20000 false /*min*/, false /*single*/);
20001
20002#line 20002 "ad_x86.cpp"
20003 }
20004}
20005
20006void minF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20007 cbuf.set_insts_mark();
20008 // Start at oper_input_base() and count operands
20009 unsigned idx0 = 1;
20010 unsigned idx1 = 1; // a
20011 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
20012 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
20013 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
20014 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
20015 {
20016 MacroAssembler _masm(&cbuf);
20017
20018#line 5607 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20019
20020 int vector_len = Assembler::AVX_128bit;
20021 __ blendvps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
20022 __ blendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
20023 __ vminss(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
20024 __ cmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
20025 __ blendvps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
20026
20027#line 20027 "ad_x86.cpp"
20028 }
20029}
20030
20031void minF_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20032 cbuf.set_insts_mark();
20033 // Start at oper_input_base() and count operands
20034 unsigned idx0 = 1;
20035 unsigned idx1 = 1; // a
20036 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
20037 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
20038 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
20039 {
20040 MacroAssembler _masm(&cbuf);
20041
20042#line 5624 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20043
20044 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
20045 true /*min*/, true /*single*/);
20046
20047#line 20047 "ad_x86.cpp"
20048 }
20049}
20050
20051void minD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20052 cbuf.set_insts_mark();
20053 // Start at oper_input_base() and count operands
20054 unsigned idx0 = 1;
20055 unsigned idx1 = 1; // a
20056 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
20057 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
20058 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
20059 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
20060 {
20061 MacroAssembler _masm(&cbuf);
20062
20063#line 5643 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20064
20065 int vector_len = Assembler::AVX_128bit;
20066 __ blendvpd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
20067 __ blendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
20068 __ vminsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
20069 __ cmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
20070 __ blendvpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
20071
20072#line 20072 "ad_x86.cpp"
20073 }
20074}
20075
20076void minD_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20077 cbuf.set_insts_mark();
20078 // Start at oper_input_base() and count operands
20079 unsigned idx0 = 1;
20080 unsigned idx1 = 1; // a
20081 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
20082 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
20083 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
20084 {
20085 MacroAssembler _masm(&cbuf);
20086
20087#line 5660 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20088
20089 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
20090 true /*min*/, false /*single*/);
20091
20092#line 20092 "ad_x86.cpp"
20093 }
20094}
20095
20096void leaP8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20097 cbuf.set_insts_mark();
20098 // Start at oper_input_base() and count operands
20099 unsigned idx0 = 2;
20100 unsigned idx1 = 2; // mem
20101 {
20102
20103#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20104
20105 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20106 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20107 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20108 emit_opcode(cbuf, Assembler::REX_W);
20109 } else {
20110 emit_opcode(cbuf, Assembler::REX_WX);
20111 }
20112 } else {
20113 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20114 emit_opcode(cbuf, Assembler::REX_WB);
20115 } else {
20116 emit_opcode(cbuf, Assembler::REX_WXB);
20117 }
20118 }
20119 } else {
20120 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20121 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20122 emit_opcode(cbuf, Assembler::REX_WR);
20123 } else {
20124 emit_opcode(cbuf, Assembler::REX_WRX);
20125 }
20126 } else {
20127 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20128 emit_opcode(cbuf, Assembler::REX_WRB);
20129 } else {
20130 emit_opcode(cbuf, Assembler::REX_WRXB);
20131 }
20132 }
20133 }
20134
20135#line 20135 "ad_x86.cpp"
20136 }
20137 {
20138
20139#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20140
20141 emit_opcode(cbuf, (0x8D /*primary()*/));
20142
20143#line 20143 "ad_x86.cpp"
20144 }
20145 {
20146
20147#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20148
20149 // High registers handle in encode_RegMem
20150 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20151 int base = opnd_array(1)->base(ra_,this,idx1);
20152 int index = opnd_array(1)->index(ra_,this,idx1);
20153 int scale = opnd_array(1)->scale();
20154 int disp = opnd_array(1)->disp(ra_,this,idx1);
20155 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20156
20157 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20158
20159#line 20159 "ad_x86.cpp"
20160 }
20161}
20162
20163void leaP32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20164 cbuf.set_insts_mark();
20165 // Start at oper_input_base() and count operands
20166 unsigned idx0 = 2;
20167 unsigned idx1 = 2; // mem
20168 {
20169
20170#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20171
20172 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20173 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20174 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20175 emit_opcode(cbuf, Assembler::REX_W);
20176 } else {
20177 emit_opcode(cbuf, Assembler::REX_WX);
20178 }
20179 } else {
20180 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20181 emit_opcode(cbuf, Assembler::REX_WB);
20182 } else {
20183 emit_opcode(cbuf, Assembler::REX_WXB);
20184 }
20185 }
20186 } else {
20187 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20188 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20189 emit_opcode(cbuf, Assembler::REX_WR);
20190 } else {
20191 emit_opcode(cbuf, Assembler::REX_WRX);
20192 }
20193 } else {
20194 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20195 emit_opcode(cbuf, Assembler::REX_WRB);
20196 } else {
20197 emit_opcode(cbuf, Assembler::REX_WRXB);
20198 }
20199 }
20200 }
20201
20202#line 20202 "ad_x86.cpp"
20203 }
20204 {
20205
20206#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20207
20208 emit_opcode(cbuf, (0x8D /*primary()*/));
20209
20210#line 20210 "ad_x86.cpp"
20211 }
20212 {
20213
20214#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20215
20216 // High registers handle in encode_RegMem
20217 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20218 int base = opnd_array(1)->base(ra_,this,idx1);
20219 int index = opnd_array(1)->index(ra_,this,idx1);
20220 int scale = opnd_array(1)->scale();
20221 int disp = opnd_array(1)->disp(ra_,this,idx1);
20222 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20223
20224 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20225
20226#line 20226 "ad_x86.cpp"
20227 }
20228}
20229
20230void leaPIdxOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20231 cbuf.set_insts_mark();
20232 // Start at oper_input_base() and count operands
20233 unsigned idx0 = 2;
20234 unsigned idx1 = 2; // mem
20235 {
20236
20237#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20238
20239 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20240 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20241 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20242 emit_opcode(cbuf, Assembler::REX_W);
20243 } else {
20244 emit_opcode(cbuf, Assembler::REX_WX);
20245 }
20246 } else {
20247 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20248 emit_opcode(cbuf, Assembler::REX_WB);
20249 } else {
20250 emit_opcode(cbuf, Assembler::REX_WXB);
20251 }
20252 }
20253 } else {
20254 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20255 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20256 emit_opcode(cbuf, Assembler::REX_WR);
20257 } else {
20258 emit_opcode(cbuf, Assembler::REX_WRX);
20259 }
20260 } else {
20261 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20262 emit_opcode(cbuf, Assembler::REX_WRB);
20263 } else {
20264 emit_opcode(cbuf, Assembler::REX_WRXB);
20265 }
20266 }
20267 }
20268
20269#line 20269 "ad_x86.cpp"
20270 }
20271 {
20272
20273#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20274
20275 emit_opcode(cbuf, (0x8D /*primary()*/));
20276
20277#line 20277 "ad_x86.cpp"
20278 }
20279 {
20280
20281#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20282
20283 // High registers handle in encode_RegMem
20284 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20285 int base = opnd_array(1)->base(ra_,this,idx1);
20286 int index = opnd_array(1)->index(ra_,this,idx1);
20287 int scale = opnd_array(1)->scale();
20288 int disp = opnd_array(1)->disp(ra_,this,idx1);
20289 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20290
20291 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20292
20293#line 20293 "ad_x86.cpp"
20294 }
20295}
20296
20297void leaPIdxScaleNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20298 cbuf.set_insts_mark();
20299 // Start at oper_input_base() and count operands
20300 unsigned idx0 = 2;
20301 unsigned idx1 = 2; // mem
20302 {
20303
20304#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20305
20306 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20307 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20308 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20309 emit_opcode(cbuf, Assembler::REX_W);
20310 } else {
20311 emit_opcode(cbuf, Assembler::REX_WX);
20312 }
20313 } else {
20314 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20315 emit_opcode(cbuf, Assembler::REX_WB);
20316 } else {
20317 emit_opcode(cbuf, Assembler::REX_WXB);
20318 }
20319 }
20320 } else {
20321 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20322 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20323 emit_opcode(cbuf, Assembler::REX_WR);
20324 } else {
20325 emit_opcode(cbuf, Assembler::REX_WRX);
20326 }
20327 } else {
20328 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20329 emit_opcode(cbuf, Assembler::REX_WRB);
20330 } else {
20331 emit_opcode(cbuf, Assembler::REX_WRXB);
20332 }
20333 }
20334 }
20335
20336#line 20336 "ad_x86.cpp"
20337 }
20338 {
20339
20340#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20341
20342 emit_opcode(cbuf, (0x8D /*primary()*/));
20343
20344#line 20344 "ad_x86.cpp"
20345 }
20346 {
20347
20348#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20349
20350 // High registers handle in encode_RegMem
20351 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20352 int base = opnd_array(1)->base(ra_,this,idx1);
20353 int index = opnd_array(1)->index(ra_,this,idx1);
20354 int scale = opnd_array(1)->scale();
20355 int disp = opnd_array(1)->disp(ra_,this,idx1);
20356 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20357
20358 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20359
20360#line 20360 "ad_x86.cpp"
20361 }
20362}
20363
20364void leaPPosIdxScaleNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20365 cbuf.set_insts_mark();
20366 // Start at oper_input_base() and count operands
20367 unsigned idx0 = 2;
20368 unsigned idx1 = 2; // mem
20369 {
20370
20371#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20372
20373 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20374 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20375 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20376 emit_opcode(cbuf, Assembler::REX_W);
20377 } else {
20378 emit_opcode(cbuf, Assembler::REX_WX);
20379 }
20380 } else {
20381 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20382 emit_opcode(cbuf, Assembler::REX_WB);
20383 } else {
20384 emit_opcode(cbuf, Assembler::REX_WXB);
20385 }
20386 }
20387 } else {
20388 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20389 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20390 emit_opcode(cbuf, Assembler::REX_WR);
20391 } else {
20392 emit_opcode(cbuf, Assembler::REX_WRX);
20393 }
20394 } else {
20395 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20396 emit_opcode(cbuf, Assembler::REX_WRB);
20397 } else {
20398 emit_opcode(cbuf, Assembler::REX_WRXB);
20399 }
20400 }
20401 }
20402
20403#line 20403 "ad_x86.cpp"
20404 }
20405 {
20406
20407#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20408
20409 emit_opcode(cbuf, (0x8D /*primary()*/));
20410
20411#line 20411 "ad_x86.cpp"
20412 }
20413 {
20414
20415#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20416
20417 // High registers handle in encode_RegMem
20418 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20419 int base = opnd_array(1)->base(ra_,this,idx1);
20420 int index = opnd_array(1)->index(ra_,this,idx1);
20421 int scale = opnd_array(1)->scale();
20422 int disp = opnd_array(1)->disp(ra_,this,idx1);
20423 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20424
20425 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20426
20427#line 20427 "ad_x86.cpp"
20428 }
20429}
20430
20431void leaPIdxScaleOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20432 cbuf.set_insts_mark();
20433 // Start at oper_input_base() and count operands
20434 unsigned idx0 = 2;
20435 unsigned idx1 = 2; // mem
20436 {
20437
20438#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20439
20440 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20441 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20442 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20443 emit_opcode(cbuf, Assembler::REX_W);
20444 } else {
20445 emit_opcode(cbuf, Assembler::REX_WX);
20446 }
20447 } else {
20448 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20449 emit_opcode(cbuf, Assembler::REX_WB);
20450 } else {
20451 emit_opcode(cbuf, Assembler::REX_WXB);
20452 }
20453 }
20454 } else {
20455 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20456 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20457 emit_opcode(cbuf, Assembler::REX_WR);
20458 } else {
20459 emit_opcode(cbuf, Assembler::REX_WRX);
20460 }
20461 } else {
20462 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20463 emit_opcode(cbuf, Assembler::REX_WRB);
20464 } else {
20465 emit_opcode(cbuf, Assembler::REX_WRXB);
20466 }
20467 }
20468 }
20469
20470#line 20470 "ad_x86.cpp"
20471 }
20472 {
20473
20474#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20475
20476 emit_opcode(cbuf, (0x8D /*primary()*/));
20477
20478#line 20478 "ad_x86.cpp"
20479 }
20480 {
20481
20482#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20483
20484 // High registers handle in encode_RegMem
20485 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20486 int base = opnd_array(1)->base(ra_,this,idx1);
20487 int index = opnd_array(1)->index(ra_,this,idx1);
20488 int scale = opnd_array(1)->scale();
20489 int disp = opnd_array(1)->disp(ra_,this,idx1);
20490 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20491
20492 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20493
20494#line 20494 "ad_x86.cpp"
20495 }
20496}
20497
20498void leaPPosIdxOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20499 cbuf.set_insts_mark();
20500 // Start at oper_input_base() and count operands
20501 unsigned idx0 = 2;
20502 unsigned idx1 = 2; // mem
20503 {
20504
20505#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20506
20507 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20508 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20509 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20510 emit_opcode(cbuf, Assembler::REX_W);
20511 } else {
20512 emit_opcode(cbuf, Assembler::REX_WX);
20513 }
20514 } else {
20515 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20516 emit_opcode(cbuf, Assembler::REX_WB);
20517 } else {
20518 emit_opcode(cbuf, Assembler::REX_WXB);
20519 }
20520 }
20521 } else {
20522 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20523 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20524 emit_opcode(cbuf, Assembler::REX_WR);
20525 } else {
20526 emit_opcode(cbuf, Assembler::REX_WRX);
20527 }
20528 } else {
20529 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20530 emit_opcode(cbuf, Assembler::REX_WRB);
20531 } else {
20532 emit_opcode(cbuf, Assembler::REX_WRXB);
20533 }
20534 }
20535 }
20536
20537#line 20537 "ad_x86.cpp"
20538 }
20539 {
20540
20541#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20542
20543 emit_opcode(cbuf, (0x8D /*primary()*/));
20544
20545#line 20545 "ad_x86.cpp"
20546 }
20547 {
20548
20549#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20550
20551 // High registers handle in encode_RegMem
20552 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20553 int base = opnd_array(1)->base(ra_,this,idx1);
20554 int index = opnd_array(1)->index(ra_,this,idx1);
20555 int scale = opnd_array(1)->scale();
20556 int disp = opnd_array(1)->disp(ra_,this,idx1);
20557 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20558
20559 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20560
20561#line 20561 "ad_x86.cpp"
20562 }
20563}
20564
20565void leaPPosIdxScaleOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20566 cbuf.set_insts_mark();
20567 // Start at oper_input_base() and count operands
20568 unsigned idx0 = 2;
20569 unsigned idx1 = 2; // mem
20570 {
20571
20572#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20573
20574 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20575 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20576 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20577 emit_opcode(cbuf, Assembler::REX_W);
20578 } else {
20579 emit_opcode(cbuf, Assembler::REX_WX);
20580 }
20581 } else {
20582 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20583 emit_opcode(cbuf, Assembler::REX_WB);
20584 } else {
20585 emit_opcode(cbuf, Assembler::REX_WXB);
20586 }
20587 }
20588 } else {
20589 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20590 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20591 emit_opcode(cbuf, Assembler::REX_WR);
20592 } else {
20593 emit_opcode(cbuf, Assembler::REX_WRX);
20594 }
20595 } else {
20596 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20597 emit_opcode(cbuf, Assembler::REX_WRB);
20598 } else {
20599 emit_opcode(cbuf, Assembler::REX_WRXB);
20600 }
20601 }
20602 }
20603
20604#line 20604 "ad_x86.cpp"
20605 }
20606 {
20607
20608#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20609
20610 emit_opcode(cbuf, (0x8D /*primary()*/));
20611
20612#line 20612 "ad_x86.cpp"
20613 }
20614 {
20615
20616#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20617
20618 // High registers handle in encode_RegMem
20619 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20620 int base = opnd_array(1)->base(ra_,this,idx1);
20621 int index = opnd_array(1)->index(ra_,this,idx1);
20622 int scale = opnd_array(1)->scale();
20623 int disp = opnd_array(1)->disp(ra_,this,idx1);
20624 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20625
20626 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20627
20628#line 20628 "ad_x86.cpp"
20629 }
20630}
20631
20632void leaPCompressedOopOffsetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20633 cbuf.set_insts_mark();
20634 // Start at oper_input_base() and count operands
20635 unsigned idx0 = 2;
20636 unsigned idx1 = 2; // mem
20637 {
20638
20639#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20640
20641 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20642 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20643 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20644 emit_opcode(cbuf, Assembler::REX_W);
20645 } else {
20646 emit_opcode(cbuf, Assembler::REX_WX);
20647 }
20648 } else {
20649 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20650 emit_opcode(cbuf, Assembler::REX_WB);
20651 } else {
20652 emit_opcode(cbuf, Assembler::REX_WXB);
20653 }
20654 }
20655 } else {
20656 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20657 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20658 emit_opcode(cbuf, Assembler::REX_WR);
20659 } else {
20660 emit_opcode(cbuf, Assembler::REX_WRX);
20661 }
20662 } else {
20663 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20664 emit_opcode(cbuf, Assembler::REX_WRB);
20665 } else {
20666 emit_opcode(cbuf, Assembler::REX_WRXB);
20667 }
20668 }
20669 }
20670
20671#line 20671 "ad_x86.cpp"
20672 }
20673 {
20674
20675#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20676
20677 emit_opcode(cbuf, (0x8D /*primary()*/));
20678
20679#line 20679 "ad_x86.cpp"
20680 }
20681 {
20682
20683#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20684
20685 // High registers handle in encode_RegMem
20686 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20687 int base = opnd_array(1)->base(ra_,this,idx1);
20688 int index = opnd_array(1)->index(ra_,this,idx1);
20689 int scale = opnd_array(1)->scale();
20690 int disp = opnd_array(1)->disp(ra_,this,idx1);
20691 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20692
20693 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20694
20695#line 20695 "ad_x86.cpp"
20696 }
20697}
20698
20699void leaP8NarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20700 cbuf.set_insts_mark();
20701 // Start at oper_input_base() and count operands
20702 unsigned idx0 = 2;
20703 unsigned idx1 = 2; // mem
20704 {
20705
20706#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20707
20708 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20709 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20710 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20711 emit_opcode(cbuf, Assembler::REX_W);
20712 } else {
20713 emit_opcode(cbuf, Assembler::REX_WX);
20714 }
20715 } else {
20716 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20717 emit_opcode(cbuf, Assembler::REX_WB);
20718 } else {
20719 emit_opcode(cbuf, Assembler::REX_WXB);
20720 }
20721 }
20722 } else {
20723 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20724 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20725 emit_opcode(cbuf, Assembler::REX_WR);
20726 } else {
20727 emit_opcode(cbuf, Assembler::REX_WRX);
20728 }
20729 } else {
20730 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20731 emit_opcode(cbuf, Assembler::REX_WRB);
20732 } else {
20733 emit_opcode(cbuf, Assembler::REX_WRXB);
20734 }
20735 }
20736 }
20737
20738#line 20738 "ad_x86.cpp"
20739 }
20740 {
20741
20742#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20743
20744 emit_opcode(cbuf, (0x8D /*primary()*/));
20745
20746#line 20746 "ad_x86.cpp"
20747 }
20748 {
20749
20750#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20751
20752 // High registers handle in encode_RegMem
20753 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20754 int base = opnd_array(1)->base(ra_,this,idx1);
20755 int index = opnd_array(1)->index(ra_,this,idx1);
20756 int scale = opnd_array(1)->scale();
20757 int disp = opnd_array(1)->disp(ra_,this,idx1);
20758 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20759
20760 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20761
20762#line 20762 "ad_x86.cpp"
20763 }
20764}
20765
20766void leaP32NarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20767 cbuf.set_insts_mark();
20768 // Start at oper_input_base() and count operands
20769 unsigned idx0 = 2;
20770 unsigned idx1 = 2; // mem
20771 {
20772
20773#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20774
20775 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20776 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20777 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20778 emit_opcode(cbuf, Assembler::REX_W);
20779 } else {
20780 emit_opcode(cbuf, Assembler::REX_WX);
20781 }
20782 } else {
20783 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20784 emit_opcode(cbuf, Assembler::REX_WB);
20785 } else {
20786 emit_opcode(cbuf, Assembler::REX_WXB);
20787 }
20788 }
20789 } else {
20790 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20791 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20792 emit_opcode(cbuf, Assembler::REX_WR);
20793 } else {
20794 emit_opcode(cbuf, Assembler::REX_WRX);
20795 }
20796 } else {
20797 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20798 emit_opcode(cbuf, Assembler::REX_WRB);
20799 } else {
20800 emit_opcode(cbuf, Assembler::REX_WRXB);
20801 }
20802 }
20803 }
20804
20805#line 20805 "ad_x86.cpp"
20806 }
20807 {
20808
20809#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20810
20811 emit_opcode(cbuf, (0x8D /*primary()*/));
20812
20813#line 20813 "ad_x86.cpp"
20814 }
20815 {
20816
20817#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20818
20819 // High registers handle in encode_RegMem
20820 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20821 int base = opnd_array(1)->base(ra_,this,idx1);
20822 int index = opnd_array(1)->index(ra_,this,idx1);
20823 int scale = opnd_array(1)->scale();
20824 int disp = opnd_array(1)->disp(ra_,this,idx1);
20825 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20826
20827 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20828
20829#line 20829 "ad_x86.cpp"
20830 }
20831}
20832
20833void leaPIdxOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20834 cbuf.set_insts_mark();
20835 // Start at oper_input_base() and count operands
20836 unsigned idx0 = 2;
20837 unsigned idx1 = 2; // mem
20838 {
20839
20840#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20841
20842 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20843 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20844 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20845 emit_opcode(cbuf, Assembler::REX_W);
20846 } else {
20847 emit_opcode(cbuf, Assembler::REX_WX);
20848 }
20849 } else {
20850 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20851 emit_opcode(cbuf, Assembler::REX_WB);
20852 } else {
20853 emit_opcode(cbuf, Assembler::REX_WXB);
20854 }
20855 }
20856 } else {
20857 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20858 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20859 emit_opcode(cbuf, Assembler::REX_WR);
20860 } else {
20861 emit_opcode(cbuf, Assembler::REX_WRX);
20862 }
20863 } else {
20864 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20865 emit_opcode(cbuf, Assembler::REX_WRB);
20866 } else {
20867 emit_opcode(cbuf, Assembler::REX_WRXB);
20868 }
20869 }
20870 }
20871
20872#line 20872 "ad_x86.cpp"
20873 }
20874 {
20875
20876#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20877
20878 emit_opcode(cbuf, (0x8D /*primary()*/));
20879
20880#line 20880 "ad_x86.cpp"
20881 }
20882 {
20883
20884#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20885
20886 // High registers handle in encode_RegMem
20887 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20888 int base = opnd_array(1)->base(ra_,this,idx1);
20889 int index = opnd_array(1)->index(ra_,this,idx1);
20890 int scale = opnd_array(1)->scale();
20891 int disp = opnd_array(1)->disp(ra_,this,idx1);
20892 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20893
20894 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20895
20896#line 20896 "ad_x86.cpp"
20897 }
20898}
20899
20900void leaPIdxScaleNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20901 cbuf.set_insts_mark();
20902 // Start at oper_input_base() and count operands
20903 unsigned idx0 = 2;
20904 unsigned idx1 = 2; // mem
20905 {
20906
20907#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20908
20909 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20910 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20911 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20912 emit_opcode(cbuf, Assembler::REX_W);
20913 } else {
20914 emit_opcode(cbuf, Assembler::REX_WX);
20915 }
20916 } else {
20917 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20918 emit_opcode(cbuf, Assembler::REX_WB);
20919 } else {
20920 emit_opcode(cbuf, Assembler::REX_WXB);
20921 }
20922 }
20923 } else {
20924 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20925 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20926 emit_opcode(cbuf, Assembler::REX_WR);
20927 } else {
20928 emit_opcode(cbuf, Assembler::REX_WRX);
20929 }
20930 } else {
20931 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20932 emit_opcode(cbuf, Assembler::REX_WRB);
20933 } else {
20934 emit_opcode(cbuf, Assembler::REX_WRXB);
20935 }
20936 }
20937 }
20938
20939#line 20939 "ad_x86.cpp"
20940 }
20941 {
20942
20943#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20944
20945 emit_opcode(cbuf, (0x8D /*primary()*/));
20946
20947#line 20947 "ad_x86.cpp"
20948 }
20949 {
20950
20951#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20952
20953 // High registers handle in encode_RegMem
20954 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20955 int base = opnd_array(1)->base(ra_,this,idx1);
20956 int index = opnd_array(1)->index(ra_,this,idx1);
20957 int scale = opnd_array(1)->scale();
20958 int disp = opnd_array(1)->disp(ra_,this,idx1);
20959 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20960
20961 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20962
20963#line 20963 "ad_x86.cpp"
20964 }
20965}
20966
20967void leaPIdxScaleOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20968 cbuf.set_insts_mark();
20969 // Start at oper_input_base() and count operands
20970 unsigned idx0 = 2;
20971 unsigned idx1 = 2; // mem
20972 {
20973
20974#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
20975
20976 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20977 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20978 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20979 emit_opcode(cbuf, Assembler::REX_W);
20980 } else {
20981 emit_opcode(cbuf, Assembler::REX_WX);
20982 }
20983 } else {
20984 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20985 emit_opcode(cbuf, Assembler::REX_WB);
20986 } else {
20987 emit_opcode(cbuf, Assembler::REX_WXB);
20988 }
20989 }
20990 } else {
20991 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20992 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20993 emit_opcode(cbuf, Assembler::REX_WR);
20994 } else {
20995 emit_opcode(cbuf, Assembler::REX_WRX);
20996 }
20997 } else {
20998 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20999 emit_opcode(cbuf, Assembler::REX_WRB);
21000 } else {
21001 emit_opcode(cbuf, Assembler::REX_WRXB);
21002 }
21003 }
21004 }
21005
21006#line 21006 "ad_x86.cpp"
21007 }
21008 {
21009
21010#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21011
21012 emit_opcode(cbuf, (0x8D /*primary()*/));
21013
21014#line 21014 "ad_x86.cpp"
21015 }
21016 {
21017
21018#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21019
21020 // High registers handle in encode_RegMem
21021 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21022 int base = opnd_array(1)->base(ra_,this,idx1);
21023 int index = opnd_array(1)->index(ra_,this,idx1);
21024 int scale = opnd_array(1)->scale();
21025 int disp = opnd_array(1)->disp(ra_,this,idx1);
21026 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21027
21028 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21029
21030#line 21030 "ad_x86.cpp"
21031 }
21032}
21033
21034void leaPPosIdxOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21035 cbuf.set_insts_mark();
21036 // Start at oper_input_base() and count operands
21037 unsigned idx0 = 2;
21038 unsigned idx1 = 2; // mem
21039 {
21040
21041#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21042
21043 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21044 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21045 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21046 emit_opcode(cbuf, Assembler::REX_W);
21047 } else {
21048 emit_opcode(cbuf, Assembler::REX_WX);
21049 }
21050 } else {
21051 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21052 emit_opcode(cbuf, Assembler::REX_WB);
21053 } else {
21054 emit_opcode(cbuf, Assembler::REX_WXB);
21055 }
21056 }
21057 } else {
21058 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21059 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21060 emit_opcode(cbuf, Assembler::REX_WR);
21061 } else {
21062 emit_opcode(cbuf, Assembler::REX_WRX);
21063 }
21064 } else {
21065 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21066 emit_opcode(cbuf, Assembler::REX_WRB);
21067 } else {
21068 emit_opcode(cbuf, Assembler::REX_WRXB);
21069 }
21070 }
21071 }
21072
21073#line 21073 "ad_x86.cpp"
21074 }
21075 {
21076
21077#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21078
21079 emit_opcode(cbuf, (0x8D /*primary()*/));
21080
21081#line 21081 "ad_x86.cpp"
21082 }
21083 {
21084
21085#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21086
21087 // High registers handle in encode_RegMem
21088 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21089 int base = opnd_array(1)->base(ra_,this,idx1);
21090 int index = opnd_array(1)->index(ra_,this,idx1);
21091 int scale = opnd_array(1)->scale();
21092 int disp = opnd_array(1)->disp(ra_,this,idx1);
21093 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21094
21095 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21096
21097#line 21097 "ad_x86.cpp"
21098 }
21099}
21100
21101void leaPPosIdxScaleOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21102 cbuf.set_insts_mark();
21103 // Start at oper_input_base() and count operands
21104 unsigned idx0 = 2;
21105 unsigned idx1 = 2; // mem
21106 {
21107
21108#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21109
21110 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21111 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21112 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21113 emit_opcode(cbuf, Assembler::REX_W);
21114 } else {
21115 emit_opcode(cbuf, Assembler::REX_WX);
21116 }
21117 } else {
21118 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21119 emit_opcode(cbuf, Assembler::REX_WB);
21120 } else {
21121 emit_opcode(cbuf, Assembler::REX_WXB);
21122 }
21123 }
21124 } else {
21125 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21126 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21127 emit_opcode(cbuf, Assembler::REX_WR);
21128 } else {
21129 emit_opcode(cbuf, Assembler::REX_WRX);
21130 }
21131 } else {
21132 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21133 emit_opcode(cbuf, Assembler::REX_WRB);
21134 } else {
21135 emit_opcode(cbuf, Assembler::REX_WRXB);
21136 }
21137 }
21138 }
21139
21140#line 21140 "ad_x86.cpp"
21141 }
21142 {
21143
21144#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21145
21146 emit_opcode(cbuf, (0x8D /*primary()*/));
21147
21148#line 21148 "ad_x86.cpp"
21149 }
21150 {
21151
21152#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21153
21154 // High registers handle in encode_RegMem
21155 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21156 int base = opnd_array(1)->base(ra_,this,idx1);
21157 int index = opnd_array(1)->index(ra_,this,idx1);
21158 int scale = opnd_array(1)->scale();
21159 int disp = opnd_array(1)->disp(ra_,this,idx1);
21160 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21161
21162 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21163
21164#line 21164 "ad_x86.cpp"
21165 }
21166}
21167
21168void loadConINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21169 cbuf.set_insts_mark();
21170 // Start at oper_input_base() and count operands
21171 unsigned idx0 = 1;
21172 unsigned idx1 = 1; // src
21173 {
21174
21175#line 2219 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21176
21177 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21178 if (dstenc >= 8) {
21179 emit_opcode(cbuf, Assembler::REX_B);
21180 dstenc -= 8;
21181 }
21182 emit_opcode(cbuf, 0xB8 | dstenc);
21183 emit_d32(cbuf, opnd_array(1)->constant());
21184
21185#line 21185 "ad_x86.cpp"
21186 }
21187}
21188
21189void loadConI0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21190 cbuf.set_insts_mark();
21191 // Start at oper_input_base() and count operands
21192 unsigned idx0 = 1;
21193 unsigned idx1 = 1; // src
21194 {
21195
21196#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21197
21198 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21199 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 8) {
21200 emit_opcode(cbuf, Assembler::REX_B);
21201 }
21202 } else {
21203 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21204 emit_opcode(cbuf, Assembler::REX_R);
21205 } else {
21206 emit_opcode(cbuf, Assembler::REX_RB);
21207 }
21208 }
21209
21210#line 21210 "ad_x86.cpp"
21211 }
21212 {
21213
21214#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21215
21216 emit_opcode(cbuf, (0x33 /*primary()*/));
21217
21218#line 21218 "ad_x86.cpp"
21219 }
21220 {
21221
21222#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21223
21224 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
21225
21226#line 21226 "ad_x86.cpp"
21227 }
21228}
21229
21230void loadConLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21231 cbuf.set_insts_mark();
21232 // Start at oper_input_base() and count operands
21233 unsigned idx0 = 1;
21234 unsigned idx1 = 1; // src
21235 {
21236
21237#line 2230 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21238
21239 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21240 if (dstenc < 8) {
21241 emit_opcode(cbuf, Assembler::REX_W);
21242 } else {
21243 emit_opcode(cbuf, Assembler::REX_WB);
21244 dstenc -= 8;
21245 }
21246 emit_opcode(cbuf, 0xB8 | dstenc);
21247 emit_d64(cbuf, opnd_array(1)->constantL());
21248
21249#line 21249 "ad_x86.cpp"
21250 }
21251}
21252
21253void loadConL0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21254 cbuf.set_insts_mark();
21255 // Start at oper_input_base() and count operands
21256 unsigned idx0 = 1;
21257 unsigned idx1 = 1; // src
21258 {
21259
21260#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21261
21262 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21263 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 8) {
21264 emit_opcode(cbuf, Assembler::REX_B);
21265 }
21266 } else {
21267 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21268 emit_opcode(cbuf, Assembler::REX_R);
21269 } else {
21270 emit_opcode(cbuf, Assembler::REX_RB);
21271 }
21272 }
21273
21274#line 21274 "ad_x86.cpp"
21275 }
21276 {
21277
21278#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21279
21280 emit_opcode(cbuf, (0x33 /*primary()*/));
21281
21282#line 21282 "ad_x86.cpp"
21283 }
21284 {
21285
21286#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21287
21288 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
21289
21290#line 21290 "ad_x86.cpp"
21291 }
21292}
21293
21294void loadConUL32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21295 cbuf.set_insts_mark();
21296 // Start at oper_input_base() and count operands
21297 unsigned idx0 = 1;
21298 unsigned idx1 = 1; // src
21299 {
21300
21301#line 2243 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21302
21303 // same as load_immI, but this time we care about zeroes in the high word
21304 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21305 if (dstenc >= 8) {
21306 emit_opcode(cbuf, Assembler::REX_B);
21307 dstenc -= 8;
21308 }
21309 emit_opcode(cbuf, 0xB8 | dstenc);
21310 emit_d32(cbuf, opnd_array(1)->constantL());
21311
21312#line 21312 "ad_x86.cpp"
21313 }
21314}
21315
21316void loadConL32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21317 cbuf.set_insts_mark();
21318 // Start at oper_input_base() and count operands
21319 unsigned idx0 = 1;
21320 unsigned idx1 = 1; // src
21321 {
21322
21323#line 2255 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21324
21325 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21326 if (dstenc < 8) {
21327 emit_opcode(cbuf, Assembler::REX_W);
21328 } else {
21329 emit_opcode(cbuf, Assembler::REX_WB);
21330 dstenc -= 8;
21331 }
21332 emit_opcode(cbuf, 0xC7);
21333 emit_rm(cbuf, 0x03, 0x00, dstenc);
21334 emit_d32(cbuf, opnd_array(1)->constantL());
21335
21336#line 21336 "ad_x86.cpp"
21337 }
21338}
21339
21340void loadConPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21341 cbuf.set_insts_mark();
21342 // Start at oper_input_base() and count operands
21343 unsigned idx0 = 1;
21344 unsigned idx1 = 1; // con
21345 {
21346
21347#line 2281 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21348
21349 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21350 if (dstenc < 8) {
21351 emit_opcode(cbuf, Assembler::REX_W);
21352 } else {
21353 emit_opcode(cbuf, Assembler::REX_WB);
21354 dstenc -= 8;
21355 }
21356 emit_opcode(cbuf, 0xB8 | dstenc);
21357 // This next line should be generated from ADLC
21358 if (opnd_array(1)->constant_reloc() != relocInfo::none) {
21359 emit_d64_reloc(cbuf, opnd_array(1)->constant(), opnd_array(1)->constant_reloc(), RELOC_IMM64);
21360 } else {
21361 emit_d64(cbuf, opnd_array(1)->constant());
21362 }
21363
21364#line 21364 "ad_x86.cpp"
21365 }
21366}
21367
21368void loadConP0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21369 cbuf.set_insts_mark();
21370 // Start at oper_input_base() and count operands
21371 unsigned idx0 = 1;
21372 unsigned idx1 = 1; // src
21373 {
21374
21375#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21376
21377 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21378 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 8) {
21379 emit_opcode(cbuf, Assembler::REX_B);
21380 }
21381 } else {
21382 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21383 emit_opcode(cbuf, Assembler::REX_R);
21384 } else {
21385 emit_opcode(cbuf, Assembler::REX_RB);
21386 }
21387 }
21388
21389#line 21389 "ad_x86.cpp"
21390 }
21391 {
21392
21393#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21394
21395 emit_opcode(cbuf, (0x33 /*primary()*/));
21396
21397#line 21397 "ad_x86.cpp"
21398 }
21399 {
21400
21401#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21402
21403 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
21404
21405#line 21405 "ad_x86.cpp"
21406 }
21407}
21408
21409void loadConP31Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21410 cbuf.set_insts_mark();
21411 // Start at oper_input_base() and count operands
21412 unsigned idx0 = 1;
21413 unsigned idx1 = 1; // src
21414 {
21415
21416#line 2269 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21417
21418 // same as load_immI, but this time we care about zeroes in the high word
21419 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
21420 if (dstenc >= 8) {
21421 emit_opcode(cbuf, Assembler::REX_B);
21422 dstenc -= 8;
21423 }
21424 emit_opcode(cbuf, 0xB8 | dstenc);
21425
21426if ( opnd_array(1)->constant_reloc() != relocInfo::none ) {
21427 emit_d32_reloc(cbuf, opnd_array(1)->constant(), opnd_array(1)->constant_reloc(), 0);
21428} else {
21429 emit_d32(cbuf, opnd_array(1)->constant());
21430};
21431
21432#line 21432 "ad_x86.cpp"
21433 }
21434}
21435
21436void loadConFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21437 cbuf.set_insts_mark();
21438 // Start at oper_input_base() and count operands
21439 unsigned idx0 = 1;
21440 unsigned idx1 = 1; // con
21441 {
21442 MacroAssembler _masm(&cbuf);
21443
21444#line 5962 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21445
21446 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
21447
21448#line 21448 "ad_x86.cpp"
21449 }
21450}
21451
21452void loadConFNode::eval_constant(Compile* C) {
21453 {
21454
21455#line 5963 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21456 _constant = C->constant_table().add(this, opnd_array(1));
21457#line 21457 "ad_x86.cpp"
21458 }
21459}
21460void loadConN0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21461 cbuf.set_insts_mark();
21462 // Start at oper_input_base() and count operands
21463 unsigned idx0 = 1;
21464 unsigned idx1 = 1; // src
21465 {
21466 MacroAssembler _masm(&cbuf);
21467
21468#line 5972 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21469
21470 __ xorq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
21471
21472#line 21472 "ad_x86.cpp"
21473 }
21474}
21475
21476void loadConNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21477 cbuf.set_insts_mark();
21478 // Start at oper_input_base() and count operands
21479 unsigned idx0 = 1;
21480 unsigned idx1 = 1; // src
21481 {
21482 MacroAssembler _masm(&cbuf);
21483
21484#line 5983 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21485
21486 address con = (address)opnd_array(1)->constant();
21487 if (con == NULL) {
21488 ShouldNotReachHere();
21489 } else {
21490 __ set_narrow_oop(opnd_array(0)->as_Register(ra_,this)/* dst */, (jobject)opnd_array(1)->constant());
21491 }
21492
21493#line 21493 "ad_x86.cpp"
21494 }
21495}
21496
21497void loadConNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21498 cbuf.set_insts_mark();
21499 // Start at oper_input_base() and count operands
21500 unsigned idx0 = 1;
21501 unsigned idx1 = 1; // src
21502 {
21503 MacroAssembler _masm(&cbuf);
21504
21505#line 5999 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21506
21507 address con = (address)opnd_array(1)->constant();
21508 if (con == NULL) {
21509 ShouldNotReachHere();
21510 } else {
21511 __ set_narrow_klass(opnd_array(0)->as_Register(ra_,this)/* dst */, (Klass*)opnd_array(1)->constant());
21512 }
21513
21514#line 21514 "ad_x86.cpp"
21515 }
21516}
21517
21518void loadConF0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21519 cbuf.set_insts_mark();
21520 // Start at oper_input_base() and count operands
21521 unsigned idx0 = 1;
21522 unsigned idx1 = 1; // src
21523 {
21524 MacroAssembler _masm(&cbuf);
21525
21526#line 6016 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21527
21528 __ xorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
21529
21530#line 21530 "ad_x86.cpp"
21531 }
21532}
21533
21534void loadConDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21535 cbuf.set_insts_mark();
21536 // Start at oper_input_base() and count operands
21537 unsigned idx0 = 1;
21538 unsigned idx1 = 1; // con
21539 {
21540 MacroAssembler _masm(&cbuf);
21541
21542#line 6027 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21543
21544 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
21545
21546#line 21546 "ad_x86.cpp"
21547 }
21548}
21549
21550void loadConDNode::eval_constant(Compile* C) {
21551 {
21552
21553#line 6028 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21554 _constant = C->constant_table().add(this, opnd_array(1));
21555#line 21555 "ad_x86.cpp"
21556 }
21557}
21558void loadConD0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21559 cbuf.set_insts_mark();
21560 // Start at oper_input_base() and count operands
21561 unsigned idx0 = 1;
21562 unsigned idx1 = 1; // src
21563 {
21564 MacroAssembler _masm(&cbuf);
21565
21566#line 6039 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21567
21568 __ xorpd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
21569
21570#line 21570 "ad_x86.cpp"
21571 }
21572}
21573
21574void loadSSINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21575 cbuf.set_insts_mark();
21576 // Start at oper_input_base() and count operands
21577 unsigned idx0 = 1;
21578 unsigned idx1 = 1; // src
21579 {
21580
21581#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21582
21583 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21584 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21585 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
21586 emit_opcode(cbuf, Assembler::REX_X);
21587 }
21588 } else {
21589 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21590 emit_opcode(cbuf, Assembler::REX_B);
21591 } else {
21592 emit_opcode(cbuf, Assembler::REX_XB);
21593 }
21594 }
21595 } else {
21596 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21597 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21598 emit_opcode(cbuf, Assembler::REX_R);
21599 } else {
21600 emit_opcode(cbuf, Assembler::REX_RX);
21601 }
21602 } else {
21603 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21604 emit_opcode(cbuf, Assembler::REX_RB);
21605 } else {
21606 emit_opcode(cbuf, Assembler::REX_RXB);
21607 }
21608 }
21609 }
21610
21611#line 21611 "ad_x86.cpp"
21612 }
21613 {
21614
21615#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21616
21617 emit_opcode(cbuf, (0x8B /*primary()*/));
21618
21619#line 21619 "ad_x86.cpp"
21620 }
21621 {
21622
21623#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21624
21625 // High registers handle in encode_RegMem
21626 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21627 int base = opnd_array(1)->base(ra_,this,idx1);
21628 int index = opnd_array(1)->index(ra_,this,idx1);
21629 int scale = opnd_array(1)->scale();
21630 int disp = opnd_array(1)->disp(ra_,this,idx1);
21631 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21632
21633 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21634
21635#line 21635 "ad_x86.cpp"
21636 }
21637}
21638
21639void loadSSLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21640 cbuf.set_insts_mark();
21641 // Start at oper_input_base() and count operands
21642 unsigned idx0 = 1;
21643 unsigned idx1 = 1; // src
21644 {
21645
21646#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21647
21648 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21649 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21650 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21651 emit_opcode(cbuf, Assembler::REX_W);
21652 } else {
21653 emit_opcode(cbuf, Assembler::REX_WX);
21654 }
21655 } else {
21656 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21657 emit_opcode(cbuf, Assembler::REX_WB);
21658 } else {
21659 emit_opcode(cbuf, Assembler::REX_WXB);
21660 }
21661 }
21662 } else {
21663 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21664 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21665 emit_opcode(cbuf, Assembler::REX_WR);
21666 } else {
21667 emit_opcode(cbuf, Assembler::REX_WRX);
21668 }
21669 } else {
21670 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21671 emit_opcode(cbuf, Assembler::REX_WRB);
21672 } else {
21673 emit_opcode(cbuf, Assembler::REX_WRXB);
21674 }
21675 }
21676 }
21677
21678#line 21678 "ad_x86.cpp"
21679 }
21680 {
21681
21682#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21683
21684 emit_opcode(cbuf, (0x8B /*primary()*/));
21685
21686#line 21686 "ad_x86.cpp"
21687 }
21688 {
21689
21690#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21691
21692 // High registers handle in encode_RegMem
21693 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21694 int base = opnd_array(1)->base(ra_,this,idx1);
21695 int index = opnd_array(1)->index(ra_,this,idx1);
21696 int scale = opnd_array(1)->scale();
21697 int disp = opnd_array(1)->disp(ra_,this,idx1);
21698 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21699
21700 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21701
21702#line 21702 "ad_x86.cpp"
21703 }
21704}
21705
21706void loadSSPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21707 cbuf.set_insts_mark();
21708 // Start at oper_input_base() and count operands
21709 unsigned idx0 = 1;
21710 unsigned idx1 = 1; // src
21711 {
21712
21713#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21714
21715 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
21716 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21717 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21718 emit_opcode(cbuf, Assembler::REX_W);
21719 } else {
21720 emit_opcode(cbuf, Assembler::REX_WX);
21721 }
21722 } else {
21723 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21724 emit_opcode(cbuf, Assembler::REX_WB);
21725 } else {
21726 emit_opcode(cbuf, Assembler::REX_WXB);
21727 }
21728 }
21729 } else {
21730 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21731 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21732 emit_opcode(cbuf, Assembler::REX_WR);
21733 } else {
21734 emit_opcode(cbuf, Assembler::REX_WRX);
21735 }
21736 } else {
21737 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21738 emit_opcode(cbuf, Assembler::REX_WRB);
21739 } else {
21740 emit_opcode(cbuf, Assembler::REX_WRXB);
21741 }
21742 }
21743 }
21744
21745#line 21745 "ad_x86.cpp"
21746 }
21747 {
21748
21749#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21750
21751 emit_opcode(cbuf, (0x8B /*primary()*/));
21752
21753#line 21753 "ad_x86.cpp"
21754 }
21755 {
21756
21757#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21758
21759 // High registers handle in encode_RegMem
21760 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
21761 int base = opnd_array(1)->base(ra_,this,idx1);
21762 int index = opnd_array(1)->index(ra_,this,idx1);
21763 int scale = opnd_array(1)->scale();
21764 int disp = opnd_array(1)->disp(ra_,this,idx1);
21765 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21766
21767 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21768
21769#line 21769 "ad_x86.cpp"
21770 }
21771}
21772
21773void loadSSFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21774 cbuf.set_insts_mark();
21775 // Start at oper_input_base() and count operands
21776 unsigned idx0 = 1;
21777 unsigned idx1 = 1; // src
21778 {
21779 MacroAssembler _masm(&cbuf);
21780
21781#line 6084 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21782
21783 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
21784
21785#line 21785 "ad_x86.cpp"
21786 }
21787}
21788
21789void loadSSDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21790 cbuf.set_insts_mark();
21791 // Start at oper_input_base() and count operands
21792 unsigned idx0 = 1;
21793 unsigned idx1 = 1; // src
21794 {
21795 MacroAssembler _masm(&cbuf);
21796
21797#line 6097 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21798
21799 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
21800
21801#line 21801 "ad_x86.cpp"
21802 }
21803}
21804
21805void prefetchAllocNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21806 cbuf.set_insts_mark();
21807 // Start at oper_input_base() and count operands
21808 unsigned idx0 = 2;
21809 unsigned idx1 = 2; //
21810 {
21811 MacroAssembler _masm(&cbuf);
21812
21813#line 6112 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21814
21815 __ prefetchw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21816
21817#line 21817 "ad_x86.cpp"
21818 }
21819}
21820
21821void prefetchAllocNTANode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21822 cbuf.set_insts_mark();
21823 // Start at oper_input_base() and count operands
21824 unsigned idx0 = 2;
21825 unsigned idx1 = 2; //
21826 {
21827 MacroAssembler _masm(&cbuf);
21828
21829#line 6124 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21830
21831 __ prefetchnta(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21832
21833#line 21833 "ad_x86.cpp"
21834 }
21835}
21836
21837void prefetchAllocT0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21838 cbuf.set_insts_mark();
21839 // Start at oper_input_base() and count operands
21840 unsigned idx0 = 2;
21841 unsigned idx1 = 2; //
21842 {
21843 MacroAssembler _masm(&cbuf);
21844
21845#line 6136 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21846
21847 __ prefetcht0(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21848
21849#line 21849 "ad_x86.cpp"
21850 }
21851}
21852
21853void prefetchAllocT2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21854 cbuf.set_insts_mark();
21855 // Start at oper_input_base() and count operands
21856 unsigned idx0 = 2;
21857 unsigned idx1 = 2; //
21858 {
21859 MacroAssembler _masm(&cbuf);
21860
21861#line 6148 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21862
21863 __ prefetcht2(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21864
21865#line 21865 "ad_x86.cpp"
21866 }
21867}
21868
21869void storeBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21870 cbuf.set_insts_mark();
21871 // Start at oper_input_base() and count operands
21872 unsigned idx0 = 2;
21873 unsigned idx1 = 2; // mem
21874 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21875 {
21876
21877#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21878
21879 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
21880 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21881 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
21882 emit_opcode(cbuf, Assembler::REX_X);
21883 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
21884 emit_opcode(cbuf, Assembler::REX);
21885 }
21886 } else {
21887 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21888 emit_opcode(cbuf, Assembler::REX_B);
21889 } else {
21890 emit_opcode(cbuf, Assembler::REX_XB);
21891 }
21892 }
21893 } else {
21894 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21895 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21896 emit_opcode(cbuf, Assembler::REX_R);
21897 } else {
21898 emit_opcode(cbuf, Assembler::REX_RX);
21899 }
21900 } else {
21901 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21902 emit_opcode(cbuf, Assembler::REX_RB);
21903 } else {
21904 emit_opcode(cbuf, Assembler::REX_RXB);
21905 }
21906 }
21907 }
21908
21909#line 21909 "ad_x86.cpp"
21910 }
21911 {
21912
21913#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21914
21915 emit_opcode(cbuf, (0x88 /*primary()*/));
21916
21917#line 21917 "ad_x86.cpp"
21918 }
21919 {
21920
21921#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21922
21923 // High registers handle in encode_RegMem
21924 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
21925 int base = opnd_array(1)->base(ra_,this,idx1);
21926 int index = opnd_array(1)->index(ra_,this,idx1);
21927 int scale = opnd_array(1)->scale();
21928 int disp = opnd_array(1)->disp(ra_,this,idx1);
21929 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
21930
21931 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
21932
21933#line 21933 "ad_x86.cpp"
21934 }
21935}
21936
21937void storeCNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21938 cbuf.set_insts_mark();
21939 // Start at oper_input_base() and count operands
21940 unsigned idx0 = 2;
21941 unsigned idx1 = 2; // mem
21942 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21943 {
21944
21945#line 1836 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21946
21947 emit_opcode(cbuf, 0x66);
21948
21949#line 21949 "ad_x86.cpp"
21950 }
21951 {
21952
21953#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21954
21955 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
21956 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21957 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
21958 emit_opcode(cbuf, Assembler::REX_X);
21959 }
21960 } else {
21961 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21962 emit_opcode(cbuf, Assembler::REX_B);
21963 } else {
21964 emit_opcode(cbuf, Assembler::REX_XB);
21965 }
21966 }
21967 } else {
21968 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
21969 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21970 emit_opcode(cbuf, Assembler::REX_R);
21971 } else {
21972 emit_opcode(cbuf, Assembler::REX_RX);
21973 }
21974 } else {
21975 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
21976 emit_opcode(cbuf, Assembler::REX_RB);
21977 } else {
21978 emit_opcode(cbuf, Assembler::REX_RXB);
21979 }
21980 }
21981 }
21982
21983#line 21983 "ad_x86.cpp"
21984 }
21985 {
21986
21987#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21988
21989 emit_opcode(cbuf, (0x89 /*primary()*/));
21990
21991#line 21991 "ad_x86.cpp"
21992 }
21993 {
21994
21995#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
21996
21997 // High registers handle in encode_RegMem
21998 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
21999 int base = opnd_array(1)->base(ra_,this,idx1);
22000 int index = opnd_array(1)->index(ra_,this,idx1);
22001 int scale = opnd_array(1)->scale();
22002 int disp = opnd_array(1)->disp(ra_,this,idx1);
22003 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
22004
22005 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
22006
22007#line 22007 "ad_x86.cpp"
22008 }
22009}
22010
22011void storeINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22012 cbuf.set_insts_mark();
22013 // Start at oper_input_base() and count operands
22014 unsigned idx0 = 2;
22015 unsigned idx1 = 2; // mem
22016 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22017 {
22018
22019#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22020
22021 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
22022 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22023 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22024 emit_opcode(cbuf, Assembler::REX_X);
22025 }
22026 } else {
22027 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22028 emit_opcode(cbuf, Assembler::REX_B);
22029 } else {
22030 emit_opcode(cbuf, Assembler::REX_XB);
22031 }
22032 }
22033 } else {
22034 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22035 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22036 emit_opcode(cbuf, Assembler::REX_R);
22037 } else {
22038 emit_opcode(cbuf, Assembler::REX_RX);
22039 }
22040 } else {
22041 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22042 emit_opcode(cbuf, Assembler::REX_RB);
22043 } else {
22044 emit_opcode(cbuf, Assembler::REX_RXB);
22045 }
22046 }
22047 }
22048
22049#line 22049 "ad_x86.cpp"
22050 }
22051 {
22052
22053#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22054
22055 emit_opcode(cbuf, (0x89 /*primary()*/));
22056
22057#line 22057 "ad_x86.cpp"
22058 }
22059 {
22060
22061#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22062
22063 // High registers handle in encode_RegMem
22064 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
22065 int base = opnd_array(1)->base(ra_,this,idx1);
22066 int index = opnd_array(1)->index(ra_,this,idx1);
22067 int scale = opnd_array(1)->scale();
22068 int disp = opnd_array(1)->disp(ra_,this,idx1);
22069 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
22070
22071 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
22072
22073#line 22073 "ad_x86.cpp"
22074 }
22075}
22076
22077void storeLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22078 cbuf.set_insts_mark();
22079 // Start at oper_input_base() and count operands
22080 unsigned idx0 = 2;
22081 unsigned idx1 = 2; // mem
22082 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22083 {
22084
22085#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22086
22087 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
22088 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22089 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22090 emit_opcode(cbuf, Assembler::REX_W);
22091 } else {
22092 emit_opcode(cbuf, Assembler::REX_WX);
22093 }
22094 } else {
22095 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22096 emit_opcode(cbuf, Assembler::REX_WB);
22097 } else {
22098 emit_opcode(cbuf, Assembler::REX_WXB);
22099 }
22100 }
22101 } else {
22102 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22103 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22104 emit_opcode(cbuf, Assembler::REX_WR);
22105 } else {
22106 emit_opcode(cbuf, Assembler::REX_WRX);
22107 }
22108 } else {
22109 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22110 emit_opcode(cbuf, Assembler::REX_WRB);
22111 } else {
22112 emit_opcode(cbuf, Assembler::REX_WRXB);
22113 }
22114 }
22115 }
22116
22117#line 22117 "ad_x86.cpp"
22118 }
22119 {
22120
22121#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22122
22123 emit_opcode(cbuf, (0x89 /*primary()*/));
22124
22125#line 22125 "ad_x86.cpp"
22126 }
22127 {
22128
22129#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22130
22131 // High registers handle in encode_RegMem
22132 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
22133 int base = opnd_array(1)->base(ra_,this,idx1);
22134 int index = opnd_array(1)->index(ra_,this,idx1);
22135 int scale = opnd_array(1)->scale();
22136 int disp = opnd_array(1)->disp(ra_,this,idx1);
22137 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
22138
22139 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
22140
22141#line 22141 "ad_x86.cpp"
22142 }
22143}
22144
22145void storePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22146 cbuf.set_insts_mark();
22147 // Start at oper_input_base() and count operands
22148 unsigned idx0 = 2;
22149 unsigned idx1 = 2; // mem
22150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22151 {
22152
22153#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22154
22155 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
22156 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22157 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22158 emit_opcode(cbuf, Assembler::REX_W);
22159 } else {
22160 emit_opcode(cbuf, Assembler::REX_WX);
22161 }
22162 } else {
22163 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22164 emit_opcode(cbuf, Assembler::REX_WB);
22165 } else {
22166 emit_opcode(cbuf, Assembler::REX_WXB);
22167 }
22168 }
22169 } else {
22170 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22171 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22172 emit_opcode(cbuf, Assembler::REX_WR);
22173 } else {
22174 emit_opcode(cbuf, Assembler::REX_WRX);
22175 }
22176 } else {
22177 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22178 emit_opcode(cbuf, Assembler::REX_WRB);
22179 } else {
22180 emit_opcode(cbuf, Assembler::REX_WRXB);
22181 }
22182 }
22183 }
22184
22185#line 22185 "ad_x86.cpp"
22186 }
22187 {
22188
22189#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22190
22191 emit_opcode(cbuf, (0x89 /*primary()*/));
22192
22193#line 22193 "ad_x86.cpp"
22194 }
22195 {
22196
22197#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22198
22199 // High registers handle in encode_RegMem
22200 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
22201 int base = opnd_array(1)->base(ra_,this,idx1);
22202 int index = opnd_array(1)->index(ra_,this,idx1);
22203 int scale = opnd_array(1)->scale();
22204 int disp = opnd_array(1)->disp(ra_,this,idx1);
22205 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
22206
22207 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
22208
22209#line 22209 "ad_x86.cpp"
22210 }
22211}
22212
22213void storeImmP0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22214 cbuf.set_insts_mark();
22215 // Start at oper_input_base() and count operands
22216 unsigned idx0 = 2;
22217 unsigned idx1 = 2; // mem
22218 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22219 {
22220 MacroAssembler _masm(&cbuf);
22221
22222#line 6223 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22223
22224 __ movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22225
22226#line 22226 "ad_x86.cpp"
22227 }
22228}
22229
22230void storeImmPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22231 cbuf.set_insts_mark();
22232 // Start at oper_input_base() and count operands
22233 unsigned idx0 = 2;
22234 unsigned idx1 = 2; // mem
22235 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22236 {
22237
22238#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22239
22240 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22241 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22242 emit_opcode(cbuf, Assembler::REX_WB);
22243 } else {
22244 emit_opcode(cbuf, Assembler::REX_WXB);
22245 }
22246 } else {
22247 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22248 emit_opcode(cbuf, Assembler::REX_W);
22249 } else {
22250 emit_opcode(cbuf, Assembler::REX_WX);
22251 }
22252 }
22253
22254#line 22254 "ad_x86.cpp"
22255 }
22256 {
22257
22258#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22259
22260 emit_opcode(cbuf, (0xC7 /*primary()*/));
22261
22262#line 22262 "ad_x86.cpp"
22263 }
22264 {
22265
22266#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22267
22268 int rm_byte_opcode = (0x00);
22269
22270 // High registers handle in encode_RegMem
22271 int base = opnd_array(1)->base(ra_,this,idx1);
22272 int index = opnd_array(1)->index(ra_,this,idx1);
22273 int scale = opnd_array(1)->scale();
22274 int displace = opnd_array(1)->disp(ra_,this,idx1);
22275
22276 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22277 // working with static
22278 // globals
22279 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22280 disp_reloc);
22281
22282#line 22282 "ad_x86.cpp"
22283 }
22284 {
22285
22286#line 2299 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22287
22288 // Output immediate
22289
22290if ( opnd_array(2)->constant_reloc() != relocInfo::none ) {
22291 emit_d32_reloc(cbuf, opnd_array(2)->constant(), opnd_array(2)->constant_reloc(), 0);
22292} else {
22293 emit_d32(cbuf, opnd_array(2)->constant());
22294};
22295
22296#line 22296 "ad_x86.cpp"
22297 }
22298}
22299
22300void storeNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22301 cbuf.set_insts_mark();
22302 // Start at oper_input_base() and count operands
22303 unsigned idx0 = 2;
22304 unsigned idx1 = 2; // mem
22305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22306 {
22307 MacroAssembler _masm(&cbuf);
22308
22309#line 6248 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22310
22311 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22312
22313#line 22313 "ad_x86.cpp"
22314 }
22315}
22316
22317void storeNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22318 cbuf.set_insts_mark();
22319 // Start at oper_input_base() and count operands
22320 unsigned idx0 = 2;
22321 unsigned idx1 = 2; // mem
22322 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22323 {
22324 MacroAssembler _masm(&cbuf);
22325
22326#line 6260 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22327
22328 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22329
22330#line 22330 "ad_x86.cpp"
22331 }
22332}
22333
22334void storeImmN0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22335 cbuf.set_insts_mark();
22336 // Start at oper_input_base() and count operands
22337 unsigned idx0 = 2;
22338 unsigned idx1 = 2; // mem
22339 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22340 {
22341 MacroAssembler _masm(&cbuf);
22342
22343#line 6273 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22344
22345 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22346
22347#line 22347 "ad_x86.cpp"
22348 }
22349}
22350
22351void storeImmNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22352 cbuf.set_insts_mark();
22353 // Start at oper_input_base() and count operands
22354 unsigned idx0 = 2;
22355 unsigned idx1 = 2; // mem
22356 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22357 {
22358 MacroAssembler _masm(&cbuf);
22359
22360#line 6285 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22361
22362 address con = (address)opnd_array(2)->constant();
22363 if (con == NULL) {
22364 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (int32_t)0);
22365 } else {
22366 __ set_narrow_oop(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (jobject)opnd_array(2)->constant());
22367 }
22368
22369#line 22369 "ad_x86.cpp"
22370 }
22371}
22372
22373void storeImmNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22374 cbuf.set_insts_mark();
22375 // Start at oper_input_base() and count operands
22376 unsigned idx0 = 2;
22377 unsigned idx1 = 2; // mem
22378 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22379 {
22380 MacroAssembler _masm(&cbuf);
22381
22382#line 6302 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22383
22384 __ set_narrow_klass(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (Klass*)opnd_array(2)->constant());
22385
22386#line 22386 "ad_x86.cpp"
22387 }
22388}
22389
22390void storeImmI0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22391 cbuf.set_insts_mark();
22392 // Start at oper_input_base() and count operands
22393 unsigned idx0 = 2;
22394 unsigned idx1 = 2; // mem
22395 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22396 {
22397 MacroAssembler _masm(&cbuf);
22398
22399#line 6316 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22400
22401 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22402
22403#line 22403 "ad_x86.cpp"
22404 }
22405}
22406
22407void storeImmINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22408 cbuf.set_insts_mark();
22409 // Start at oper_input_base() and count operands
22410 unsigned idx0 = 2;
22411 unsigned idx1 = 2; // mem
22412 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22413 {
22414
22415#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22416
22417 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22418 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22419 emit_opcode(cbuf, Assembler::REX_B);
22420 } else {
22421 emit_opcode(cbuf, Assembler::REX_XB);
22422 }
22423 } else {
22424 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22425 emit_opcode(cbuf, Assembler::REX_X);
22426 }
22427 }
22428
22429#line 22429 "ad_x86.cpp"
22430 }
22431 {
22432
22433#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22434
22435 emit_opcode(cbuf, (0xC7 /*primary()*/));
22436
22437#line 22437 "ad_x86.cpp"
22438 }
22439 {
22440
22441#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22442
22443 int rm_byte_opcode = (0x00);
22444
22445 // High registers handle in encode_RegMem
22446 int base = opnd_array(1)->base(ra_,this,idx1);
22447 int index = opnd_array(1)->index(ra_,this,idx1);
22448 int scale = opnd_array(1)->scale();
22449 int displace = opnd_array(1)->disp(ra_,this,idx1);
22450
22451 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22452 // working with static
22453 // globals
22454 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22455 disp_reloc);
22456
22457#line 22457 "ad_x86.cpp"
22458 }
22459 {
22460
22461#line 2299 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22462
22463 // Output immediate
22464 emit_d32(cbuf, opnd_array(2)->constant());
22465
22466#line 22466 "ad_x86.cpp"
22467 }
22468}
22469
22470void storeImmL0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22471 cbuf.set_insts_mark();
22472 // Start at oper_input_base() and count operands
22473 unsigned idx0 = 2;
22474 unsigned idx1 = 2; // mem
22475 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22476 {
22477 MacroAssembler _masm(&cbuf);
22478
22479#line 6341 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22480
22481 __ movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22482
22483#line 22483 "ad_x86.cpp"
22484 }
22485}
22486
22487void storeImmLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22488 cbuf.set_insts_mark();
22489 // Start at oper_input_base() and count operands
22490 unsigned idx0 = 2;
22491 unsigned idx1 = 2; // mem
22492 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22493 {
22494
22495#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22496
22497 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22498 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22499 emit_opcode(cbuf, Assembler::REX_WB);
22500 } else {
22501 emit_opcode(cbuf, Assembler::REX_WXB);
22502 }
22503 } else {
22504 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22505 emit_opcode(cbuf, Assembler::REX_W);
22506 } else {
22507 emit_opcode(cbuf, Assembler::REX_WX);
22508 }
22509 }
22510
22511#line 22511 "ad_x86.cpp"
22512 }
22513 {
22514
22515#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22516
22517 emit_opcode(cbuf, (0xC7 /*primary()*/));
22518
22519#line 22519 "ad_x86.cpp"
22520 }
22521 {
22522
22523#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22524
22525 int rm_byte_opcode = (0x00);
22526
22527 // High registers handle in encode_RegMem
22528 int base = opnd_array(1)->base(ra_,this,idx1);
22529 int index = opnd_array(1)->index(ra_,this,idx1);
22530 int scale = opnd_array(1)->scale();
22531 int displace = opnd_array(1)->disp(ra_,this,idx1);
22532
22533 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22534 // working with static
22535 // globals
22536 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22537 disp_reloc);
22538
22539#line 22539 "ad_x86.cpp"
22540 }
22541 {
22542
22543#line 2299 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22544
22545 // Output immediate
22546 emit_d32(cbuf, opnd_array(2)->constantL());
22547
22548#line 22548 "ad_x86.cpp"
22549 }
22550}
22551
22552void storeImmC0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22553 cbuf.set_insts_mark();
22554 // Start at oper_input_base() and count operands
22555 unsigned idx0 = 2;
22556 unsigned idx1 = 2; // mem
22557 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22558 {
22559 MacroAssembler _masm(&cbuf);
22560
22561#line 6366 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22562
22563 __ movw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22564
22565#line 22565 "ad_x86.cpp"
22566 }
22567}
22568
22569void storeImmI16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22570 cbuf.set_insts_mark();
22571 // Start at oper_input_base() and count operands
22572 unsigned idx0 = 2;
22573 unsigned idx1 = 2; // mem
22574 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22575 {
22576
22577#line 1836 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22578
22579 emit_opcode(cbuf, 0x66);
22580
22581#line 22581 "ad_x86.cpp"
22582 }
22583 {
22584
22585#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22586
22587 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22588 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22589 emit_opcode(cbuf, Assembler::REX_B);
22590 } else {
22591 emit_opcode(cbuf, Assembler::REX_XB);
22592 }
22593 } else {
22594 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22595 emit_opcode(cbuf, Assembler::REX_X);
22596 }
22597 }
22598
22599#line 22599 "ad_x86.cpp"
22600 }
22601 {
22602
22603#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22604
22605 emit_opcode(cbuf, (0xC7 /*primary()*/));
22606
22607#line 22607 "ad_x86.cpp"
22608 }
22609 {
22610
22611#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22612
22613 int rm_byte_opcode = (0x00);
22614
22615 // High registers handle in encode_RegMem
22616 int base = opnd_array(1)->base(ra_,this,idx1);
22617 int index = opnd_array(1)->index(ra_,this,idx1);
22618 int scale = opnd_array(1)->scale();
22619 int displace = opnd_array(1)->disp(ra_,this,idx1);
22620
22621 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22622 // working with static
22623 // globals
22624 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22625 disp_reloc);
22626
22627#line 22627 "ad_x86.cpp"
22628 }
22629 {
22630
22631#line 2313 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22632
22633 // Output immediate
22634 emit_d16(cbuf, opnd_array(2)->constant());
22635
22636#line 22636 "ad_x86.cpp"
22637 }
22638}
22639
22640void storeImmB0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22641 cbuf.set_insts_mark();
22642 // Start at oper_input_base() and count operands
22643 unsigned idx0 = 2;
22644 unsigned idx1 = 2; // mem
22645 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22646 {
22647 MacroAssembler _masm(&cbuf);
22648
22649#line 6392 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22650
22651 __ movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22652
22653#line 22653 "ad_x86.cpp"
22654 }
22655}
22656
22657void storeImmBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22658 cbuf.set_insts_mark();
22659 // Start at oper_input_base() and count operands
22660 unsigned idx0 = 2;
22661 unsigned idx1 = 2; // mem
22662 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22663 {
22664
22665#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22666
22667 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22668 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22669 emit_opcode(cbuf, Assembler::REX_B);
22670 } else {
22671 emit_opcode(cbuf, Assembler::REX_XB);
22672 }
22673 } else {
22674 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22675 emit_opcode(cbuf, Assembler::REX_X);
22676 }
22677 }
22678
22679#line 22679 "ad_x86.cpp"
22680 }
22681 {
22682
22683#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22684
22685 emit_opcode(cbuf, (0xC6 /*primary()*/));
22686
22687#line 22687 "ad_x86.cpp"
22688 }
22689 {
22690
22691#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22692
22693 int rm_byte_opcode = (0x00);
22694
22695 // High registers handle in encode_RegMem
22696 int base = opnd_array(1)->base(ra_,this,idx1);
22697 int index = opnd_array(1)->index(ra_,this,idx1);
22698 int scale = opnd_array(1)->scale();
22699 int displace = opnd_array(1)->disp(ra_,this,idx1);
22700
22701 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22702 // working with static
22703 // globals
22704 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22705 disp_reloc);
22706
22707#line 22707 "ad_x86.cpp"
22708 }
22709 {
22710
22711#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22712
22713 // Check for 8-bit immediate, and set sign extend bit in opcode
22714 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
22715 emit_d8(cbuf, opnd_array(2)->constant());
22716 } else {
22717 // 32-bit immediate
22718 emit_d32(cbuf, opnd_array(2)->constant());
22719 }
22720
22721#line 22721 "ad_x86.cpp"
22722 }
22723}
22724
22725void storeImmCM0_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22726 cbuf.set_insts_mark();
22727 // Start at oper_input_base() and count operands
22728 unsigned idx0 = 2;
22729 unsigned idx1 = 2; // mem
22730 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22731 {
22732 MacroAssembler _masm(&cbuf);
22733
22734#line 6417 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22735
22736 __ movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22737
22738#line 22738 "ad_x86.cpp"
22739 }
22740}
22741
22742void storeImmCM0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22743 cbuf.set_insts_mark();
22744 // Start at oper_input_base() and count operands
22745 unsigned idx0 = 2;
22746 unsigned idx1 = 2; // mem
22747 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22748 {
22749
22750#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22751
22752 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22753 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22754 emit_opcode(cbuf, Assembler::REX_B);
22755 } else {
22756 emit_opcode(cbuf, Assembler::REX_XB);
22757 }
22758 } else {
22759 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22760 emit_opcode(cbuf, Assembler::REX_X);
22761 }
22762 }
22763
22764#line 22764 "ad_x86.cpp"
22765 }
22766 {
22767
22768#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22769
22770 emit_opcode(cbuf, (0xC6 /*primary()*/));
22771
22772#line 22772 "ad_x86.cpp"
22773 }
22774 {
22775
22776#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22777
22778 int rm_byte_opcode = (0x00);
22779
22780 // High registers handle in encode_RegMem
22781 int base = opnd_array(1)->base(ra_,this,idx1);
22782 int index = opnd_array(1)->index(ra_,this,idx1);
22783 int scale = opnd_array(1)->scale();
22784 int displace = opnd_array(1)->disp(ra_,this,idx1);
22785
22786 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22787 // working with static
22788 // globals
22789 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22790 disp_reloc);
22791
22792#line 22792 "ad_x86.cpp"
22793 }
22794 {
22795
22796#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22797
22798 // Check for 8-bit immediate, and set sign extend bit in opcode
22799 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
22800 emit_d8(cbuf, opnd_array(2)->constant());
22801 } else {
22802 // 32-bit immediate
22803 emit_d32(cbuf, opnd_array(2)->constant());
22804 }
22805
22806#line 22806 "ad_x86.cpp"
22807 }
22808}
22809
22810void storeFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22811 cbuf.set_insts_mark();
22812 // Start at oper_input_base() and count operands
22813 unsigned idx0 = 2;
22814 unsigned idx1 = 2; // mem
22815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22816 {
22817 MacroAssembler _masm(&cbuf);
22818
22819#line 6441 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22820
22821 __ movflt(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
22822
22823#line 22823 "ad_x86.cpp"
22824 }
22825}
22826
22827void storeF0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22828 cbuf.set_insts_mark();
22829 // Start at oper_input_base() and count operands
22830 unsigned idx0 = 2;
22831 unsigned idx1 = 2; // mem
22832 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22833 {
22834 MacroAssembler _masm(&cbuf);
22835
22836#line 6455 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22837
22838 __ movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
22839
22840#line 22840 "ad_x86.cpp"
22841 }
22842}
22843
22844void storeF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22845 cbuf.set_insts_mark();
22846 // Start at oper_input_base() and count operands
22847 unsigned idx0 = 2;
22848 unsigned idx1 = 2; // mem
22849 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22850 {
22851
22852#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22853
22854 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22855 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22856 emit_opcode(cbuf, Assembler::REX_B);
22857 } else {
22858 emit_opcode(cbuf, Assembler::REX_XB);
22859 }
22860 } else {
22861 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22862 emit_opcode(cbuf, Assembler::REX_X);
22863 }
22864 }
22865
22866#line 22866 "ad_x86.cpp"
22867 }
22868 {
22869
22870#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22871
22872 emit_opcode(cbuf, (0xC7 /*primary()*/));
22873
22874#line 22874 "ad_x86.cpp"
22875 }
22876 {
22877
22878#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22879
22880 int rm_byte_opcode = (0x00);
22881
22882 // High registers handle in encode_RegMem
22883 int base = opnd_array(1)->base(ra_,this,idx1);
22884 int index = opnd_array(1)->index(ra_,this,idx1);
22885 int scale = opnd_array(1)->scale();
22886 int displace = opnd_array(1)->disp(ra_,this,idx1);
22887
22888 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22889 // working with static
22890 // globals
22891 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22892 disp_reloc);
22893
22894#line 22894 "ad_x86.cpp"
22895 }
22896 {
22897
22898#line 2305 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22899
22900 // Output Float immediate bits
22901 jfloat jf = opnd_array(2)->constantF();
22902 jint jf_as_bits = jint_cast(jf);
22903 emit_d32(cbuf, jf_as_bits);
22904
22905#line 22905 "ad_x86.cpp"
22906 }
22907}
22908
22909void storeDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22910 cbuf.set_insts_mark();
22911 // Start at oper_input_base() and count operands
22912 unsigned idx0 = 2;
22913 unsigned idx1 = 2; // mem
22914 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22915 {
22916 MacroAssembler _masm(&cbuf);
22917
22918#line 6479 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22919
22920 __ movdbl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
22921
22922#line 22922 "ad_x86.cpp"
22923 }
22924}
22925
22926void storeD0_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22927 cbuf.set_insts_mark();
22928 // Start at oper_input_base() and count operands
22929 unsigned idx0 = 2;
22930 unsigned idx1 = 2; // mem
22931 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22932 {
22933
22934#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22935
22936 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
22937 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22938 emit_opcode(cbuf, Assembler::REX_WB);
22939 } else {
22940 emit_opcode(cbuf, Assembler::REX_WXB);
22941 }
22942 } else {
22943 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22944 emit_opcode(cbuf, Assembler::REX_W);
22945 } else {
22946 emit_opcode(cbuf, Assembler::REX_WX);
22947 }
22948 }
22949
22950#line 22950 "ad_x86.cpp"
22951 }
22952 {
22953
22954#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22955
22956 emit_opcode(cbuf, (0xC7 /*primary()*/));
22957
22958#line 22958 "ad_x86.cpp"
22959 }
22960 {
22961
22962#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22963
22964 int rm_byte_opcode = (0x00);
22965
22966 // High registers handle in encode_RegMem
22967 int base = opnd_array(1)->base(ra_,this,idx1);
22968 int index = opnd_array(1)->index(ra_,this,idx1);
22969 int scale = opnd_array(1)->scale();
22970 int displace = opnd_array(1)->disp(ra_,this,idx1);
22971
22972 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
22973 // working with static
22974 // globals
22975 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
22976 disp_reloc);
22977
22978#line 22978 "ad_x86.cpp"
22979 }
22980 {
22981
22982#line 2305 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
22983
22984 // Output Float immediate bits
22985 jfloat jf = opnd_array(2)->constantD();
22986 jint jf_as_bits = jint_cast(jf);
22987 emit_d32(cbuf, jf_as_bits);
22988
22989#line 22989 "ad_x86.cpp"
22990 }
22991}
22992
22993void storeD0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22994 cbuf.set_insts_mark();
22995 // Start at oper_input_base() and count operands
22996 unsigned idx0 = 2;
22997 unsigned idx1 = 2; // mem
22998 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
22999 {
23000 MacroAssembler _masm(&cbuf);
23001
23002#line 6505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23003
23004 __ movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
23005
23006#line 23006 "ad_x86.cpp"
23007 }
23008}
23009
23010void storeSSINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23011 cbuf.set_insts_mark();
23012 // Start at oper_input_base() and count operands
23013 unsigned idx0 = 1;
23014 unsigned idx1 = 1; // src
23015 {
23016
23017#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23018
23019 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
23020 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23021 if (opnd_array(0)->index(ra_,this,idx0) >= 8) {
23022 emit_opcode(cbuf, Assembler::REX_X);
23023 }
23024 } else {
23025 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23026 emit_opcode(cbuf, Assembler::REX_B);
23027 } else {
23028 emit_opcode(cbuf, Assembler::REX_XB);
23029 }
23030 }
23031 } else {
23032 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23033 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23034 emit_opcode(cbuf, Assembler::REX_R);
23035 } else {
23036 emit_opcode(cbuf, Assembler::REX_RX);
23037 }
23038 } else {
23039 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23040 emit_opcode(cbuf, Assembler::REX_RB);
23041 } else {
23042 emit_opcode(cbuf, Assembler::REX_RXB);
23043 }
23044 }
23045 }
23046
23047#line 23047 "ad_x86.cpp"
23048 }
23049 {
23050
23051#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23052
23053 emit_opcode(cbuf, (0x89 /*primary()*/));
23054
23055#line 23055 "ad_x86.cpp"
23056 }
23057 {
23058
23059#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23060
23061 // High registers handle in encode_RegMem
23062 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
23063 int base = opnd_array(0)->base(ra_,this,idx0);
23064 int index = opnd_array(0)->index(ra_,this,idx0);
23065 int scale = opnd_array(0)->scale();
23066 int disp = opnd_array(0)->disp(ra_,this,0);
23067 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
23068
23069 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
23070
23071#line 23071 "ad_x86.cpp"
23072 }
23073}
23074
23075void storeSSLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23076 cbuf.set_insts_mark();
23077 // Start at oper_input_base() and count operands
23078 unsigned idx0 = 1;
23079 unsigned idx1 = 1; // src
23080 {
23081
23082#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23083
23084 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
23085 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23086 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23087 emit_opcode(cbuf, Assembler::REX_W);
23088 } else {
23089 emit_opcode(cbuf, Assembler::REX_WX);
23090 }
23091 } else {
23092 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23093 emit_opcode(cbuf, Assembler::REX_WB);
23094 } else {
23095 emit_opcode(cbuf, Assembler::REX_WXB);
23096 }
23097 }
23098 } else {
23099 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23100 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23101 emit_opcode(cbuf, Assembler::REX_WR);
23102 } else {
23103 emit_opcode(cbuf, Assembler::REX_WRX);
23104 }
23105 } else {
23106 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23107 emit_opcode(cbuf, Assembler::REX_WRB);
23108 } else {
23109 emit_opcode(cbuf, Assembler::REX_WRXB);
23110 }
23111 }
23112 }
23113
23114#line 23114 "ad_x86.cpp"
23115 }
23116 {
23117
23118#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23119
23120 emit_opcode(cbuf, (0x89 /*primary()*/));
23121
23122#line 23122 "ad_x86.cpp"
23123 }
23124 {
23125
23126#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23127
23128 // High registers handle in encode_RegMem
23129 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
23130 int base = opnd_array(0)->base(ra_,this,idx0);
23131 int index = opnd_array(0)->index(ra_,this,idx0);
23132 int scale = opnd_array(0)->scale();
23133 int disp = opnd_array(0)->disp(ra_,this,0);
23134 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
23135
23136 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
23137
23138#line 23138 "ad_x86.cpp"
23139 }
23140}
23141
23142void storeSSPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23143 cbuf.set_insts_mark();
23144 // Start at oper_input_base() and count operands
23145 unsigned idx0 = 1;
23146 unsigned idx1 = 1; // src
23147 {
23148
23149#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23150
23151 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
23152 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23153 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23154 emit_opcode(cbuf, Assembler::REX_W);
23155 } else {
23156 emit_opcode(cbuf, Assembler::REX_WX);
23157 }
23158 } else {
23159 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23160 emit_opcode(cbuf, Assembler::REX_WB);
23161 } else {
23162 emit_opcode(cbuf, Assembler::REX_WXB);
23163 }
23164 }
23165 } else {
23166 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
23167 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23168 emit_opcode(cbuf, Assembler::REX_WR);
23169 } else {
23170 emit_opcode(cbuf, Assembler::REX_WRX);
23171 }
23172 } else {
23173 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
23174 emit_opcode(cbuf, Assembler::REX_WRB);
23175 } else {
23176 emit_opcode(cbuf, Assembler::REX_WRXB);
23177 }
23178 }
23179 }
23180
23181#line 23181 "ad_x86.cpp"
23182 }
23183 {
23184
23185#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23186
23187 emit_opcode(cbuf, (0x89 /*primary()*/));
23188
23189#line 23189 "ad_x86.cpp"
23190 }
23191 {
23192
23193#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23194
23195 // High registers handle in encode_RegMem
23196 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
23197 int base = opnd_array(0)->base(ra_,this,idx0);
23198 int index = opnd_array(0)->index(ra_,this,idx0);
23199 int scale = opnd_array(0)->scale();
23200 int disp = opnd_array(0)->disp(ra_,this,0);
23201 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
23202
23203 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
23204
23205#line 23205 "ad_x86.cpp"
23206 }
23207}
23208
23209void storeSSFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23210 cbuf.set_insts_mark();
23211 // Start at oper_input_base() and count operands
23212 unsigned idx0 = 1;
23213 unsigned idx1 = 1; // src
23214 {
23215 MacroAssembler _masm(&cbuf);
23216
23217#line 6550 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23218
23219 __ movflt(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
23220
23221#line 23221 "ad_x86.cpp"
23222 }
23223}
23224
23225void storeSSDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23226 cbuf.set_insts_mark();
23227 // Start at oper_input_base() and count operands
23228 unsigned idx0 = 1;
23229 unsigned idx1 = 1; // src
23230 {
23231 MacroAssembler _masm(&cbuf);
23232
23233#line 6562 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23234
23235 __ movdbl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
23236
23237#line 23237 "ad_x86.cpp"
23238 }
23239}
23240
23241void bytes_reverse_intNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23242 cbuf.set_insts_mark();
23243 // Start at oper_input_base() and count operands
23244 unsigned idx0 = 1;
23245 unsigned idx1 = 1; // dst
23246 {
23247
23248#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23249
23250 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
23251 emit_opcode(cbuf, Assembler::REX_B);
23252 }
23253
23254#line 23254 "ad_x86.cpp"
23255 }
23256 {
23257
23258#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23259
23260 emit_opcode(cbuf, (0x0F /*primary()*/));
23261
23262#line 23262 "ad_x86.cpp"
23263 }
23264 {
23265
23266#line 2058 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23267
23268 // BSWAP
23269 emit_cc(cbuf, (0xC8 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */);
23270
23271#line 23271 "ad_x86.cpp"
23272 }
23273}
23274
23275void bytes_reverse_longNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23276 cbuf.set_insts_mark();
23277 // Start at oper_input_base() and count operands
23278 unsigned idx0 = 1;
23279 unsigned idx1 = 1; // dst
23280 {
23281
23282#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23283
23284 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
23285 emit_opcode(cbuf, Assembler::REX_W);
23286 } else {
23287 emit_opcode(cbuf, Assembler::REX_WB);
23288 }
23289
23290#line 23290 "ad_x86.cpp"
23291 }
23292 {
23293
23294#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23295
23296 emit_opcode(cbuf, (0x0F /*primary()*/));
23297
23298#line 23298 "ad_x86.cpp"
23299 }
23300 {
23301
23302#line 2058 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23303
23304 // BSWAP
23305 emit_cc(cbuf, (0xC8 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */);
23306
23307#line 23307 "ad_x86.cpp"
23308 }
23309}
23310
23311void bytes_reverse_unsigned_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23312 cbuf.set_insts_mark();
23313 // Start at oper_input_base() and count operands
23314 unsigned idx0 = 1;
23315 unsigned idx1 = 1; // dst
23316 {
23317 MacroAssembler _masm(&cbuf);
23318
23319#line 6593 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23320
23321 __ bswapl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
23322 __ shrl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 16);
23323
23324#line 23324 "ad_x86.cpp"
23325 }
23326}
23327
23328void bytes_reverse_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23329 cbuf.set_insts_mark();
23330 // Start at oper_input_base() and count operands
23331 unsigned idx0 = 1;
23332 unsigned idx1 = 1; // dst
23333 {
23334 MacroAssembler _masm(&cbuf);
23335
23336#line 6606 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23337
23338 __ bswapl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
23339 __ sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 16);
23340
23341#line 23341 "ad_x86.cpp"
23342 }
23343}
23344
23345void countLeadingZerosINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23346 cbuf.set_insts_mark();
23347 // Start at oper_input_base() and count operands
23348 unsigned idx0 = 1;
23349 unsigned idx1 = 1; // src
23350 {
23351 MacroAssembler _masm(&cbuf);
23352
23353#line 6621 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23354
23355 __ lzcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23356
23357#line 23357 "ad_x86.cpp"
23358 }
23359}
23360
23361void countLeadingZerosI_bsrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23362 cbuf.set_insts_mark();
23363 // Start at oper_input_base() and count operands
23364 unsigned idx0 = 1;
23365 unsigned idx1 = 1; // src
23366 {
23367 MacroAssembler _masm(&cbuf);
23368
23369#line 6638 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23370
23371 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
23372 Register Rsrc = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23373 Label skip;
23374 __ bsrl(Rdst, Rsrc);
23375 __ jccb(Assembler::notZero, skip);
23376 __ movl(Rdst, -1);
23377 __ bind(skip);
23378 __ negl(Rdst);
23379 __ addl(Rdst, BitsPerInt - 1);
23380
23381#line 23381 "ad_x86.cpp"
23382 }
23383}
23384
23385void countLeadingZerosLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23386 cbuf.set_insts_mark();
23387 // Start at oper_input_base() and count operands
23388 unsigned idx0 = 1;
23389 unsigned idx1 = 1; // src
23390 {
23391 MacroAssembler _masm(&cbuf);
23392
23393#line 6658 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23394
23395 __ lzcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23396
23397#line 23397 "ad_x86.cpp"
23398 }
23399}
23400
23401void countLeadingZerosL_bsrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23402 cbuf.set_insts_mark();
23403 // Start at oper_input_base() and count operands
23404 unsigned idx0 = 1;
23405 unsigned idx1 = 1; // src
23406 {
23407 MacroAssembler _masm(&cbuf);
23408
23409#line 6675 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23410
23411 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
23412 Register Rsrc = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23413 Label skip;
23414 __ bsrq(Rdst, Rsrc);
23415 __ jccb(Assembler::notZero, skip);
23416 __ movl(Rdst, -1);
23417 __ bind(skip);
23418 __ negl(Rdst);
23419 __ addl(Rdst, BitsPerLong - 1);
23420
23421#line 23421 "ad_x86.cpp"
23422 }
23423}
23424
23425void countTrailingZerosINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23426 cbuf.set_insts_mark();
23427 // Start at oper_input_base() and count operands
23428 unsigned idx0 = 1;
23429 unsigned idx1 = 1; // src
23430 {
23431 MacroAssembler _masm(&cbuf);
23432
23433#line 6695 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23434
23435 __ tzcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23436
23437#line 23437 "ad_x86.cpp"
23438 }
23439}
23440
23441void countTrailingZerosI_bsfNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23442 cbuf.set_insts_mark();
23443 // Start at oper_input_base() and count operands
23444 unsigned idx0 = 1;
23445 unsigned idx1 = 1; // src
23446 {
23447 MacroAssembler _masm(&cbuf);
23448
23449#line 6710 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23450
23451 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
23452 Label done;
23453 __ bsfl(Rdst, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23454 __ jccb(Assembler::notZero, done);
23455 __ movl(Rdst, BitsPerInt);
23456 __ bind(done);
23457
23458#line 23458 "ad_x86.cpp"
23459 }
23460}
23461
23462void countTrailingZerosLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23463 cbuf.set_insts_mark();
23464 // Start at oper_input_base() and count operands
23465 unsigned idx0 = 1;
23466 unsigned idx1 = 1; // src
23467 {
23468 MacroAssembler _masm(&cbuf);
23469
23470#line 6727 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23471
23472 __ tzcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23473
23474#line 23474 "ad_x86.cpp"
23475 }
23476}
23477
23478void countTrailingZerosL_bsfNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23479 cbuf.set_insts_mark();
23480 // Start at oper_input_base() and count operands
23481 unsigned idx0 = 1;
23482 unsigned idx1 = 1; // src
23483 {
23484 MacroAssembler _masm(&cbuf);
23485
23486#line 6742 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23487
23488 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
23489 Label done;
23490 __ bsfq(Rdst, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23491 __ jccb(Assembler::notZero, done);
23492 __ movl(Rdst, BitsPerLong);
23493 __ bind(done);
23494
23495#line 23495 "ad_x86.cpp"
23496 }
23497}
23498
23499void popCountINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23500 cbuf.set_insts_mark();
23501 // Start at oper_input_base() and count operands
23502 unsigned idx0 = 1;
23503 unsigned idx1 = 1; // src
23504 {
23505 MacroAssembler _masm(&cbuf);
23506
23507#line 6762 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23508
23509 __ popcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23510
23511#line 23511 "ad_x86.cpp"
23512 }
23513}
23514
23515void popCountI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23516 cbuf.set_insts_mark();
23517 // Start at oper_input_base() and count operands
23518 unsigned idx0 = 2;
23519 unsigned idx1 = 2; // mem
23520 {
23521 MacroAssembler _masm(&cbuf);
23522
23523#line 6774 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23524
23525 __ popcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23526
23527#line 23527 "ad_x86.cpp"
23528 }
23529}
23530
23531void popCountLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23532 cbuf.set_insts_mark();
23533 // Start at oper_input_base() and count operands
23534 unsigned idx0 = 1;
23535 unsigned idx1 = 1; // src
23536 {
23537 MacroAssembler _masm(&cbuf);
23538
23539#line 6787 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23540
23541 __ popcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23542
23543#line 23543 "ad_x86.cpp"
23544 }
23545}
23546
23547void popCountL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23548 cbuf.set_insts_mark();
23549 // Start at oper_input_base() and count operands
23550 unsigned idx0 = 2;
23551 unsigned idx1 = 2; // mem
23552 {
23553 MacroAssembler _masm(&cbuf);
23554
23555#line 6800 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23556
23557 __ popcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23558
23559#line 23559 "ad_x86.cpp"
23560 }
23561}
23562
23563void membar_acquireNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23564 cbuf.set_insts_mark();
23565 // Start at oper_input_base() and count operands
23566 unsigned idx0 = 1;
23567 unsigned idx1 = 1; //
23568 // User did not define which encode class to use.
23569}
23570
23571uint membar_acquireNode::size(PhaseRegAlloc *ra_) const {
23572 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23573 return (VerifyOops ? MachNode::size(ra_) : 0);
23574}
23575
23576void membar_acquire_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23577 cbuf.set_insts_mark();
23578 // Start at oper_input_base() and count operands
23579 unsigned idx0 = 1;
23580 unsigned idx1 = 1; //
23581 // User did not define which encode class to use.
23582}
23583
23584uint membar_acquire_0Node::size(PhaseRegAlloc *ra_) const {
23585 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23586 return (VerifyOops ? MachNode::size(ra_) : 0);
23587}
23588
23589void membar_acquire_lockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23590 cbuf.set_insts_mark();
23591 // Start at oper_input_base() and count operands
23592 unsigned idx0 = 1;
23593 unsigned idx1 = 1; //
23594 // User did not define which encode class to use.
23595}
23596
23597uint membar_acquire_lockNode::size(PhaseRegAlloc *ra_) const {
23598 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23599 return (VerifyOops ? MachNode::size(ra_) : 0);
23600}
23601
23602void membar_releaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23603 cbuf.set_insts_mark();
23604 // Start at oper_input_base() and count operands
23605 unsigned idx0 = 1;
23606 unsigned idx1 = 1; //
23607 // User did not define which encode class to use.
23608}
23609
23610uint membar_releaseNode::size(PhaseRegAlloc *ra_) const {
23611 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23612 return (VerifyOops ? MachNode::size(ra_) : 0);
23613}
23614
23615void membar_release_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23616 cbuf.set_insts_mark();
23617 // Start at oper_input_base() and count operands
23618 unsigned idx0 = 1;
23619 unsigned idx1 = 1; //
23620 // User did not define which encode class to use.
23621}
23622
23623uint membar_release_0Node::size(PhaseRegAlloc *ra_) const {
23624 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23625 return (VerifyOops ? MachNode::size(ra_) : 0);
23626}
23627
23628void membar_release_lockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23629 cbuf.set_insts_mark();
23630 // Start at oper_input_base() and count operands
23631 unsigned idx0 = 1;
23632 unsigned idx1 = 1; //
23633 // User did not define which encode class to use.
23634}
23635
23636uint membar_release_lockNode::size(PhaseRegAlloc *ra_) const {
23637 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23638 return (VerifyOops ? MachNode::size(ra_) : 0);
23639}
23640
23641void membar_volatileNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23642 cbuf.set_insts_mark();
23643 // Start at oper_input_base() and count operands
23644 unsigned idx0 = 1;
23645 unsigned idx1 = 1; //
23646 {
23647 MacroAssembler _masm(&cbuf);
23648
23649#line 6865 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23650
23651 __ membar(Assembler::StoreLoad);
23652
23653#line 23653 "ad_x86.cpp"
23654 }
23655}
23656
23657void unnecessary_membar_volatileNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23658 cbuf.set_insts_mark();
23659 // Start at oper_input_base() and count operands
23660 unsigned idx0 = 1;
23661 unsigned idx1 = 1; //
23662 // User did not define which encode class to use.
23663}
23664
23665uint unnecessary_membar_volatileNode::size(PhaseRegAlloc *ra_) const {
23666 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23667 return (VerifyOops ? MachNode::size(ra_) : 0);
23668}
23669
23670void membar_storestoreNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23671 cbuf.set_insts_mark();
23672 // Start at oper_input_base() and count operands
23673 unsigned idx0 = 1;
23674 unsigned idx1 = 1; //
23675 // User did not define which encode class to use.
23676}
23677
23678uint membar_storestoreNode::size(PhaseRegAlloc *ra_) const {
23679 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
23680 return (VerifyOops ? MachNode::size(ra_) : 0);
23681}
23682
23683void castX2PNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23684 cbuf.set_insts_mark();
23685 // Start at oper_input_base() and count operands
23686 unsigned idx0 = 1;
23687 unsigned idx1 = 1; // src
23688 {
23689 MacroAssembler _masm(&cbuf);
23690
23691#line 6900 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23692
23693 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
23694 __ movptr(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23695 }
23696
23697#line 23697 "ad_x86.cpp"
23698 }
23699}
23700
23701void castP2XNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23702 cbuf.set_insts_mark();
23703 // Start at oper_input_base() and count operands
23704 unsigned idx0 = 1;
23705 unsigned idx1 = 1; // src
23706 {
23707 MacroAssembler _masm(&cbuf);
23708
23709#line 6913 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23710
23711 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
23712 __ movptr(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23713 }
23714
23715#line 23715 "ad_x86.cpp"
23716 }
23717}
23718
23719void convP2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23720 cbuf.set_insts_mark();
23721 // Start at oper_input_base() and count operands
23722 unsigned idx0 = 1;
23723 unsigned idx1 = 1; // src
23724 {
23725 MacroAssembler _masm(&cbuf);
23726
23727#line 6927 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23728
23729 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23730
23731#line 23731 "ad_x86.cpp"
23732 }
23733}
23734
23735void convN2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23736 cbuf.set_insts_mark();
23737 // Start at oper_input_base() and count operands
23738 unsigned idx0 = 1;
23739 unsigned idx1 = 1; // src
23740 {
23741 MacroAssembler _masm(&cbuf);
23742
23743#line 6941 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23744
23745 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23746
23747#line 23747 "ad_x86.cpp"
23748 }
23749}
23750
23751void encodeHeapOopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23752 cbuf.set_insts_mark();
23753 // Start at oper_input_base() and count operands
23754 unsigned idx0 = 1;
23755 unsigned idx1 = 1; // src
23756 {
23757 MacroAssembler _masm(&cbuf);
23758
23759#line 6953 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23760
23761 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23762 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
23763 if (s != d) {
23764 __ movq(d, s);
23765 }
23766 __ encode_heap_oop(d);
23767
23768#line 23768 "ad_x86.cpp"
23769 }
23770}
23771
23772void encodeHeapOop_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23773 cbuf.set_insts_mark();
23774 // Start at oper_input_base() and count operands
23775 unsigned idx0 = 1;
23776 unsigned idx1 = 1; // src
23777 {
23778 MacroAssembler _masm(&cbuf);
23779
23780#line 6969 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23781
23782 __ encode_heap_oop_not_null(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23783
23784#line 23784 "ad_x86.cpp"
23785 }
23786}
23787
23788void decodeHeapOopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23789 cbuf.set_insts_mark();
23790 // Start at oper_input_base() and count operands
23791 unsigned idx0 = 1;
23792 unsigned idx1 = 1; // src
23793 {
23794 MacroAssembler _masm(&cbuf);
23795
23796#line 6981 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23797
23798 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23799 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
23800 if (s != d) {
23801 __ movq(d, s);
23802 }
23803 __ decode_heap_oop(d);
23804
23805#line 23805 "ad_x86.cpp"
23806 }
23807}
23808
23809void decodeHeapOop_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23810 cbuf.set_insts_mark();
23811 // Start at oper_input_base() and count operands
23812 unsigned idx0 = 1;
23813 unsigned idx1 = 1; // src
23814 {
23815 MacroAssembler _masm(&cbuf);
23816
23817#line 6998 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23818
23819 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23820 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
23821 if (s != d) {
23822 __ decode_heap_oop_not_null(d, s);
23823 } else {
23824 __ decode_heap_oop_not_null(d);
23825 }
23826
23827#line 23827 "ad_x86.cpp"
23828 }
23829}
23830
23831void encodeKlass_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23832 cbuf.set_insts_mark();
23833 // Start at oper_input_base() and count operands
23834 unsigned idx0 = 1;
23835 unsigned idx1 = 1; // src
23836 {
23837 MacroAssembler _masm(&cbuf);
23838
23839#line 7014 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23840
23841 __ encode_klass_not_null(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23842
23843#line 23843 "ad_x86.cpp"
23844 }
23845}
23846
23847void decodeKlass_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23848 cbuf.set_insts_mark();
23849 // Start at oper_input_base() and count operands
23850 unsigned idx0 = 1;
23851 unsigned idx1 = 1; // src
23852 {
23853 MacroAssembler _masm(&cbuf);
23854
23855#line 7024 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23856
23857 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
23858 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
23859 if (s != d) {
23860 __ decode_klass_not_null(d, s);
23861 } else {
23862 __ decode_klass_not_null(d);
23863 }
23864
23865#line 23865 "ad_x86.cpp"
23866 }
23867}
23868
23869void jumpXtnd_offsetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23870 cbuf.set_insts_mark();
23871 ra_->C->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
23872 // Start at oper_input_base() and count operands
23873 unsigned idx0 = 1;
23874 unsigned idx1 = 1; // shift
23875 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dest
23876 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
23877 {
23878 MacroAssembler _masm(&cbuf);
23879
23880#line 7048 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23881
23882 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
23883 // to do that and the compiler is using that register as one it can allocate.
23884 // So we build it all by hand.
23885 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
23886 // ArrayAddress dispatch(table, index);
23887 Address dispatch(opnd_array(3)->as_Register(ra_,this,idx3)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, (Address::ScaleFactor) opnd_array(2)->constant());
23888 __ lea(opnd_array(3)->as_Register(ra_,this,idx3)/* dest */, InternalAddress(__ code()->consts()->start() + constant_offset()));
23889 __ jmp(dispatch);
23890
23891#line 23891 "ad_x86.cpp"
23892 }
23893}
23894
23895void jumpXtnd_offsetNode::eval_constant(Compile* C) {
23896 _constant = C->constant_table().add_jump_table(this);
23897 // User did not define an encode section.
23898}
23899void jumpXtnd_addrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23900 cbuf.set_insts_mark();
23901 ra_->C->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
23902 // Start at oper_input_base() and count operands
23903 unsigned idx0 = 1;
23904 unsigned idx1 = 1; // shift
23905 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // offset
23906 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dest
23907 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
23908 {
23909 MacroAssembler _masm(&cbuf);
23910
23911#line 7068 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23912
23913 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
23914 // to do that and the compiler is using that register as one it can allocate.
23915 // So we build it all by hand.
23916 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
23917 // ArrayAddress dispatch(table, index);
23918 Address dispatch(opnd_array(4)->as_Register(ra_,this,idx4)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, (Address::ScaleFactor) opnd_array(2)->constant(), (int) opnd_array(3)->constantL());
23919 __ lea(opnd_array(4)->as_Register(ra_,this,idx4)/* dest */, InternalAddress(__ code()->consts()->start() + constant_offset()));
23920 __ jmp(dispatch);
23921
23922#line 23922 "ad_x86.cpp"
23923 }
23924}
23925
23926void jumpXtnd_addrNode::eval_constant(Compile* C) {
23927 _constant = C->constant_table().add_jump_table(this);
23928 // User did not define an encode section.
23929}
23930void jumpXtndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23931 cbuf.set_insts_mark();
23932 ra_->C->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
23933 // Start at oper_input_base() and count operands
23934 unsigned idx0 = 1;
23935 unsigned idx1 = 1; // dest
23936 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
23937 {
23938 MacroAssembler _masm(&cbuf);
23939
23940#line 7088 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23941
23942 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
23943 // to do that and the compiler is using that register as one it can allocate.
23944 // So we build it all by hand.
23945 // Address index(noreg, switch_reg, Address::times_1);
23946 // ArrayAddress dispatch(table, index);
23947 Address dispatch(opnd_array(2)->as_Register(ra_,this,idx2)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, Address::times_1);
23948 __ lea(opnd_array(2)->as_Register(ra_,this,idx2)/* dest */, InternalAddress(__ code()->consts()->start() + constant_offset()));
23949 __ jmp(dispatch);
23950
23951#line 23951 "ad_x86.cpp"
23952 }
23953}
23954
23955void jumpXtndNode::eval_constant(Compile* C) {
23956 _constant = C->constant_table().add_jump_table(this);
23957 // User did not define an encode section.
23958}
23959void cmovI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23960 cbuf.set_insts_mark();
23961 // Start at oper_input_base() and count operands
23962 unsigned idx0 = 1;
23963 unsigned idx1 = 1; // cop
23964 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
23965 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23966 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
23967 {
23968
23969#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23970
23971 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
23972 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ >= 8) {
23973 emit_opcode(cbuf, Assembler::REX_B);
23974 }
23975 } else {
23976 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
23977 emit_opcode(cbuf, Assembler::REX_R);
23978 } else {
23979 emit_opcode(cbuf, Assembler::REX_RB);
23980 }
23981 }
23982
23983#line 23983 "ad_x86.cpp"
23984 }
23985 {
23986
23987#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23988
23989 // CMOV
23990 emit_d8(cbuf, (0x0F /*primary()*/));
23991 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
23992
23993#line 23993 "ad_x86.cpp"
23994 }
23995 {
23996
23997#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
23998
23999 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24000
24001#line 24001 "ad_x86.cpp"
24002 }
24003}
24004
24005void cmovI_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24006 cbuf.set_insts_mark();
24007 // Start at oper_input_base() and count operands
24008 unsigned idx0 = 1;
24009 unsigned idx1 = 1; // cop
24010 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24011 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24012 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24013 {
24014
24015#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24016
24017 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24018 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ >= 8) {
24019 emit_opcode(cbuf, Assembler::REX_B);
24020 }
24021 } else {
24022 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24023 emit_opcode(cbuf, Assembler::REX_R);
24024 } else {
24025 emit_opcode(cbuf, Assembler::REX_RB);
24026 }
24027 }
24028
24029#line 24029 "ad_x86.cpp"
24030 }
24031 {
24032
24033#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24034
24035 // CMOV
24036 emit_d8(cbuf, (0x0F /*primary()*/));
24037 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24038
24039#line 24039 "ad_x86.cpp"
24040 }
24041 {
24042
24043#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24044
24045 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24046
24047#line 24047 "ad_x86.cpp"
24048 }
24049}
24050
24051void cmovI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24052 cbuf.set_insts_mark();
24053 // Start at oper_input_base() and count operands
24054 unsigned idx0 = 2;
24055 unsigned idx1 = 2; // cop
24056 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24057 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24058 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24059 {
24060
24061#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24062
24063 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24064 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24065 if (opnd_array(4)->index(ra_,this,idx4) >= 8) {
24066 emit_opcode(cbuf, Assembler::REX_X);
24067 }
24068 } else {
24069 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24070 emit_opcode(cbuf, Assembler::REX_B);
24071 } else {
24072 emit_opcode(cbuf, Assembler::REX_XB);
24073 }
24074 }
24075 } else {
24076 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24077 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24078 emit_opcode(cbuf, Assembler::REX_R);
24079 } else {
24080 emit_opcode(cbuf, Assembler::REX_RX);
24081 }
24082 } else {
24083 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24084 emit_opcode(cbuf, Assembler::REX_RB);
24085 } else {
24086 emit_opcode(cbuf, Assembler::REX_RXB);
24087 }
24088 }
24089 }
24090
24091#line 24091 "ad_x86.cpp"
24092 }
24093 {
24094
24095#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24096
24097 // CMOV
24098 emit_d8(cbuf, (0x0F /*primary()*/));
24099 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24100
24101#line 24101 "ad_x86.cpp"
24102 }
24103 {
24104
24105#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24106
24107 // High registers handle in encode_RegMem
24108 int reg = opnd_array(3)->reg(ra_,this,idx3)/* dst */;
24109 int base = opnd_array(4)->base(ra_,this,idx4);
24110 int index = opnd_array(4)->index(ra_,this,idx4);
24111 int scale = opnd_array(4)->scale();
24112 int disp = opnd_array(4)->disp(ra_,this,idx4);
24113 relocInfo::relocType disp_reloc = opnd_array(4)->disp_reloc();
24114
24115 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24116
24117#line 24117 "ad_x86.cpp"
24118 }
24119}
24120
24121void cmovI_memUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24122 cbuf.set_insts_mark();
24123 // Start at oper_input_base() and count operands
24124 unsigned idx0 = 2;
24125 unsigned idx1 = 2; // cop
24126 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24127 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24128 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24129 {
24130
24131#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24132
24133 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24134 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24135 if (opnd_array(4)->index(ra_,this,idx4) >= 8) {
24136 emit_opcode(cbuf, Assembler::REX_X);
24137 }
24138 } else {
24139 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24140 emit_opcode(cbuf, Assembler::REX_B);
24141 } else {
24142 emit_opcode(cbuf, Assembler::REX_XB);
24143 }
24144 }
24145 } else {
24146 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24147 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24148 emit_opcode(cbuf, Assembler::REX_R);
24149 } else {
24150 emit_opcode(cbuf, Assembler::REX_RX);
24151 }
24152 } else {
24153 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24154 emit_opcode(cbuf, Assembler::REX_RB);
24155 } else {
24156 emit_opcode(cbuf, Assembler::REX_RXB);
24157 }
24158 }
24159 }
24160
24161#line 24161 "ad_x86.cpp"
24162 }
24163 {
24164
24165#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24166
24167 // CMOV
24168 emit_d8(cbuf, (0x0F /*primary()*/));
24169 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24170
24171#line 24171 "ad_x86.cpp"
24172 }
24173 {
24174
24175#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24176
24177 // High registers handle in encode_RegMem
24178 int reg = opnd_array(3)->reg(ra_,this,idx3)/* dst */;
24179 int base = opnd_array(4)->base(ra_,this,idx4);
24180 int index = opnd_array(4)->index(ra_,this,idx4);
24181 int scale = opnd_array(4)->scale();
24182 int disp = opnd_array(4)->disp(ra_,this,idx4);
24183 relocInfo::relocType disp_reloc = opnd_array(4)->disp_reloc();
24184
24185 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24186
24187#line 24187 "ad_x86.cpp"
24188 }
24189}
24190
24191void cmovN_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24192 cbuf.set_insts_mark();
24193 // Start at oper_input_base() and count operands
24194 unsigned idx0 = 1;
24195 unsigned idx1 = 1; // cop
24196 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24197 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24198 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24199 {
24200
24201#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24202
24203 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24204 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ >= 8) {
24205 emit_opcode(cbuf, Assembler::REX_B);
24206 }
24207 } else {
24208 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24209 emit_opcode(cbuf, Assembler::REX_R);
24210 } else {
24211 emit_opcode(cbuf, Assembler::REX_RB);
24212 }
24213 }
24214
24215#line 24215 "ad_x86.cpp"
24216 }
24217 {
24218
24219#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24220
24221 // CMOV
24222 emit_d8(cbuf, (0x0F /*primary()*/));
24223 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24224
24225#line 24225 "ad_x86.cpp"
24226 }
24227 {
24228
24229#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24230
24231 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24232
24233#line 24233 "ad_x86.cpp"
24234 }
24235}
24236
24237void cmovN_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24238 cbuf.set_insts_mark();
24239 // Start at oper_input_base() and count operands
24240 unsigned idx0 = 1;
24241 unsigned idx1 = 1; // cop
24242 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24243 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24244 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24245 {
24246
24247#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24248
24249 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24250 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ >= 8) {
24251 emit_opcode(cbuf, Assembler::REX_B);
24252 }
24253 } else {
24254 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24255 emit_opcode(cbuf, Assembler::REX_R);
24256 } else {
24257 emit_opcode(cbuf, Assembler::REX_RB);
24258 }
24259 }
24260
24261#line 24261 "ad_x86.cpp"
24262 }
24263 {
24264
24265#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24266
24267 // CMOV
24268 emit_d8(cbuf, (0x0F /*primary()*/));
24269 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24270
24271#line 24271 "ad_x86.cpp"
24272 }
24273 {
24274
24275#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24276
24277 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24278
24279#line 24279 "ad_x86.cpp"
24280 }
24281}
24282
24283void cmovP_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24284 cbuf.set_insts_mark();
24285 // Start at oper_input_base() and count operands
24286 unsigned idx0 = 1;
24287 unsigned idx1 = 1; // cop
24288 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24289 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24290 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24291 {
24292
24293#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24294
24295 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24296 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24297 emit_opcode(cbuf, Assembler::REX_W);
24298 } else {
24299 emit_opcode(cbuf, Assembler::REX_WB);
24300 }
24301 } else {
24302 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24303 emit_opcode(cbuf, Assembler::REX_WR);
24304 } else {
24305 emit_opcode(cbuf, Assembler::REX_WRB);
24306 }
24307 }
24308
24309#line 24309 "ad_x86.cpp"
24310 }
24311 {
24312
24313#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24314
24315 // CMOV
24316 emit_d8(cbuf, (0x0F /*primary()*/));
24317 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24318
24319#line 24319 "ad_x86.cpp"
24320 }
24321 {
24322
24323#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24324
24325 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24326
24327#line 24327 "ad_x86.cpp"
24328 }
24329}
24330
24331void cmovP_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24332 cbuf.set_insts_mark();
24333 // Start at oper_input_base() and count operands
24334 unsigned idx0 = 1;
24335 unsigned idx1 = 1; // cop
24336 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24337 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24338 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24339 {
24340
24341#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24342
24343 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24344 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24345 emit_opcode(cbuf, Assembler::REX_W);
24346 } else {
24347 emit_opcode(cbuf, Assembler::REX_WB);
24348 }
24349 } else {
24350 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24351 emit_opcode(cbuf, Assembler::REX_WR);
24352 } else {
24353 emit_opcode(cbuf, Assembler::REX_WRB);
24354 }
24355 }
24356
24357#line 24357 "ad_x86.cpp"
24358 }
24359 {
24360
24361#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24362
24363 // CMOV
24364 emit_d8(cbuf, (0x0F /*primary()*/));
24365 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24366
24367#line 24367 "ad_x86.cpp"
24368 }
24369 {
24370
24371#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24372
24373 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24374
24375#line 24375 "ad_x86.cpp"
24376 }
24377}
24378
24379void cmovL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24380 cbuf.set_insts_mark();
24381 // Start at oper_input_base() and count operands
24382 unsigned idx0 = 1;
24383 unsigned idx1 = 1; // cop
24384 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24385 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24386 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24387 {
24388
24389#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24390
24391 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24392 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24393 emit_opcode(cbuf, Assembler::REX_W);
24394 } else {
24395 emit_opcode(cbuf, Assembler::REX_WB);
24396 }
24397 } else {
24398 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24399 emit_opcode(cbuf, Assembler::REX_WR);
24400 } else {
24401 emit_opcode(cbuf, Assembler::REX_WRB);
24402 }
24403 }
24404
24405#line 24405 "ad_x86.cpp"
24406 }
24407 {
24408
24409#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24410
24411 // CMOV
24412 emit_d8(cbuf, (0x0F /*primary()*/));
24413 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24414
24415#line 24415 "ad_x86.cpp"
24416 }
24417 {
24418
24419#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24420
24421 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24422
24423#line 24423 "ad_x86.cpp"
24424 }
24425}
24426
24427void cmovL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24428 cbuf.set_insts_mark();
24429 // Start at oper_input_base() and count operands
24430 unsigned idx0 = 2;
24431 unsigned idx1 = 2; // cop
24432 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24433 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24434 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24435 {
24436
24437#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24438
24439 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24440 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24441 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24442 emit_opcode(cbuf, Assembler::REX_W);
24443 } else {
24444 emit_opcode(cbuf, Assembler::REX_WX);
24445 }
24446 } else {
24447 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24448 emit_opcode(cbuf, Assembler::REX_WB);
24449 } else {
24450 emit_opcode(cbuf, Assembler::REX_WXB);
24451 }
24452 }
24453 } else {
24454 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24455 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24456 emit_opcode(cbuf, Assembler::REX_WR);
24457 } else {
24458 emit_opcode(cbuf, Assembler::REX_WRX);
24459 }
24460 } else {
24461 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24462 emit_opcode(cbuf, Assembler::REX_WRB);
24463 } else {
24464 emit_opcode(cbuf, Assembler::REX_WRXB);
24465 }
24466 }
24467 }
24468
24469#line 24469 "ad_x86.cpp"
24470 }
24471 {
24472
24473#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24474
24475 // CMOV
24476 emit_d8(cbuf, (0x0F /*primary()*/));
24477 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24478
24479#line 24479 "ad_x86.cpp"
24480 }
24481 {
24482
24483#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24484
24485 // High registers handle in encode_RegMem
24486 int reg = opnd_array(3)->reg(ra_,this,idx3)/* dst */;
24487 int base = opnd_array(4)->base(ra_,this,idx4);
24488 int index = opnd_array(4)->index(ra_,this,idx4);
24489 int scale = opnd_array(4)->scale();
24490 int disp = opnd_array(4)->disp(ra_,this,idx4);
24491 relocInfo::relocType disp_reloc = opnd_array(4)->disp_reloc();
24492
24493 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24494
24495#line 24495 "ad_x86.cpp"
24496 }
24497}
24498
24499void cmovL_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24500 cbuf.set_insts_mark();
24501 // Start at oper_input_base() and count operands
24502 unsigned idx0 = 1;
24503 unsigned idx1 = 1; // cop
24504 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24505 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24506 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24507 {
24508
24509#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24510
24511 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24512 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24513 emit_opcode(cbuf, Assembler::REX_W);
24514 } else {
24515 emit_opcode(cbuf, Assembler::REX_WB);
24516 }
24517 } else {
24518 if (opnd_array(4)->reg(ra_,this,idx4)/* src */ < 8) {
24519 emit_opcode(cbuf, Assembler::REX_WR);
24520 } else {
24521 emit_opcode(cbuf, Assembler::REX_WRB);
24522 }
24523 }
24524
24525#line 24525 "ad_x86.cpp"
24526 }
24527 {
24528
24529#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24530
24531 // CMOV
24532 emit_d8(cbuf, (0x0F /*primary()*/));
24533 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24534
24535#line 24535 "ad_x86.cpp"
24536 }
24537 {
24538
24539#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24540
24541 emit_rm(cbuf, 0x3, opnd_array(3)->reg(ra_,this,idx3)/* dst */ & 7, opnd_array(4)->reg(ra_,this,idx4)/* src */ & 7);
24542
24543#line 24543 "ad_x86.cpp"
24544 }
24545}
24546
24547void cmovL_memUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24548 cbuf.set_insts_mark();
24549 // Start at oper_input_base() and count operands
24550 unsigned idx0 = 2;
24551 unsigned idx1 = 2; // cop
24552 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24553 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24554 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24555 {
24556
24557#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24558
24559 if (opnd_array(3)->reg(ra_,this,idx3)/* dst */ < 8) {
24560 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24561 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24562 emit_opcode(cbuf, Assembler::REX_W);
24563 } else {
24564 emit_opcode(cbuf, Assembler::REX_WX);
24565 }
24566 } else {
24567 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24568 emit_opcode(cbuf, Assembler::REX_WB);
24569 } else {
24570 emit_opcode(cbuf, Assembler::REX_WXB);
24571 }
24572 }
24573 } else {
24574 if (opnd_array(4)->base(ra_,this,idx4) < 8) {
24575 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24576 emit_opcode(cbuf, Assembler::REX_WR);
24577 } else {
24578 emit_opcode(cbuf, Assembler::REX_WRX);
24579 }
24580 } else {
24581 if (opnd_array(4)->index(ra_,this,idx4) < 8) {
24582 emit_opcode(cbuf, Assembler::REX_WRB);
24583 } else {
24584 emit_opcode(cbuf, Assembler::REX_WRXB);
24585 }
24586 }
24587 }
24588
24589#line 24589 "ad_x86.cpp"
24590 }
24591 {
24592
24593#line 2076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24594
24595 // CMOV
24596 emit_d8(cbuf, (0x0F /*primary()*/));
24597 emit_cc(cbuf, (0x40 /*secondary()*/), opnd_array(1)->ccode());
24598
24599#line 24599 "ad_x86.cpp"
24600 }
24601 {
24602
24603#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24604
24605 // High registers handle in encode_RegMem
24606 int reg = opnd_array(3)->reg(ra_,this,idx3)/* dst */;
24607 int base = opnd_array(4)->base(ra_,this,idx4);
24608 int index = opnd_array(4)->index(ra_,this,idx4);
24609 int scale = opnd_array(4)->scale();
24610 int disp = opnd_array(4)->disp(ra_,this,idx4);
24611 relocInfo::relocType disp_reloc = opnd_array(4)->disp_reloc();
24612
24613 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24614
24615#line 24615 "ad_x86.cpp"
24616 }
24617}
24618
24619void cmovF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24620 cbuf.set_insts_mark();
24621 // Start at oper_input_base() and count operands
24622 unsigned idx0 = 1;
24623 unsigned idx1 = 1; // cop
24624 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24625 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24626 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24627 {
24628 MacroAssembler _masm(&cbuf);
24629
24630#line 7321 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24631
24632 Label Lskip;
24633 // Invert sense of branch from sense of CMOV
24634 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip);
24635 __ movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
24636 __ bind(Lskip);
24637
24638#line 24638 "ad_x86.cpp"
24639 }
24640}
24641
24642void cmovF_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24643 cbuf.set_insts_mark();
24644 // Start at oper_input_base() and count operands
24645 unsigned idx0 = 1;
24646 unsigned idx1 = 1; // cop
24647 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24648 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24649 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24650 {
24651 MacroAssembler _masm(&cbuf);
24652
24653#line 7351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24654
24655 Label Lskip;
24656 // Invert sense of branch from sense of CMOV
24657 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip);
24658 __ movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
24659 __ bind(Lskip);
24660
24661#line 24661 "ad_x86.cpp"
24662 }
24663}
24664
24665void cmovD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24666 cbuf.set_insts_mark();
24667 // Start at oper_input_base() and count operands
24668 unsigned idx0 = 1;
24669 unsigned idx1 = 1; // cop
24670 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24671 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24672 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24673 {
24674 MacroAssembler _masm(&cbuf);
24675
24676#line 7377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24677
24678 Label Lskip;
24679 // Invert sense of branch from sense of CMOV
24680 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip);
24681 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
24682 __ bind(Lskip);
24683
24684#line 24684 "ad_x86.cpp"
24685 }
24686}
24687
24688void cmovD_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24689 cbuf.set_insts_mark();
24690 // Start at oper_input_base() and count operands
24691 unsigned idx0 = 1;
24692 unsigned idx1 = 1; // cop
24693 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
24694 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24695 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
24696 {
24697 MacroAssembler _masm(&cbuf);
24698
24699#line 7395 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24700
24701 Label Lskip;
24702 // Invert sense of branch from sense of CMOV
24703 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip);
24704 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
24705 __ bind(Lskip);
24706
24707#line 24707 "ad_x86.cpp"
24708 }
24709}
24710
24711void addI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24712 cbuf.set_insts_mark();
24713 // Start at oper_input_base() and count operands
24714 unsigned idx0 = 1;
24715 unsigned idx1 = 1; // dst
24716 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24717 {
24718
24719#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24720
24721 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
24722 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
24723 emit_opcode(cbuf, Assembler::REX_B);
24724 }
24725 } else {
24726 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
24727 emit_opcode(cbuf, Assembler::REX_R);
24728 } else {
24729 emit_opcode(cbuf, Assembler::REX_RB);
24730 }
24731 }
24732
24733#line 24733 "ad_x86.cpp"
24734 }
24735 {
24736
24737#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24738
24739 emit_opcode(cbuf, (0x03 /*primary()*/));
24740
24741#line 24741 "ad_x86.cpp"
24742 }
24743 {
24744
24745#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24746
24747 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
24748
24749#line 24749 "ad_x86.cpp"
24750 }
24751}
24752
24753void addI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24754 cbuf.set_insts_mark();
24755 // Start at oper_input_base() and count operands
24756 unsigned idx0 = 1;
24757 unsigned idx1 = 1; // dst
24758 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24759 {
24760
24761#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24762
24763 // OpcSEr/m
24764 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
24765 if (dstenc >= 8) {
24766 emit_opcode(cbuf, Assembler::REX_B);
24767 dstenc -= 8;
24768 }
24769 // Emit primary opcode and set sign-extend bit
24770 // Check for 8-bit immediate, and set sign extend bit in opcode
24771 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
24772 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
24773 } else {
24774 // 32-bit immediate
24775 emit_opcode(cbuf, (0x81 /*primary()*/));
24776 }
24777 // Emit r/m byte with secondary opcode, after primary opcode.
24778 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), dstenc);
24779
24780#line 24780 "ad_x86.cpp"
24781 }
24782 {
24783
24784#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24785
24786 // Check for 8-bit immediate, and set sign extend bit in opcode
24787 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
24788 emit_d8(cbuf, opnd_array(2)->constant());
24789 } else {
24790 // 32-bit immediate
24791 emit_d32(cbuf, opnd_array(2)->constant());
24792 }
24793
24794#line 24794 "ad_x86.cpp"
24795 }
24796}
24797
24798void addI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24799 cbuf.set_insts_mark();
24800 // Start at oper_input_base() and count operands
24801 unsigned idx0 = 2;
24802 unsigned idx1 = 2; // dst
24803 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24804 {
24805
24806#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24807
24808 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
24809 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
24810 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
24811 emit_opcode(cbuf, Assembler::REX_X);
24812 }
24813 } else {
24814 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
24815 emit_opcode(cbuf, Assembler::REX_B);
24816 } else {
24817 emit_opcode(cbuf, Assembler::REX_XB);
24818 }
24819 }
24820 } else {
24821 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
24822 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
24823 emit_opcode(cbuf, Assembler::REX_R);
24824 } else {
24825 emit_opcode(cbuf, Assembler::REX_RX);
24826 }
24827 } else {
24828 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
24829 emit_opcode(cbuf, Assembler::REX_RB);
24830 } else {
24831 emit_opcode(cbuf, Assembler::REX_RXB);
24832 }
24833 }
24834 }
24835
24836#line 24836 "ad_x86.cpp"
24837 }
24838 {
24839
24840#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24841
24842 emit_opcode(cbuf, (0x03 /*primary()*/));
24843
24844#line 24844 "ad_x86.cpp"
24845 }
24846 {
24847
24848#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24849
24850 // High registers handle in encode_RegMem
24851 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
24852 int base = opnd_array(2)->base(ra_,this,idx2);
24853 int index = opnd_array(2)->index(ra_,this,idx2);
24854 int scale = opnd_array(2)->scale();
24855 int disp = opnd_array(2)->disp(ra_,this,idx2);
24856 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
24857
24858 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24859
24860#line 24860 "ad_x86.cpp"
24861 }
24862}
24863
24864void addI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24865 cbuf.set_insts_mark();
24866 // Start at oper_input_base() and count operands
24867 unsigned idx0 = 2;
24868 unsigned idx1 = 2; // src
24869 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
24870 {
24871
24872#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24873
24874 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
24875 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
24876 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
24877 emit_opcode(cbuf, Assembler::REX_X);
24878 }
24879 } else {
24880 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24881 emit_opcode(cbuf, Assembler::REX_B);
24882 } else {
24883 emit_opcode(cbuf, Assembler::REX_XB);
24884 }
24885 }
24886 } else {
24887 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
24888 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24889 emit_opcode(cbuf, Assembler::REX_R);
24890 } else {
24891 emit_opcode(cbuf, Assembler::REX_RX);
24892 }
24893 } else {
24894 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24895 emit_opcode(cbuf, Assembler::REX_RB);
24896 } else {
24897 emit_opcode(cbuf, Assembler::REX_RXB);
24898 }
24899 }
24900 }
24901
24902#line 24902 "ad_x86.cpp"
24903 }
24904 {
24905
24906#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24907
24908 emit_opcode(cbuf, (0x03 /*primary()*/));
24909
24910#line 24910 "ad_x86.cpp"
24911 }
24912 {
24913
24914#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24915
24916 // High registers handle in encode_RegMem
24917 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
24918 int base = opnd_array(1)->base(ra_,this,idx1);
24919 int index = opnd_array(1)->index(ra_,this,idx1);
24920 int scale = opnd_array(1)->scale();
24921 int disp = opnd_array(1)->disp(ra_,this,idx1);
24922 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
24923
24924 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24925
24926#line 24926 "ad_x86.cpp"
24927 }
24928}
24929
24930void addI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24931 cbuf.set_insts_mark();
24932 // Start at oper_input_base() and count operands
24933 unsigned idx0 = 2;
24934 unsigned idx1 = 2; // dst
24935 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24936 {
24937
24938#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24939
24940 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
24941 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
24942 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
24943 emit_opcode(cbuf, Assembler::REX_X);
24944 }
24945 } else {
24946 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24947 emit_opcode(cbuf, Assembler::REX_B);
24948 } else {
24949 emit_opcode(cbuf, Assembler::REX_XB);
24950 }
24951 }
24952 } else {
24953 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
24954 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24955 emit_opcode(cbuf, Assembler::REX_R);
24956 } else {
24957 emit_opcode(cbuf, Assembler::REX_RX);
24958 }
24959 } else {
24960 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
24961 emit_opcode(cbuf, Assembler::REX_RB);
24962 } else {
24963 emit_opcode(cbuf, Assembler::REX_RXB);
24964 }
24965 }
24966 }
24967
24968#line 24968 "ad_x86.cpp"
24969 }
24970 {
24971
24972#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24973
24974 emit_opcode(cbuf, (0x01 /*primary()*/));
24975
24976#line 24976 "ad_x86.cpp"
24977 }
24978 {
24979
24980#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
24981
24982 // High registers handle in encode_RegMem
24983 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
24984 int base = opnd_array(1)->base(ra_,this,idx1);
24985 int index = opnd_array(1)->index(ra_,this,idx1);
24986 int scale = opnd_array(1)->scale();
24987 int disp = opnd_array(1)->disp(ra_,this,idx1);
24988 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
24989
24990 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
24991
24992#line 24992 "ad_x86.cpp"
24993 }
24994}
24995
24996void addI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24997 cbuf.set_insts_mark();
24998 // Start at oper_input_base() and count operands
24999 unsigned idx0 = 2;
25000 unsigned idx1 = 2; // dst
25001 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25002 {
25003
25004#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25005
25006 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
25007 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25008 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
25009 emit_opcode(cbuf, Assembler::REX_X);
25010 }
25011 } else {
25012 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25013 emit_opcode(cbuf, Assembler::REX_B);
25014 } else {
25015 emit_opcode(cbuf, Assembler::REX_XB);
25016 }
25017 }
25018 } else {
25019 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25020 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25021 emit_opcode(cbuf, Assembler::REX_R);
25022 } else {
25023 emit_opcode(cbuf, Assembler::REX_RX);
25024 }
25025 } else {
25026 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25027 emit_opcode(cbuf, Assembler::REX_RB);
25028 } else {
25029 emit_opcode(cbuf, Assembler::REX_RXB);
25030 }
25031 }
25032 }
25033
25034#line 25034 "ad_x86.cpp"
25035 }
25036 {
25037
25038#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25039
25040 emit_opcode(cbuf, (0x01 /*primary()*/));
25041
25042#line 25042 "ad_x86.cpp"
25043 }
25044 {
25045
25046#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25047
25048 // High registers handle in encode_RegMem
25049 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
25050 int base = opnd_array(1)->base(ra_,this,idx1);
25051 int index = opnd_array(1)->index(ra_,this,idx1);
25052 int scale = opnd_array(1)->scale();
25053 int disp = opnd_array(1)->disp(ra_,this,idx1);
25054 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
25055
25056 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
25057
25058#line 25058 "ad_x86.cpp"
25059 }
25060}
25061
25062void addI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25063 cbuf.set_insts_mark();
25064 // Start at oper_input_base() and count operands
25065 unsigned idx0 = 2;
25066 unsigned idx1 = 2; // dst
25067 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25068 {
25069
25070#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25071
25072 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25073 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25074 emit_opcode(cbuf, Assembler::REX_B);
25075 } else {
25076 emit_opcode(cbuf, Assembler::REX_XB);
25077 }
25078 } else {
25079 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
25080 emit_opcode(cbuf, Assembler::REX_X);
25081 }
25082 }
25083
25084#line 25084 "ad_x86.cpp"
25085 }
25086 {
25087
25088#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25089
25090 // Emit primary opcode and set sign-extend bit
25091 // Check for 8-bit immediate, and set sign extend bit in opcode
25092 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
25093 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
25094 } else {
25095 // 32-bit immediate
25096 emit_opcode(cbuf, (0x81 /*primary()*/));
25097 }
25098
25099#line 25099 "ad_x86.cpp"
25100 }
25101 {
25102
25103#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25104
25105 int rm_byte_opcode = (0x00);
25106
25107 // High registers handle in encode_RegMem
25108 int base = opnd_array(1)->base(ra_,this,idx1);
25109 int index = opnd_array(1)->index(ra_,this,idx1);
25110 int scale = opnd_array(1)->scale();
25111 int displace = opnd_array(1)->disp(ra_,this,idx1);
25112
25113 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25114 // working with static
25115 // globals
25116 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25117 disp_reloc);
25118
25119#line 25119 "ad_x86.cpp"
25120 }
25121 {
25122
25123#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25124
25125 // Check for 8-bit immediate, and set sign extend bit in opcode
25126 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
25127 emit_d8(cbuf, opnd_array(2)->constant());
25128 } else {
25129 // 32-bit immediate
25130 emit_d32(cbuf, opnd_array(2)->constant());
25131 }
25132
25133#line 25133 "ad_x86.cpp"
25134 }
25135}
25136
25137void incI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25138 cbuf.set_insts_mark();
25139 // Start at oper_input_base() and count operands
25140 unsigned idx0 = 1;
25141 unsigned idx1 = 1; // dst
25142 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25143 {
25144
25145#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25146
25147 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
25148 emit_opcode(cbuf, Assembler::REX_B);
25149 }
25150
25151#line 25151 "ad_x86.cpp"
25152 }
25153 {
25154
25155#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25156
25157 emit_opcode(cbuf, (0xFF /*primary()*/));
25158
25159#line 25159 "ad_x86.cpp"
25160 }
25161 {
25162
25163#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25164
25165 // INC, DEC, IDIV, IMOD, JMP indirect, ...
25166 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
25167
25168#line 25168 "ad_x86.cpp"
25169 }
25170}
25171
25172void incI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25173 cbuf.set_insts_mark();
25174 // Start at oper_input_base() and count operands
25175 unsigned idx0 = 2;
25176 unsigned idx1 = 2; // dst
25177 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25178 {
25179
25180#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25181
25182 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25183 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25184 emit_opcode(cbuf, Assembler::REX_B);
25185 } else {
25186 emit_opcode(cbuf, Assembler::REX_XB);
25187 }
25188 } else {
25189 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
25190 emit_opcode(cbuf, Assembler::REX_X);
25191 }
25192 }
25193
25194#line 25194 "ad_x86.cpp"
25195 }
25196 {
25197
25198#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25199
25200 emit_opcode(cbuf, (0xFF /*primary()*/));
25201
25202#line 25202 "ad_x86.cpp"
25203 }
25204 {
25205
25206#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25207
25208 int rm_byte_opcode = (0x00);
25209
25210 // High registers handle in encode_RegMem
25211 int base = opnd_array(1)->base(ra_,this,idx1);
25212 int index = opnd_array(1)->index(ra_,this,idx1);
25213 int scale = opnd_array(1)->scale();
25214 int displace = opnd_array(1)->disp(ra_,this,idx1);
25215
25216 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25217 // working with static
25218 // globals
25219 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25220 disp_reloc);
25221
25222#line 25222 "ad_x86.cpp"
25223 }
25224}
25225
25226void decI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25227 cbuf.set_insts_mark();
25228 // Start at oper_input_base() and count operands
25229 unsigned idx0 = 1;
25230 unsigned idx1 = 1; // dst
25231 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25232 {
25233
25234#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25235
25236 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
25237 emit_opcode(cbuf, Assembler::REX_B);
25238 }
25239
25240#line 25240 "ad_x86.cpp"
25241 }
25242 {
25243
25244#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25245
25246 emit_opcode(cbuf, (0xFF /*primary()*/));
25247
25248#line 25248 "ad_x86.cpp"
25249 }
25250 {
25251
25252#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25253
25254 // INC, DEC, IDIV, IMOD, JMP indirect, ...
25255 emit_rm(cbuf, 0x3, (0x01 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
25256
25257#line 25257 "ad_x86.cpp"
25258 }
25259}
25260
25261void decI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25262 cbuf.set_insts_mark();
25263 // Start at oper_input_base() and count operands
25264 unsigned idx0 = 2;
25265 unsigned idx1 = 2; // dst
25266 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25267 {
25268
25269#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25270
25271 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25272 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25273 emit_opcode(cbuf, Assembler::REX_B);
25274 } else {
25275 emit_opcode(cbuf, Assembler::REX_XB);
25276 }
25277 } else {
25278 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
25279 emit_opcode(cbuf, Assembler::REX_X);
25280 }
25281 }
25282
25283#line 25283 "ad_x86.cpp"
25284 }
25285 {
25286
25287#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25288
25289 emit_opcode(cbuf, (0xFF /*primary()*/));
25290
25291#line 25291 "ad_x86.cpp"
25292 }
25293 {
25294
25295#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25296
25297 int rm_byte_opcode = (0x01);
25298
25299 // High registers handle in encode_RegMem
25300 int base = opnd_array(1)->base(ra_,this,idx1);
25301 int index = opnd_array(1)->index(ra_,this,idx1);
25302 int scale = opnd_array(1)->scale();
25303 int displace = opnd_array(1)->disp(ra_,this,idx1);
25304
25305 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25306 // working with static
25307 // globals
25308 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25309 disp_reloc);
25310
25311#line 25311 "ad_x86.cpp"
25312 }
25313}
25314
25315void leaI_rReg_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25316 cbuf.set_insts_mark();
25317 // Start at oper_input_base() and count operands
25318 unsigned idx0 = 1;
25319 unsigned idx1 = 1; // src0
25320 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25321 {
25322
25323#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25324
25325 emit_opcode(cbuf, (0x67));
25326
25327#line 25327 "ad_x86.cpp"
25328 }
25329 {
25330
25331#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25332
25333 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
25334 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ >= 8) {
25335 emit_opcode(cbuf, Assembler::REX_B);
25336 }
25337 } else {
25338 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ < 8) {
25339 emit_opcode(cbuf, Assembler::REX_R);
25340 } else {
25341 emit_opcode(cbuf, Assembler::REX_RB);
25342 }
25343 }
25344
25345#line 25345 "ad_x86.cpp"
25346 }
25347 {
25348
25349#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25350
25351 emit_opcode(cbuf, (0x8D /*primary()*/));
25352
25353#line 25353 "ad_x86.cpp"
25354 }
25355 {
25356
25357#line 2568 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25358
25359 int reg_encoding = opnd_array(0)->reg(ra_,this)/* dst */;
25360 int base = opnd_array(1)->reg(ra_,this,idx1)/* src0 */; // 0xFFFFFFFF indicates no base
25361 int index = 0x04; // 0x04 indicates no index
25362 int scale = 0x00; // 0x00 indicates no scale
25363 int displace = opnd_array(2)->constant(); // 0x00 indicates no displacement
25364 relocInfo::relocType disp_reloc = relocInfo::none;
25365 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
25366 disp_reloc);
25367
25368#line 25368 "ad_x86.cpp"
25369 }
25370}
25371
25372void addL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25373 cbuf.set_insts_mark();
25374 // Start at oper_input_base() and count operands
25375 unsigned idx0 = 1;
25376 unsigned idx1 = 1; // dst
25377 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25378 {
25379
25380#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25381
25382 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
25383 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
25384 emit_opcode(cbuf, Assembler::REX_W);
25385 } else {
25386 emit_opcode(cbuf, Assembler::REX_WB);
25387 }
25388 } else {
25389 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
25390 emit_opcode(cbuf, Assembler::REX_WR);
25391 } else {
25392 emit_opcode(cbuf, Assembler::REX_WRB);
25393 }
25394 }
25395
25396#line 25396 "ad_x86.cpp"
25397 }
25398 {
25399
25400#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25401
25402 emit_opcode(cbuf, (0x03 /*primary()*/));
25403
25404#line 25404 "ad_x86.cpp"
25405 }
25406 {
25407
25408#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25409
25410 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
25411
25412#line 25412 "ad_x86.cpp"
25413 }
25414}
25415
25416void addL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25417 cbuf.set_insts_mark();
25418 // Start at oper_input_base() and count operands
25419 unsigned idx0 = 1;
25420 unsigned idx1 = 1; // dst
25421 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25422 {
25423
25424#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25425
25426 // OpcSEr/m
25427 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
25428 if (dstenc < 8) {
25429 emit_opcode(cbuf, Assembler::REX_W);
25430 } else {
25431 emit_opcode(cbuf, Assembler::REX_WB);
25432 dstenc -= 8;
25433 }
25434 // Emit primary opcode and set sign-extend bit
25435 // Check for 8-bit immediate, and set sign extend bit in opcode
25436 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
25437 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
25438 } else {
25439 // 32-bit immediate
25440 emit_opcode(cbuf, (0x81 /*primary()*/));
25441 }
25442 // Emit r/m byte with secondary opcode, after primary opcode.
25443 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), dstenc);
25444
25445#line 25445 "ad_x86.cpp"
25446 }
25447 {
25448
25449#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25450
25451 // Check for 8-bit immediate, and set sign extend bit in opcode
25452 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
25453 emit_d8(cbuf, opnd_array(2)->constantL());
25454 } else {
25455 // 32-bit immediate
25456 emit_d32(cbuf, opnd_array(2)->constantL());
25457 }
25458
25459#line 25459 "ad_x86.cpp"
25460 }
25461}
25462
25463void addL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25464 cbuf.set_insts_mark();
25465 // Start at oper_input_base() and count operands
25466 unsigned idx0 = 2;
25467 unsigned idx1 = 2; // dst
25468 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25469 {
25470
25471#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25472
25473 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
25474 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
25475 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
25476 emit_opcode(cbuf, Assembler::REX_W);
25477 } else {
25478 emit_opcode(cbuf, Assembler::REX_WX);
25479 }
25480 } else {
25481 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
25482 emit_opcode(cbuf, Assembler::REX_WB);
25483 } else {
25484 emit_opcode(cbuf, Assembler::REX_WXB);
25485 }
25486 }
25487 } else {
25488 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
25489 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
25490 emit_opcode(cbuf, Assembler::REX_WR);
25491 } else {
25492 emit_opcode(cbuf, Assembler::REX_WRX);
25493 }
25494 } else {
25495 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
25496 emit_opcode(cbuf, Assembler::REX_WRB);
25497 } else {
25498 emit_opcode(cbuf, Assembler::REX_WRXB);
25499 }
25500 }
25501 }
25502
25503#line 25503 "ad_x86.cpp"
25504 }
25505 {
25506
25507#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25508
25509 emit_opcode(cbuf, (0x03 /*primary()*/));
25510
25511#line 25511 "ad_x86.cpp"
25512 }
25513 {
25514
25515#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25516
25517 // High registers handle in encode_RegMem
25518 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
25519 int base = opnd_array(2)->base(ra_,this,idx2);
25520 int index = opnd_array(2)->index(ra_,this,idx2);
25521 int scale = opnd_array(2)->scale();
25522 int disp = opnd_array(2)->disp(ra_,this,idx2);
25523 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
25524
25525 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
25526
25527#line 25527 "ad_x86.cpp"
25528 }
25529}
25530
25531void addL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25532 cbuf.set_insts_mark();
25533 // Start at oper_input_base() and count operands
25534 unsigned idx0 = 2;
25535 unsigned idx1 = 2; // src
25536 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
25537 {
25538
25539#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25540
25541 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
25542 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25543 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25544 emit_opcode(cbuf, Assembler::REX_W);
25545 } else {
25546 emit_opcode(cbuf, Assembler::REX_WX);
25547 }
25548 } else {
25549 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25550 emit_opcode(cbuf, Assembler::REX_WB);
25551 } else {
25552 emit_opcode(cbuf, Assembler::REX_WXB);
25553 }
25554 }
25555 } else {
25556 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25557 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25558 emit_opcode(cbuf, Assembler::REX_WR);
25559 } else {
25560 emit_opcode(cbuf, Assembler::REX_WRX);
25561 }
25562 } else {
25563 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25564 emit_opcode(cbuf, Assembler::REX_WRB);
25565 } else {
25566 emit_opcode(cbuf, Assembler::REX_WRXB);
25567 }
25568 }
25569 }
25570
25571#line 25571 "ad_x86.cpp"
25572 }
25573 {
25574
25575#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25576
25577 emit_opcode(cbuf, (0x03 /*primary()*/));
25578
25579#line 25579 "ad_x86.cpp"
25580 }
25581 {
25582
25583#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25584
25585 // High registers handle in encode_RegMem
25586 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
25587 int base = opnd_array(1)->base(ra_,this,idx1);
25588 int index = opnd_array(1)->index(ra_,this,idx1);
25589 int scale = opnd_array(1)->scale();
25590 int disp = opnd_array(1)->disp(ra_,this,idx1);
25591 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
25592
25593 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
25594
25595#line 25595 "ad_x86.cpp"
25596 }
25597}
25598
25599void addL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25600 cbuf.set_insts_mark();
25601 // Start at oper_input_base() and count operands
25602 unsigned idx0 = 2;
25603 unsigned idx1 = 2; // dst
25604 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25605 {
25606
25607#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25608
25609 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
25610 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25611 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25612 emit_opcode(cbuf, Assembler::REX_W);
25613 } else {
25614 emit_opcode(cbuf, Assembler::REX_WX);
25615 }
25616 } else {
25617 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25618 emit_opcode(cbuf, Assembler::REX_WB);
25619 } else {
25620 emit_opcode(cbuf, Assembler::REX_WXB);
25621 }
25622 }
25623 } else {
25624 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25625 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25626 emit_opcode(cbuf, Assembler::REX_WR);
25627 } else {
25628 emit_opcode(cbuf, Assembler::REX_WRX);
25629 }
25630 } else {
25631 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25632 emit_opcode(cbuf, Assembler::REX_WRB);
25633 } else {
25634 emit_opcode(cbuf, Assembler::REX_WRXB);
25635 }
25636 }
25637 }
25638
25639#line 25639 "ad_x86.cpp"
25640 }
25641 {
25642
25643#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25644
25645 emit_opcode(cbuf, (0x01 /*primary()*/));
25646
25647#line 25647 "ad_x86.cpp"
25648 }
25649 {
25650
25651#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25652
25653 // High registers handle in encode_RegMem
25654 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
25655 int base = opnd_array(1)->base(ra_,this,idx1);
25656 int index = opnd_array(1)->index(ra_,this,idx1);
25657 int scale = opnd_array(1)->scale();
25658 int disp = opnd_array(1)->disp(ra_,this,idx1);
25659 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
25660
25661 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
25662
25663#line 25663 "ad_x86.cpp"
25664 }
25665}
25666
25667void addL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25668 cbuf.set_insts_mark();
25669 // Start at oper_input_base() and count operands
25670 unsigned idx0 = 2;
25671 unsigned idx1 = 2; // dst
25672 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25673 {
25674
25675#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25676
25677 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
25678 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25679 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25680 emit_opcode(cbuf, Assembler::REX_W);
25681 } else {
25682 emit_opcode(cbuf, Assembler::REX_WX);
25683 }
25684 } else {
25685 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25686 emit_opcode(cbuf, Assembler::REX_WB);
25687 } else {
25688 emit_opcode(cbuf, Assembler::REX_WXB);
25689 }
25690 }
25691 } else {
25692 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
25693 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25694 emit_opcode(cbuf, Assembler::REX_WR);
25695 } else {
25696 emit_opcode(cbuf, Assembler::REX_WRX);
25697 }
25698 } else {
25699 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25700 emit_opcode(cbuf, Assembler::REX_WRB);
25701 } else {
25702 emit_opcode(cbuf, Assembler::REX_WRXB);
25703 }
25704 }
25705 }
25706
25707#line 25707 "ad_x86.cpp"
25708 }
25709 {
25710
25711#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25712
25713 emit_opcode(cbuf, (0x01 /*primary()*/));
25714
25715#line 25715 "ad_x86.cpp"
25716 }
25717 {
25718
25719#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25720
25721 // High registers handle in encode_RegMem
25722 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
25723 int base = opnd_array(1)->base(ra_,this,idx1);
25724 int index = opnd_array(1)->index(ra_,this,idx1);
25725 int scale = opnd_array(1)->scale();
25726 int disp = opnd_array(1)->disp(ra_,this,idx1);
25727 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
25728
25729 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
25730
25731#line 25731 "ad_x86.cpp"
25732 }
25733}
25734
25735void addL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25736 cbuf.set_insts_mark();
25737 // Start at oper_input_base() and count operands
25738 unsigned idx0 = 2;
25739 unsigned idx1 = 2; // dst
25740 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25741 {
25742
25743#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25744
25745 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25746 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25747 emit_opcode(cbuf, Assembler::REX_WB);
25748 } else {
25749 emit_opcode(cbuf, Assembler::REX_WXB);
25750 }
25751 } else {
25752 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25753 emit_opcode(cbuf, Assembler::REX_W);
25754 } else {
25755 emit_opcode(cbuf, Assembler::REX_WX);
25756 }
25757 }
25758
25759#line 25759 "ad_x86.cpp"
25760 }
25761 {
25762
25763#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25764
25765 // Emit primary opcode and set sign-extend bit
25766 // Check for 8-bit immediate, and set sign extend bit in opcode
25767 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
25768 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
25769 } else {
25770 // 32-bit immediate
25771 emit_opcode(cbuf, (0x81 /*primary()*/));
25772 }
25773
25774#line 25774 "ad_x86.cpp"
25775 }
25776 {
25777
25778#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25779
25780 int rm_byte_opcode = (0x00);
25781
25782 // High registers handle in encode_RegMem
25783 int base = opnd_array(1)->base(ra_,this,idx1);
25784 int index = opnd_array(1)->index(ra_,this,idx1);
25785 int scale = opnd_array(1)->scale();
25786 int displace = opnd_array(1)->disp(ra_,this,idx1);
25787
25788 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25789 // working with static
25790 // globals
25791 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25792 disp_reloc);
25793
25794#line 25794 "ad_x86.cpp"
25795 }
25796 {
25797
25798#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25799
25800 // Check for 8-bit immediate, and set sign extend bit in opcode
25801 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
25802 emit_d8(cbuf, opnd_array(2)->constantL());
25803 } else {
25804 // 32-bit immediate
25805 emit_d32(cbuf, opnd_array(2)->constantL());
25806 }
25807
25808#line 25808 "ad_x86.cpp"
25809 }
25810}
25811
25812void incL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25813 cbuf.set_insts_mark();
25814 // Start at oper_input_base() and count operands
25815 unsigned idx0 = 1;
25816 unsigned idx1 = 1; // dst
25817 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25818 {
25819
25820#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25821
25822 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
25823 emit_opcode(cbuf, Assembler::REX_W);
25824 } else {
25825 emit_opcode(cbuf, Assembler::REX_WB);
25826 }
25827
25828#line 25828 "ad_x86.cpp"
25829 }
25830 {
25831
25832#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25833
25834 emit_opcode(cbuf, (0xFF /*primary()*/));
25835
25836#line 25836 "ad_x86.cpp"
25837 }
25838 {
25839
25840#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25841
25842 // INC, DEC, IDIV, IMOD, JMP indirect, ...
25843 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
25844
25845#line 25845 "ad_x86.cpp"
25846 }
25847}
25848
25849void incL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25850 cbuf.set_insts_mark();
25851 // Start at oper_input_base() and count operands
25852 unsigned idx0 = 2;
25853 unsigned idx1 = 2; // dst
25854 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25855 {
25856
25857#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25858
25859 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25860 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25861 emit_opcode(cbuf, Assembler::REX_WB);
25862 } else {
25863 emit_opcode(cbuf, Assembler::REX_WXB);
25864 }
25865 } else {
25866 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25867 emit_opcode(cbuf, Assembler::REX_W);
25868 } else {
25869 emit_opcode(cbuf, Assembler::REX_WX);
25870 }
25871 }
25872
25873#line 25873 "ad_x86.cpp"
25874 }
25875 {
25876
25877#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25878
25879 emit_opcode(cbuf, (0xFF /*primary()*/));
25880
25881#line 25881 "ad_x86.cpp"
25882 }
25883 {
25884
25885#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25886
25887 int rm_byte_opcode = (0x00);
25888
25889 // High registers handle in encode_RegMem
25890 int base = opnd_array(1)->base(ra_,this,idx1);
25891 int index = opnd_array(1)->index(ra_,this,idx1);
25892 int scale = opnd_array(1)->scale();
25893 int displace = opnd_array(1)->disp(ra_,this,idx1);
25894
25895 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25896 // working with static
25897 // globals
25898 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25899 disp_reloc);
25900
25901#line 25901 "ad_x86.cpp"
25902 }
25903}
25904
25905void decL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25906 cbuf.set_insts_mark();
25907 // Start at oper_input_base() and count operands
25908 unsigned idx0 = 1;
25909 unsigned idx1 = 1; // dst
25910 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25911 {
25912
25913#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25914
25915 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
25916 emit_opcode(cbuf, Assembler::REX_W);
25917 } else {
25918 emit_opcode(cbuf, Assembler::REX_WB);
25919 }
25920
25921#line 25921 "ad_x86.cpp"
25922 }
25923 {
25924
25925#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25926
25927 emit_opcode(cbuf, (0xFF /*primary()*/));
25928
25929#line 25929 "ad_x86.cpp"
25930 }
25931 {
25932
25933#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25934
25935 // INC, DEC, IDIV, IMOD, JMP indirect, ...
25936 emit_rm(cbuf, 0x3, (0x01 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
25937
25938#line 25938 "ad_x86.cpp"
25939 }
25940}
25941
25942void decL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25943 cbuf.set_insts_mark();
25944 // Start at oper_input_base() and count operands
25945 unsigned idx0 = 2;
25946 unsigned idx1 = 2; // dst
25947 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25948 {
25949
25950#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25951
25952 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
25953 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25954 emit_opcode(cbuf, Assembler::REX_WB);
25955 } else {
25956 emit_opcode(cbuf, Assembler::REX_WXB);
25957 }
25958 } else {
25959 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
25960 emit_opcode(cbuf, Assembler::REX_W);
25961 } else {
25962 emit_opcode(cbuf, Assembler::REX_WX);
25963 }
25964 }
25965
25966#line 25966 "ad_x86.cpp"
25967 }
25968 {
25969
25970#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25971
25972 emit_opcode(cbuf, (0xFF /*primary()*/));
25973
25974#line 25974 "ad_x86.cpp"
25975 }
25976 {
25977
25978#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
25979
25980 int rm_byte_opcode = (0x01);
25981
25982 // High registers handle in encode_RegMem
25983 int base = opnd_array(1)->base(ra_,this,idx1);
25984 int index = opnd_array(1)->index(ra_,this,idx1);
25985 int scale = opnd_array(1)->scale();
25986 int displace = opnd_array(1)->disp(ra_,this,idx1);
25987
25988 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
25989 // working with static
25990 // globals
25991 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
25992 disp_reloc);
25993
25994#line 25994 "ad_x86.cpp"
25995 }
25996}
25997
25998void leaL_rReg_immLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25999 cbuf.set_insts_mark();
26000 // Start at oper_input_base() and count operands
26001 unsigned idx0 = 1;
26002 unsigned idx1 = 1; // src0
26003 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
26004 {
26005
26006#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26007
26008 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
26009 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ < 8) {
26010 emit_opcode(cbuf, Assembler::REX_W);
26011 } else {
26012 emit_opcode(cbuf, Assembler::REX_WB);
26013 }
26014 } else {
26015 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ < 8) {
26016 emit_opcode(cbuf, Assembler::REX_WR);
26017 } else {
26018 emit_opcode(cbuf, Assembler::REX_WRB);
26019 }
26020 }
26021
26022#line 26022 "ad_x86.cpp"
26023 }
26024 {
26025
26026#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26027
26028 emit_opcode(cbuf, (0x8D /*primary()*/));
26029
26030#line 26030 "ad_x86.cpp"
26031 }
26032 {
26033
26034#line 2568 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26035
26036 int reg_encoding = opnd_array(0)->reg(ra_,this)/* dst */;
26037 int base = opnd_array(1)->reg(ra_,this,idx1)/* src0 */; // 0xFFFFFFFF indicates no base
26038 int index = 0x04; // 0x04 indicates no index
26039 int scale = 0x00; // 0x00 indicates no scale
26040 int displace = opnd_array(2)->constantL(); // 0x00 indicates no displacement
26041 relocInfo::relocType disp_reloc = relocInfo::none;
26042 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
26043 disp_reloc);
26044
26045#line 26045 "ad_x86.cpp"
26046 }
26047}
26048
26049void addP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26050 cbuf.set_insts_mark();
26051 // Start at oper_input_base() and count operands
26052 unsigned idx0 = 2;
26053 unsigned idx1 = 2; // dst
26054 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26055 {
26056
26057#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26058
26059 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
26060 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
26061 emit_opcode(cbuf, Assembler::REX_W);
26062 } else {
26063 emit_opcode(cbuf, Assembler::REX_WB);
26064 }
26065 } else {
26066 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
26067 emit_opcode(cbuf, Assembler::REX_WR);
26068 } else {
26069 emit_opcode(cbuf, Assembler::REX_WRB);
26070 }
26071 }
26072
26073#line 26073 "ad_x86.cpp"
26074 }
26075 {
26076
26077#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26078
26079 emit_opcode(cbuf, (0x03 /*primary()*/));
26080
26081#line 26081 "ad_x86.cpp"
26082 }
26083 {
26084
26085#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26086
26087 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
26088
26089#line 26089 "ad_x86.cpp"
26090 }
26091}
26092
26093void addP_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26094 cbuf.set_insts_mark();
26095 // Start at oper_input_base() and count operands
26096 unsigned idx0 = 2;
26097 unsigned idx1 = 2; // dst
26098 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26099 {
26100
26101#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26102
26103 // OpcSEr/m
26104 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
26105 if (dstenc < 8) {
26106 emit_opcode(cbuf, Assembler::REX_W);
26107 } else {
26108 emit_opcode(cbuf, Assembler::REX_WB);
26109 dstenc -= 8;
26110 }
26111 // Emit primary opcode and set sign-extend bit
26112 // Check for 8-bit immediate, and set sign extend bit in opcode
26113 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
26114 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
26115 } else {
26116 // 32-bit immediate
26117 emit_opcode(cbuf, (0x81 /*primary()*/));
26118 }
26119 // Emit r/m byte with secondary opcode, after primary opcode.
26120 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), dstenc);
26121
26122#line 26122 "ad_x86.cpp"
26123 }
26124 {
26125
26126#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26127
26128 // Check for 8-bit immediate, and set sign extend bit in opcode
26129 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
26130 emit_d8(cbuf, opnd_array(2)->constantL());
26131 } else {
26132 // 32-bit immediate
26133 emit_d32(cbuf, opnd_array(2)->constantL());
26134 }
26135
26136#line 26136 "ad_x86.cpp"
26137 }
26138}
26139
26140void leaP_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26141 cbuf.set_insts_mark();
26142 // Start at oper_input_base() and count operands
26143 unsigned idx0 = 2;
26144 unsigned idx1 = 2; // src0
26145 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
26146 {
26147
26148#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26149
26150 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
26151 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ < 8) {
26152 emit_opcode(cbuf, Assembler::REX_W);
26153 } else {
26154 emit_opcode(cbuf, Assembler::REX_WB);
26155 }
26156 } else {
26157 if (opnd_array(1)->reg(ra_,this,idx1)/* src0 */ < 8) {
26158 emit_opcode(cbuf, Assembler::REX_WR);
26159 } else {
26160 emit_opcode(cbuf, Assembler::REX_WRB);
26161 }
26162 }
26163
26164#line 26164 "ad_x86.cpp"
26165 }
26166 {
26167
26168#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26169
26170 emit_opcode(cbuf, (0x8D /*primary()*/));
26171
26172#line 26172 "ad_x86.cpp"
26173 }
26174 {
26175
26176#line 2568 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26177
26178 int reg_encoding = opnd_array(0)->reg(ra_,this)/* dst */;
26179 int base = opnd_array(1)->reg(ra_,this,idx1)/* src0 */; // 0xFFFFFFFF indicates no base
26180 int index = 0x04; // 0x04 indicates no index
26181 int scale = 0x00; // 0x00 indicates no scale
26182 int displace = opnd_array(2)->constantL(); // 0x00 indicates no displacement
26183 relocInfo::relocType disp_reloc = relocInfo::none;
26184 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
26185 disp_reloc);
26186
26187#line 26187 "ad_x86.cpp"
26188 }
26189}
26190
26191void checkCastPPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26192 cbuf.set_insts_mark();
26193 // Start at oper_input_base() and count operands
26194 unsigned idx0 = 1;
26195 unsigned idx1 = 1; // dst
26196 // User did not define which encode class to use.
26197}
26198
26199uint checkCastPPNode::size(PhaseRegAlloc *ra_) const {
26200 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
26201 return (VerifyOops ? MachNode::size(ra_) : 0);
26202}
26203
26204void castPPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26205 cbuf.set_insts_mark();
26206 // Start at oper_input_base() and count operands
26207 unsigned idx0 = 1;
26208 unsigned idx1 = 1; // dst
26209 // User did not define which encode class to use.
26210}
26211
26212uint castPPNode::size(PhaseRegAlloc *ra_) const {
26213 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
26214 return (VerifyOops ? MachNode::size(ra_) : 0);
26215}
26216
26217void castIINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26218 cbuf.set_insts_mark();
26219 // Start at oper_input_base() and count operands
26220 unsigned idx0 = 1;
26221 unsigned idx1 = 1; // dst
26222 // User did not define which encode class to use.
26223}
26224
26225uint castIINode::size(PhaseRegAlloc *ra_) const {
26226 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
26227 return (VerifyOops ? MachNode::size(ra_) : 0);
26228}
26229
26230void loadPLockedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26231 cbuf.set_insts_mark();
26232 // Start at oper_input_base() and count operands
26233 unsigned idx0 = 2;
26234 unsigned idx1 = 2; // mem
26235 {
26236
26237#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26238
26239 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
26240 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26241 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26242 emit_opcode(cbuf, Assembler::REX_W);
26243 } else {
26244 emit_opcode(cbuf, Assembler::REX_WX);
26245 }
26246 } else {
26247 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26248 emit_opcode(cbuf, Assembler::REX_WB);
26249 } else {
26250 emit_opcode(cbuf, Assembler::REX_WXB);
26251 }
26252 }
26253 } else {
26254 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26255 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26256 emit_opcode(cbuf, Assembler::REX_WR);
26257 } else {
26258 emit_opcode(cbuf, Assembler::REX_WRX);
26259 }
26260 } else {
26261 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26262 emit_opcode(cbuf, Assembler::REX_WRB);
26263 } else {
26264 emit_opcode(cbuf, Assembler::REX_WRXB);
26265 }
26266 }
26267 }
26268
26269#line 26269 "ad_x86.cpp"
26270 }
26271 {
26272
26273#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26274
26275 emit_opcode(cbuf, (0x8B /*primary()*/));
26276
26277#line 26277 "ad_x86.cpp"
26278 }
26279 {
26280
26281#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26282
26283 // High registers handle in encode_RegMem
26284 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
26285 int base = opnd_array(1)->base(ra_,this,idx1);
26286 int index = opnd_array(1)->index(ra_,this,idx1);
26287 int scale = opnd_array(1)->scale();
26288 int disp = opnd_array(1)->disp(ra_,this,idx1);
26289 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26290
26291 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26292
26293#line 26293 "ad_x86.cpp"
26294 }
26295}
26296
26297void storePConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26298 cbuf.set_insts_mark();
26299 // Start at oper_input_base() and count operands
26300 unsigned idx0 = 2;
26301 unsigned idx1 = 2; // heap_top_ptr
26302 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26303 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26304 {
26305
26306#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26307
26308 emit_opcode(cbuf, 0xF0); // lock
26309
26310#line 26310 "ad_x86.cpp"
26311 }
26312 {
26313
26314#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26315
26316 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26317 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26318 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26319 emit_opcode(cbuf, Assembler::REX_W);
26320 } else {
26321 emit_opcode(cbuf, Assembler::REX_WX);
26322 }
26323 } else {
26324 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26325 emit_opcode(cbuf, Assembler::REX_WB);
26326 } else {
26327 emit_opcode(cbuf, Assembler::REX_WXB);
26328 }
26329 }
26330 } else {
26331 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26332 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26333 emit_opcode(cbuf, Assembler::REX_WR);
26334 } else {
26335 emit_opcode(cbuf, Assembler::REX_WRX);
26336 }
26337 } else {
26338 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26339 emit_opcode(cbuf, Assembler::REX_WRB);
26340 } else {
26341 emit_opcode(cbuf, Assembler::REX_WRXB);
26342 }
26343 }
26344 }
26345
26346#line 26346 "ad_x86.cpp"
26347 }
26348 {
26349
26350#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26351
26352 emit_opcode(cbuf, (0x0F /*primary()*/));
26353
26354#line 26354 "ad_x86.cpp"
26355 }
26356 {
26357
26358#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26359
26360 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26361
26362#line 26362 "ad_x86.cpp"
26363 }
26364 {
26365
26366#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26367
26368 // High registers handle in encode_RegMem
26369 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26370 int base = opnd_array(1)->base(ra_,this,idx1);
26371 int index = opnd_array(1)->index(ra_,this,idx1);
26372 int scale = opnd_array(1)->scale();
26373 int disp = opnd_array(1)->disp(ra_,this,idx1);
26374 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26375
26376 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26377
26378#line 26378 "ad_x86.cpp"
26379 }
26380}
26381
26382void storeIConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26383 cbuf.set_insts_mark();
26384 // Start at oper_input_base() and count operands
26385 unsigned idx0 = 2;
26386 unsigned idx1 = 2; // mem
26387 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26388 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26389 {
26390
26391#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26392
26393 emit_opcode(cbuf, 0xF0); // lock
26394
26395#line 26395 "ad_x86.cpp"
26396 }
26397 {
26398
26399#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26400
26401 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26402 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26403 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
26404 emit_opcode(cbuf, Assembler::REX_X);
26405 }
26406 } else {
26407 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26408 emit_opcode(cbuf, Assembler::REX_B);
26409 } else {
26410 emit_opcode(cbuf, Assembler::REX_XB);
26411 }
26412 }
26413 } else {
26414 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26415 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26416 emit_opcode(cbuf, Assembler::REX_R);
26417 } else {
26418 emit_opcode(cbuf, Assembler::REX_RX);
26419 }
26420 } else {
26421 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26422 emit_opcode(cbuf, Assembler::REX_RB);
26423 } else {
26424 emit_opcode(cbuf, Assembler::REX_RXB);
26425 }
26426 }
26427 }
26428
26429#line 26429 "ad_x86.cpp"
26430 }
26431 {
26432
26433#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26434
26435 emit_opcode(cbuf, (0x0F /*primary()*/));
26436
26437#line 26437 "ad_x86.cpp"
26438 }
26439 {
26440
26441#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26442
26443 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26444
26445#line 26445 "ad_x86.cpp"
26446 }
26447 {
26448
26449#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26450
26451 // High registers handle in encode_RegMem
26452 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26453 int base = opnd_array(1)->base(ra_,this,idx1);
26454 int index = opnd_array(1)->index(ra_,this,idx1);
26455 int scale = opnd_array(1)->scale();
26456 int disp = opnd_array(1)->disp(ra_,this,idx1);
26457 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26458
26459 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26460
26461#line 26461 "ad_x86.cpp"
26462 }
26463}
26464
26465void storeLConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26466 cbuf.set_insts_mark();
26467 // Start at oper_input_base() and count operands
26468 unsigned idx0 = 2;
26469 unsigned idx1 = 2; // mem
26470 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26471 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26472 {
26473
26474#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26475
26476 emit_opcode(cbuf, 0xF0); // lock
26477
26478#line 26478 "ad_x86.cpp"
26479 }
26480 {
26481
26482#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26483
26484 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26485 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26486 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26487 emit_opcode(cbuf, Assembler::REX_W);
26488 } else {
26489 emit_opcode(cbuf, Assembler::REX_WX);
26490 }
26491 } else {
26492 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26493 emit_opcode(cbuf, Assembler::REX_WB);
26494 } else {
26495 emit_opcode(cbuf, Assembler::REX_WXB);
26496 }
26497 }
26498 } else {
26499 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26500 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26501 emit_opcode(cbuf, Assembler::REX_WR);
26502 } else {
26503 emit_opcode(cbuf, Assembler::REX_WRX);
26504 }
26505 } else {
26506 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26507 emit_opcode(cbuf, Assembler::REX_WRB);
26508 } else {
26509 emit_opcode(cbuf, Assembler::REX_WRXB);
26510 }
26511 }
26512 }
26513
26514#line 26514 "ad_x86.cpp"
26515 }
26516 {
26517
26518#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26519
26520 emit_opcode(cbuf, (0x0F /*primary()*/));
26521
26522#line 26522 "ad_x86.cpp"
26523 }
26524 {
26525
26526#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26527
26528 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26529
26530#line 26530 "ad_x86.cpp"
26531 }
26532 {
26533
26534#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26535
26536 // High registers handle in encode_RegMem
26537 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26538 int base = opnd_array(1)->base(ra_,this,idx1);
26539 int index = opnd_array(1)->index(ra_,this,idx1);
26540 int scale = opnd_array(1)->scale();
26541 int disp = opnd_array(1)->disp(ra_,this,idx1);
26542 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26543
26544 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26545
26546#line 26546 "ad_x86.cpp"
26547 }
26548}
26549
26550void compareAndSwapPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26551 cbuf.set_insts_mark();
26552 // Start at oper_input_base() and count operands
26553 unsigned idx0 = 2;
26554 unsigned idx1 = 2; // mem_ptr
26555 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26556 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26557 {
26558
26559#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26560
26561 emit_opcode(cbuf, 0xF0); // lock
26562
26563#line 26563 "ad_x86.cpp"
26564 }
26565 {
26566
26567#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26568
26569 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26570 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26571 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26572 emit_opcode(cbuf, Assembler::REX_W);
26573 } else {
26574 emit_opcode(cbuf, Assembler::REX_WX);
26575 }
26576 } else {
26577 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26578 emit_opcode(cbuf, Assembler::REX_WB);
26579 } else {
26580 emit_opcode(cbuf, Assembler::REX_WXB);
26581 }
26582 }
26583 } else {
26584 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26585 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26586 emit_opcode(cbuf, Assembler::REX_WR);
26587 } else {
26588 emit_opcode(cbuf, Assembler::REX_WRX);
26589 }
26590 } else {
26591 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26592 emit_opcode(cbuf, Assembler::REX_WRB);
26593 } else {
26594 emit_opcode(cbuf, Assembler::REX_WRXB);
26595 }
26596 }
26597 }
26598
26599#line 26599 "ad_x86.cpp"
26600 }
26601 {
26602
26603#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26604
26605 emit_opcode(cbuf, (0x0F /*primary()*/));
26606
26607#line 26607 "ad_x86.cpp"
26608 }
26609 {
26610
26611#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26612
26613 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26614
26615#line 26615 "ad_x86.cpp"
26616 }
26617 {
26618
26619#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26620
26621 // High registers handle in encode_RegMem
26622 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26623 int base = opnd_array(1)->base(ra_,this,idx1);
26624 int index = opnd_array(1)->index(ra_,this,idx1);
26625 int scale = opnd_array(1)->scale();
26626 int disp = opnd_array(1)->disp(ra_,this,idx1);
26627 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26628
26629 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26630
26631#line 26631 "ad_x86.cpp"
26632 }
26633 {
26634
26635#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26636
26637 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26638 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26639 }
26640
26641#line 26641 "ad_x86.cpp"
26642 }
26643 {
26644
26645#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26646
26647 emit_opcode(cbuf, (0x0F));
26648
26649#line 26649 "ad_x86.cpp"
26650 }
26651 {
26652
26653#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26654
26655 emit_opcode(cbuf, (0x94));
26656
26657#line 26657 "ad_x86.cpp"
26658 }
26659 {
26660
26661#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26662
26663 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
26664
26665#line 26665 "ad_x86.cpp"
26666 }
26667 {
26668
26669#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26670
26671 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26672 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26673 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26674 }
26675 } else {
26676 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26677 emit_opcode(cbuf, Assembler::REX_R);
26678 } else {
26679 emit_opcode(cbuf, Assembler::REX_RB);
26680 }
26681 }
26682
26683#line 26683 "ad_x86.cpp"
26684 }
26685 {
26686
26687#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26688
26689 emit_opcode(cbuf, (0xF));
26690
26691#line 26691 "ad_x86.cpp"
26692 }
26693 {
26694
26695#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26696
26697 emit_opcode(cbuf, (0xB6));
26698
26699#line 26699 "ad_x86.cpp"
26700 }
26701 {
26702
26703#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26704
26705 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
26706
26707#line 26707 "ad_x86.cpp"
26708 }
26709}
26710
26711void compareAndSwapP_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26712 cbuf.set_insts_mark();
26713 // Start at oper_input_base() and count operands
26714 unsigned idx0 = 2;
26715 unsigned idx1 = 2; // mem_ptr
26716 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26717 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26718 {
26719
26720#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26721
26722 emit_opcode(cbuf, 0xF0); // lock
26723
26724#line 26724 "ad_x86.cpp"
26725 }
26726 {
26727
26728#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26729
26730 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26731 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26732 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26733 emit_opcode(cbuf, Assembler::REX_W);
26734 } else {
26735 emit_opcode(cbuf, Assembler::REX_WX);
26736 }
26737 } else {
26738 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26739 emit_opcode(cbuf, Assembler::REX_WB);
26740 } else {
26741 emit_opcode(cbuf, Assembler::REX_WXB);
26742 }
26743 }
26744 } else {
26745 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26746 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26747 emit_opcode(cbuf, Assembler::REX_WR);
26748 } else {
26749 emit_opcode(cbuf, Assembler::REX_WRX);
26750 }
26751 } else {
26752 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26753 emit_opcode(cbuf, Assembler::REX_WRB);
26754 } else {
26755 emit_opcode(cbuf, Assembler::REX_WRXB);
26756 }
26757 }
26758 }
26759
26760#line 26760 "ad_x86.cpp"
26761 }
26762 {
26763
26764#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26765
26766 emit_opcode(cbuf, (0x0F /*primary()*/));
26767
26768#line 26768 "ad_x86.cpp"
26769 }
26770 {
26771
26772#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26773
26774 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26775
26776#line 26776 "ad_x86.cpp"
26777 }
26778 {
26779
26780#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26781
26782 // High registers handle in encode_RegMem
26783 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26784 int base = opnd_array(1)->base(ra_,this,idx1);
26785 int index = opnd_array(1)->index(ra_,this,idx1);
26786 int scale = opnd_array(1)->scale();
26787 int disp = opnd_array(1)->disp(ra_,this,idx1);
26788 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26789
26790 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26791
26792#line 26792 "ad_x86.cpp"
26793 }
26794 {
26795
26796#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26797
26798 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26799 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26800 }
26801
26802#line 26802 "ad_x86.cpp"
26803 }
26804 {
26805
26806#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26807
26808 emit_opcode(cbuf, (0x0F));
26809
26810#line 26810 "ad_x86.cpp"
26811 }
26812 {
26813
26814#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26815
26816 emit_opcode(cbuf, (0x94));
26817
26818#line 26818 "ad_x86.cpp"
26819 }
26820 {
26821
26822#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26823
26824 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
26825
26826#line 26826 "ad_x86.cpp"
26827 }
26828 {
26829
26830#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26831
26832 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26833 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26834 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26835 }
26836 } else {
26837 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26838 emit_opcode(cbuf, Assembler::REX_R);
26839 } else {
26840 emit_opcode(cbuf, Assembler::REX_RB);
26841 }
26842 }
26843
26844#line 26844 "ad_x86.cpp"
26845 }
26846 {
26847
26848#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26849
26850 emit_opcode(cbuf, (0xF));
26851
26852#line 26852 "ad_x86.cpp"
26853 }
26854 {
26855
26856#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26857
26858 emit_opcode(cbuf, (0xB6));
26859
26860#line 26860 "ad_x86.cpp"
26861 }
26862 {
26863
26864#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26865
26866 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
26867
26868#line 26868 "ad_x86.cpp"
26869 }
26870}
26871
26872void compareAndSwapLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26873 cbuf.set_insts_mark();
26874 // Start at oper_input_base() and count operands
26875 unsigned idx0 = 2;
26876 unsigned idx1 = 2; // mem_ptr
26877 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
26878 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
26879 {
26880
26881#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26882
26883 emit_opcode(cbuf, 0xF0); // lock
26884
26885#line 26885 "ad_x86.cpp"
26886 }
26887 {
26888
26889#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26890
26891 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
26892 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26893 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26894 emit_opcode(cbuf, Assembler::REX_W);
26895 } else {
26896 emit_opcode(cbuf, Assembler::REX_WX);
26897 }
26898 } else {
26899 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26900 emit_opcode(cbuf, Assembler::REX_WB);
26901 } else {
26902 emit_opcode(cbuf, Assembler::REX_WXB);
26903 }
26904 }
26905 } else {
26906 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
26907 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26908 emit_opcode(cbuf, Assembler::REX_WR);
26909 } else {
26910 emit_opcode(cbuf, Assembler::REX_WRX);
26911 }
26912 } else {
26913 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
26914 emit_opcode(cbuf, Assembler::REX_WRB);
26915 } else {
26916 emit_opcode(cbuf, Assembler::REX_WRXB);
26917 }
26918 }
26919 }
26920
26921#line 26921 "ad_x86.cpp"
26922 }
26923 {
26924
26925#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26926
26927 emit_opcode(cbuf, (0x0F /*primary()*/));
26928
26929#line 26929 "ad_x86.cpp"
26930 }
26931 {
26932
26933#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26934
26935 emit_opcode(cbuf, (0xB1 /*secondary()*/));
26936
26937#line 26937 "ad_x86.cpp"
26938 }
26939 {
26940
26941#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26942
26943 // High registers handle in encode_RegMem
26944 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
26945 int base = opnd_array(1)->base(ra_,this,idx1);
26946 int index = opnd_array(1)->index(ra_,this,idx1);
26947 int scale = opnd_array(1)->scale();
26948 int disp = opnd_array(1)->disp(ra_,this,idx1);
26949 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
26950
26951 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
26952
26953#line 26953 "ad_x86.cpp"
26954 }
26955 {
26956
26957#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26958
26959 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26960 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26961 }
26962
26963#line 26963 "ad_x86.cpp"
26964 }
26965 {
26966
26967#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26968
26969 emit_opcode(cbuf, (0x0F));
26970
26971#line 26971 "ad_x86.cpp"
26972 }
26973 {
26974
26975#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26976
26977 emit_opcode(cbuf, (0x94));
26978
26979#line 26979 "ad_x86.cpp"
26980 }
26981 {
26982
26983#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26984
26985 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
26986
26987#line 26987 "ad_x86.cpp"
26988 }
26989 {
26990
26991#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
26992
26993 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26994 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
26995 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
26996 }
26997 } else {
26998 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
26999 emit_opcode(cbuf, Assembler::REX_R);
27000 } else {
27001 emit_opcode(cbuf, Assembler::REX_RB);
27002 }
27003 }
27004
27005#line 27005 "ad_x86.cpp"
27006 }
27007 {
27008
27009#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27010
27011 emit_opcode(cbuf, (0xF));
27012
27013#line 27013 "ad_x86.cpp"
27014 }
27015 {
27016
27017#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27018
27019 emit_opcode(cbuf, (0xB6));
27020
27021#line 27021 "ad_x86.cpp"
27022 }
27023 {
27024
27025#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27026
27027 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27028
27029#line 27029 "ad_x86.cpp"
27030 }
27031}
27032
27033void compareAndSwapL_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27034 cbuf.set_insts_mark();
27035 // Start at oper_input_base() and count operands
27036 unsigned idx0 = 2;
27037 unsigned idx1 = 2; // mem_ptr
27038 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27039 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27040 {
27041
27042#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27043
27044 emit_opcode(cbuf, 0xF0); // lock
27045
27046#line 27046 "ad_x86.cpp"
27047 }
27048 {
27049
27050#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27051
27052 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27053 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27054 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27055 emit_opcode(cbuf, Assembler::REX_W);
27056 } else {
27057 emit_opcode(cbuf, Assembler::REX_WX);
27058 }
27059 } else {
27060 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27061 emit_opcode(cbuf, Assembler::REX_WB);
27062 } else {
27063 emit_opcode(cbuf, Assembler::REX_WXB);
27064 }
27065 }
27066 } else {
27067 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27068 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27069 emit_opcode(cbuf, Assembler::REX_WR);
27070 } else {
27071 emit_opcode(cbuf, Assembler::REX_WRX);
27072 }
27073 } else {
27074 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27075 emit_opcode(cbuf, Assembler::REX_WRB);
27076 } else {
27077 emit_opcode(cbuf, Assembler::REX_WRXB);
27078 }
27079 }
27080 }
27081
27082#line 27082 "ad_x86.cpp"
27083 }
27084 {
27085
27086#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27087
27088 emit_opcode(cbuf, (0x0F /*primary()*/));
27089
27090#line 27090 "ad_x86.cpp"
27091 }
27092 {
27093
27094#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27095
27096 emit_opcode(cbuf, (0xB1 /*secondary()*/));
27097
27098#line 27098 "ad_x86.cpp"
27099 }
27100 {
27101
27102#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27103
27104 // High registers handle in encode_RegMem
27105 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27106 int base = opnd_array(1)->base(ra_,this,idx1);
27107 int index = opnd_array(1)->index(ra_,this,idx1);
27108 int scale = opnd_array(1)->scale();
27109 int disp = opnd_array(1)->disp(ra_,this,idx1);
27110 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27111
27112 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27113
27114#line 27114 "ad_x86.cpp"
27115 }
27116 {
27117
27118#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27119
27120 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27121 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27122 }
27123
27124#line 27124 "ad_x86.cpp"
27125 }
27126 {
27127
27128#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27129
27130 emit_opcode(cbuf, (0x0F));
27131
27132#line 27132 "ad_x86.cpp"
27133 }
27134 {
27135
27136#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27137
27138 emit_opcode(cbuf, (0x94));
27139
27140#line 27140 "ad_x86.cpp"
27141 }
27142 {
27143
27144#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27145
27146 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27147
27148#line 27148 "ad_x86.cpp"
27149 }
27150 {
27151
27152#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27153
27154 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27155 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27156 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27157 }
27158 } else {
27159 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27160 emit_opcode(cbuf, Assembler::REX_R);
27161 } else {
27162 emit_opcode(cbuf, Assembler::REX_RB);
27163 }
27164 }
27165
27166#line 27166 "ad_x86.cpp"
27167 }
27168 {
27169
27170#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27171
27172 emit_opcode(cbuf, (0xF));
27173
27174#line 27174 "ad_x86.cpp"
27175 }
27176 {
27177
27178#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27179
27180 emit_opcode(cbuf, (0xB6));
27181
27182#line 27182 "ad_x86.cpp"
27183 }
27184 {
27185
27186#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27187
27188 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27189
27190#line 27190 "ad_x86.cpp"
27191 }
27192}
27193
27194void compareAndSwapINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27195 cbuf.set_insts_mark();
27196 // Start at oper_input_base() and count operands
27197 unsigned idx0 = 2;
27198 unsigned idx1 = 2; // mem_ptr
27199 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27200 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27201 {
27202
27203#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27204
27205 emit_opcode(cbuf, 0xF0); // lock
27206
27207#line 27207 "ad_x86.cpp"
27208 }
27209 {
27210
27211#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27212
27213 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27214 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27215 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
27216 emit_opcode(cbuf, Assembler::REX_X);
27217 }
27218 } else {
27219 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27220 emit_opcode(cbuf, Assembler::REX_B);
27221 } else {
27222 emit_opcode(cbuf, Assembler::REX_XB);
27223 }
27224 }
27225 } else {
27226 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27227 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27228 emit_opcode(cbuf, Assembler::REX_R);
27229 } else {
27230 emit_opcode(cbuf, Assembler::REX_RX);
27231 }
27232 } else {
27233 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27234 emit_opcode(cbuf, Assembler::REX_RB);
27235 } else {
27236 emit_opcode(cbuf, Assembler::REX_RXB);
27237 }
27238 }
27239 }
27240
27241#line 27241 "ad_x86.cpp"
27242 }
27243 {
27244
27245#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27246
27247 emit_opcode(cbuf, (0x0F /*primary()*/));
27248
27249#line 27249 "ad_x86.cpp"
27250 }
27251 {
27252
27253#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27254
27255 emit_opcode(cbuf, (0xB1 /*secondary()*/));
27256
27257#line 27257 "ad_x86.cpp"
27258 }
27259 {
27260
27261#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27262
27263 // High registers handle in encode_RegMem
27264 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27265 int base = opnd_array(1)->base(ra_,this,idx1);
27266 int index = opnd_array(1)->index(ra_,this,idx1);
27267 int scale = opnd_array(1)->scale();
27268 int disp = opnd_array(1)->disp(ra_,this,idx1);
27269 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27270
27271 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27272
27273#line 27273 "ad_x86.cpp"
27274 }
27275 {
27276
27277#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27278
27279 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27280 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27281 }
27282
27283#line 27283 "ad_x86.cpp"
27284 }
27285 {
27286
27287#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27288
27289 emit_opcode(cbuf, (0x0F));
27290
27291#line 27291 "ad_x86.cpp"
27292 }
27293 {
27294
27295#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27296
27297 emit_opcode(cbuf, (0x94));
27298
27299#line 27299 "ad_x86.cpp"
27300 }
27301 {
27302
27303#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27304
27305 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27306
27307#line 27307 "ad_x86.cpp"
27308 }
27309 {
27310
27311#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27312
27313 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27314 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27315 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27316 }
27317 } else {
27318 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27319 emit_opcode(cbuf, Assembler::REX_R);
27320 } else {
27321 emit_opcode(cbuf, Assembler::REX_RB);
27322 }
27323 }
27324
27325#line 27325 "ad_x86.cpp"
27326 }
27327 {
27328
27329#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27330
27331 emit_opcode(cbuf, (0xF));
27332
27333#line 27333 "ad_x86.cpp"
27334 }
27335 {
27336
27337#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27338
27339 emit_opcode(cbuf, (0xB6));
27340
27341#line 27341 "ad_x86.cpp"
27342 }
27343 {
27344
27345#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27346
27347 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27348
27349#line 27349 "ad_x86.cpp"
27350 }
27351}
27352
27353void compareAndSwapI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27354 cbuf.set_insts_mark();
27355 // Start at oper_input_base() and count operands
27356 unsigned idx0 = 2;
27357 unsigned idx1 = 2; // mem_ptr
27358 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27359 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27360 {
27361
27362#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27363
27364 emit_opcode(cbuf, 0xF0); // lock
27365
27366#line 27366 "ad_x86.cpp"
27367 }
27368 {
27369
27370#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27371
27372 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27373 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27374 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
27375 emit_opcode(cbuf, Assembler::REX_X);
27376 }
27377 } else {
27378 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27379 emit_opcode(cbuf, Assembler::REX_B);
27380 } else {
27381 emit_opcode(cbuf, Assembler::REX_XB);
27382 }
27383 }
27384 } else {
27385 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27386 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27387 emit_opcode(cbuf, Assembler::REX_R);
27388 } else {
27389 emit_opcode(cbuf, Assembler::REX_RX);
27390 }
27391 } else {
27392 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27393 emit_opcode(cbuf, Assembler::REX_RB);
27394 } else {
27395 emit_opcode(cbuf, Assembler::REX_RXB);
27396 }
27397 }
27398 }
27399
27400#line 27400 "ad_x86.cpp"
27401 }
27402 {
27403
27404#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27405
27406 emit_opcode(cbuf, (0x0F /*primary()*/));
27407
27408#line 27408 "ad_x86.cpp"
27409 }
27410 {
27411
27412#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27413
27414 emit_opcode(cbuf, (0xB1 /*secondary()*/));
27415
27416#line 27416 "ad_x86.cpp"
27417 }
27418 {
27419
27420#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27421
27422 // High registers handle in encode_RegMem
27423 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27424 int base = opnd_array(1)->base(ra_,this,idx1);
27425 int index = opnd_array(1)->index(ra_,this,idx1);
27426 int scale = opnd_array(1)->scale();
27427 int disp = opnd_array(1)->disp(ra_,this,idx1);
27428 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27429
27430 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27431
27432#line 27432 "ad_x86.cpp"
27433 }
27434 {
27435
27436#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27437
27438 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27439 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27440 }
27441
27442#line 27442 "ad_x86.cpp"
27443 }
27444 {
27445
27446#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27447
27448 emit_opcode(cbuf, (0x0F));
27449
27450#line 27450 "ad_x86.cpp"
27451 }
27452 {
27453
27454#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27455
27456 emit_opcode(cbuf, (0x94));
27457
27458#line 27458 "ad_x86.cpp"
27459 }
27460 {
27461
27462#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27463
27464 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27465
27466#line 27466 "ad_x86.cpp"
27467 }
27468 {
27469
27470#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27471
27472 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27473 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27474 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27475 }
27476 } else {
27477 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27478 emit_opcode(cbuf, Assembler::REX_R);
27479 } else {
27480 emit_opcode(cbuf, Assembler::REX_RB);
27481 }
27482 }
27483
27484#line 27484 "ad_x86.cpp"
27485 }
27486 {
27487
27488#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27489
27490 emit_opcode(cbuf, (0xF));
27491
27492#line 27492 "ad_x86.cpp"
27493 }
27494 {
27495
27496#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27497
27498 emit_opcode(cbuf, (0xB6));
27499
27500#line 27500 "ad_x86.cpp"
27501 }
27502 {
27503
27504#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27505
27506 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27507
27508#line 27508 "ad_x86.cpp"
27509 }
27510}
27511
27512void compareAndSwapBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27513 cbuf.set_insts_mark();
27514 // Start at oper_input_base() and count operands
27515 unsigned idx0 = 2;
27516 unsigned idx1 = 2; // mem_ptr
27517 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27518 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27519 {
27520
27521#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27522
27523 emit_opcode(cbuf, 0xF0); // lock
27524
27525#line 27525 "ad_x86.cpp"
27526 }
27527 {
27528
27529#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27530
27531 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27532 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27533 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
27534 emit_opcode(cbuf, Assembler::REX_X);
27535 } else if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ >= 4) {
27536 emit_opcode(cbuf, Assembler::REX);
27537 }
27538 } else {
27539 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27540 emit_opcode(cbuf, Assembler::REX_B);
27541 } else {
27542 emit_opcode(cbuf, Assembler::REX_XB);
27543 }
27544 }
27545 } else {
27546 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27547 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27548 emit_opcode(cbuf, Assembler::REX_R);
27549 } else {
27550 emit_opcode(cbuf, Assembler::REX_RX);
27551 }
27552 } else {
27553 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27554 emit_opcode(cbuf, Assembler::REX_RB);
27555 } else {
27556 emit_opcode(cbuf, Assembler::REX_RXB);
27557 }
27558 }
27559 }
27560
27561#line 27561 "ad_x86.cpp"
27562 }
27563 {
27564
27565#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27566
27567 emit_opcode(cbuf, (0x0F /*primary()*/));
27568
27569#line 27569 "ad_x86.cpp"
27570 }
27571 {
27572
27573#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27574
27575 emit_opcode(cbuf, (0xB0 /*secondary()*/));
27576
27577#line 27577 "ad_x86.cpp"
27578 }
27579 {
27580
27581#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27582
27583 // High registers handle in encode_RegMem
27584 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27585 int base = opnd_array(1)->base(ra_,this,idx1);
27586 int index = opnd_array(1)->index(ra_,this,idx1);
27587 int scale = opnd_array(1)->scale();
27588 int disp = opnd_array(1)->disp(ra_,this,idx1);
27589 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27590
27591 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27592
27593#line 27593 "ad_x86.cpp"
27594 }
27595 {
27596
27597#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27598
27599 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27600 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27601 }
27602
27603#line 27603 "ad_x86.cpp"
27604 }
27605 {
27606
27607#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27608
27609 emit_opcode(cbuf, (0x0F));
27610
27611#line 27611 "ad_x86.cpp"
27612 }
27613 {
27614
27615#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27616
27617 emit_opcode(cbuf, (0x94));
27618
27619#line 27619 "ad_x86.cpp"
27620 }
27621 {
27622
27623#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27624
27625 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27626
27627#line 27627 "ad_x86.cpp"
27628 }
27629 {
27630
27631#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27632
27633 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27634 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27635 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27636 }
27637 } else {
27638 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27639 emit_opcode(cbuf, Assembler::REX_R);
27640 } else {
27641 emit_opcode(cbuf, Assembler::REX_RB);
27642 }
27643 }
27644
27645#line 27645 "ad_x86.cpp"
27646 }
27647 {
27648
27649#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27650
27651 emit_opcode(cbuf, (0xF));
27652
27653#line 27653 "ad_x86.cpp"
27654 }
27655 {
27656
27657#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27658
27659 emit_opcode(cbuf, (0xB6));
27660
27661#line 27661 "ad_x86.cpp"
27662 }
27663 {
27664
27665#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27666
27667 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27668
27669#line 27669 "ad_x86.cpp"
27670 }
27671}
27672
27673void compareAndSwapB_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27674 cbuf.set_insts_mark();
27675 // Start at oper_input_base() and count operands
27676 unsigned idx0 = 2;
27677 unsigned idx1 = 2; // mem_ptr
27678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27679 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27680 {
27681
27682#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27683
27684 emit_opcode(cbuf, 0xF0); // lock
27685
27686#line 27686 "ad_x86.cpp"
27687 }
27688 {
27689
27690#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27691
27692 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27693 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27694 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
27695 emit_opcode(cbuf, Assembler::REX_X);
27696 } else if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ >= 4) {
27697 emit_opcode(cbuf, Assembler::REX);
27698 }
27699 } else {
27700 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27701 emit_opcode(cbuf, Assembler::REX_B);
27702 } else {
27703 emit_opcode(cbuf, Assembler::REX_XB);
27704 }
27705 }
27706 } else {
27707 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27708 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27709 emit_opcode(cbuf, Assembler::REX_R);
27710 } else {
27711 emit_opcode(cbuf, Assembler::REX_RX);
27712 }
27713 } else {
27714 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27715 emit_opcode(cbuf, Assembler::REX_RB);
27716 } else {
27717 emit_opcode(cbuf, Assembler::REX_RXB);
27718 }
27719 }
27720 }
27721
27722#line 27722 "ad_x86.cpp"
27723 }
27724 {
27725
27726#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27727
27728 emit_opcode(cbuf, (0x0F /*primary()*/));
27729
27730#line 27730 "ad_x86.cpp"
27731 }
27732 {
27733
27734#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27735
27736 emit_opcode(cbuf, (0xB0 /*secondary()*/));
27737
27738#line 27738 "ad_x86.cpp"
27739 }
27740 {
27741
27742#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27743
27744 // High registers handle in encode_RegMem
27745 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27746 int base = opnd_array(1)->base(ra_,this,idx1);
27747 int index = opnd_array(1)->index(ra_,this,idx1);
27748 int scale = opnd_array(1)->scale();
27749 int disp = opnd_array(1)->disp(ra_,this,idx1);
27750 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27751
27752 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27753
27754#line 27754 "ad_x86.cpp"
27755 }
27756 {
27757
27758#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27759
27760 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27761 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27762 }
27763
27764#line 27764 "ad_x86.cpp"
27765 }
27766 {
27767
27768#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27769
27770 emit_opcode(cbuf, (0x0F));
27771
27772#line 27772 "ad_x86.cpp"
27773 }
27774 {
27775
27776#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27777
27778 emit_opcode(cbuf, (0x94));
27779
27780#line 27780 "ad_x86.cpp"
27781 }
27782 {
27783
27784#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27785
27786 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27787
27788#line 27788 "ad_x86.cpp"
27789 }
27790 {
27791
27792#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27793
27794 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27795 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27796 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27797 }
27798 } else {
27799 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27800 emit_opcode(cbuf, Assembler::REX_R);
27801 } else {
27802 emit_opcode(cbuf, Assembler::REX_RB);
27803 }
27804 }
27805
27806#line 27806 "ad_x86.cpp"
27807 }
27808 {
27809
27810#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27811
27812 emit_opcode(cbuf, (0xF));
27813
27814#line 27814 "ad_x86.cpp"
27815 }
27816 {
27817
27818#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27819
27820 emit_opcode(cbuf, (0xB6));
27821
27822#line 27822 "ad_x86.cpp"
27823 }
27824 {
27825
27826#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27827
27828 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27829
27830#line 27830 "ad_x86.cpp"
27831 }
27832}
27833
27834void compareAndSwapSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27835 cbuf.set_insts_mark();
27836 // Start at oper_input_base() and count operands
27837 unsigned idx0 = 2;
27838 unsigned idx1 = 2; // mem_ptr
27839 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
27840 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
27841 {
27842
27843#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27844
27845 emit_opcode(cbuf, 0xF0); // lock
27846
27847#line 27847 "ad_x86.cpp"
27848 }
27849 {
27850
27851#line 1836 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27852
27853 emit_opcode(cbuf, 0x66);
27854
27855#line 27855 "ad_x86.cpp"
27856 }
27857 {
27858
27859#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27860
27861 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
27862 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27863 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
27864 emit_opcode(cbuf, Assembler::REX_X);
27865 }
27866 } else {
27867 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27868 emit_opcode(cbuf, Assembler::REX_B);
27869 } else {
27870 emit_opcode(cbuf, Assembler::REX_XB);
27871 }
27872 }
27873 } else {
27874 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
27875 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27876 emit_opcode(cbuf, Assembler::REX_R);
27877 } else {
27878 emit_opcode(cbuf, Assembler::REX_RX);
27879 }
27880 } else {
27881 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
27882 emit_opcode(cbuf, Assembler::REX_RB);
27883 } else {
27884 emit_opcode(cbuf, Assembler::REX_RXB);
27885 }
27886 }
27887 }
27888
27889#line 27889 "ad_x86.cpp"
27890 }
27891 {
27892
27893#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27894
27895 emit_opcode(cbuf, (0x0F /*primary()*/));
27896
27897#line 27897 "ad_x86.cpp"
27898 }
27899 {
27900
27901#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27902
27903 emit_opcode(cbuf, (0xB1 /*secondary()*/));
27904
27905#line 27905 "ad_x86.cpp"
27906 }
27907 {
27908
27909#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27910
27911 // High registers handle in encode_RegMem
27912 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
27913 int base = opnd_array(1)->base(ra_,this,idx1);
27914 int index = opnd_array(1)->index(ra_,this,idx1);
27915 int scale = opnd_array(1)->scale();
27916 int disp = opnd_array(1)->disp(ra_,this,idx1);
27917 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
27918
27919 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
27920
27921#line 27921 "ad_x86.cpp"
27922 }
27923 {
27924
27925#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27926
27927 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27928 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27929 }
27930
27931#line 27931 "ad_x86.cpp"
27932 }
27933 {
27934
27935#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27936
27937 emit_opcode(cbuf, (0x0F));
27938
27939#line 27939 "ad_x86.cpp"
27940 }
27941 {
27942
27943#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27944
27945 emit_opcode(cbuf, (0x94));
27946
27947#line 27947 "ad_x86.cpp"
27948 }
27949 {
27950
27951#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27952
27953 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27954
27955#line 27955 "ad_x86.cpp"
27956 }
27957 {
27958
27959#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27960
27961 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27962 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
27963 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
27964 }
27965 } else {
27966 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
27967 emit_opcode(cbuf, Assembler::REX_R);
27968 } else {
27969 emit_opcode(cbuf, Assembler::REX_RB);
27970 }
27971 }
27972
27973#line 27973 "ad_x86.cpp"
27974 }
27975 {
27976
27977#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27978
27979 emit_opcode(cbuf, (0xF));
27980
27981#line 27981 "ad_x86.cpp"
27982 }
27983 {
27984
27985#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27986
27987 emit_opcode(cbuf, (0xB6));
27988
27989#line 27989 "ad_x86.cpp"
27990 }
27991 {
27992
27993#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
27994
27995 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
27996
27997#line 27997 "ad_x86.cpp"
27998 }
27999}
28000
28001void compareAndSwapS_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28002 cbuf.set_insts_mark();
28003 // Start at oper_input_base() and count operands
28004 unsigned idx0 = 2;
28005 unsigned idx1 = 2; // mem_ptr
28006 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28007 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28008 {
28009
28010#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28011
28012 emit_opcode(cbuf, 0xF0); // lock
28013
28014#line 28014 "ad_x86.cpp"
28015 }
28016 {
28017
28018#line 1836 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28019
28020 emit_opcode(cbuf, 0x66);
28021
28022#line 28022 "ad_x86.cpp"
28023 }
28024 {
28025
28026#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28027
28028 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28029 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28030 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28031 emit_opcode(cbuf, Assembler::REX_X);
28032 }
28033 } else {
28034 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28035 emit_opcode(cbuf, Assembler::REX_B);
28036 } else {
28037 emit_opcode(cbuf, Assembler::REX_XB);
28038 }
28039 }
28040 } else {
28041 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28042 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28043 emit_opcode(cbuf, Assembler::REX_R);
28044 } else {
28045 emit_opcode(cbuf, Assembler::REX_RX);
28046 }
28047 } else {
28048 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28049 emit_opcode(cbuf, Assembler::REX_RB);
28050 } else {
28051 emit_opcode(cbuf, Assembler::REX_RXB);
28052 }
28053 }
28054 }
28055
28056#line 28056 "ad_x86.cpp"
28057 }
28058 {
28059
28060#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28061
28062 emit_opcode(cbuf, (0x0F /*primary()*/));
28063
28064#line 28064 "ad_x86.cpp"
28065 }
28066 {
28067
28068#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28069
28070 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28071
28072#line 28072 "ad_x86.cpp"
28073 }
28074 {
28075
28076#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28077
28078 // High registers handle in encode_RegMem
28079 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28080 int base = opnd_array(1)->base(ra_,this,idx1);
28081 int index = opnd_array(1)->index(ra_,this,idx1);
28082 int scale = opnd_array(1)->scale();
28083 int disp = opnd_array(1)->disp(ra_,this,idx1);
28084 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28085
28086 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28087
28088#line 28088 "ad_x86.cpp"
28089 }
28090 {
28091
28092#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28093
28094 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28095 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28096 }
28097
28098#line 28098 "ad_x86.cpp"
28099 }
28100 {
28101
28102#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28103
28104 emit_opcode(cbuf, (0x0F));
28105
28106#line 28106 "ad_x86.cpp"
28107 }
28108 {
28109
28110#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28111
28112 emit_opcode(cbuf, (0x94));
28113
28114#line 28114 "ad_x86.cpp"
28115 }
28116 {
28117
28118#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28119
28120 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28121
28122#line 28122 "ad_x86.cpp"
28123 }
28124 {
28125
28126#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28127
28128 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28129 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28130 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28131 }
28132 } else {
28133 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28134 emit_opcode(cbuf, Assembler::REX_R);
28135 } else {
28136 emit_opcode(cbuf, Assembler::REX_RB);
28137 }
28138 }
28139
28140#line 28140 "ad_x86.cpp"
28141 }
28142 {
28143
28144#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28145
28146 emit_opcode(cbuf, (0xF));
28147
28148#line 28148 "ad_x86.cpp"
28149 }
28150 {
28151
28152#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28153
28154 emit_opcode(cbuf, (0xB6));
28155
28156#line 28156 "ad_x86.cpp"
28157 }
28158 {
28159
28160#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28161
28162 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28163
28164#line 28164 "ad_x86.cpp"
28165 }
28166}
28167
28168void compareAndSwapNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28169 cbuf.set_insts_mark();
28170 // Start at oper_input_base() and count operands
28171 unsigned idx0 = 2;
28172 unsigned idx1 = 2; // mem_ptr
28173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28174 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28175 {
28176
28177#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28178
28179 emit_opcode(cbuf, 0xF0); // lock
28180
28181#line 28181 "ad_x86.cpp"
28182 }
28183 {
28184
28185#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28186
28187 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28188 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28189 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28190 emit_opcode(cbuf, Assembler::REX_X);
28191 }
28192 } else {
28193 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28194 emit_opcode(cbuf, Assembler::REX_B);
28195 } else {
28196 emit_opcode(cbuf, Assembler::REX_XB);
28197 }
28198 }
28199 } else {
28200 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28201 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28202 emit_opcode(cbuf, Assembler::REX_R);
28203 } else {
28204 emit_opcode(cbuf, Assembler::REX_RX);
28205 }
28206 } else {
28207 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28208 emit_opcode(cbuf, Assembler::REX_RB);
28209 } else {
28210 emit_opcode(cbuf, Assembler::REX_RXB);
28211 }
28212 }
28213 }
28214
28215#line 28215 "ad_x86.cpp"
28216 }
28217 {
28218
28219#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28220
28221 emit_opcode(cbuf, (0x0F /*primary()*/));
28222
28223#line 28223 "ad_x86.cpp"
28224 }
28225 {
28226
28227#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28228
28229 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28230
28231#line 28231 "ad_x86.cpp"
28232 }
28233 {
28234
28235#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28236
28237 // High registers handle in encode_RegMem
28238 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28239 int base = opnd_array(1)->base(ra_,this,idx1);
28240 int index = opnd_array(1)->index(ra_,this,idx1);
28241 int scale = opnd_array(1)->scale();
28242 int disp = opnd_array(1)->disp(ra_,this,idx1);
28243 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28244
28245 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28246
28247#line 28247 "ad_x86.cpp"
28248 }
28249 {
28250
28251#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28252
28253 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28254 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28255 }
28256
28257#line 28257 "ad_x86.cpp"
28258 }
28259 {
28260
28261#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28262
28263 emit_opcode(cbuf, (0x0F));
28264
28265#line 28265 "ad_x86.cpp"
28266 }
28267 {
28268
28269#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28270
28271 emit_opcode(cbuf, (0x94));
28272
28273#line 28273 "ad_x86.cpp"
28274 }
28275 {
28276
28277#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28278
28279 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28280
28281#line 28281 "ad_x86.cpp"
28282 }
28283 {
28284
28285#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28286
28287 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28288 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28289 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28290 }
28291 } else {
28292 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28293 emit_opcode(cbuf, Assembler::REX_R);
28294 } else {
28295 emit_opcode(cbuf, Assembler::REX_RB);
28296 }
28297 }
28298
28299#line 28299 "ad_x86.cpp"
28300 }
28301 {
28302
28303#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28304
28305 emit_opcode(cbuf, (0xF));
28306
28307#line 28307 "ad_x86.cpp"
28308 }
28309 {
28310
28311#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28312
28313 emit_opcode(cbuf, (0xB6));
28314
28315#line 28315 "ad_x86.cpp"
28316 }
28317 {
28318
28319#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28320
28321 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28322
28323#line 28323 "ad_x86.cpp"
28324 }
28325}
28326
28327void compareAndSwapN_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28328 cbuf.set_insts_mark();
28329 // Start at oper_input_base() and count operands
28330 unsigned idx0 = 2;
28331 unsigned idx1 = 2; // mem_ptr
28332 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28333 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28334 {
28335
28336#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28337
28338 emit_opcode(cbuf, 0xF0); // lock
28339
28340#line 28340 "ad_x86.cpp"
28341 }
28342 {
28343
28344#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28345
28346 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28347 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28348 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28349 emit_opcode(cbuf, Assembler::REX_X);
28350 }
28351 } else {
28352 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28353 emit_opcode(cbuf, Assembler::REX_B);
28354 } else {
28355 emit_opcode(cbuf, Assembler::REX_XB);
28356 }
28357 }
28358 } else {
28359 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28360 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28361 emit_opcode(cbuf, Assembler::REX_R);
28362 } else {
28363 emit_opcode(cbuf, Assembler::REX_RX);
28364 }
28365 } else {
28366 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28367 emit_opcode(cbuf, Assembler::REX_RB);
28368 } else {
28369 emit_opcode(cbuf, Assembler::REX_RXB);
28370 }
28371 }
28372 }
28373
28374#line 28374 "ad_x86.cpp"
28375 }
28376 {
28377
28378#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28379
28380 emit_opcode(cbuf, (0x0F /*primary()*/));
28381
28382#line 28382 "ad_x86.cpp"
28383 }
28384 {
28385
28386#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28387
28388 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28389
28390#line 28390 "ad_x86.cpp"
28391 }
28392 {
28393
28394#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28395
28396 // High registers handle in encode_RegMem
28397 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28398 int base = opnd_array(1)->base(ra_,this,idx1);
28399 int index = opnd_array(1)->index(ra_,this,idx1);
28400 int scale = opnd_array(1)->scale();
28401 int disp = opnd_array(1)->disp(ra_,this,idx1);
28402 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28403
28404 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28405
28406#line 28406 "ad_x86.cpp"
28407 }
28408 {
28409
28410#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28411
28412 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28413 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28414 }
28415
28416#line 28416 "ad_x86.cpp"
28417 }
28418 {
28419
28420#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28421
28422 emit_opcode(cbuf, (0x0F));
28423
28424#line 28424 "ad_x86.cpp"
28425 }
28426 {
28427
28428#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28429
28430 emit_opcode(cbuf, (0x94));
28431
28432#line 28432 "ad_x86.cpp"
28433 }
28434 {
28435
28436#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28437
28438 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28439
28440#line 28440 "ad_x86.cpp"
28441 }
28442 {
28443
28444#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28445
28446 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28447 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
28448 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
28449 }
28450 } else {
28451 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
28452 emit_opcode(cbuf, Assembler::REX_R);
28453 } else {
28454 emit_opcode(cbuf, Assembler::REX_RB);
28455 }
28456 }
28457
28458#line 28458 "ad_x86.cpp"
28459 }
28460 {
28461
28462#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28463
28464 emit_opcode(cbuf, (0xF));
28465
28466#line 28466 "ad_x86.cpp"
28467 }
28468 {
28469
28470#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28471
28472 emit_opcode(cbuf, (0xB6));
28473
28474#line 28474 "ad_x86.cpp"
28475 }
28476 {
28477
28478#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28479
28480 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
28481
28482#line 28482 "ad_x86.cpp"
28483 }
28484}
28485
28486void compareAndExchangeBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28487 cbuf.set_insts_mark();
28488 // Start at oper_input_base() and count operands
28489 unsigned idx0 = 2;
28490 unsigned idx1 = 2; // mem_ptr
28491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28492 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28493 {
28494
28495#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28496
28497 emit_opcode(cbuf, 0xF0); // lock
28498
28499#line 28499 "ad_x86.cpp"
28500 }
28501 {
28502
28503#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28504
28505 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28506 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28507 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28508 emit_opcode(cbuf, Assembler::REX_X);
28509 } else if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ >= 4) {
28510 emit_opcode(cbuf, Assembler::REX);
28511 }
28512 } else {
28513 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28514 emit_opcode(cbuf, Assembler::REX_B);
28515 } else {
28516 emit_opcode(cbuf, Assembler::REX_XB);
28517 }
28518 }
28519 } else {
28520 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28521 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28522 emit_opcode(cbuf, Assembler::REX_R);
28523 } else {
28524 emit_opcode(cbuf, Assembler::REX_RX);
28525 }
28526 } else {
28527 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28528 emit_opcode(cbuf, Assembler::REX_RB);
28529 } else {
28530 emit_opcode(cbuf, Assembler::REX_RXB);
28531 }
28532 }
28533 }
28534
28535#line 28535 "ad_x86.cpp"
28536 }
28537 {
28538
28539#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28540
28541 emit_opcode(cbuf, (0x0F /*primary()*/));
28542
28543#line 28543 "ad_x86.cpp"
28544 }
28545 {
28546
28547#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28548
28549 emit_opcode(cbuf, (0xB0 /*secondary()*/));
28550
28551#line 28551 "ad_x86.cpp"
28552 }
28553 {
28554
28555#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28556
28557 // High registers handle in encode_RegMem
28558 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28559 int base = opnd_array(1)->base(ra_,this,idx1);
28560 int index = opnd_array(1)->index(ra_,this,idx1);
28561 int scale = opnd_array(1)->scale();
28562 int disp = opnd_array(1)->disp(ra_,this,idx1);
28563 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28564
28565 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28566
28567#line 28567 "ad_x86.cpp"
28568 }
28569}
28570
28571void compareAndExchangeSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28572 cbuf.set_insts_mark();
28573 // Start at oper_input_base() and count operands
28574 unsigned idx0 = 2;
28575 unsigned idx1 = 2; // mem_ptr
28576 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28577 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28578 {
28579
28580#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28581
28582 emit_opcode(cbuf, 0xF0); // lock
28583
28584#line 28584 "ad_x86.cpp"
28585 }
28586 {
28587
28588#line 1836 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28589
28590 emit_opcode(cbuf, 0x66);
28591
28592#line 28592 "ad_x86.cpp"
28593 }
28594 {
28595
28596#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28597
28598 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28599 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28600 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28601 emit_opcode(cbuf, Assembler::REX_X);
28602 }
28603 } else {
28604 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28605 emit_opcode(cbuf, Assembler::REX_B);
28606 } else {
28607 emit_opcode(cbuf, Assembler::REX_XB);
28608 }
28609 }
28610 } else {
28611 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28612 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28613 emit_opcode(cbuf, Assembler::REX_R);
28614 } else {
28615 emit_opcode(cbuf, Assembler::REX_RX);
28616 }
28617 } else {
28618 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28619 emit_opcode(cbuf, Assembler::REX_RB);
28620 } else {
28621 emit_opcode(cbuf, Assembler::REX_RXB);
28622 }
28623 }
28624 }
28625
28626#line 28626 "ad_x86.cpp"
28627 }
28628 {
28629
28630#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28631
28632 emit_opcode(cbuf, (0x0F /*primary()*/));
28633
28634#line 28634 "ad_x86.cpp"
28635 }
28636 {
28637
28638#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28639
28640 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28641
28642#line 28642 "ad_x86.cpp"
28643 }
28644 {
28645
28646#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28647
28648 // High registers handle in encode_RegMem
28649 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28650 int base = opnd_array(1)->base(ra_,this,idx1);
28651 int index = opnd_array(1)->index(ra_,this,idx1);
28652 int scale = opnd_array(1)->scale();
28653 int disp = opnd_array(1)->disp(ra_,this,idx1);
28654 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28655
28656 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28657
28658#line 28658 "ad_x86.cpp"
28659 }
28660}
28661
28662void compareAndExchangeINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28663 cbuf.set_insts_mark();
28664 // Start at oper_input_base() and count operands
28665 unsigned idx0 = 2;
28666 unsigned idx1 = 2; // mem_ptr
28667 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28668 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28669 {
28670
28671#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28672
28673 emit_opcode(cbuf, 0xF0); // lock
28674
28675#line 28675 "ad_x86.cpp"
28676 }
28677 {
28678
28679#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28680
28681 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28682 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28683 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28684 emit_opcode(cbuf, Assembler::REX_X);
28685 }
28686 } else {
28687 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28688 emit_opcode(cbuf, Assembler::REX_B);
28689 } else {
28690 emit_opcode(cbuf, Assembler::REX_XB);
28691 }
28692 }
28693 } else {
28694 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28695 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28696 emit_opcode(cbuf, Assembler::REX_R);
28697 } else {
28698 emit_opcode(cbuf, Assembler::REX_RX);
28699 }
28700 } else {
28701 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28702 emit_opcode(cbuf, Assembler::REX_RB);
28703 } else {
28704 emit_opcode(cbuf, Assembler::REX_RXB);
28705 }
28706 }
28707 }
28708
28709#line 28709 "ad_x86.cpp"
28710 }
28711 {
28712
28713#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28714
28715 emit_opcode(cbuf, (0x0F /*primary()*/));
28716
28717#line 28717 "ad_x86.cpp"
28718 }
28719 {
28720
28721#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28722
28723 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28724
28725#line 28725 "ad_x86.cpp"
28726 }
28727 {
28728
28729#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28730
28731 // High registers handle in encode_RegMem
28732 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28733 int base = opnd_array(1)->base(ra_,this,idx1);
28734 int index = opnd_array(1)->index(ra_,this,idx1);
28735 int scale = opnd_array(1)->scale();
28736 int disp = opnd_array(1)->disp(ra_,this,idx1);
28737 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28738
28739 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28740
28741#line 28741 "ad_x86.cpp"
28742 }
28743}
28744
28745void compareAndExchangeLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28746 cbuf.set_insts_mark();
28747 // Start at oper_input_base() and count operands
28748 unsigned idx0 = 2;
28749 unsigned idx1 = 2; // mem_ptr
28750 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28751 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28752 {
28753
28754#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28755
28756 emit_opcode(cbuf, 0xF0); // lock
28757
28758#line 28758 "ad_x86.cpp"
28759 }
28760 {
28761
28762#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28763
28764 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28765 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28766 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28767 emit_opcode(cbuf, Assembler::REX_W);
28768 } else {
28769 emit_opcode(cbuf, Assembler::REX_WX);
28770 }
28771 } else {
28772 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28773 emit_opcode(cbuf, Assembler::REX_WB);
28774 } else {
28775 emit_opcode(cbuf, Assembler::REX_WXB);
28776 }
28777 }
28778 } else {
28779 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28780 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28781 emit_opcode(cbuf, Assembler::REX_WR);
28782 } else {
28783 emit_opcode(cbuf, Assembler::REX_WRX);
28784 }
28785 } else {
28786 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28787 emit_opcode(cbuf, Assembler::REX_WRB);
28788 } else {
28789 emit_opcode(cbuf, Assembler::REX_WRXB);
28790 }
28791 }
28792 }
28793
28794#line 28794 "ad_x86.cpp"
28795 }
28796 {
28797
28798#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28799
28800 emit_opcode(cbuf, (0x0F /*primary()*/));
28801
28802#line 28802 "ad_x86.cpp"
28803 }
28804 {
28805
28806#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28807
28808 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28809
28810#line 28810 "ad_x86.cpp"
28811 }
28812 {
28813
28814#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28815
28816 // High registers handle in encode_RegMem
28817 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28818 int base = opnd_array(1)->base(ra_,this,idx1);
28819 int index = opnd_array(1)->index(ra_,this,idx1);
28820 int scale = opnd_array(1)->scale();
28821 int disp = opnd_array(1)->disp(ra_,this,idx1);
28822 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28823
28824 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28825
28826#line 28826 "ad_x86.cpp"
28827 }
28828}
28829
28830void compareAndExchangeNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28831 cbuf.set_insts_mark();
28832 // Start at oper_input_base() and count operands
28833 unsigned idx0 = 2;
28834 unsigned idx1 = 2; // mem_ptr
28835 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28836 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28837 {
28838
28839#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28840
28841 emit_opcode(cbuf, 0xF0); // lock
28842
28843#line 28843 "ad_x86.cpp"
28844 }
28845 {
28846
28847#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28848
28849 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28850 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28851 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
28852 emit_opcode(cbuf, Assembler::REX_X);
28853 }
28854 } else {
28855 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28856 emit_opcode(cbuf, Assembler::REX_B);
28857 } else {
28858 emit_opcode(cbuf, Assembler::REX_XB);
28859 }
28860 }
28861 } else {
28862 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28863 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28864 emit_opcode(cbuf, Assembler::REX_R);
28865 } else {
28866 emit_opcode(cbuf, Assembler::REX_RX);
28867 }
28868 } else {
28869 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28870 emit_opcode(cbuf, Assembler::REX_RB);
28871 } else {
28872 emit_opcode(cbuf, Assembler::REX_RXB);
28873 }
28874 }
28875 }
28876
28877#line 28877 "ad_x86.cpp"
28878 }
28879 {
28880
28881#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28882
28883 emit_opcode(cbuf, (0x0F /*primary()*/));
28884
28885#line 28885 "ad_x86.cpp"
28886 }
28887 {
28888
28889#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28890
28891 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28892
28893#line 28893 "ad_x86.cpp"
28894 }
28895 {
28896
28897#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28898
28899 // High registers handle in encode_RegMem
28900 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28901 int base = opnd_array(1)->base(ra_,this,idx1);
28902 int index = opnd_array(1)->index(ra_,this,idx1);
28903 int scale = opnd_array(1)->scale();
28904 int disp = opnd_array(1)->disp(ra_,this,idx1);
28905 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28906
28907 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28908
28909#line 28909 "ad_x86.cpp"
28910 }
28911}
28912
28913void compareAndExchangePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28914 cbuf.set_insts_mark();
28915 // Start at oper_input_base() and count operands
28916 unsigned idx0 = 2;
28917 unsigned idx1 = 2; // mem_ptr
28918 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
28919 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
28920 {
28921
28922#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28923
28924 emit_opcode(cbuf, 0xF0); // lock
28925
28926#line 28926 "ad_x86.cpp"
28927 }
28928 {
28929
28930#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28931
28932 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
28933 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28934 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28935 emit_opcode(cbuf, Assembler::REX_W);
28936 } else {
28937 emit_opcode(cbuf, Assembler::REX_WX);
28938 }
28939 } else {
28940 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28941 emit_opcode(cbuf, Assembler::REX_WB);
28942 } else {
28943 emit_opcode(cbuf, Assembler::REX_WXB);
28944 }
28945 }
28946 } else {
28947 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
28948 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28949 emit_opcode(cbuf, Assembler::REX_WR);
28950 } else {
28951 emit_opcode(cbuf, Assembler::REX_WRX);
28952 }
28953 } else {
28954 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
28955 emit_opcode(cbuf, Assembler::REX_WRB);
28956 } else {
28957 emit_opcode(cbuf, Assembler::REX_WRXB);
28958 }
28959 }
28960 }
28961
28962#line 28962 "ad_x86.cpp"
28963 }
28964 {
28965
28966#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28967
28968 emit_opcode(cbuf, (0x0F /*primary()*/));
28969
28970#line 28970 "ad_x86.cpp"
28971 }
28972 {
28973
28974#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28975
28976 emit_opcode(cbuf, (0xB1 /*secondary()*/));
28977
28978#line 28978 "ad_x86.cpp"
28979 }
28980 {
28981
28982#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
28983
28984 // High registers handle in encode_RegMem
28985 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
28986 int base = opnd_array(1)->base(ra_,this,idx1);
28987 int index = opnd_array(1)->index(ra_,this,idx1);
28988 int scale = opnd_array(1)->scale();
28989 int disp = opnd_array(1)->disp(ra_,this,idx1);
28990 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
28991
28992 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
28993
28994#line 28994 "ad_x86.cpp"
28995 }
28996}
28997
28998void xaddB_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28999 cbuf.set_insts_mark();
29000 // Start at oper_input_base() and count operands
29001 unsigned idx0 = 2;
29002 unsigned idx1 = 2; // mem
29003 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
29004 {
29005 MacroAssembler _masm(&cbuf);
29006
29007#line 8058 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29008
29009 __ lock();
29010 __ addb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29011
29012#line 29012 "ad_x86.cpp"
29013 }
29014}
29015
29016void xaddBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29017 cbuf.set_insts_mark();
29018 // Start at oper_input_base() and count operands
29019 unsigned idx0 = 2;
29020 unsigned idx1 = 2; // mem
29021 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29022 {
29023 MacroAssembler _masm(&cbuf);
29024
29025#line 8069 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29026
29027 __ lock();
29028 __ xaddb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
29029
29030#line 29030 "ad_x86.cpp"
29031 }
29032}
29033
29034void xaddS_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29035 cbuf.set_insts_mark();
29036 // Start at oper_input_base() and count operands
29037 unsigned idx0 = 2;
29038 unsigned idx1 = 2; // mem
29039 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
29040 {
29041 MacroAssembler _masm(&cbuf);
29042
29043#line 8081 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29044
29045 __ lock();
29046 __ addw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29047
29048#line 29048 "ad_x86.cpp"
29049 }
29050}
29051
29052void xaddSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29053 cbuf.set_insts_mark();
29054 // Start at oper_input_base() and count operands
29055 unsigned idx0 = 2;
29056 unsigned idx1 = 2; // mem
29057 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29058 {
29059 MacroAssembler _masm(&cbuf);
29060
29061#line 8092 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29062
29063 __ lock();
29064 __ xaddw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
29065
29066#line 29066 "ad_x86.cpp"
29067 }
29068}
29069
29070void xaddI_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29071 cbuf.set_insts_mark();
29072 // Start at oper_input_base() and count operands
29073 unsigned idx0 = 2;
29074 unsigned idx1 = 2; // mem
29075 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
29076 {
29077 MacroAssembler _masm(&cbuf);
29078
29079#line 8104 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29080
29081 __ lock();
29082 __ addl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29083
29084#line 29084 "ad_x86.cpp"
29085 }
29086}
29087
29088void xaddINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29089 cbuf.set_insts_mark();
29090 // Start at oper_input_base() and count operands
29091 unsigned idx0 = 2;
29092 unsigned idx1 = 2; // mem
29093 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29094 {
29095 MacroAssembler _masm(&cbuf);
29096
29097#line 8115 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29098
29099 __ lock();
29100 __ xaddl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
29101
29102#line 29102 "ad_x86.cpp"
29103 }
29104}
29105
29106void xaddL_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29107 cbuf.set_insts_mark();
29108 // Start at oper_input_base() and count operands
29109 unsigned idx0 = 2;
29110 unsigned idx1 = 2; // mem
29111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
29112 {
29113 MacroAssembler _masm(&cbuf);
29114
29115#line 8127 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29116
29117 __ lock();
29118 __ addq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
29119
29120#line 29120 "ad_x86.cpp"
29121 }
29122}
29123
29124void xaddLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29125 cbuf.set_insts_mark();
29126 // Start at oper_input_base() and count operands
29127 unsigned idx0 = 2;
29128 unsigned idx1 = 2; // mem
29129 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29130 {
29131 MacroAssembler _masm(&cbuf);
29132
29133#line 8138 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29134
29135 __ lock();
29136 __ xaddq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
29137
29138#line 29138 "ad_x86.cpp"
29139 }
29140}
29141
29142void xchgBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29143 cbuf.set_insts_mark();
29144 // Start at oper_input_base() and count operands
29145 unsigned idx0 = 2;
29146 unsigned idx1 = 2; // mem
29147 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29148 {
29149 MacroAssembler _masm(&cbuf);
29150
29151#line 8148 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29152
29153 __ xchgb(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29154
29155#line 29155 "ad_x86.cpp"
29156 }
29157}
29158
29159void xchgSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29160 cbuf.set_insts_mark();
29161 // Start at oper_input_base() and count operands
29162 unsigned idx0 = 2;
29163 unsigned idx1 = 2; // mem
29164 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29165 {
29166 MacroAssembler _masm(&cbuf);
29167
29168#line 8157 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29169
29170 __ xchgw(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29171
29172#line 29172 "ad_x86.cpp"
29173 }
29174}
29175
29176void xchgINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29177 cbuf.set_insts_mark();
29178 // Start at oper_input_base() and count operands
29179 unsigned idx0 = 2;
29180 unsigned idx1 = 2; // mem
29181 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29182 {
29183 MacroAssembler _masm(&cbuf);
29184
29185#line 8166 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29186
29187 __ xchgl(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29188
29189#line 29189 "ad_x86.cpp"
29190 }
29191}
29192
29193void xchgLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29194 cbuf.set_insts_mark();
29195 // Start at oper_input_base() and count operands
29196 unsigned idx0 = 2;
29197 unsigned idx1 = 2; // mem
29198 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29199 {
29200 MacroAssembler _masm(&cbuf);
29201
29202#line 8175 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29203
29204 __ xchgq(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29205
29206#line 29206 "ad_x86.cpp"
29207 }
29208}
29209
29210void xchgPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29211 cbuf.set_insts_mark();
29212 // Start at oper_input_base() and count operands
29213 unsigned idx0 = 2;
29214 unsigned idx1 = 2; // mem
29215 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29216 {
29217 MacroAssembler _masm(&cbuf);
29218
29219#line 8184 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29220
29221 __ xchgq(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29222
29223#line 29223 "ad_x86.cpp"
29224 }
29225}
29226
29227void xchgNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29228 cbuf.set_insts_mark();
29229 // Start at oper_input_base() and count operands
29230 unsigned idx0 = 2;
29231 unsigned idx1 = 2; // mem
29232 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
29233 {
29234 MacroAssembler _masm(&cbuf);
29235
29236#line 8193 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29237
29238 __ xchgl(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29239
29240#line 29240 "ad_x86.cpp"
29241 }
29242}
29243
29244void absI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29245 cbuf.set_insts_mark();
29246 // Start at oper_input_base() and count operands
29247 unsigned idx0 = 1;
29248 unsigned idx1 = 1; // src
29249 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
29250 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
29251 {
29252 MacroAssembler _masm(&cbuf);
29253
29254#line 8212 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29255
29256 __ movl(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29257 __ sarl(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, 31);
29258 __ movl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29259 __ xorl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
29260 __ subl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
29261
29262#line 29262 "ad_x86.cpp"
29263 }
29264}
29265
29266void absL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29267 cbuf.set_insts_mark();
29268 // Start at oper_input_base() and count operands
29269 unsigned idx0 = 1;
29270 unsigned idx1 = 1; // src
29271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
29272 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
29273 {
29274 MacroAssembler _masm(&cbuf);
29275
29276#line 8234 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29277
29278 __ movq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29279 __ sarq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, 63);
29280 __ movq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29281 __ xorq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
29282 __ subq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
29283
29284#line 29284 "ad_x86.cpp"
29285 }
29286}
29287
29288void subI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29289 cbuf.set_insts_mark();
29290 // Start at oper_input_base() and count operands
29291 unsigned idx0 = 1;
29292 unsigned idx1 = 1; // dst
29293 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29294 {
29295
29296#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29297
29298 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
29299 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
29300 emit_opcode(cbuf, Assembler::REX_B);
29301 }
29302 } else {
29303 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
29304 emit_opcode(cbuf, Assembler::REX_R);
29305 } else {
29306 emit_opcode(cbuf, Assembler::REX_RB);
29307 }
29308 }
29309
29310#line 29310 "ad_x86.cpp"
29311 }
29312 {
29313
29314#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29315
29316 emit_opcode(cbuf, (0x2B /*primary()*/));
29317
29318#line 29318 "ad_x86.cpp"
29319 }
29320 {
29321
29322#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29323
29324 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
29325
29326#line 29326 "ad_x86.cpp"
29327 }
29328}
29329
29330void subI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29331 cbuf.set_insts_mark();
29332 // Start at oper_input_base() and count operands
29333 unsigned idx0 = 1;
29334 unsigned idx1 = 1; // dst
29335 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29336 {
29337
29338#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29339
29340 // OpcSEr/m
29341 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
29342 if (dstenc >= 8) {
29343 emit_opcode(cbuf, Assembler::REX_B);
29344 dstenc -= 8;
29345 }
29346 // Emit primary opcode and set sign-extend bit
29347 // Check for 8-bit immediate, and set sign extend bit in opcode
29348 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
29349 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
29350 } else {
29351 // 32-bit immediate
29352 emit_opcode(cbuf, (0x81 /*primary()*/));
29353 }
29354 // Emit r/m byte with secondary opcode, after primary opcode.
29355 emit_rm(cbuf, 0x3, (0x05 /*secondary()*/), dstenc);
29356
29357#line 29357 "ad_x86.cpp"
29358 }
29359 {
29360
29361#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29362
29363 // Check for 8-bit immediate, and set sign extend bit in opcode
29364 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
29365 emit_d8(cbuf, opnd_array(2)->constant());
29366 } else {
29367 // 32-bit immediate
29368 emit_d32(cbuf, opnd_array(2)->constant());
29369 }
29370
29371#line 29371 "ad_x86.cpp"
29372 }
29373}
29374
29375void subI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29376 cbuf.set_insts_mark();
29377 // Start at oper_input_base() and count operands
29378 unsigned idx0 = 2;
29379 unsigned idx1 = 2; // dst
29380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29381 {
29382
29383#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29384
29385 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
29386 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
29387 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
29388 emit_opcode(cbuf, Assembler::REX_X);
29389 }
29390 } else {
29391 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29392 emit_opcode(cbuf, Assembler::REX_B);
29393 } else {
29394 emit_opcode(cbuf, Assembler::REX_XB);
29395 }
29396 }
29397 } else {
29398 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
29399 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29400 emit_opcode(cbuf, Assembler::REX_R);
29401 } else {
29402 emit_opcode(cbuf, Assembler::REX_RX);
29403 }
29404 } else {
29405 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29406 emit_opcode(cbuf, Assembler::REX_RB);
29407 } else {
29408 emit_opcode(cbuf, Assembler::REX_RXB);
29409 }
29410 }
29411 }
29412
29413#line 29413 "ad_x86.cpp"
29414 }
29415 {
29416
29417#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29418
29419 emit_opcode(cbuf, (0x2B /*primary()*/));
29420
29421#line 29421 "ad_x86.cpp"
29422 }
29423 {
29424
29425#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29426
29427 // High registers handle in encode_RegMem
29428 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
29429 int base = opnd_array(2)->base(ra_,this,idx2);
29430 int index = opnd_array(2)->index(ra_,this,idx2);
29431 int scale = opnd_array(2)->scale();
29432 int disp = opnd_array(2)->disp(ra_,this,idx2);
29433 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
29434
29435 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
29436
29437#line 29437 "ad_x86.cpp"
29438 }
29439}
29440
29441void subI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29442 cbuf.set_insts_mark();
29443 // Start at oper_input_base() and count operands
29444 unsigned idx0 = 2;
29445 unsigned idx1 = 2; // dst
29446 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29447 {
29448
29449#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29450
29451 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
29452 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
29453 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
29454 emit_opcode(cbuf, Assembler::REX_X);
29455 }
29456 } else {
29457 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29458 emit_opcode(cbuf, Assembler::REX_B);
29459 } else {
29460 emit_opcode(cbuf, Assembler::REX_XB);
29461 }
29462 }
29463 } else {
29464 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
29465 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29466 emit_opcode(cbuf, Assembler::REX_R);
29467 } else {
29468 emit_opcode(cbuf, Assembler::REX_RX);
29469 }
29470 } else {
29471 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29472 emit_opcode(cbuf, Assembler::REX_RB);
29473 } else {
29474 emit_opcode(cbuf, Assembler::REX_RXB);
29475 }
29476 }
29477 }
29478
29479#line 29479 "ad_x86.cpp"
29480 }
29481 {
29482
29483#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29484
29485 emit_opcode(cbuf, (0x29 /*primary()*/));
29486
29487#line 29487 "ad_x86.cpp"
29488 }
29489 {
29490
29491#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29492
29493 // High registers handle in encode_RegMem
29494 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
29495 int base = opnd_array(1)->base(ra_,this,idx1);
29496 int index = opnd_array(1)->index(ra_,this,idx1);
29497 int scale = opnd_array(1)->scale();
29498 int disp = opnd_array(1)->disp(ra_,this,idx1);
29499 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
29500
29501 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
29502
29503#line 29503 "ad_x86.cpp"
29504 }
29505}
29506
29507void subI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29508 cbuf.set_insts_mark();
29509 // Start at oper_input_base() and count operands
29510 unsigned idx0 = 2;
29511 unsigned idx1 = 2; // dst
29512 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29513 {
29514
29515#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29516
29517 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
29518 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29519 emit_opcode(cbuf, Assembler::REX_B);
29520 } else {
29521 emit_opcode(cbuf, Assembler::REX_XB);
29522 }
29523 } else {
29524 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
29525 emit_opcode(cbuf, Assembler::REX_X);
29526 }
29527 }
29528
29529#line 29529 "ad_x86.cpp"
29530 }
29531 {
29532
29533#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29534
29535 // Emit primary opcode and set sign-extend bit
29536 // Check for 8-bit immediate, and set sign extend bit in opcode
29537 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
29538 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
29539 } else {
29540 // 32-bit immediate
29541 emit_opcode(cbuf, (0x81 /*primary()*/));
29542 }
29543
29544#line 29544 "ad_x86.cpp"
29545 }
29546 {
29547
29548#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29549
29550 int rm_byte_opcode = (0x05);
29551
29552 // High registers handle in encode_RegMem
29553 int base = opnd_array(1)->base(ra_,this,idx1);
29554 int index = opnd_array(1)->index(ra_,this,idx1);
29555 int scale = opnd_array(1)->scale();
29556 int displace = opnd_array(1)->disp(ra_,this,idx1);
29557
29558 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
29559 // working with static
29560 // globals
29561 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
29562 disp_reloc);
29563
29564#line 29564 "ad_x86.cpp"
29565 }
29566 {
29567
29568#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29569
29570 // Check for 8-bit immediate, and set sign extend bit in opcode
29571 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
29572 emit_d8(cbuf, opnd_array(2)->constant());
29573 } else {
29574 // 32-bit immediate
29575 emit_d32(cbuf, opnd_array(2)->constant());
29576 }
29577
29578#line 29578 "ad_x86.cpp"
29579 }
29580}
29581
29582void subL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29583 cbuf.set_insts_mark();
29584 // Start at oper_input_base() and count operands
29585 unsigned idx0 = 1;
29586 unsigned idx1 = 1; // dst
29587 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29588 {
29589
29590#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29591
29592 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
29593 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
29594 emit_opcode(cbuf, Assembler::REX_W);
29595 } else {
29596 emit_opcode(cbuf, Assembler::REX_WB);
29597 }
29598 } else {
29599 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
29600 emit_opcode(cbuf, Assembler::REX_WR);
29601 } else {
29602 emit_opcode(cbuf, Assembler::REX_WRB);
29603 }
29604 }
29605
29606#line 29606 "ad_x86.cpp"
29607 }
29608 {
29609
29610#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29611
29612 emit_opcode(cbuf, (0x2B /*primary()*/));
29613
29614#line 29614 "ad_x86.cpp"
29615 }
29616 {
29617
29618#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29619
29620 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
29621
29622#line 29622 "ad_x86.cpp"
29623 }
29624}
29625
29626void subL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29627 cbuf.set_insts_mark();
29628 // Start at oper_input_base() and count operands
29629 unsigned idx0 = 1;
29630 unsigned idx1 = 1; // dst
29631 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29632 {
29633
29634#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29635
29636 // OpcSEr/m
29637 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
29638 if (dstenc < 8) {
29639 emit_opcode(cbuf, Assembler::REX_W);
29640 } else {
29641 emit_opcode(cbuf, Assembler::REX_WB);
29642 dstenc -= 8;
29643 }
29644 // Emit primary opcode and set sign-extend bit
29645 // Check for 8-bit immediate, and set sign extend bit in opcode
29646 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
29647 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
29648 } else {
29649 // 32-bit immediate
29650 emit_opcode(cbuf, (0x81 /*primary()*/));
29651 }
29652 // Emit r/m byte with secondary opcode, after primary opcode.
29653 emit_rm(cbuf, 0x3, (0x05 /*secondary()*/), dstenc);
29654
29655#line 29655 "ad_x86.cpp"
29656 }
29657 {
29658
29659#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29660
29661 // Check for 8-bit immediate, and set sign extend bit in opcode
29662 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
29663 emit_d8(cbuf, opnd_array(2)->constantL());
29664 } else {
29665 // 32-bit immediate
29666 emit_d32(cbuf, opnd_array(2)->constantL());
29667 }
29668
29669#line 29669 "ad_x86.cpp"
29670 }
29671}
29672
29673void subL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29674 cbuf.set_insts_mark();
29675 // Start at oper_input_base() and count operands
29676 unsigned idx0 = 2;
29677 unsigned idx1 = 2; // dst
29678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29679 {
29680
29681#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29682
29683 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
29684 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
29685 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29686 emit_opcode(cbuf, Assembler::REX_W);
29687 } else {
29688 emit_opcode(cbuf, Assembler::REX_WX);
29689 }
29690 } else {
29691 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29692 emit_opcode(cbuf, Assembler::REX_WB);
29693 } else {
29694 emit_opcode(cbuf, Assembler::REX_WXB);
29695 }
29696 }
29697 } else {
29698 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
29699 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29700 emit_opcode(cbuf, Assembler::REX_WR);
29701 } else {
29702 emit_opcode(cbuf, Assembler::REX_WRX);
29703 }
29704 } else {
29705 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
29706 emit_opcode(cbuf, Assembler::REX_WRB);
29707 } else {
29708 emit_opcode(cbuf, Assembler::REX_WRXB);
29709 }
29710 }
29711 }
29712
29713#line 29713 "ad_x86.cpp"
29714 }
29715 {
29716
29717#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29718
29719 emit_opcode(cbuf, (0x2B /*primary()*/));
29720
29721#line 29721 "ad_x86.cpp"
29722 }
29723 {
29724
29725#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29726
29727 // High registers handle in encode_RegMem
29728 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
29729 int base = opnd_array(2)->base(ra_,this,idx2);
29730 int index = opnd_array(2)->index(ra_,this,idx2);
29731 int scale = opnd_array(2)->scale();
29732 int disp = opnd_array(2)->disp(ra_,this,idx2);
29733 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
29734
29735 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
29736
29737#line 29737 "ad_x86.cpp"
29738 }
29739}
29740
29741void subL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29742 cbuf.set_insts_mark();
29743 // Start at oper_input_base() and count operands
29744 unsigned idx0 = 2;
29745 unsigned idx1 = 2; // dst
29746 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29747 {
29748
29749#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29750
29751 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
29752 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
29753 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29754 emit_opcode(cbuf, Assembler::REX_W);
29755 } else {
29756 emit_opcode(cbuf, Assembler::REX_WX);
29757 }
29758 } else {
29759 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29760 emit_opcode(cbuf, Assembler::REX_WB);
29761 } else {
29762 emit_opcode(cbuf, Assembler::REX_WXB);
29763 }
29764 }
29765 } else {
29766 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
29767 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29768 emit_opcode(cbuf, Assembler::REX_WR);
29769 } else {
29770 emit_opcode(cbuf, Assembler::REX_WRX);
29771 }
29772 } else {
29773 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29774 emit_opcode(cbuf, Assembler::REX_WRB);
29775 } else {
29776 emit_opcode(cbuf, Assembler::REX_WRXB);
29777 }
29778 }
29779 }
29780
29781#line 29781 "ad_x86.cpp"
29782 }
29783 {
29784
29785#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29786
29787 emit_opcode(cbuf, (0x29 /*primary()*/));
29788
29789#line 29789 "ad_x86.cpp"
29790 }
29791 {
29792
29793#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29794
29795 // High registers handle in encode_RegMem
29796 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
29797 int base = opnd_array(1)->base(ra_,this,idx1);
29798 int index = opnd_array(1)->index(ra_,this,idx1);
29799 int scale = opnd_array(1)->scale();
29800 int disp = opnd_array(1)->disp(ra_,this,idx1);
29801 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
29802
29803 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
29804
29805#line 29805 "ad_x86.cpp"
29806 }
29807}
29808
29809void subL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29810 cbuf.set_insts_mark();
29811 // Start at oper_input_base() and count operands
29812 unsigned idx0 = 2;
29813 unsigned idx1 = 2; // dst
29814 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29815 {
29816
29817#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29818
29819 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
29820 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29821 emit_opcode(cbuf, Assembler::REX_WB);
29822 } else {
29823 emit_opcode(cbuf, Assembler::REX_WXB);
29824 }
29825 } else {
29826 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29827 emit_opcode(cbuf, Assembler::REX_W);
29828 } else {
29829 emit_opcode(cbuf, Assembler::REX_WX);
29830 }
29831 }
29832
29833#line 29833 "ad_x86.cpp"
29834 }
29835 {
29836
29837#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29838
29839 // Emit primary opcode and set sign-extend bit
29840 // Check for 8-bit immediate, and set sign extend bit in opcode
29841 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
29842 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
29843 } else {
29844 // 32-bit immediate
29845 emit_opcode(cbuf, (0x81 /*primary()*/));
29846 }
29847
29848#line 29848 "ad_x86.cpp"
29849 }
29850 {
29851
29852#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29853
29854 int rm_byte_opcode = (0x05);
29855
29856 // High registers handle in encode_RegMem
29857 int base = opnd_array(1)->base(ra_,this,idx1);
29858 int index = opnd_array(1)->index(ra_,this,idx1);
29859 int scale = opnd_array(1)->scale();
29860 int displace = opnd_array(1)->disp(ra_,this,idx1);
29861
29862 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
29863 // working with static
29864 // globals
29865 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
29866 disp_reloc);
29867
29868#line 29868 "ad_x86.cpp"
29869 }
29870 {
29871
29872#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29873
29874 // Check for 8-bit immediate, and set sign extend bit in opcode
29875 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
29876 emit_d8(cbuf, opnd_array(2)->constantL());
29877 } else {
29878 // 32-bit immediate
29879 emit_d32(cbuf, opnd_array(2)->constantL());
29880 }
29881
29882#line 29882 "ad_x86.cpp"
29883 }
29884}
29885
29886void subP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29887 cbuf.set_insts_mark();
29888 // Start at oper_input_base() and count operands
29889 unsigned idx0 = 2;
29890 unsigned idx1 = 2; // dst
29891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src
29893 {
29894
29895#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29896
29897 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
29898 if (opnd_array(3)->reg(ra_,this,idx3)/* src */ < 8) {
29899 emit_opcode(cbuf, Assembler::REX_W);
29900 } else {
29901 emit_opcode(cbuf, Assembler::REX_WB);
29902 }
29903 } else {
29904 if (opnd_array(3)->reg(ra_,this,idx3)/* src */ < 8) {
29905 emit_opcode(cbuf, Assembler::REX_WR);
29906 } else {
29907 emit_opcode(cbuf, Assembler::REX_WRB);
29908 }
29909 }
29910
29911#line 29911 "ad_x86.cpp"
29912 }
29913 {
29914
29915#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29916
29917 emit_opcode(cbuf, (0x2B /*primary()*/));
29918
29919#line 29919 "ad_x86.cpp"
29920 }
29921 {
29922
29923#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29924
29925 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(3)->reg(ra_,this,idx3)/* src */ & 7);
29926
29927#line 29927 "ad_x86.cpp"
29928 }
29929}
29930
29931void negI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29932 cbuf.set_insts_mark();
29933 // Start at oper_input_base() and count operands
29934 unsigned idx0 = 1;
29935 unsigned idx1 = 1; // zero
29936 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
29937 {
29938
29939#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29940
29941 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ >= 8) {
29942 emit_opcode(cbuf, Assembler::REX_B);
29943 }
29944
29945#line 29945 "ad_x86.cpp"
29946 }
29947 {
29948
29949#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29950
29951 emit_opcode(cbuf, (0xF7 /*primary()*/));
29952
29953#line 29953 "ad_x86.cpp"
29954 }
29955 {
29956
29957#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29958
29959 // INC, DEC, IDIV, IMOD, JMP indirect, ...
29960 emit_rm(cbuf, 0x3, (0x03 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* dst */ & 7);
29961
29962#line 29962 "ad_x86.cpp"
29963 }
29964}
29965
29966void negI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29967 cbuf.set_insts_mark();
29968 // Start at oper_input_base() and count operands
29969 unsigned idx0 = 2;
29970 unsigned idx1 = 2; // dst
29971 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29972 {
29973
29974#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29975
29976 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
29977 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
29978 emit_opcode(cbuf, Assembler::REX_B);
29979 } else {
29980 emit_opcode(cbuf, Assembler::REX_XB);
29981 }
29982 } else {
29983 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
29984 emit_opcode(cbuf, Assembler::REX_X);
29985 }
29986 }
29987
29988#line 29988 "ad_x86.cpp"
29989 }
29990 {
29991
29992#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
29993
29994 emit_opcode(cbuf, (0xF7 /*primary()*/));
29995
29996#line 29996 "ad_x86.cpp"
29997 }
29998 {
29999
30000#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30001
30002 int rm_byte_opcode = (0x03 /*secondary()*/);
30003
30004 // High registers handle in encode_RegMem
30005 int base = opnd_array(1)->base(ra_,this,idx1);
30006 int index = opnd_array(1)->index(ra_,this,idx1);
30007 int scale = opnd_array(1)->scale();
30008 int displace = opnd_array(1)->disp(ra_,this,idx1);
30009
30010 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
30011 // working with static
30012 // globals
30013 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
30014 disp_reloc);
30015
30016#line 30016 "ad_x86.cpp"
30017 }
30018}
30019
30020void negL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30021 cbuf.set_insts_mark();
30022 // Start at oper_input_base() and count operands
30023 unsigned idx0 = 1;
30024 unsigned idx1 = 1; // zero
30025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30026 {
30027
30028#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30029
30030 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
30031 emit_opcode(cbuf, Assembler::REX_W);
30032 } else {
30033 emit_opcode(cbuf, Assembler::REX_WB);
30034 }
30035
30036#line 30036 "ad_x86.cpp"
30037 }
30038 {
30039
30040#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30041
30042 emit_opcode(cbuf, (0xF7 /*primary()*/));
30043
30044#line 30044 "ad_x86.cpp"
30045 }
30046 {
30047
30048#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30049
30050 // INC, DEC, IDIV, IMOD, JMP indirect, ...
30051 emit_rm(cbuf, 0x3, (0x03 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* dst */ & 7);
30052
30053#line 30053 "ad_x86.cpp"
30054 }
30055}
30056
30057void negL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30058 cbuf.set_insts_mark();
30059 // Start at oper_input_base() and count operands
30060 unsigned idx0 = 2;
30061 unsigned idx1 = 2; // dst
30062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
30063 {
30064
30065#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30066
30067 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
30068 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30069 emit_opcode(cbuf, Assembler::REX_WB);
30070 } else {
30071 emit_opcode(cbuf, Assembler::REX_WXB);
30072 }
30073 } else {
30074 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30075 emit_opcode(cbuf, Assembler::REX_W);
30076 } else {
30077 emit_opcode(cbuf, Assembler::REX_WX);
30078 }
30079 }
30080
30081#line 30081 "ad_x86.cpp"
30082 }
30083 {
30084
30085#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30086
30087 emit_opcode(cbuf, (0xF7 /*primary()*/));
30088
30089#line 30089 "ad_x86.cpp"
30090 }
30091 {
30092
30093#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30094
30095 int rm_byte_opcode = (0x03 /*secondary()*/);
30096
30097 // High registers handle in encode_RegMem
30098 int base = opnd_array(1)->base(ra_,this,idx1);
30099 int index = opnd_array(1)->index(ra_,this,idx1);
30100 int scale = opnd_array(1)->scale();
30101 int displace = opnd_array(1)->disp(ra_,this,idx1);
30102
30103 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
30104 // working with static
30105 // globals
30106 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
30107 disp_reloc);
30108
30109#line 30109 "ad_x86.cpp"
30110 }
30111}
30112
30113void mulI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30114 cbuf.set_insts_mark();
30115 // Start at oper_input_base() and count operands
30116 unsigned idx0 = 1;
30117 unsigned idx1 = 1; // dst
30118 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30119 {
30120
30121#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30122
30123 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
30124 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
30125 emit_opcode(cbuf, Assembler::REX_B);
30126 }
30127 } else {
30128 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
30129 emit_opcode(cbuf, Assembler::REX_R);
30130 } else {
30131 emit_opcode(cbuf, Assembler::REX_RB);
30132 }
30133 }
30134
30135#line 30135 "ad_x86.cpp"
30136 }
30137 {
30138
30139#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30140
30141 emit_opcode(cbuf, (0x0F /*primary()*/));
30142
30143#line 30143 "ad_x86.cpp"
30144 }
30145 {
30146
30147#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30148
30149 emit_opcode(cbuf, (0xAF /*secondary()*/));
30150
30151#line 30151 "ad_x86.cpp"
30152 }
30153 {
30154
30155#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30156
30157 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
30158
30159#line 30159 "ad_x86.cpp"
30160 }
30161}
30162
30163void mulI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30164 cbuf.set_insts_mark();
30165 // Start at oper_input_base() and count operands
30166 unsigned idx0 = 1;
30167 unsigned idx1 = 1; // src
30168 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
30169 {
30170
30171#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30172
30173 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
30174 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
30175 emit_opcode(cbuf, Assembler::REX_B);
30176 }
30177 } else {
30178 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
30179 emit_opcode(cbuf, Assembler::REX_R);
30180 } else {
30181 emit_opcode(cbuf, Assembler::REX_RB);
30182 }
30183 }
30184
30185#line 30185 "ad_x86.cpp"
30186 }
30187 {
30188
30189#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30190
30191 // Emit primary opcode and set sign-extend bit
30192 // Check for 8-bit immediate, and set sign extend bit in opcode
30193 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
30194 emit_opcode(cbuf, (0x69 /*primary()*/) | 0x02);
30195 } else {
30196 // 32-bit immediate
30197 emit_opcode(cbuf, (0x69 /*primary()*/));
30198 }
30199
30200#line 30200 "ad_x86.cpp"
30201 }
30202 {
30203
30204#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30205
30206 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
30207
30208#line 30208 "ad_x86.cpp"
30209 }
30210 {
30211
30212#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30213
30214 // Check for 8-bit immediate, and set sign extend bit in opcode
30215 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
30216 emit_d8(cbuf, opnd_array(2)->constant());
30217 } else {
30218 // 32-bit immediate
30219 emit_d32(cbuf, opnd_array(2)->constant());
30220 }
30221
30222#line 30222 "ad_x86.cpp"
30223 }
30224}
30225
30226void mulI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30227 cbuf.set_insts_mark();
30228 // Start at oper_input_base() and count operands
30229 unsigned idx0 = 2;
30230 unsigned idx1 = 2; // dst
30231 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30232 {
30233
30234#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30235
30236 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
30237 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
30238 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
30239 emit_opcode(cbuf, Assembler::REX_X);
30240 }
30241 } else {
30242 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30243 emit_opcode(cbuf, Assembler::REX_B);
30244 } else {
30245 emit_opcode(cbuf, Assembler::REX_XB);
30246 }
30247 }
30248 } else {
30249 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
30250 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30251 emit_opcode(cbuf, Assembler::REX_R);
30252 } else {
30253 emit_opcode(cbuf, Assembler::REX_RX);
30254 }
30255 } else {
30256 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30257 emit_opcode(cbuf, Assembler::REX_RB);
30258 } else {
30259 emit_opcode(cbuf, Assembler::REX_RXB);
30260 }
30261 }
30262 }
30263
30264#line 30264 "ad_x86.cpp"
30265 }
30266 {
30267
30268#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30269
30270 emit_opcode(cbuf, (0x0F /*primary()*/));
30271
30272#line 30272 "ad_x86.cpp"
30273 }
30274 {
30275
30276#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30277
30278 emit_opcode(cbuf, (0xAF /*secondary()*/));
30279
30280#line 30280 "ad_x86.cpp"
30281 }
30282 {
30283
30284#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30285
30286 // High registers handle in encode_RegMem
30287 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
30288 int base = opnd_array(2)->base(ra_,this,idx2);
30289 int index = opnd_array(2)->index(ra_,this,idx2);
30290 int scale = opnd_array(2)->scale();
30291 int disp = opnd_array(2)->disp(ra_,this,idx2);
30292 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
30293
30294 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30295
30296#line 30296 "ad_x86.cpp"
30297 }
30298}
30299
30300void mulI_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30301 cbuf.set_insts_mark();
30302 // Start at oper_input_base() and count operands
30303 unsigned idx0 = 2;
30304 unsigned idx1 = 2; // src
30305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30306 {
30307
30308#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30309
30310 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
30311 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30312 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
30313 emit_opcode(cbuf, Assembler::REX_X);
30314 }
30315 } else {
30316 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30317 emit_opcode(cbuf, Assembler::REX_B);
30318 } else {
30319 emit_opcode(cbuf, Assembler::REX_XB);
30320 }
30321 }
30322 } else {
30323 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30324 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30325 emit_opcode(cbuf, Assembler::REX_R);
30326 } else {
30327 emit_opcode(cbuf, Assembler::REX_RX);
30328 }
30329 } else {
30330 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30331 emit_opcode(cbuf, Assembler::REX_RB);
30332 } else {
30333 emit_opcode(cbuf, Assembler::REX_RXB);
30334 }
30335 }
30336 }
30337
30338#line 30338 "ad_x86.cpp"
30339 }
30340 {
30341
30342#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30343
30344 emit_opcode(cbuf, (0x0F /*primary()*/));
30345
30346#line 30346 "ad_x86.cpp"
30347 }
30348 {
30349
30350#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30351
30352 emit_opcode(cbuf, (0xAF /*secondary()*/));
30353
30354#line 30354 "ad_x86.cpp"
30355 }
30356 {
30357
30358#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30359
30360 // High registers handle in encode_RegMem
30361 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
30362 int base = opnd_array(1)->base(ra_,this,idx1);
30363 int index = opnd_array(1)->index(ra_,this,idx1);
30364 int scale = opnd_array(1)->scale();
30365 int disp = opnd_array(1)->disp(ra_,this,idx1);
30366 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
30367
30368 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30369
30370#line 30370 "ad_x86.cpp"
30371 }
30372}
30373
30374void mulI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30375 cbuf.set_insts_mark();
30376 // Start at oper_input_base() and count operands
30377 unsigned idx0 = 2;
30378 unsigned idx1 = 2; // src
30379 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
30380 {
30381
30382#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30383
30384 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
30385 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30386 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
30387 emit_opcode(cbuf, Assembler::REX_X);
30388 }
30389 } else {
30390 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30391 emit_opcode(cbuf, Assembler::REX_B);
30392 } else {
30393 emit_opcode(cbuf, Assembler::REX_XB);
30394 }
30395 }
30396 } else {
30397 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30398 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30399 emit_opcode(cbuf, Assembler::REX_R);
30400 } else {
30401 emit_opcode(cbuf, Assembler::REX_RX);
30402 }
30403 } else {
30404 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30405 emit_opcode(cbuf, Assembler::REX_RB);
30406 } else {
30407 emit_opcode(cbuf, Assembler::REX_RXB);
30408 }
30409 }
30410 }
30411
30412#line 30412 "ad_x86.cpp"
30413 }
30414 {
30415
30416#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30417
30418 // Emit primary opcode and set sign-extend bit
30419 // Check for 8-bit immediate, and set sign extend bit in opcode
30420 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
30421 emit_opcode(cbuf, (0x69 /*primary()*/) | 0x02);
30422 } else {
30423 // 32-bit immediate
30424 emit_opcode(cbuf, (0x69 /*primary()*/));
30425 }
30426
30427#line 30427 "ad_x86.cpp"
30428 }
30429 {
30430
30431#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30432
30433 // High registers handle in encode_RegMem
30434 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
30435 int base = opnd_array(1)->base(ra_,this,idx1);
30436 int index = opnd_array(1)->index(ra_,this,idx1);
30437 int scale = opnd_array(1)->scale();
30438 int disp = opnd_array(1)->disp(ra_,this,idx1);
30439 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
30440
30441 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30442
30443#line 30443 "ad_x86.cpp"
30444 }
30445 {
30446
30447#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30448
30449 // Check for 8-bit immediate, and set sign extend bit in opcode
30450 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
30451 emit_d8(cbuf, opnd_array(2)->constant());
30452 } else {
30453 // 32-bit immediate
30454 emit_d32(cbuf, opnd_array(2)->constant());
30455 }
30456
30457#line 30457 "ad_x86.cpp"
30458 }
30459}
30460
30461void mulL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30462 cbuf.set_insts_mark();
30463 // Start at oper_input_base() and count operands
30464 unsigned idx0 = 1;
30465 unsigned idx1 = 1; // dst
30466 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30467 {
30468
30469#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30470
30471 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
30472 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
30473 emit_opcode(cbuf, Assembler::REX_W);
30474 } else {
30475 emit_opcode(cbuf, Assembler::REX_WB);
30476 }
30477 } else {
30478 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
30479 emit_opcode(cbuf, Assembler::REX_WR);
30480 } else {
30481 emit_opcode(cbuf, Assembler::REX_WRB);
30482 }
30483 }
30484
30485#line 30485 "ad_x86.cpp"
30486 }
30487 {
30488
30489#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30490
30491 emit_opcode(cbuf, (0x0F /*primary()*/));
30492
30493#line 30493 "ad_x86.cpp"
30494 }
30495 {
30496
30497#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30498
30499 emit_opcode(cbuf, (0xAF /*secondary()*/));
30500
30501#line 30501 "ad_x86.cpp"
30502 }
30503 {
30504
30505#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30506
30507 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
30508
30509#line 30509 "ad_x86.cpp"
30510 }
30511}
30512
30513void mulL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30514 cbuf.set_insts_mark();
30515 // Start at oper_input_base() and count operands
30516 unsigned idx0 = 1;
30517 unsigned idx1 = 1; // src
30518 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
30519 {
30520
30521#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30522
30523 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
30524 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
30525 emit_opcode(cbuf, Assembler::REX_W);
30526 } else {
30527 emit_opcode(cbuf, Assembler::REX_WB);
30528 }
30529 } else {
30530 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
30531 emit_opcode(cbuf, Assembler::REX_WR);
30532 } else {
30533 emit_opcode(cbuf, Assembler::REX_WRB);
30534 }
30535 }
30536
30537#line 30537 "ad_x86.cpp"
30538 }
30539 {
30540
30541#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30542
30543 // Emit primary opcode and set sign-extend bit
30544 // Check for 8-bit immediate, and set sign extend bit in opcode
30545 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
30546 emit_opcode(cbuf, (0x69 /*primary()*/) | 0x02);
30547 } else {
30548 // 32-bit immediate
30549 emit_opcode(cbuf, (0x69 /*primary()*/));
30550 }
30551
30552#line 30552 "ad_x86.cpp"
30553 }
30554 {
30555
30556#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30557
30558 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
30559
30560#line 30560 "ad_x86.cpp"
30561 }
30562 {
30563
30564#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30565
30566 // Check for 8-bit immediate, and set sign extend bit in opcode
30567 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
30568 emit_d8(cbuf, opnd_array(2)->constantL());
30569 } else {
30570 // 32-bit immediate
30571 emit_d32(cbuf, opnd_array(2)->constantL());
30572 }
30573
30574#line 30574 "ad_x86.cpp"
30575 }
30576}
30577
30578void mulL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30579 cbuf.set_insts_mark();
30580 // Start at oper_input_base() and count operands
30581 unsigned idx0 = 2;
30582 unsigned idx1 = 2; // dst
30583 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30584 {
30585
30586#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30587
30588 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
30589 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
30590 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30591 emit_opcode(cbuf, Assembler::REX_W);
30592 } else {
30593 emit_opcode(cbuf, Assembler::REX_WX);
30594 }
30595 } else {
30596 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30597 emit_opcode(cbuf, Assembler::REX_WB);
30598 } else {
30599 emit_opcode(cbuf, Assembler::REX_WXB);
30600 }
30601 }
30602 } else {
30603 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
30604 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30605 emit_opcode(cbuf, Assembler::REX_WR);
30606 } else {
30607 emit_opcode(cbuf, Assembler::REX_WRX);
30608 }
30609 } else {
30610 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
30611 emit_opcode(cbuf, Assembler::REX_WRB);
30612 } else {
30613 emit_opcode(cbuf, Assembler::REX_WRXB);
30614 }
30615 }
30616 }
30617
30618#line 30618 "ad_x86.cpp"
30619 }
30620 {
30621
30622#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30623
30624 emit_opcode(cbuf, (0x0F /*primary()*/));
30625
30626#line 30626 "ad_x86.cpp"
30627 }
30628 {
30629
30630#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30631
30632 emit_opcode(cbuf, (0xAF /*secondary()*/));
30633
30634#line 30634 "ad_x86.cpp"
30635 }
30636 {
30637
30638#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30639
30640 // High registers handle in encode_RegMem
30641 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
30642 int base = opnd_array(2)->base(ra_,this,idx2);
30643 int index = opnd_array(2)->index(ra_,this,idx2);
30644 int scale = opnd_array(2)->scale();
30645 int disp = opnd_array(2)->disp(ra_,this,idx2);
30646 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
30647
30648 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30649
30650#line 30650 "ad_x86.cpp"
30651 }
30652}
30653
30654void mulL_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30655 cbuf.set_insts_mark();
30656 // Start at oper_input_base() and count operands
30657 unsigned idx0 = 2;
30658 unsigned idx1 = 2; // src
30659 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30660 {
30661
30662#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30663
30664 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
30665 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30666 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30667 emit_opcode(cbuf, Assembler::REX_W);
30668 } else {
30669 emit_opcode(cbuf, Assembler::REX_WX);
30670 }
30671 } else {
30672 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30673 emit_opcode(cbuf, Assembler::REX_WB);
30674 } else {
30675 emit_opcode(cbuf, Assembler::REX_WXB);
30676 }
30677 }
30678 } else {
30679 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30680 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30681 emit_opcode(cbuf, Assembler::REX_WR);
30682 } else {
30683 emit_opcode(cbuf, Assembler::REX_WRX);
30684 }
30685 } else {
30686 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30687 emit_opcode(cbuf, Assembler::REX_WRB);
30688 } else {
30689 emit_opcode(cbuf, Assembler::REX_WRXB);
30690 }
30691 }
30692 }
30693
30694#line 30694 "ad_x86.cpp"
30695 }
30696 {
30697
30698#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30699
30700 emit_opcode(cbuf, (0x0F /*primary()*/));
30701
30702#line 30702 "ad_x86.cpp"
30703 }
30704 {
30705
30706#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30707
30708 emit_opcode(cbuf, (0xAF /*secondary()*/));
30709
30710#line 30710 "ad_x86.cpp"
30711 }
30712 {
30713
30714#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30715
30716 // High registers handle in encode_RegMem
30717 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
30718 int base = opnd_array(1)->base(ra_,this,idx1);
30719 int index = opnd_array(1)->index(ra_,this,idx1);
30720 int scale = opnd_array(1)->scale();
30721 int disp = opnd_array(1)->disp(ra_,this,idx1);
30722 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
30723
30724 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30725
30726#line 30726 "ad_x86.cpp"
30727 }
30728}
30729
30730void mulL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30731 cbuf.set_insts_mark();
30732 // Start at oper_input_base() and count operands
30733 unsigned idx0 = 2;
30734 unsigned idx1 = 2; // src
30735 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
30736 {
30737
30738#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30739
30740 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
30741 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30742 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30743 emit_opcode(cbuf, Assembler::REX_W);
30744 } else {
30745 emit_opcode(cbuf, Assembler::REX_WX);
30746 }
30747 } else {
30748 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30749 emit_opcode(cbuf, Assembler::REX_WB);
30750 } else {
30751 emit_opcode(cbuf, Assembler::REX_WXB);
30752 }
30753 }
30754 } else {
30755 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
30756 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30757 emit_opcode(cbuf, Assembler::REX_WR);
30758 } else {
30759 emit_opcode(cbuf, Assembler::REX_WRX);
30760 }
30761 } else {
30762 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
30763 emit_opcode(cbuf, Assembler::REX_WRB);
30764 } else {
30765 emit_opcode(cbuf, Assembler::REX_WRXB);
30766 }
30767 }
30768 }
30769
30770#line 30770 "ad_x86.cpp"
30771 }
30772 {
30773
30774#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30775
30776 // Emit primary opcode and set sign-extend bit
30777 // Check for 8-bit immediate, and set sign extend bit in opcode
30778 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
30779 emit_opcode(cbuf, (0x69 /*primary()*/) | 0x02);
30780 } else {
30781 // 32-bit immediate
30782 emit_opcode(cbuf, (0x69 /*primary()*/));
30783 }
30784
30785#line 30785 "ad_x86.cpp"
30786 }
30787 {
30788
30789#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30790
30791 // High registers handle in encode_RegMem
30792 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
30793 int base = opnd_array(1)->base(ra_,this,idx1);
30794 int index = opnd_array(1)->index(ra_,this,idx1);
30795 int scale = opnd_array(1)->scale();
30796 int disp = opnd_array(1)->disp(ra_,this,idx1);
30797 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
30798
30799 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
30800
30801#line 30801 "ad_x86.cpp"
30802 }
30803 {
30804
30805#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30806
30807 // Check for 8-bit immediate, and set sign extend bit in opcode
30808 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
30809 emit_d8(cbuf, opnd_array(2)->constantL());
30810 } else {
30811 // 32-bit immediate
30812 emit_d32(cbuf, opnd_array(2)->constantL());
30813 }
30814
30815#line 30815 "ad_x86.cpp"
30816 }
30817}
30818
30819void mulHiL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30820 cbuf.set_insts_mark();
30821 // Start at oper_input_base() and count operands
30822 unsigned idx0 = 1;
30823 unsigned idx1 = 1; // src
30824 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
30825 {
30826
30827#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30828
30829 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
30830 emit_opcode(cbuf, Assembler::REX_W);
30831 } else {
30832 emit_opcode(cbuf, Assembler::REX_WB);
30833 }
30834
30835#line 30835 "ad_x86.cpp"
30836 }
30837 {
30838
30839#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30840
30841 emit_opcode(cbuf, (0xF7 /*primary()*/));
30842
30843#line 30843 "ad_x86.cpp"
30844 }
30845 {
30846
30847#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30848
30849 // INC, DEC, IDIV, IMOD, JMP indirect, ...
30850 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
30851
30852#line 30852 "ad_x86.cpp"
30853 }
30854}
30855
30856void divI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30857 cbuf.set_insts_mark();
30858 // Start at oper_input_base() and count operands
30859 unsigned idx0 = 1;
30860 unsigned idx1 = 1; // rax
30861 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
30862 {
30863
30864#line 1857 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30865
30866 // Full implementation of Java idiv and irem; checks for
30867 // special case as described in JVM spec., p.243 & p.271.
30868 //
30869 // normal case special case
30870 //
30871 // input : rax: dividend min_int
30872 // reg: divisor -1
30873 //
30874 // output: rax: quotient (= rax idiv reg) min_int
30875 // rdx: remainder (= rax irem reg) 0
30876 //
30877 // Code sequnce:
30878 //
30879 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
30880 // 5: 75 07/08 jne e <normal>
30881 // 7: 33 d2 xor %edx,%edx
30882 // [div >= 8 -> offset + 1]
30883 // [REX_B]
30884 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
30885 // c: 74 03/04 je 11 <done>
30886 // 000000000000000e <normal>:
30887 // e: 99 cltd
30888 // [div >= 8 -> offset + 1]
30889 // [REX_B]
30890 // f: f7 f9 idiv $div
30891 // 0000000000000011 <done>:
30892
30893 // cmp $0x80000000,%eax
30894 emit_opcode(cbuf, 0x3d);
30895 emit_d8(cbuf, 0x00);
30896 emit_d8(cbuf, 0x00);
30897 emit_d8(cbuf, 0x00);
30898 emit_d8(cbuf, 0x80);
30899
30900 // jne e <normal>
30901 emit_opcode(cbuf, 0x75);
30902 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x07 : 0x08);
30903
30904 // xor %edx,%edx
30905 emit_opcode(cbuf, 0x33);
30906 emit_d8(cbuf, 0xD2);
30907
30908 // cmp $0xffffffffffffffff,%ecx
30909 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
30910 emit_opcode(cbuf, Assembler::REX_B);
30911 }
30912 emit_opcode(cbuf, 0x83);
30913 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
30914 emit_d8(cbuf, 0xFF);
30915
30916 // je 11 <done>
30917 emit_opcode(cbuf, 0x74);
30918 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x03 : 0x04);
30919
30920 // <normal>
30921 // cltd
30922 emit_opcode(cbuf, 0x99);
30923
30924 // idivl (note: must be emitted by the user of this rule)
30925 // <done>
30926
30927#line 30927 "ad_x86.cpp"
30928 }
30929 {
30930
30931#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30932
30933 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
30934 emit_opcode(cbuf, Assembler::REX_B);
30935 }
30936
30937#line 30937 "ad_x86.cpp"
30938 }
30939 {
30940
30941#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30942
30943 emit_opcode(cbuf, (0xF7 /*primary()*/));
30944
30945#line 30945 "ad_x86.cpp"
30946 }
30947 {
30948
30949#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30950
30951 // INC, DEC, IDIV, IMOD, JMP indirect, ...
30952 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
30953
30954#line 30954 "ad_x86.cpp"
30955 }
30956}
30957
30958void divL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30959 cbuf.set_insts_mark();
30960 // Start at oper_input_base() and count operands
30961 unsigned idx0 = 1;
30962 unsigned idx1 = 1; // rax
30963 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
30964 {
30965
30966#line 1921 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
30967
30968 // Full implementation of Java ldiv and lrem; checks for
30969 // special case as described in JVM spec., p.243 & p.271.
30970 //
30971 // normal case special case
30972 //
30973 // input : rax: dividend min_long
30974 // reg: divisor -1
30975 //
30976 // output: rax: quotient (= rax idiv reg) min_long
30977 // rdx: remainder (= rax irem reg) 0
30978 //
30979 // Code sequnce:
30980 //
30981 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
30982 // 7: 00 00 80
30983 // a: 48 39 d0 cmp %rdx,%rax
30984 // d: 75 08 jne 17 <normal>
30985 // f: 33 d2 xor %edx,%edx
30986 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
30987 // 15: 74 05 je 1c <done>
30988 // 0000000000000017 <normal>:
30989 // 17: 48 99 cqto
30990 // 19: 48 f7 f9 idiv $div
30991 // 000000000000001c <done>:
30992
30993 // mov $0x8000000000000000,%rdx
30994 emit_opcode(cbuf, Assembler::REX_W);
30995 emit_opcode(cbuf, 0xBA);
30996 emit_d8(cbuf, 0x00);
30997 emit_d8(cbuf, 0x00);
30998 emit_d8(cbuf, 0x00);
30999 emit_d8(cbuf, 0x00);
31000 emit_d8(cbuf, 0x00);
31001 emit_d8(cbuf, 0x00);
31002 emit_d8(cbuf, 0x00);
31003 emit_d8(cbuf, 0x80);
31004
31005 // cmp %rdx,%rax
31006 emit_opcode(cbuf, Assembler::REX_W);
31007 emit_opcode(cbuf, 0x39);
31008 emit_d8(cbuf, 0xD0);
31009
31010 // jne 17 <normal>
31011 emit_opcode(cbuf, 0x75);
31012 emit_d8(cbuf, 0x08);
31013
31014 // xor %edx,%edx
31015 emit_opcode(cbuf, 0x33);
31016 emit_d8(cbuf, 0xD2);
31017
31018 // cmp $0xffffffffffffffff,$div
31019 emit_opcode(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? Assembler::REX_W : Assembler::REX_WB);
31020 emit_opcode(cbuf, 0x83);
31021 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31022 emit_d8(cbuf, 0xFF);
31023
31024 // je 1e <done>
31025 emit_opcode(cbuf, 0x74);
31026 emit_d8(cbuf, 0x05);
31027
31028 // <normal>
31029 // cqto
31030 emit_opcode(cbuf, Assembler::REX_W);
31031 emit_opcode(cbuf, 0x99);
31032
31033 // idivq (note: must be emitted by the user of this rule)
31034 // <done>
31035
31036#line 31036 "ad_x86.cpp"
31037 }
31038 {
31039
31040#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31041
31042 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8) {
31043 emit_opcode(cbuf, Assembler::REX_W);
31044 } else {
31045 emit_opcode(cbuf, Assembler::REX_WB);
31046 }
31047
31048#line 31048 "ad_x86.cpp"
31049 }
31050 {
31051
31052#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31053
31054 emit_opcode(cbuf, (0xF7 /*primary()*/));
31055
31056#line 31056 "ad_x86.cpp"
31057 }
31058 {
31059
31060#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31061
31062 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31063 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31064
31065#line 31065 "ad_x86.cpp"
31066 }
31067}
31068
31069void divModI_rReg_divmodNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31070 cbuf.set_insts_mark();
31071 // Start at oper_input_base() and count operands
31072 unsigned idx0 = 1;
31073 unsigned idx1 = 1; // div
31074 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
31075 {
31076
31077#line 1857 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31078
31079 // Full implementation of Java idiv and irem; checks for
31080 // special case as described in JVM spec., p.243 & p.271.
31081 //
31082 // normal case special case
31083 //
31084 // input : rax: dividend min_int
31085 // reg: divisor -1
31086 //
31087 // output: rax: quotient (= rax idiv reg) min_int
31088 // rdx: remainder (= rax irem reg) 0
31089 //
31090 // Code sequnce:
31091 //
31092 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
31093 // 5: 75 07/08 jne e <normal>
31094 // 7: 33 d2 xor %edx,%edx
31095 // [div >= 8 -> offset + 1]
31096 // [REX_B]
31097 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
31098 // c: 74 03/04 je 11 <done>
31099 // 000000000000000e <normal>:
31100 // e: 99 cltd
31101 // [div >= 8 -> offset + 1]
31102 // [REX_B]
31103 // f: f7 f9 idiv $div
31104 // 0000000000000011 <done>:
31105
31106 // cmp $0x80000000,%eax
31107 emit_opcode(cbuf, 0x3d);
31108 emit_d8(cbuf, 0x00);
31109 emit_d8(cbuf, 0x00);
31110 emit_d8(cbuf, 0x00);
31111 emit_d8(cbuf, 0x80);
31112
31113 // jne e <normal>
31114 emit_opcode(cbuf, 0x75);
31115 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x07 : 0x08);
31116
31117 // xor %edx,%edx
31118 emit_opcode(cbuf, 0x33);
31119 emit_d8(cbuf, 0xD2);
31120
31121 // cmp $0xffffffffffffffff,%ecx
31122 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
31123 emit_opcode(cbuf, Assembler::REX_B);
31124 }
31125 emit_opcode(cbuf, 0x83);
31126 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31127 emit_d8(cbuf, 0xFF);
31128
31129 // je 11 <done>
31130 emit_opcode(cbuf, 0x74);
31131 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x03 : 0x04);
31132
31133 // <normal>
31134 // cltd
31135 emit_opcode(cbuf, 0x99);
31136
31137 // idivl (note: must be emitted by the user of this rule)
31138 // <done>
31139
31140#line 31140 "ad_x86.cpp"
31141 }
31142 {
31143
31144#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31145
31146 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
31147 emit_opcode(cbuf, Assembler::REX_B);
31148 }
31149
31150#line 31150 "ad_x86.cpp"
31151 }
31152 {
31153
31154#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31155
31156 emit_opcode(cbuf, (0xF7 /*primary()*/));
31157
31158#line 31158 "ad_x86.cpp"
31159 }
31160 {
31161
31162#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31163
31164 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31165 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31166
31167#line 31167 "ad_x86.cpp"
31168 }
31169}
31170
31171void divModL_rReg_divmodNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31172 cbuf.set_insts_mark();
31173 // Start at oper_input_base() and count operands
31174 unsigned idx0 = 1;
31175 unsigned idx1 = 1; // div
31176 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
31177 {
31178
31179#line 1921 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31180
31181 // Full implementation of Java ldiv and lrem; checks for
31182 // special case as described in JVM spec., p.243 & p.271.
31183 //
31184 // normal case special case
31185 //
31186 // input : rax: dividend min_long
31187 // reg: divisor -1
31188 //
31189 // output: rax: quotient (= rax idiv reg) min_long
31190 // rdx: remainder (= rax irem reg) 0
31191 //
31192 // Code sequnce:
31193 //
31194 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
31195 // 7: 00 00 80
31196 // a: 48 39 d0 cmp %rdx,%rax
31197 // d: 75 08 jne 17 <normal>
31198 // f: 33 d2 xor %edx,%edx
31199 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
31200 // 15: 74 05 je 1c <done>
31201 // 0000000000000017 <normal>:
31202 // 17: 48 99 cqto
31203 // 19: 48 f7 f9 idiv $div
31204 // 000000000000001c <done>:
31205
31206 // mov $0x8000000000000000,%rdx
31207 emit_opcode(cbuf, Assembler::REX_W);
31208 emit_opcode(cbuf, 0xBA);
31209 emit_d8(cbuf, 0x00);
31210 emit_d8(cbuf, 0x00);
31211 emit_d8(cbuf, 0x00);
31212 emit_d8(cbuf, 0x00);
31213 emit_d8(cbuf, 0x00);
31214 emit_d8(cbuf, 0x00);
31215 emit_d8(cbuf, 0x00);
31216 emit_d8(cbuf, 0x80);
31217
31218 // cmp %rdx,%rax
31219 emit_opcode(cbuf, Assembler::REX_W);
31220 emit_opcode(cbuf, 0x39);
31221 emit_d8(cbuf, 0xD0);
31222
31223 // jne 17 <normal>
31224 emit_opcode(cbuf, 0x75);
31225 emit_d8(cbuf, 0x08);
31226
31227 // xor %edx,%edx
31228 emit_opcode(cbuf, 0x33);
31229 emit_d8(cbuf, 0xD2);
31230
31231 // cmp $0xffffffffffffffff,$div
31232 emit_opcode(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? Assembler::REX_W : Assembler::REX_WB);
31233 emit_opcode(cbuf, 0x83);
31234 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31235 emit_d8(cbuf, 0xFF);
31236
31237 // je 1e <done>
31238 emit_opcode(cbuf, 0x74);
31239 emit_d8(cbuf, 0x05);
31240
31241 // <normal>
31242 // cqto
31243 emit_opcode(cbuf, Assembler::REX_W);
31244 emit_opcode(cbuf, 0x99);
31245
31246 // idivq (note: must be emitted by the user of this rule)
31247 // <done>
31248
31249#line 31249 "ad_x86.cpp"
31250 }
31251 {
31252
31253#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31254
31255 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8) {
31256 emit_opcode(cbuf, Assembler::REX_W);
31257 } else {
31258 emit_opcode(cbuf, Assembler::REX_WB);
31259 }
31260
31261#line 31261 "ad_x86.cpp"
31262 }
31263 {
31264
31265#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31266
31267 emit_opcode(cbuf, (0xF7 /*primary()*/));
31268
31269#line 31269 "ad_x86.cpp"
31270 }
31271 {
31272
31273#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31274
31275 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31276 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31277
31278#line 31278 "ad_x86.cpp"
31279 }
31280}
31281
31282void loadConL_0x6666666666666667Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31283 cbuf.set_insts_mark();
31284 // Start at oper_input_base() and count operands
31285 unsigned idx0 = 1;
31286 unsigned idx1 = 1; //
31287 {
31288
31289#line 2230 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31290
31291 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
31292 if (dstenc < 8) {
31293 emit_opcode(cbuf, Assembler::REX_W);
31294 } else {
31295 emit_opcode(cbuf, Assembler::REX_WB);
31296 dstenc -= 8;
31297 }
31298 emit_opcode(cbuf, 0xB8 | dstenc);
31299 emit_d64(cbuf, (0x6666666666666667));
31300
31301#line 31301 "ad_x86.cpp"
31302 }
31303}
31304
31305void mul_hiNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31306 cbuf.set_insts_mark();
31307 // Start at oper_input_base() and count operands
31308 unsigned idx0 = 1;
31309 unsigned idx1 = 1; // src
31310 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
31311 {
31312
31313#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31314
31315 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
31316 emit_opcode(cbuf, Assembler::REX_W);
31317 } else {
31318 emit_opcode(cbuf, Assembler::REX_WB);
31319 }
31320
31321#line 31321 "ad_x86.cpp"
31322 }
31323 {
31324
31325#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31326
31327 emit_opcode(cbuf, (0xF7 /*primary()*/));
31328
31329#line 31329 "ad_x86.cpp"
31330 }
31331 {
31332
31333#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31334
31335 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31336 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
31337
31338#line 31338 "ad_x86.cpp"
31339 }
31340}
31341
31342void sarL_rReg_63Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31343 cbuf.set_insts_mark();
31344 // Start at oper_input_base() and count operands
31345 unsigned idx0 = 1;
31346 unsigned idx1 = 1; // cr
31347 {
31348
31349#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31350
31351 // SAL, SAR, SHR
31352 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
31353 if (dstenc < 8) {
31354 emit_opcode(cbuf, Assembler::REX_W);
31355 } else {
31356 emit_opcode(cbuf, Assembler::REX_WB);
31357 dstenc -= 8;
31358 }
31359 emit_d8(cbuf, (0xC1 /*primary()*/));
31360 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), dstenc);
31361 emit_d8(cbuf, (0x3F));
31362
31363#line 31363 "ad_x86.cpp"
31364 }
31365}
31366
31367void sarL_rReg_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31368 cbuf.set_insts_mark();
31369 // Start at oper_input_base() and count operands
31370 unsigned idx0 = 1;
31371 unsigned idx1 = 1; // cr
31372 {
31373
31374#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31375
31376 // SAL, SAR, SHR
31377 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
31378 if (dstenc < 8) {
31379 emit_opcode(cbuf, Assembler::REX_W);
31380 } else {
31381 emit_opcode(cbuf, Assembler::REX_WB);
31382 dstenc -= 8;
31383 }
31384 emit_d8(cbuf, (0xC1 /*primary()*/));
31385 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), dstenc);
31386 emit_d8(cbuf, (0x2));
31387
31388#line 31388 "ad_x86.cpp"
31389 }
31390}
31391
31392void modI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31393 cbuf.set_insts_mark();
31394 // Start at oper_input_base() and count operands
31395 unsigned idx0 = 1;
31396 unsigned idx1 = 1; // rax
31397 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
31398 {
31399
31400#line 1857 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31401
31402 // Full implementation of Java idiv and irem; checks for
31403 // special case as described in JVM spec., p.243 & p.271.
31404 //
31405 // normal case special case
31406 //
31407 // input : rax: dividend min_int
31408 // reg: divisor -1
31409 //
31410 // output: rax: quotient (= rax idiv reg) min_int
31411 // rdx: remainder (= rax irem reg) 0
31412 //
31413 // Code sequnce:
31414 //
31415 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
31416 // 5: 75 07/08 jne e <normal>
31417 // 7: 33 d2 xor %edx,%edx
31418 // [div >= 8 -> offset + 1]
31419 // [REX_B]
31420 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
31421 // c: 74 03/04 je 11 <done>
31422 // 000000000000000e <normal>:
31423 // e: 99 cltd
31424 // [div >= 8 -> offset + 1]
31425 // [REX_B]
31426 // f: f7 f9 idiv $div
31427 // 0000000000000011 <done>:
31428
31429 // cmp $0x80000000,%eax
31430 emit_opcode(cbuf, 0x3d);
31431 emit_d8(cbuf, 0x00);
31432 emit_d8(cbuf, 0x00);
31433 emit_d8(cbuf, 0x00);
31434 emit_d8(cbuf, 0x80);
31435
31436 // jne e <normal>
31437 emit_opcode(cbuf, 0x75);
31438 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x07 : 0x08);
31439
31440 // xor %edx,%edx
31441 emit_opcode(cbuf, 0x33);
31442 emit_d8(cbuf, 0xD2);
31443
31444 // cmp $0xffffffffffffffff,%ecx
31445 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
31446 emit_opcode(cbuf, Assembler::REX_B);
31447 }
31448 emit_opcode(cbuf, 0x83);
31449 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31450 emit_d8(cbuf, 0xFF);
31451
31452 // je 11 <done>
31453 emit_opcode(cbuf, 0x74);
31454 emit_d8(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? 0x03 : 0x04);
31455
31456 // <normal>
31457 // cltd
31458 emit_opcode(cbuf, 0x99);
31459
31460 // idivl (note: must be emitted by the user of this rule)
31461 // <done>
31462
31463#line 31463 "ad_x86.cpp"
31464 }
31465 {
31466
31467#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31468
31469 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ >= 8) {
31470 emit_opcode(cbuf, Assembler::REX_B);
31471 }
31472
31473#line 31473 "ad_x86.cpp"
31474 }
31475 {
31476
31477#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31478
31479 emit_opcode(cbuf, (0xF7 /*primary()*/));
31480
31481#line 31481 "ad_x86.cpp"
31482 }
31483 {
31484
31485#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31486
31487 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31488 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31489
31490#line 31490 "ad_x86.cpp"
31491 }
31492}
31493
31494void modL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31495 cbuf.set_insts_mark();
31496 // Start at oper_input_base() and count operands
31497 unsigned idx0 = 1;
31498 unsigned idx1 = 1; // rax
31499 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
31500 {
31501
31502#line 1921 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31503
31504 // Full implementation of Java ldiv and lrem; checks for
31505 // special case as described in JVM spec., p.243 & p.271.
31506 //
31507 // normal case special case
31508 //
31509 // input : rax: dividend min_long
31510 // reg: divisor -1
31511 //
31512 // output: rax: quotient (= rax idiv reg) min_long
31513 // rdx: remainder (= rax irem reg) 0
31514 //
31515 // Code sequnce:
31516 //
31517 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
31518 // 7: 00 00 80
31519 // a: 48 39 d0 cmp %rdx,%rax
31520 // d: 75 08 jne 17 <normal>
31521 // f: 33 d2 xor %edx,%edx
31522 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
31523 // 15: 74 05 je 1c <done>
31524 // 0000000000000017 <normal>:
31525 // 17: 48 99 cqto
31526 // 19: 48 f7 f9 idiv $div
31527 // 000000000000001c <done>:
31528
31529 // mov $0x8000000000000000,%rdx
31530 emit_opcode(cbuf, Assembler::REX_W);
31531 emit_opcode(cbuf, 0xBA);
31532 emit_d8(cbuf, 0x00);
31533 emit_d8(cbuf, 0x00);
31534 emit_d8(cbuf, 0x00);
31535 emit_d8(cbuf, 0x00);
31536 emit_d8(cbuf, 0x00);
31537 emit_d8(cbuf, 0x00);
31538 emit_d8(cbuf, 0x00);
31539 emit_d8(cbuf, 0x80);
31540
31541 // cmp %rdx,%rax
31542 emit_opcode(cbuf, Assembler::REX_W);
31543 emit_opcode(cbuf, 0x39);
31544 emit_d8(cbuf, 0xD0);
31545
31546 // jne 17 <normal>
31547 emit_opcode(cbuf, 0x75);
31548 emit_d8(cbuf, 0x08);
31549
31550 // xor %edx,%edx
31551 emit_opcode(cbuf, 0x33);
31552 emit_d8(cbuf, 0xD2);
31553
31554 // cmp $0xffffffffffffffff,$div
31555 emit_opcode(cbuf, opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8 ? Assembler::REX_W : Assembler::REX_WB);
31556 emit_opcode(cbuf, 0x83);
31557 emit_rm(cbuf, 0x3, 0x7, opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31558 emit_d8(cbuf, 0xFF);
31559
31560 // je 1e <done>
31561 emit_opcode(cbuf, 0x74);
31562 emit_d8(cbuf, 0x05);
31563
31564 // <normal>
31565 // cqto
31566 emit_opcode(cbuf, Assembler::REX_W);
31567 emit_opcode(cbuf, 0x99);
31568
31569 // idivq (note: must be emitted by the user of this rule)
31570 // <done>
31571
31572#line 31572 "ad_x86.cpp"
31573 }
31574 {
31575
31576#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31577
31578 if (opnd_array(2)->reg(ra_,this,idx2)/* div */ < 8) {
31579 emit_opcode(cbuf, Assembler::REX_W);
31580 } else {
31581 emit_opcode(cbuf, Assembler::REX_WB);
31582 }
31583
31584#line 31584 "ad_x86.cpp"
31585 }
31586 {
31587
31588#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31589
31590 emit_opcode(cbuf, (0xF7 /*primary()*/));
31591
31592#line 31592 "ad_x86.cpp"
31593 }
31594 {
31595
31596#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31597
31598 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31599 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(2)->reg(ra_,this,idx2)/* div */ & 7);
31600
31601#line 31601 "ad_x86.cpp"
31602 }
31603}
31604
31605void salI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31606 cbuf.set_insts_mark();
31607 // Start at oper_input_base() and count operands
31608 unsigned idx0 = 1;
31609 unsigned idx1 = 1; // dst
31610 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31611 {
31612
31613#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31614
31615 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
31616 emit_opcode(cbuf, Assembler::REX_B);
31617 }
31618
31619#line 31619 "ad_x86.cpp"
31620 }
31621 {
31622
31623#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31624
31625 emit_opcode(cbuf, (0xD1 /*primary()*/));
31626
31627#line 31627 "ad_x86.cpp"
31628 }
31629 {
31630
31631#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31632
31633 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31634 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
31635
31636#line 31636 "ad_x86.cpp"
31637 }
31638}
31639
31640void salI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31641 cbuf.set_insts_mark();
31642 // Start at oper_input_base() and count operands
31643 unsigned idx0 = 2;
31644 unsigned idx1 = 2; // dst
31645 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31646 {
31647
31648#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31649
31650 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
31651 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
31652 emit_opcode(cbuf, Assembler::REX_B);
31653 } else {
31654 emit_opcode(cbuf, Assembler::REX_XB);
31655 }
31656 } else {
31657 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
31658 emit_opcode(cbuf, Assembler::REX_X);
31659 }
31660 }
31661
31662#line 31662 "ad_x86.cpp"
31663 }
31664 {
31665
31666#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31667
31668 emit_opcode(cbuf, (0xD1 /*primary()*/));
31669
31670#line 31670 "ad_x86.cpp"
31671 }
31672 {
31673
31674#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31675
31676 int rm_byte_opcode = (0x4 /*secondary()*/);
31677
31678 // High registers handle in encode_RegMem
31679 int base = opnd_array(1)->base(ra_,this,idx1);
31680 int index = opnd_array(1)->index(ra_,this,idx1);
31681 int scale = opnd_array(1)->scale();
31682 int displace = opnd_array(1)->disp(ra_,this,idx1);
31683
31684 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
31685 // working with static
31686 // globals
31687 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
31688 disp_reloc);
31689
31690#line 31690 "ad_x86.cpp"
31691 }
31692}
31693
31694void salI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31695 cbuf.set_insts_mark();
31696 // Start at oper_input_base() and count operands
31697 unsigned idx0 = 1;
31698 unsigned idx1 = 1; // dst
31699 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31700 {
31701
31702#line 2191 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31703
31704 // SAL, SAR, SHR
31705 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
31706 if (dstenc >= 8) {
31707 emit_opcode(cbuf, Assembler::REX_B);
31708 dstenc -= 8;
31709 }
31710 emit_d8(cbuf, (0xC1 /*primary()*/));
31711 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), dstenc);
31712 emit_d8(cbuf, opnd_array(2)->constant());
31713
31714#line 31714 "ad_x86.cpp"
31715 }
31716}
31717
31718void salI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31719 cbuf.set_insts_mark();
31720 // Start at oper_input_base() and count operands
31721 unsigned idx0 = 2;
31722 unsigned idx1 = 2; // dst
31723 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31724 {
31725
31726#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31727
31728 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
31729 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
31730 emit_opcode(cbuf, Assembler::REX_B);
31731 } else {
31732 emit_opcode(cbuf, Assembler::REX_XB);
31733 }
31734 } else {
31735 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
31736 emit_opcode(cbuf, Assembler::REX_X);
31737 }
31738 }
31739
31740#line 31740 "ad_x86.cpp"
31741 }
31742 {
31743
31744#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31745
31746 emit_opcode(cbuf, (0xC1 /*primary()*/));
31747
31748#line 31748 "ad_x86.cpp"
31749 }
31750 {
31751
31752#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31753
31754 int rm_byte_opcode = (0x4 /*secondary()*/);
31755
31756 // High registers handle in encode_RegMem
31757 int base = opnd_array(1)->base(ra_,this,idx1);
31758 int index = opnd_array(1)->index(ra_,this,idx1);
31759 int scale = opnd_array(1)->scale();
31760 int displace = opnd_array(1)->disp(ra_,this,idx1);
31761
31762 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
31763 // working with static
31764 // globals
31765 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
31766 disp_reloc);
31767
31768#line 31768 "ad_x86.cpp"
31769 }
31770 {
31771
31772#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31773
31774 // Check for 8-bit immediate, and set sign extend bit in opcode
31775 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
31776 emit_d8(cbuf, opnd_array(2)->constant());
31777 } else {
31778 // 32-bit immediate
31779 emit_d32(cbuf, opnd_array(2)->constant());
31780 }
31781
31782#line 31782 "ad_x86.cpp"
31783 }
31784}
31785
31786void salI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31787 cbuf.set_insts_mark();
31788 // Start at oper_input_base() and count operands
31789 unsigned idx0 = 1;
31790 unsigned idx1 = 1; // dst
31791 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31792 {
31793
31794#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31795
31796 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
31797 emit_opcode(cbuf, Assembler::REX_B);
31798 }
31799
31800#line 31800 "ad_x86.cpp"
31801 }
31802 {
31803
31804#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31805
31806 emit_opcode(cbuf, (0xD3 /*primary()*/));
31807
31808#line 31808 "ad_x86.cpp"
31809 }
31810 {
31811
31812#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31813
31814 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31815 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
31816
31817#line 31817 "ad_x86.cpp"
31818 }
31819}
31820
31821void salI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31822 cbuf.set_insts_mark();
31823 // Start at oper_input_base() and count operands
31824 unsigned idx0 = 2;
31825 unsigned idx1 = 2; // dst
31826 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31827 {
31828
31829#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31830
31831 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
31832 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
31833 emit_opcode(cbuf, Assembler::REX_B);
31834 } else {
31835 emit_opcode(cbuf, Assembler::REX_XB);
31836 }
31837 } else {
31838 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
31839 emit_opcode(cbuf, Assembler::REX_X);
31840 }
31841 }
31842
31843#line 31843 "ad_x86.cpp"
31844 }
31845 {
31846
31847#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31848
31849 emit_opcode(cbuf, (0xD3 /*primary()*/));
31850
31851#line 31851 "ad_x86.cpp"
31852 }
31853 {
31854
31855#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31856
31857 int rm_byte_opcode = (0x4 /*secondary()*/);
31858
31859 // High registers handle in encode_RegMem
31860 int base = opnd_array(1)->base(ra_,this,idx1);
31861 int index = opnd_array(1)->index(ra_,this,idx1);
31862 int scale = opnd_array(1)->scale();
31863 int displace = opnd_array(1)->disp(ra_,this,idx1);
31864
31865 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
31866 // working with static
31867 // globals
31868 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
31869 disp_reloc);
31870
31871#line 31871 "ad_x86.cpp"
31872 }
31873}
31874
31875void sarI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31876 cbuf.set_insts_mark();
31877 // Start at oper_input_base() and count operands
31878 unsigned idx0 = 1;
31879 unsigned idx1 = 1; // dst
31880 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31881 {
31882
31883#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31884
31885 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
31886 emit_opcode(cbuf, Assembler::REX_B);
31887 }
31888
31889#line 31889 "ad_x86.cpp"
31890 }
31891 {
31892
31893#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31894
31895 emit_opcode(cbuf, (0xD1 /*primary()*/));
31896
31897#line 31897 "ad_x86.cpp"
31898 }
31899 {
31900
31901#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31902
31903 // INC, DEC, IDIV, IMOD, JMP indirect, ...
31904 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
31905
31906#line 31906 "ad_x86.cpp"
31907 }
31908}
31909
31910void sarI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31911 cbuf.set_insts_mark();
31912 // Start at oper_input_base() and count operands
31913 unsigned idx0 = 2;
31914 unsigned idx1 = 2; // dst
31915 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31916 {
31917
31918#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31919
31920 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
31921 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
31922 emit_opcode(cbuf, Assembler::REX_B);
31923 } else {
31924 emit_opcode(cbuf, Assembler::REX_XB);
31925 }
31926 } else {
31927 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
31928 emit_opcode(cbuf, Assembler::REX_X);
31929 }
31930 }
31931
31932#line 31932 "ad_x86.cpp"
31933 }
31934 {
31935
31936#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31937
31938 emit_opcode(cbuf, (0xD1 /*primary()*/));
31939
31940#line 31940 "ad_x86.cpp"
31941 }
31942 {
31943
31944#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31945
31946 int rm_byte_opcode = (0x7 /*secondary()*/);
31947
31948 // High registers handle in encode_RegMem
31949 int base = opnd_array(1)->base(ra_,this,idx1);
31950 int index = opnd_array(1)->index(ra_,this,idx1);
31951 int scale = opnd_array(1)->scale();
31952 int displace = opnd_array(1)->disp(ra_,this,idx1);
31953
31954 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
31955 // working with static
31956 // globals
31957 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
31958 disp_reloc);
31959
31960#line 31960 "ad_x86.cpp"
31961 }
31962}
31963
31964void sarI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31965 cbuf.set_insts_mark();
31966 // Start at oper_input_base() and count operands
31967 unsigned idx0 = 1;
31968 unsigned idx1 = 1; // dst
31969 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31970 {
31971
31972#line 2191 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31973
31974 // SAL, SAR, SHR
31975 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
31976 if (dstenc >= 8) {
31977 emit_opcode(cbuf, Assembler::REX_B);
31978 dstenc -= 8;
31979 }
31980 emit_d8(cbuf, (0xC1 /*primary()*/));
31981 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), dstenc);
31982 emit_d8(cbuf, opnd_array(2)->constant());
31983
31984#line 31984 "ad_x86.cpp"
31985 }
31986}
31987
31988void sarI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31989 cbuf.set_insts_mark();
31990 // Start at oper_input_base() and count operands
31991 unsigned idx0 = 2;
31992 unsigned idx1 = 2; // dst
31993 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
31994 {
31995
31996#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
31997
31998 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
31999 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32000 emit_opcode(cbuf, Assembler::REX_B);
32001 } else {
32002 emit_opcode(cbuf, Assembler::REX_XB);
32003 }
32004 } else {
32005 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
32006 emit_opcode(cbuf, Assembler::REX_X);
32007 }
32008 }
32009
32010#line 32010 "ad_x86.cpp"
32011 }
32012 {
32013
32014#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32015
32016 emit_opcode(cbuf, (0xC1 /*primary()*/));
32017
32018#line 32018 "ad_x86.cpp"
32019 }
32020 {
32021
32022#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32023
32024 int rm_byte_opcode = (0x7 /*secondary()*/);
32025
32026 // High registers handle in encode_RegMem
32027 int base = opnd_array(1)->base(ra_,this,idx1);
32028 int index = opnd_array(1)->index(ra_,this,idx1);
32029 int scale = opnd_array(1)->scale();
32030 int displace = opnd_array(1)->disp(ra_,this,idx1);
32031
32032 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32033 // working with static
32034 // globals
32035 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32036 disp_reloc);
32037
32038#line 32038 "ad_x86.cpp"
32039 }
32040 {
32041
32042#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32043
32044 // Check for 8-bit immediate, and set sign extend bit in opcode
32045 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
32046 emit_d8(cbuf, opnd_array(2)->constant());
32047 } else {
32048 // 32-bit immediate
32049 emit_d32(cbuf, opnd_array(2)->constant());
32050 }
32051
32052#line 32052 "ad_x86.cpp"
32053 }
32054}
32055
32056void sarI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32057 cbuf.set_insts_mark();
32058 // Start at oper_input_base() and count operands
32059 unsigned idx0 = 1;
32060 unsigned idx1 = 1; // dst
32061 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32062 {
32063
32064#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32065
32066 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
32067 emit_opcode(cbuf, Assembler::REX_B);
32068 }
32069
32070#line 32070 "ad_x86.cpp"
32071 }
32072 {
32073
32074#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32075
32076 emit_opcode(cbuf, (0xD3 /*primary()*/));
32077
32078#line 32078 "ad_x86.cpp"
32079 }
32080 {
32081
32082#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32083
32084 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32085 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32086
32087#line 32087 "ad_x86.cpp"
32088 }
32089}
32090
32091void sarI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32092 cbuf.set_insts_mark();
32093 // Start at oper_input_base() and count operands
32094 unsigned idx0 = 2;
32095 unsigned idx1 = 2; // dst
32096 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32097 {
32098
32099#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32100
32101 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32102 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32103 emit_opcode(cbuf, Assembler::REX_B);
32104 } else {
32105 emit_opcode(cbuf, Assembler::REX_XB);
32106 }
32107 } else {
32108 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
32109 emit_opcode(cbuf, Assembler::REX_X);
32110 }
32111 }
32112
32113#line 32113 "ad_x86.cpp"
32114 }
32115 {
32116
32117#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32118
32119 emit_opcode(cbuf, (0xD3 /*primary()*/));
32120
32121#line 32121 "ad_x86.cpp"
32122 }
32123 {
32124
32125#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32126
32127 int rm_byte_opcode = (0x7 /*secondary()*/);
32128
32129 // High registers handle in encode_RegMem
32130 int base = opnd_array(1)->base(ra_,this,idx1);
32131 int index = opnd_array(1)->index(ra_,this,idx1);
32132 int scale = opnd_array(1)->scale();
32133 int displace = opnd_array(1)->disp(ra_,this,idx1);
32134
32135 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32136 // working with static
32137 // globals
32138 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32139 disp_reloc);
32140
32141#line 32141 "ad_x86.cpp"
32142 }
32143}
32144
32145void shrI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32146 cbuf.set_insts_mark();
32147 // Start at oper_input_base() and count operands
32148 unsigned idx0 = 1;
32149 unsigned idx1 = 1; // dst
32150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32151 {
32152
32153#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32154
32155 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
32156 emit_opcode(cbuf, Assembler::REX_B);
32157 }
32158
32159#line 32159 "ad_x86.cpp"
32160 }
32161 {
32162
32163#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32164
32165 emit_opcode(cbuf, (0xD1 /*primary()*/));
32166
32167#line 32167 "ad_x86.cpp"
32168 }
32169 {
32170
32171#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32172
32173 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32174 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32175
32176#line 32176 "ad_x86.cpp"
32177 }
32178}
32179
32180void shrI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32181 cbuf.set_insts_mark();
32182 // Start at oper_input_base() and count operands
32183 unsigned idx0 = 2;
32184 unsigned idx1 = 2; // dst
32185 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32186 {
32187
32188#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32189
32190 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32191 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32192 emit_opcode(cbuf, Assembler::REX_B);
32193 } else {
32194 emit_opcode(cbuf, Assembler::REX_XB);
32195 }
32196 } else {
32197 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
32198 emit_opcode(cbuf, Assembler::REX_X);
32199 }
32200 }
32201
32202#line 32202 "ad_x86.cpp"
32203 }
32204 {
32205
32206#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32207
32208 emit_opcode(cbuf, (0xD1 /*primary()*/));
32209
32210#line 32210 "ad_x86.cpp"
32211 }
32212 {
32213
32214#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32215
32216 int rm_byte_opcode = (0x5 /*secondary()*/);
32217
32218 // High registers handle in encode_RegMem
32219 int base = opnd_array(1)->base(ra_,this,idx1);
32220 int index = opnd_array(1)->index(ra_,this,idx1);
32221 int scale = opnd_array(1)->scale();
32222 int displace = opnd_array(1)->disp(ra_,this,idx1);
32223
32224 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32225 // working with static
32226 // globals
32227 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32228 disp_reloc);
32229
32230#line 32230 "ad_x86.cpp"
32231 }
32232}
32233
32234void shrI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32235 cbuf.set_insts_mark();
32236 // Start at oper_input_base() and count operands
32237 unsigned idx0 = 1;
32238 unsigned idx1 = 1; // dst
32239 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32240 {
32241
32242#line 2191 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32243
32244 // SAL, SAR, SHR
32245 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
32246 if (dstenc >= 8) {
32247 emit_opcode(cbuf, Assembler::REX_B);
32248 dstenc -= 8;
32249 }
32250 emit_d8(cbuf, (0xC1 /*primary()*/));
32251 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), dstenc);
32252 emit_d8(cbuf, opnd_array(2)->constant());
32253
32254#line 32254 "ad_x86.cpp"
32255 }
32256}
32257
32258void shrI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32259 cbuf.set_insts_mark();
32260 // Start at oper_input_base() and count operands
32261 unsigned idx0 = 2;
32262 unsigned idx1 = 2; // dst
32263 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32264 {
32265
32266#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32267
32268 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32269 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32270 emit_opcode(cbuf, Assembler::REX_B);
32271 } else {
32272 emit_opcode(cbuf, Assembler::REX_XB);
32273 }
32274 } else {
32275 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
32276 emit_opcode(cbuf, Assembler::REX_X);
32277 }
32278 }
32279
32280#line 32280 "ad_x86.cpp"
32281 }
32282 {
32283
32284#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32285
32286 emit_opcode(cbuf, (0xC1 /*primary()*/));
32287
32288#line 32288 "ad_x86.cpp"
32289 }
32290 {
32291
32292#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32293
32294 int rm_byte_opcode = (0x5 /*secondary()*/);
32295
32296 // High registers handle in encode_RegMem
32297 int base = opnd_array(1)->base(ra_,this,idx1);
32298 int index = opnd_array(1)->index(ra_,this,idx1);
32299 int scale = opnd_array(1)->scale();
32300 int displace = opnd_array(1)->disp(ra_,this,idx1);
32301
32302 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32303 // working with static
32304 // globals
32305 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32306 disp_reloc);
32307
32308#line 32308 "ad_x86.cpp"
32309 }
32310 {
32311
32312#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32313
32314 // Check for 8-bit immediate, and set sign extend bit in opcode
32315 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
32316 emit_d8(cbuf, opnd_array(2)->constant());
32317 } else {
32318 // 32-bit immediate
32319 emit_d32(cbuf, opnd_array(2)->constant());
32320 }
32321
32322#line 32322 "ad_x86.cpp"
32323 }
32324}
32325
32326void shrI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32327 cbuf.set_insts_mark();
32328 // Start at oper_input_base() and count operands
32329 unsigned idx0 = 1;
32330 unsigned idx1 = 1; // dst
32331 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32332 {
32333
32334#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32335
32336 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
32337 emit_opcode(cbuf, Assembler::REX_B);
32338 }
32339
32340#line 32340 "ad_x86.cpp"
32341 }
32342 {
32343
32344#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32345
32346 emit_opcode(cbuf, (0xD3 /*primary()*/));
32347
32348#line 32348 "ad_x86.cpp"
32349 }
32350 {
32351
32352#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32353
32354 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32355 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32356
32357#line 32357 "ad_x86.cpp"
32358 }
32359}
32360
32361void shrI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32362 cbuf.set_insts_mark();
32363 // Start at oper_input_base() and count operands
32364 unsigned idx0 = 2;
32365 unsigned idx1 = 2; // dst
32366 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32367 {
32368
32369#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32370
32371 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32372 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32373 emit_opcode(cbuf, Assembler::REX_B);
32374 } else {
32375 emit_opcode(cbuf, Assembler::REX_XB);
32376 }
32377 } else {
32378 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
32379 emit_opcode(cbuf, Assembler::REX_X);
32380 }
32381 }
32382
32383#line 32383 "ad_x86.cpp"
32384 }
32385 {
32386
32387#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32388
32389 emit_opcode(cbuf, (0xD3 /*primary()*/));
32390
32391#line 32391 "ad_x86.cpp"
32392 }
32393 {
32394
32395#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32396
32397 int rm_byte_opcode = (0x5 /*secondary()*/);
32398
32399 // High registers handle in encode_RegMem
32400 int base = opnd_array(1)->base(ra_,this,idx1);
32401 int index = opnd_array(1)->index(ra_,this,idx1);
32402 int scale = opnd_array(1)->scale();
32403 int displace = opnd_array(1)->disp(ra_,this,idx1);
32404
32405 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32406 // working with static
32407 // globals
32408 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32409 disp_reloc);
32410
32411#line 32411 "ad_x86.cpp"
32412 }
32413}
32414
32415void salL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32416 cbuf.set_insts_mark();
32417 // Start at oper_input_base() and count operands
32418 unsigned idx0 = 1;
32419 unsigned idx1 = 1; // dst
32420 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32421 {
32422
32423#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32424
32425 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
32426 emit_opcode(cbuf, Assembler::REX_W);
32427 } else {
32428 emit_opcode(cbuf, Assembler::REX_WB);
32429 }
32430
32431#line 32431 "ad_x86.cpp"
32432 }
32433 {
32434
32435#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32436
32437 emit_opcode(cbuf, (0xD1 /*primary()*/));
32438
32439#line 32439 "ad_x86.cpp"
32440 }
32441 {
32442
32443#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32444
32445 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32446 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32447
32448#line 32448 "ad_x86.cpp"
32449 }
32450}
32451
32452void salL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32453 cbuf.set_insts_mark();
32454 // Start at oper_input_base() and count operands
32455 unsigned idx0 = 2;
32456 unsigned idx1 = 2; // dst
32457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32458 {
32459
32460#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32461
32462 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32463 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32464 emit_opcode(cbuf, Assembler::REX_WB);
32465 } else {
32466 emit_opcode(cbuf, Assembler::REX_WXB);
32467 }
32468 } else {
32469 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32470 emit_opcode(cbuf, Assembler::REX_W);
32471 } else {
32472 emit_opcode(cbuf, Assembler::REX_WX);
32473 }
32474 }
32475
32476#line 32476 "ad_x86.cpp"
32477 }
32478 {
32479
32480#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32481
32482 emit_opcode(cbuf, (0xD1 /*primary()*/));
32483
32484#line 32484 "ad_x86.cpp"
32485 }
32486 {
32487
32488#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32489
32490 int rm_byte_opcode = (0x4 /*secondary()*/);
32491
32492 // High registers handle in encode_RegMem
32493 int base = opnd_array(1)->base(ra_,this,idx1);
32494 int index = opnd_array(1)->index(ra_,this,idx1);
32495 int scale = opnd_array(1)->scale();
32496 int displace = opnd_array(1)->disp(ra_,this,idx1);
32497
32498 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32499 // working with static
32500 // globals
32501 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32502 disp_reloc);
32503
32504#line 32504 "ad_x86.cpp"
32505 }
32506}
32507
32508void salL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32509 cbuf.set_insts_mark();
32510 // Start at oper_input_base() and count operands
32511 unsigned idx0 = 1;
32512 unsigned idx1 = 1; // dst
32513 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32514 {
32515
32516#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32517
32518 // SAL, SAR, SHR
32519 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
32520 if (dstenc < 8) {
32521 emit_opcode(cbuf, Assembler::REX_W);
32522 } else {
32523 emit_opcode(cbuf, Assembler::REX_WB);
32524 dstenc -= 8;
32525 }
32526 emit_d8(cbuf, (0xC1 /*primary()*/));
32527 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), dstenc);
32528 emit_d8(cbuf, opnd_array(2)->constant());
32529
32530#line 32530 "ad_x86.cpp"
32531 }
32532}
32533
32534void salL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32535 cbuf.set_insts_mark();
32536 // Start at oper_input_base() and count operands
32537 unsigned idx0 = 2;
32538 unsigned idx1 = 2; // dst
32539 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32540 {
32541
32542#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32543
32544 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32545 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32546 emit_opcode(cbuf, Assembler::REX_WB);
32547 } else {
32548 emit_opcode(cbuf, Assembler::REX_WXB);
32549 }
32550 } else {
32551 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32552 emit_opcode(cbuf, Assembler::REX_W);
32553 } else {
32554 emit_opcode(cbuf, Assembler::REX_WX);
32555 }
32556 }
32557
32558#line 32558 "ad_x86.cpp"
32559 }
32560 {
32561
32562#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32563
32564 emit_opcode(cbuf, (0xC1 /*primary()*/));
32565
32566#line 32566 "ad_x86.cpp"
32567 }
32568 {
32569
32570#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32571
32572 int rm_byte_opcode = (0x4 /*secondary()*/);
32573
32574 // High registers handle in encode_RegMem
32575 int base = opnd_array(1)->base(ra_,this,idx1);
32576 int index = opnd_array(1)->index(ra_,this,idx1);
32577 int scale = opnd_array(1)->scale();
32578 int displace = opnd_array(1)->disp(ra_,this,idx1);
32579
32580 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32581 // working with static
32582 // globals
32583 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32584 disp_reloc);
32585
32586#line 32586 "ad_x86.cpp"
32587 }
32588 {
32589
32590#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32591
32592 // Check for 8-bit immediate, and set sign extend bit in opcode
32593 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
32594 emit_d8(cbuf, opnd_array(2)->constant());
32595 } else {
32596 // 32-bit immediate
32597 emit_d32(cbuf, opnd_array(2)->constant());
32598 }
32599
32600#line 32600 "ad_x86.cpp"
32601 }
32602}
32603
32604void salL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32605 cbuf.set_insts_mark();
32606 // Start at oper_input_base() and count operands
32607 unsigned idx0 = 1;
32608 unsigned idx1 = 1; // dst
32609 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32610 {
32611
32612#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32613
32614 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
32615 emit_opcode(cbuf, Assembler::REX_W);
32616 } else {
32617 emit_opcode(cbuf, Assembler::REX_WB);
32618 }
32619
32620#line 32620 "ad_x86.cpp"
32621 }
32622 {
32623
32624#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32625
32626 emit_opcode(cbuf, (0xD3 /*primary()*/));
32627
32628#line 32628 "ad_x86.cpp"
32629 }
32630 {
32631
32632#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32633
32634 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32635 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32636
32637#line 32637 "ad_x86.cpp"
32638 }
32639}
32640
32641void salL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32642 cbuf.set_insts_mark();
32643 // Start at oper_input_base() and count operands
32644 unsigned idx0 = 2;
32645 unsigned idx1 = 2; // dst
32646 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32647 {
32648
32649#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32650
32651 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32652 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32653 emit_opcode(cbuf, Assembler::REX_WB);
32654 } else {
32655 emit_opcode(cbuf, Assembler::REX_WXB);
32656 }
32657 } else {
32658 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32659 emit_opcode(cbuf, Assembler::REX_W);
32660 } else {
32661 emit_opcode(cbuf, Assembler::REX_WX);
32662 }
32663 }
32664
32665#line 32665 "ad_x86.cpp"
32666 }
32667 {
32668
32669#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32670
32671 emit_opcode(cbuf, (0xD3 /*primary()*/));
32672
32673#line 32673 "ad_x86.cpp"
32674 }
32675 {
32676
32677#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32678
32679 int rm_byte_opcode = (0x4 /*secondary()*/);
32680
32681 // High registers handle in encode_RegMem
32682 int base = opnd_array(1)->base(ra_,this,idx1);
32683 int index = opnd_array(1)->index(ra_,this,idx1);
32684 int scale = opnd_array(1)->scale();
32685 int displace = opnd_array(1)->disp(ra_,this,idx1);
32686
32687 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32688 // working with static
32689 // globals
32690 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32691 disp_reloc);
32692
32693#line 32693 "ad_x86.cpp"
32694 }
32695}
32696
32697void sarL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32698 cbuf.set_insts_mark();
32699 // Start at oper_input_base() and count operands
32700 unsigned idx0 = 1;
32701 unsigned idx1 = 1; // dst
32702 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32703 {
32704
32705#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32706
32707 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
32708 emit_opcode(cbuf, Assembler::REX_W);
32709 } else {
32710 emit_opcode(cbuf, Assembler::REX_WB);
32711 }
32712
32713#line 32713 "ad_x86.cpp"
32714 }
32715 {
32716
32717#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32718
32719 emit_opcode(cbuf, (0xD1 /*primary()*/));
32720
32721#line 32721 "ad_x86.cpp"
32722 }
32723 {
32724
32725#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32726
32727 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32728 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32729
32730#line 32730 "ad_x86.cpp"
32731 }
32732}
32733
32734void sarL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32735 cbuf.set_insts_mark();
32736 // Start at oper_input_base() and count operands
32737 unsigned idx0 = 2;
32738 unsigned idx1 = 2; // dst
32739 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32740 {
32741
32742#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32743
32744 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32745 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32746 emit_opcode(cbuf, Assembler::REX_WB);
32747 } else {
32748 emit_opcode(cbuf, Assembler::REX_WXB);
32749 }
32750 } else {
32751 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32752 emit_opcode(cbuf, Assembler::REX_W);
32753 } else {
32754 emit_opcode(cbuf, Assembler::REX_WX);
32755 }
32756 }
32757
32758#line 32758 "ad_x86.cpp"
32759 }
32760 {
32761
32762#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32763
32764 emit_opcode(cbuf, (0xD1 /*primary()*/));
32765
32766#line 32766 "ad_x86.cpp"
32767 }
32768 {
32769
32770#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32771
32772 int rm_byte_opcode = (0x7 /*secondary()*/);
32773
32774 // High registers handle in encode_RegMem
32775 int base = opnd_array(1)->base(ra_,this,idx1);
32776 int index = opnd_array(1)->index(ra_,this,idx1);
32777 int scale = opnd_array(1)->scale();
32778 int displace = opnd_array(1)->disp(ra_,this,idx1);
32779
32780 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32781 // working with static
32782 // globals
32783 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32784 disp_reloc);
32785
32786#line 32786 "ad_x86.cpp"
32787 }
32788}
32789
32790void sarL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32791 cbuf.set_insts_mark();
32792 // Start at oper_input_base() and count operands
32793 unsigned idx0 = 1;
32794 unsigned idx1 = 1; // dst
32795 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32796 {
32797
32798#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32799
32800 // SAL, SAR, SHR
32801 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
32802 if (dstenc < 8) {
32803 emit_opcode(cbuf, Assembler::REX_W);
32804 } else {
32805 emit_opcode(cbuf, Assembler::REX_WB);
32806 dstenc -= 8;
32807 }
32808 emit_d8(cbuf, (0xC1 /*primary()*/));
32809 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), dstenc);
32810 emit_d8(cbuf, opnd_array(2)->constant());
32811
32812#line 32812 "ad_x86.cpp"
32813 }
32814}
32815
32816void sarL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32817 cbuf.set_insts_mark();
32818 // Start at oper_input_base() and count operands
32819 unsigned idx0 = 2;
32820 unsigned idx1 = 2; // dst
32821 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32822 {
32823
32824#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32825
32826 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32827 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32828 emit_opcode(cbuf, Assembler::REX_WB);
32829 } else {
32830 emit_opcode(cbuf, Assembler::REX_WXB);
32831 }
32832 } else {
32833 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32834 emit_opcode(cbuf, Assembler::REX_W);
32835 } else {
32836 emit_opcode(cbuf, Assembler::REX_WX);
32837 }
32838 }
32839
32840#line 32840 "ad_x86.cpp"
32841 }
32842 {
32843
32844#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32845
32846 emit_opcode(cbuf, (0xC1 /*primary()*/));
32847
32848#line 32848 "ad_x86.cpp"
32849 }
32850 {
32851
32852#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32853
32854 int rm_byte_opcode = (0x7 /*secondary()*/);
32855
32856 // High registers handle in encode_RegMem
32857 int base = opnd_array(1)->base(ra_,this,idx1);
32858 int index = opnd_array(1)->index(ra_,this,idx1);
32859 int scale = opnd_array(1)->scale();
32860 int displace = opnd_array(1)->disp(ra_,this,idx1);
32861
32862 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32863 // working with static
32864 // globals
32865 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32866 disp_reloc);
32867
32868#line 32868 "ad_x86.cpp"
32869 }
32870 {
32871
32872#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32873
32874 // Check for 8-bit immediate, and set sign extend bit in opcode
32875 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
32876 emit_d8(cbuf, opnd_array(2)->constant());
32877 } else {
32878 // 32-bit immediate
32879 emit_d32(cbuf, opnd_array(2)->constant());
32880 }
32881
32882#line 32882 "ad_x86.cpp"
32883 }
32884}
32885
32886void sarL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32887 cbuf.set_insts_mark();
32888 // Start at oper_input_base() and count operands
32889 unsigned idx0 = 1;
32890 unsigned idx1 = 1; // dst
32891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32892 {
32893
32894#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32895
32896 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
32897 emit_opcode(cbuf, Assembler::REX_W);
32898 } else {
32899 emit_opcode(cbuf, Assembler::REX_WB);
32900 }
32901
32902#line 32902 "ad_x86.cpp"
32903 }
32904 {
32905
32906#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32907
32908 emit_opcode(cbuf, (0xD3 /*primary()*/));
32909
32910#line 32910 "ad_x86.cpp"
32911 }
32912 {
32913
32914#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32915
32916 // INC, DEC, IDIV, IMOD, JMP indirect, ...
32917 emit_rm(cbuf, 0x3, (0x7 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
32918
32919#line 32919 "ad_x86.cpp"
32920 }
32921}
32922
32923void sarL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32924 cbuf.set_insts_mark();
32925 // Start at oper_input_base() and count operands
32926 unsigned idx0 = 2;
32927 unsigned idx1 = 2; // dst
32928 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32929 {
32930
32931#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32932
32933 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
32934 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32935 emit_opcode(cbuf, Assembler::REX_WB);
32936 } else {
32937 emit_opcode(cbuf, Assembler::REX_WXB);
32938 }
32939 } else {
32940 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
32941 emit_opcode(cbuf, Assembler::REX_W);
32942 } else {
32943 emit_opcode(cbuf, Assembler::REX_WX);
32944 }
32945 }
32946
32947#line 32947 "ad_x86.cpp"
32948 }
32949 {
32950
32951#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32952
32953 emit_opcode(cbuf, (0xD3 /*primary()*/));
32954
32955#line 32955 "ad_x86.cpp"
32956 }
32957 {
32958
32959#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32960
32961 int rm_byte_opcode = (0x7 /*secondary()*/);
32962
32963 // High registers handle in encode_RegMem
32964 int base = opnd_array(1)->base(ra_,this,idx1);
32965 int index = opnd_array(1)->index(ra_,this,idx1);
32966 int scale = opnd_array(1)->scale();
32967 int displace = opnd_array(1)->disp(ra_,this,idx1);
32968
32969 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
32970 // working with static
32971 // globals
32972 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
32973 disp_reloc);
32974
32975#line 32975 "ad_x86.cpp"
32976 }
32977}
32978
32979void shrL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32980 cbuf.set_insts_mark();
32981 // Start at oper_input_base() and count operands
32982 unsigned idx0 = 1;
32983 unsigned idx1 = 1; // dst
32984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
32985 {
32986
32987#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
32988
32989 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
32990 emit_opcode(cbuf, Assembler::REX_W);
32991 } else {
32992 emit_opcode(cbuf, Assembler::REX_WB);
32993 }
32994
32995#line 32995 "ad_x86.cpp"
32996 }
32997 {
32998
32999#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33000
33001 emit_opcode(cbuf, (0xD1 /*primary()*/));
33002
33003#line 33003 "ad_x86.cpp"
33004 }
33005 {
33006
33007#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33008
33009 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33010 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33011
33012#line 33012 "ad_x86.cpp"
33013 }
33014}
33015
33016void shrL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33017 cbuf.set_insts_mark();
33018 // Start at oper_input_base() and count operands
33019 unsigned idx0 = 2;
33020 unsigned idx1 = 2; // dst
33021 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
33022 {
33023
33024#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33025
33026 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
33027 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33028 emit_opcode(cbuf, Assembler::REX_WB);
33029 } else {
33030 emit_opcode(cbuf, Assembler::REX_WXB);
33031 }
33032 } else {
33033 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33034 emit_opcode(cbuf, Assembler::REX_W);
33035 } else {
33036 emit_opcode(cbuf, Assembler::REX_WX);
33037 }
33038 }
33039
33040#line 33040 "ad_x86.cpp"
33041 }
33042 {
33043
33044#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33045
33046 emit_opcode(cbuf, (0xD1 /*primary()*/));
33047
33048#line 33048 "ad_x86.cpp"
33049 }
33050 {
33051
33052#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33053
33054 int rm_byte_opcode = (0x5 /*secondary()*/);
33055
33056 // High registers handle in encode_RegMem
33057 int base = opnd_array(1)->base(ra_,this,idx1);
33058 int index = opnd_array(1)->index(ra_,this,idx1);
33059 int scale = opnd_array(1)->scale();
33060 int displace = opnd_array(1)->disp(ra_,this,idx1);
33061
33062 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
33063 // working with static
33064 // globals
33065 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
33066 disp_reloc);
33067
33068#line 33068 "ad_x86.cpp"
33069 }
33070}
33071
33072void shrL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33073 cbuf.set_insts_mark();
33074 // Start at oper_input_base() and count operands
33075 unsigned idx0 = 1;
33076 unsigned idx1 = 1; // dst
33077 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
33078 {
33079
33080#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33081
33082 // SAL, SAR, SHR
33083 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33084 if (dstenc < 8) {
33085 emit_opcode(cbuf, Assembler::REX_W);
33086 } else {
33087 emit_opcode(cbuf, Assembler::REX_WB);
33088 dstenc -= 8;
33089 }
33090 emit_d8(cbuf, (0xC1 /*primary()*/));
33091 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), dstenc);
33092 emit_d8(cbuf, opnd_array(2)->constant());
33093
33094#line 33094 "ad_x86.cpp"
33095 }
33096}
33097
33098void shrL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33099 cbuf.set_insts_mark();
33100 // Start at oper_input_base() and count operands
33101 unsigned idx0 = 2;
33102 unsigned idx1 = 2; // dst
33103 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
33104 {
33105
33106#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33107
33108 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
33109 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33110 emit_opcode(cbuf, Assembler::REX_WB);
33111 } else {
33112 emit_opcode(cbuf, Assembler::REX_WXB);
33113 }
33114 } else {
33115 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33116 emit_opcode(cbuf, Assembler::REX_W);
33117 } else {
33118 emit_opcode(cbuf, Assembler::REX_WX);
33119 }
33120 }
33121
33122#line 33122 "ad_x86.cpp"
33123 }
33124 {
33125
33126#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33127
33128 emit_opcode(cbuf, (0xC1 /*primary()*/));
33129
33130#line 33130 "ad_x86.cpp"
33131 }
33132 {
33133
33134#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33135
33136 int rm_byte_opcode = (0x5 /*secondary()*/);
33137
33138 // High registers handle in encode_RegMem
33139 int base = opnd_array(1)->base(ra_,this,idx1);
33140 int index = opnd_array(1)->index(ra_,this,idx1);
33141 int scale = opnd_array(1)->scale();
33142 int displace = opnd_array(1)->disp(ra_,this,idx1);
33143
33144 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
33145 // working with static
33146 // globals
33147 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
33148 disp_reloc);
33149
33150#line 33150 "ad_x86.cpp"
33151 }
33152 {
33153
33154#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33155
33156 // Check for 8-bit immediate, and set sign extend bit in opcode
33157 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
33158 emit_d8(cbuf, opnd_array(2)->constant());
33159 } else {
33160 // 32-bit immediate
33161 emit_d32(cbuf, opnd_array(2)->constant());
33162 }
33163
33164#line 33164 "ad_x86.cpp"
33165 }
33166}
33167
33168void shrL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33169 cbuf.set_insts_mark();
33170 // Start at oper_input_base() and count operands
33171 unsigned idx0 = 1;
33172 unsigned idx1 = 1; // dst
33173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
33174 {
33175
33176#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33177
33178 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33179 emit_opcode(cbuf, Assembler::REX_W);
33180 } else {
33181 emit_opcode(cbuf, Assembler::REX_WB);
33182 }
33183
33184#line 33184 "ad_x86.cpp"
33185 }
33186 {
33187
33188#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33189
33190 emit_opcode(cbuf, (0xD3 /*primary()*/));
33191
33192#line 33192 "ad_x86.cpp"
33193 }
33194 {
33195
33196#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33197
33198 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33199 emit_rm(cbuf, 0x3, (0x5 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33200
33201#line 33201 "ad_x86.cpp"
33202 }
33203}
33204
33205void shrL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33206 cbuf.set_insts_mark();
33207 // Start at oper_input_base() and count operands
33208 unsigned idx0 = 2;
33209 unsigned idx1 = 2; // dst
33210 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
33211 {
33212
33213#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33214
33215 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
33216 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33217 emit_opcode(cbuf, Assembler::REX_WB);
33218 } else {
33219 emit_opcode(cbuf, Assembler::REX_WXB);
33220 }
33221 } else {
33222 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
33223 emit_opcode(cbuf, Assembler::REX_W);
33224 } else {
33225 emit_opcode(cbuf, Assembler::REX_WX);
33226 }
33227 }
33228
33229#line 33229 "ad_x86.cpp"
33230 }
33231 {
33232
33233#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33234
33235 emit_opcode(cbuf, (0xD3 /*primary()*/));
33236
33237#line 33237 "ad_x86.cpp"
33238 }
33239 {
33240
33241#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33242
33243 int rm_byte_opcode = (0x5 /*secondary()*/);
33244
33245 // High registers handle in encode_RegMem
33246 int base = opnd_array(1)->base(ra_,this,idx1);
33247 int index = opnd_array(1)->index(ra_,this,idx1);
33248 int scale = opnd_array(1)->scale();
33249 int displace = opnd_array(1)->disp(ra_,this,idx1);
33250
33251 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
33252 // working with static
33253 // globals
33254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
33255 disp_reloc);
33256
33257#line 33257 "ad_x86.cpp"
33258 }
33259}
33260
33261void i2bNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33262 cbuf.set_insts_mark();
33263 // Start at oper_input_base() and count operands
33264 unsigned idx0 = 1;
33265 unsigned idx1 = 1; // src
33266 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
33267 {
33268
33269#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33270
33271 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
33272 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 4) {
33273 emit_opcode(cbuf, opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8 ? Assembler::REX : Assembler::REX_B);
33274 }
33275 } else {
33276 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
33277 emit_opcode(cbuf, Assembler::REX_R);
33278 } else {
33279 emit_opcode(cbuf, Assembler::REX_RB);
33280 }
33281 }
33282
33283#line 33283 "ad_x86.cpp"
33284 }
33285 {
33286
33287#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33288
33289 emit_opcode(cbuf, (0x0F /*primary()*/));
33290
33291#line 33291 "ad_x86.cpp"
33292 }
33293 {
33294
33295#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33296
33297 emit_opcode(cbuf, (0xBE /*secondary()*/));
33298
33299#line 33299 "ad_x86.cpp"
33300 }
33301 {
33302
33303#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33304
33305 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
33306
33307#line 33307 "ad_x86.cpp"
33308 }
33309}
33310
33311void i2sNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33312 cbuf.set_insts_mark();
33313 // Start at oper_input_base() and count operands
33314 unsigned idx0 = 1;
33315 unsigned idx1 = 1; // src
33316 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
33317 {
33318
33319#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33320
33321 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
33322 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
33323 emit_opcode(cbuf, Assembler::REX_B);
33324 }
33325 } else {
33326 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
33327 emit_opcode(cbuf, Assembler::REX_R);
33328 } else {
33329 emit_opcode(cbuf, Assembler::REX_RB);
33330 }
33331 }
33332
33333#line 33333 "ad_x86.cpp"
33334 }
33335 {
33336
33337#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33338
33339 emit_opcode(cbuf, (0x0F /*primary()*/));
33340
33341#line 33341 "ad_x86.cpp"
33342 }
33343 {
33344
33345#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33346
33347 emit_opcode(cbuf, (0xBF /*secondary()*/));
33348
33349#line 33349 "ad_x86.cpp"
33350 }
33351 {
33352
33353#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33354
33355 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
33356
33357#line 33357 "ad_x86.cpp"
33358 }
33359}
33360
33361void rolI_rReg_imm1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33362 cbuf.set_insts_mark();
33363 // Start at oper_input_base() and count operands
33364 unsigned idx0 = 1;
33365 unsigned idx1 = 1; // cr
33366 {
33367
33368#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33369
33370 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
33371 emit_opcode(cbuf, Assembler::REX_B);
33372 }
33373
33374#line 33374 "ad_x86.cpp"
33375 }
33376 {
33377
33378#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33379
33380 emit_opcode(cbuf, (0xD1 /*primary()*/));
33381
33382#line 33382 "ad_x86.cpp"
33383 }
33384 {
33385
33386#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33387
33388 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33389 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33390
33391#line 33391 "ad_x86.cpp"
33392 }
33393}
33394
33395void rolI_rReg_imm8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33396 cbuf.set_insts_mark();
33397 // Start at oper_input_base() and count operands
33398 unsigned idx0 = 1;
33399 unsigned idx1 = 1; // shift
33400 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33401 {
33402
33403#line 2191 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33404
33405 // SAL, SAR, SHR
33406 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33407 if (dstenc >= 8) {
33408 emit_opcode(cbuf, Assembler::REX_B);
33409 dstenc -= 8;
33410 }
33411 emit_d8(cbuf, (0xC1 /*primary()*/));
33412 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), dstenc);
33413 emit_d8(cbuf, opnd_array(2)->constant());
33414
33415#line 33415 "ad_x86.cpp"
33416 }
33417}
33418
33419void rolI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33420 cbuf.set_insts_mark();
33421 // Start at oper_input_base() and count operands
33422 unsigned idx0 = 1;
33423 unsigned idx1 = 1; // shift
33424 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33425 {
33426
33427#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33428
33429 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
33430 emit_opcode(cbuf, Assembler::REX_B);
33431 }
33432
33433#line 33433 "ad_x86.cpp"
33434 }
33435 {
33436
33437#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33438
33439 emit_opcode(cbuf, (0xD3 /*primary()*/));
33440
33441#line 33441 "ad_x86.cpp"
33442 }
33443 {
33444
33445#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33446
33447 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33448 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33449
33450#line 33450 "ad_x86.cpp"
33451 }
33452}
33453
33454void rorI_rReg_imm1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33455 cbuf.set_insts_mark();
33456 // Start at oper_input_base() and count operands
33457 unsigned idx0 = 1;
33458 unsigned idx1 = 1; // cr
33459 {
33460
33461#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33462
33463 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
33464 emit_opcode(cbuf, Assembler::REX_B);
33465 }
33466
33467#line 33467 "ad_x86.cpp"
33468 }
33469 {
33470
33471#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33472
33473 emit_opcode(cbuf, (0xD1 /*primary()*/));
33474
33475#line 33475 "ad_x86.cpp"
33476 }
33477 {
33478
33479#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33480
33481 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33482 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33483
33484#line 33484 "ad_x86.cpp"
33485 }
33486}
33487
33488void rorI_rReg_imm8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33489 cbuf.set_insts_mark();
33490 // Start at oper_input_base() and count operands
33491 unsigned idx0 = 1;
33492 unsigned idx1 = 1; // shift
33493 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33494 {
33495
33496#line 2191 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33497
33498 // SAL, SAR, SHR
33499 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33500 if (dstenc >= 8) {
33501 emit_opcode(cbuf, Assembler::REX_B);
33502 dstenc -= 8;
33503 }
33504 emit_d8(cbuf, (0xC1 /*primary()*/));
33505 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), dstenc);
33506 emit_d8(cbuf, opnd_array(2)->constant());
33507
33508#line 33508 "ad_x86.cpp"
33509 }
33510}
33511
33512void rorI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33513 cbuf.set_insts_mark();
33514 // Start at oper_input_base() and count operands
33515 unsigned idx0 = 1;
33516 unsigned idx1 = 1; // shift
33517 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33518 {
33519
33520#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33521
33522 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
33523 emit_opcode(cbuf, Assembler::REX_B);
33524 }
33525
33526#line 33526 "ad_x86.cpp"
33527 }
33528 {
33529
33530#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33531
33532 emit_opcode(cbuf, (0xD3 /*primary()*/));
33533
33534#line 33534 "ad_x86.cpp"
33535 }
33536 {
33537
33538#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33539
33540 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33541 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33542
33543#line 33543 "ad_x86.cpp"
33544 }
33545}
33546
33547void rolL_rReg_imm1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33548 cbuf.set_insts_mark();
33549 // Start at oper_input_base() and count operands
33550 unsigned idx0 = 1;
33551 unsigned idx1 = 1; // cr
33552 {
33553
33554#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33555
33556 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33557 emit_opcode(cbuf, Assembler::REX_W);
33558 } else {
33559 emit_opcode(cbuf, Assembler::REX_WB);
33560 }
33561
33562#line 33562 "ad_x86.cpp"
33563 }
33564 {
33565
33566#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33567
33568 emit_opcode(cbuf, (0xD1 /*primary()*/));
33569
33570#line 33570 "ad_x86.cpp"
33571 }
33572 {
33573
33574#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33575
33576 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33577 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33578
33579#line 33579 "ad_x86.cpp"
33580 }
33581}
33582
33583void rolL_rReg_imm8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33584 cbuf.set_insts_mark();
33585 // Start at oper_input_base() and count operands
33586 unsigned idx0 = 1;
33587 unsigned idx1 = 1; // shift
33588 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33589 {
33590
33591#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33592
33593 // SAL, SAR, SHR
33594 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33595 if (dstenc < 8) {
33596 emit_opcode(cbuf, Assembler::REX_W);
33597 } else {
33598 emit_opcode(cbuf, Assembler::REX_WB);
33599 dstenc -= 8;
33600 }
33601 emit_d8(cbuf, (0xC1 /*primary()*/));
33602 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), dstenc);
33603 emit_d8(cbuf, opnd_array(2)->constant());
33604
33605#line 33605 "ad_x86.cpp"
33606 }
33607}
33608
33609void rolL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33610 cbuf.set_insts_mark();
33611 // Start at oper_input_base() and count operands
33612 unsigned idx0 = 1;
33613 unsigned idx1 = 1; // shift
33614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33615 {
33616
33617#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33618
33619 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33620 emit_opcode(cbuf, Assembler::REX_W);
33621 } else {
33622 emit_opcode(cbuf, Assembler::REX_WB);
33623 }
33624
33625#line 33625 "ad_x86.cpp"
33626 }
33627 {
33628
33629#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33630
33631 emit_opcode(cbuf, (0xD3 /*primary()*/));
33632
33633#line 33633 "ad_x86.cpp"
33634 }
33635 {
33636
33637#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33638
33639 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33640 emit_rm(cbuf, 0x3, (0x0 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33641
33642#line 33642 "ad_x86.cpp"
33643 }
33644}
33645
33646void rorL_rReg_imm1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33647 cbuf.set_insts_mark();
33648 // Start at oper_input_base() and count operands
33649 unsigned idx0 = 1;
33650 unsigned idx1 = 1; // cr
33651 {
33652
33653#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33654
33655 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33656 emit_opcode(cbuf, Assembler::REX_W);
33657 } else {
33658 emit_opcode(cbuf, Assembler::REX_WB);
33659 }
33660
33661#line 33661 "ad_x86.cpp"
33662 }
33663 {
33664
33665#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33666
33667 emit_opcode(cbuf, (0xD1 /*primary()*/));
33668
33669#line 33669 "ad_x86.cpp"
33670 }
33671 {
33672
33673#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33674
33675 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33676 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33677
33678#line 33678 "ad_x86.cpp"
33679 }
33680}
33681
33682void rorL_rReg_imm8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33683 cbuf.set_insts_mark();
33684 // Start at oper_input_base() and count operands
33685 unsigned idx0 = 1;
33686 unsigned idx1 = 1; // shift
33687 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33688 {
33689
33690#line 2204 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33691
33692 // SAL, SAR, SHR
33693 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33694 if (dstenc < 8) {
33695 emit_opcode(cbuf, Assembler::REX_W);
33696 } else {
33697 emit_opcode(cbuf, Assembler::REX_WB);
33698 dstenc -= 8;
33699 }
33700 emit_d8(cbuf, (0xC1 /*primary()*/));
33701 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), dstenc);
33702 emit_d8(cbuf, opnd_array(2)->constant());
33703
33704#line 33704 "ad_x86.cpp"
33705 }
33706}
33707
33708void rorL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33709 cbuf.set_insts_mark();
33710 // Start at oper_input_base() and count operands
33711 unsigned idx0 = 1;
33712 unsigned idx1 = 1; // shift
33713 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
33714 {
33715
33716#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33717
33718 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33719 emit_opcode(cbuf, Assembler::REX_W);
33720 } else {
33721 emit_opcode(cbuf, Assembler::REX_WB);
33722 }
33723
33724#line 33724 "ad_x86.cpp"
33725 }
33726 {
33727
33728#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33729
33730 emit_opcode(cbuf, (0xD3 /*primary()*/));
33731
33732#line 33732 "ad_x86.cpp"
33733 }
33734 {
33735
33736#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33737
33738 // INC, DEC, IDIV, IMOD, JMP indirect, ...
33739 emit_rm(cbuf, 0x3, (0x1 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33740
33741#line 33741 "ad_x86.cpp"
33742 }
33743}
33744
33745void andI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33746 cbuf.set_insts_mark();
33747 // Start at oper_input_base() and count operands
33748 unsigned idx0 = 1;
33749 unsigned idx1 = 1; // dst
33750 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
33751 {
33752
33753#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33754
33755 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33756 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
33757 emit_opcode(cbuf, Assembler::REX_B);
33758 }
33759 } else {
33760 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
33761 emit_opcode(cbuf, Assembler::REX_R);
33762 } else {
33763 emit_opcode(cbuf, Assembler::REX_RB);
33764 }
33765 }
33766
33767#line 33767 "ad_x86.cpp"
33768 }
33769 {
33770
33771#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33772
33773 emit_opcode(cbuf, (0x23 /*primary()*/));
33774
33775#line 33775 "ad_x86.cpp"
33776 }
33777 {
33778
33779#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33780
33781 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
33782
33783#line 33783 "ad_x86.cpp"
33784 }
33785}
33786
33787void andI_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33788 cbuf.set_insts_mark();
33789 // Start at oper_input_base() and count operands
33790 unsigned idx0 = 1;
33791 unsigned idx1 = 1; // dst
33792 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
33793 {
33794
33795#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33796
33797 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33798 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 4) {
33799 emit_opcode(cbuf, opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8 ? Assembler::REX : Assembler::REX_B);
33800 }
33801 } else {
33802 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33803 emit_opcode(cbuf, Assembler::REX_R);
33804 } else {
33805 emit_opcode(cbuf, Assembler::REX_RB);
33806 }
33807 }
33808
33809#line 33809 "ad_x86.cpp"
33810 }
33811 {
33812
33813#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33814
33815 emit_opcode(cbuf, (0x0F /*primary()*/));
33816
33817#line 33817 "ad_x86.cpp"
33818 }
33819 {
33820
33821#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33822
33823 emit_opcode(cbuf, (0xB6 /*secondary()*/));
33824
33825#line 33825 "ad_x86.cpp"
33826 }
33827 {
33828
33829#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33830
33831 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33832
33833#line 33833 "ad_x86.cpp"
33834 }
33835}
33836
33837void andI2L_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33838 cbuf.set_insts_mark();
33839 // Start at oper_input_base() and count operands
33840 unsigned idx0 = 1;
33841 unsigned idx1 = 1; // src
33842 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
33843 {
33844
33845#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33846
33847 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
33848 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 4) {
33849 emit_opcode(cbuf, opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8 ? Assembler::REX : Assembler::REX_B);
33850 }
33851 } else {
33852 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
33853 emit_opcode(cbuf, Assembler::REX_R);
33854 } else {
33855 emit_opcode(cbuf, Assembler::REX_RB);
33856 }
33857 }
33858
33859#line 33859 "ad_x86.cpp"
33860 }
33861 {
33862
33863#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33864
33865 emit_opcode(cbuf, (0x0F /*primary()*/));
33866
33867#line 33867 "ad_x86.cpp"
33868 }
33869 {
33870
33871#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33872
33873 emit_opcode(cbuf, (0xB6 /*secondary()*/));
33874
33875#line 33875 "ad_x86.cpp"
33876 }
33877 {
33878
33879#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33880
33881 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
33882
33883#line 33883 "ad_x86.cpp"
33884 }
33885}
33886
33887void andI_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33888 cbuf.set_insts_mark();
33889 // Start at oper_input_base() and count operands
33890 unsigned idx0 = 1;
33891 unsigned idx1 = 1; // dst
33892 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
33893 {
33894
33895#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33896
33897 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33898 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ >= 8) {
33899 emit_opcode(cbuf, Assembler::REX_B);
33900 }
33901 } else {
33902 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
33903 emit_opcode(cbuf, Assembler::REX_R);
33904 } else {
33905 emit_opcode(cbuf, Assembler::REX_RB);
33906 }
33907 }
33908
33909#line 33909 "ad_x86.cpp"
33910 }
33911 {
33912
33913#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33914
33915 emit_opcode(cbuf, (0x0F /*primary()*/));
33916
33917#line 33917 "ad_x86.cpp"
33918 }
33919 {
33920
33921#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33922
33923 emit_opcode(cbuf, (0xB7 /*secondary()*/));
33924
33925#line 33925 "ad_x86.cpp"
33926 }
33927 {
33928
33929#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33930
33931 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
33932
33933#line 33933 "ad_x86.cpp"
33934 }
33935}
33936
33937void andI2L_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33938 cbuf.set_insts_mark();
33939 // Start at oper_input_base() and count operands
33940 unsigned idx0 = 1;
33941 unsigned idx1 = 1; // src
33942 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
33943 {
33944
33945#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33946
33947 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
33948 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
33949 emit_opcode(cbuf, Assembler::REX_B);
33950 }
33951 } else {
33952 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
33953 emit_opcode(cbuf, Assembler::REX_R);
33954 } else {
33955 emit_opcode(cbuf, Assembler::REX_RB);
33956 }
33957 }
33958
33959#line 33959 "ad_x86.cpp"
33960 }
33961 {
33962
33963#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33964
33965 emit_opcode(cbuf, (0x0F /*primary()*/));
33966
33967#line 33967 "ad_x86.cpp"
33968 }
33969 {
33970
33971#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33972
33973 emit_opcode(cbuf, (0xB7 /*secondary()*/));
33974
33975#line 33975 "ad_x86.cpp"
33976 }
33977 {
33978
33979#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33980
33981 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
33982
33983#line 33983 "ad_x86.cpp"
33984 }
33985}
33986
33987void andI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33988 cbuf.set_insts_mark();
33989 // Start at oper_input_base() and count operands
33990 unsigned idx0 = 1;
33991 unsigned idx1 = 1; // dst
33992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
33993 {
33994
33995#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
33996
33997 // OpcSEr/m
33998 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
33999 if (dstenc >= 8) {
34000 emit_opcode(cbuf, Assembler::REX_B);
34001 dstenc -= 8;
34002 }
34003 // Emit primary opcode and set sign-extend bit
34004 // Check for 8-bit immediate, and set sign extend bit in opcode
34005 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34006 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
34007 } else {
34008 // 32-bit immediate
34009 emit_opcode(cbuf, (0x81 /*primary()*/));
34010 }
34011 // Emit r/m byte with secondary opcode, after primary opcode.
34012 emit_rm(cbuf, 0x3, (0x04 /*secondary()*/), dstenc);
34013
34014#line 34014 "ad_x86.cpp"
34015 }
34016 {
34017
34018#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34019
34020 // Check for 8-bit immediate, and set sign extend bit in opcode
34021 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34022 emit_d8(cbuf, opnd_array(2)->constant());
34023 } else {
34024 // 32-bit immediate
34025 emit_d32(cbuf, opnd_array(2)->constant());
34026 }
34027
34028#line 34028 "ad_x86.cpp"
34029 }
34030}
34031
34032void andI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34033 cbuf.set_insts_mark();
34034 // Start at oper_input_base() and count operands
34035 unsigned idx0 = 2;
34036 unsigned idx1 = 2; // dst
34037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34038 {
34039
34040#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34041
34042 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
34043 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
34044 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
34045 emit_opcode(cbuf, Assembler::REX_X);
34046 }
34047 } else {
34048 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34049 emit_opcode(cbuf, Assembler::REX_B);
34050 } else {
34051 emit_opcode(cbuf, Assembler::REX_XB);
34052 }
34053 }
34054 } else {
34055 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
34056 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34057 emit_opcode(cbuf, Assembler::REX_R);
34058 } else {
34059 emit_opcode(cbuf, Assembler::REX_RX);
34060 }
34061 } else {
34062 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34063 emit_opcode(cbuf, Assembler::REX_RB);
34064 } else {
34065 emit_opcode(cbuf, Assembler::REX_RXB);
34066 }
34067 }
34068 }
34069
34070#line 34070 "ad_x86.cpp"
34071 }
34072 {
34073
34074#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34075
34076 emit_opcode(cbuf, (0x23 /*primary()*/));
34077
34078#line 34078 "ad_x86.cpp"
34079 }
34080 {
34081
34082#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34083
34084 // High registers handle in encode_RegMem
34085 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
34086 int base = opnd_array(2)->base(ra_,this,idx2);
34087 int index = opnd_array(2)->index(ra_,this,idx2);
34088 int scale = opnd_array(2)->scale();
34089 int disp = opnd_array(2)->disp(ra_,this,idx2);
34090 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
34091
34092 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34093
34094#line 34094 "ad_x86.cpp"
34095 }
34096}
34097
34098void andI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34099 cbuf.set_insts_mark();
34100 // Start at oper_input_base() and count operands
34101 unsigned idx0 = 2;
34102 unsigned idx1 = 2; // src
34103 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
34104 {
34105
34106#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34107
34108 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
34109 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34110 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34111 emit_opcode(cbuf, Assembler::REX_X);
34112 }
34113 } else {
34114 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34115 emit_opcode(cbuf, Assembler::REX_B);
34116 } else {
34117 emit_opcode(cbuf, Assembler::REX_XB);
34118 }
34119 }
34120 } else {
34121 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34122 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34123 emit_opcode(cbuf, Assembler::REX_R);
34124 } else {
34125 emit_opcode(cbuf, Assembler::REX_RX);
34126 }
34127 } else {
34128 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34129 emit_opcode(cbuf, Assembler::REX_RB);
34130 } else {
34131 emit_opcode(cbuf, Assembler::REX_RXB);
34132 }
34133 }
34134 }
34135
34136#line 34136 "ad_x86.cpp"
34137 }
34138 {
34139
34140#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34141
34142 emit_opcode(cbuf, (0x23 /*primary()*/));
34143
34144#line 34144 "ad_x86.cpp"
34145 }
34146 {
34147
34148#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34149
34150 // High registers handle in encode_RegMem
34151 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
34152 int base = opnd_array(1)->base(ra_,this,idx1);
34153 int index = opnd_array(1)->index(ra_,this,idx1);
34154 int scale = opnd_array(1)->scale();
34155 int disp = opnd_array(1)->disp(ra_,this,idx1);
34156 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34157
34158 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34159
34160#line 34160 "ad_x86.cpp"
34161 }
34162}
34163
34164void andB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34165 cbuf.set_insts_mark();
34166 // Start at oper_input_base() and count operands
34167 unsigned idx0 = 2;
34168 unsigned idx1 = 2; // dst
34169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34170 {
34171
34172#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34173
34174 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
34175 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34176 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34177 emit_opcode(cbuf, Assembler::REX_X);
34178 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
34179 emit_opcode(cbuf, Assembler::REX);
34180 }
34181 } else {
34182 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34183 emit_opcode(cbuf, Assembler::REX_B);
34184 } else {
34185 emit_opcode(cbuf, Assembler::REX_XB);
34186 }
34187 }
34188 } else {
34189 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34190 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34191 emit_opcode(cbuf, Assembler::REX_R);
34192 } else {
34193 emit_opcode(cbuf, Assembler::REX_RX);
34194 }
34195 } else {
34196 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34197 emit_opcode(cbuf, Assembler::REX_RB);
34198 } else {
34199 emit_opcode(cbuf, Assembler::REX_RXB);
34200 }
34201 }
34202 }
34203
34204#line 34204 "ad_x86.cpp"
34205 }
34206 {
34207
34208#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34209
34210 emit_opcode(cbuf, (0x20 /*primary()*/));
34211
34212#line 34212 "ad_x86.cpp"
34213 }
34214 {
34215
34216#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34217
34218 // High registers handle in encode_RegMem
34219 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
34220 int base = opnd_array(1)->base(ra_,this,idx1);
34221 int index = opnd_array(1)->index(ra_,this,idx1);
34222 int scale = opnd_array(1)->scale();
34223 int disp = opnd_array(1)->disp(ra_,this,idx1);
34224 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34225
34226 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34227
34228#line 34228 "ad_x86.cpp"
34229 }
34230}
34231
34232void andB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34233 cbuf.set_insts_mark();
34234 // Start at oper_input_base() and count operands
34235 unsigned idx0 = 2;
34236 unsigned idx1 = 2; // dst
34237 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34238 {
34239
34240#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34241
34242 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
34243 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34244 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34245 emit_opcode(cbuf, Assembler::REX_X);
34246 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
34247 emit_opcode(cbuf, Assembler::REX);
34248 }
34249 } else {
34250 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34251 emit_opcode(cbuf, Assembler::REX_B);
34252 } else {
34253 emit_opcode(cbuf, Assembler::REX_XB);
34254 }
34255 }
34256 } else {
34257 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34258 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34259 emit_opcode(cbuf, Assembler::REX_R);
34260 } else {
34261 emit_opcode(cbuf, Assembler::REX_RX);
34262 }
34263 } else {
34264 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34265 emit_opcode(cbuf, Assembler::REX_RB);
34266 } else {
34267 emit_opcode(cbuf, Assembler::REX_RXB);
34268 }
34269 }
34270 }
34271
34272#line 34272 "ad_x86.cpp"
34273 }
34274 {
34275
34276#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34277
34278 emit_opcode(cbuf, (0x20 /*primary()*/));
34279
34280#line 34280 "ad_x86.cpp"
34281 }
34282 {
34283
34284#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34285
34286 // High registers handle in encode_RegMem
34287 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
34288 int base = opnd_array(1)->base(ra_,this,idx1);
34289 int index = opnd_array(1)->index(ra_,this,idx1);
34290 int scale = opnd_array(1)->scale();
34291 int disp = opnd_array(1)->disp(ra_,this,idx1);
34292 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34293
34294 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34295
34296#line 34296 "ad_x86.cpp"
34297 }
34298}
34299
34300void andI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34301 cbuf.set_insts_mark();
34302 // Start at oper_input_base() and count operands
34303 unsigned idx0 = 2;
34304 unsigned idx1 = 2; // dst
34305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34306 {
34307
34308#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34309
34310 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
34311 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34312 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34313 emit_opcode(cbuf, Assembler::REX_X);
34314 }
34315 } else {
34316 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34317 emit_opcode(cbuf, Assembler::REX_B);
34318 } else {
34319 emit_opcode(cbuf, Assembler::REX_XB);
34320 }
34321 }
34322 } else {
34323 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34324 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34325 emit_opcode(cbuf, Assembler::REX_R);
34326 } else {
34327 emit_opcode(cbuf, Assembler::REX_RX);
34328 }
34329 } else {
34330 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34331 emit_opcode(cbuf, Assembler::REX_RB);
34332 } else {
34333 emit_opcode(cbuf, Assembler::REX_RXB);
34334 }
34335 }
34336 }
34337
34338#line 34338 "ad_x86.cpp"
34339 }
34340 {
34341
34342#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34343
34344 emit_opcode(cbuf, (0x21 /*primary()*/));
34345
34346#line 34346 "ad_x86.cpp"
34347 }
34348 {
34349
34350#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34351
34352 // High registers handle in encode_RegMem
34353 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
34354 int base = opnd_array(1)->base(ra_,this,idx1);
34355 int index = opnd_array(1)->index(ra_,this,idx1);
34356 int scale = opnd_array(1)->scale();
34357 int disp = opnd_array(1)->disp(ra_,this,idx1);
34358 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34359
34360 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34361
34362#line 34362 "ad_x86.cpp"
34363 }
34364}
34365
34366void andI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34367 cbuf.set_insts_mark();
34368 // Start at oper_input_base() and count operands
34369 unsigned idx0 = 2;
34370 unsigned idx1 = 2; // dst
34371 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34372 {
34373
34374#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34375
34376 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
34377 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34378 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34379 emit_opcode(cbuf, Assembler::REX_X);
34380 }
34381 } else {
34382 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34383 emit_opcode(cbuf, Assembler::REX_B);
34384 } else {
34385 emit_opcode(cbuf, Assembler::REX_XB);
34386 }
34387 }
34388 } else {
34389 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34390 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34391 emit_opcode(cbuf, Assembler::REX_R);
34392 } else {
34393 emit_opcode(cbuf, Assembler::REX_RX);
34394 }
34395 } else {
34396 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34397 emit_opcode(cbuf, Assembler::REX_RB);
34398 } else {
34399 emit_opcode(cbuf, Assembler::REX_RXB);
34400 }
34401 }
34402 }
34403
34404#line 34404 "ad_x86.cpp"
34405 }
34406 {
34407
34408#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34409
34410 emit_opcode(cbuf, (0x21 /*primary()*/));
34411
34412#line 34412 "ad_x86.cpp"
34413 }
34414 {
34415
34416#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34417
34418 // High registers handle in encode_RegMem
34419 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
34420 int base = opnd_array(1)->base(ra_,this,idx1);
34421 int index = opnd_array(1)->index(ra_,this,idx1);
34422 int scale = opnd_array(1)->scale();
34423 int disp = opnd_array(1)->disp(ra_,this,idx1);
34424 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34425
34426 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34427
34428#line 34428 "ad_x86.cpp"
34429 }
34430}
34431
34432void andI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34433 cbuf.set_insts_mark();
34434 // Start at oper_input_base() and count operands
34435 unsigned idx0 = 2;
34436 unsigned idx1 = 2; // dst
34437 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34438 {
34439
34440#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34441
34442 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
34443 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34444 emit_opcode(cbuf, Assembler::REX_B);
34445 } else {
34446 emit_opcode(cbuf, Assembler::REX_XB);
34447 }
34448 } else {
34449 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34450 emit_opcode(cbuf, Assembler::REX_X);
34451 }
34452 }
34453
34454#line 34454 "ad_x86.cpp"
34455 }
34456 {
34457
34458#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34459
34460 // Emit primary opcode and set sign-extend bit
34461 // Check for 8-bit immediate, and set sign extend bit in opcode
34462 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34463 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
34464 } else {
34465 // 32-bit immediate
34466 emit_opcode(cbuf, (0x81 /*primary()*/));
34467 }
34468
34469#line 34469 "ad_x86.cpp"
34470 }
34471 {
34472
34473#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34474
34475 int rm_byte_opcode = (0x4 /*secondary()*/);
34476
34477 // High registers handle in encode_RegMem
34478 int base = opnd_array(1)->base(ra_,this,idx1);
34479 int index = opnd_array(1)->index(ra_,this,idx1);
34480 int scale = opnd_array(1)->scale();
34481 int displace = opnd_array(1)->disp(ra_,this,idx1);
34482
34483 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
34484 // working with static
34485 // globals
34486 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
34487 disp_reloc);
34488
34489#line 34489 "ad_x86.cpp"
34490 }
34491 {
34492
34493#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34494
34495 // Check for 8-bit immediate, and set sign extend bit in opcode
34496 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34497 emit_d8(cbuf, opnd_array(2)->constant());
34498 } else {
34499 // 32-bit immediate
34500 emit_d32(cbuf, opnd_array(2)->constant());
34501 }
34502
34503#line 34503 "ad_x86.cpp"
34504 }
34505}
34506
34507void andnI_rReg_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34508 cbuf.set_insts_mark();
34509 // Start at oper_input_base() and count operands
34510 unsigned idx0 = 2;
34511 unsigned idx1 = 2; // src1
34512 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34513 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
34514 {
34515 MacroAssembler _masm(&cbuf);
34516
34517#line 9621 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34518
34519 __ andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()));
34520
34521#line 34521 "ad_x86.cpp"
34522 }
34523}
34524
34525void andnI_rReg_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34526 cbuf.set_insts_mark();
34527 // Start at oper_input_base() and count operands
34528 unsigned idx0 = 2;
34529 unsigned idx1 = 2; // src2
34530 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
34531 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
34532 {
34533 MacroAssembler _masm(&cbuf);
34534
34535#line 9621 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34536
34537 __ andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34538
34539#line 34539 "ad_x86.cpp"
34540 }
34541}
34542
34543void andnI_rReg_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34544 cbuf.set_insts_mark();
34545 // Start at oper_input_base() and count operands
34546 unsigned idx0 = 1;
34547 unsigned idx1 = 1; // src1
34548 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34549 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
34550 {
34551 MacroAssembler _masm(&cbuf);
34552
34553#line 9634 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34554
34555 __ andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* src2 */);
34556
34557#line 34557 "ad_x86.cpp"
34558 }
34559}
34560
34561void andnI_rReg_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34562 cbuf.set_insts_mark();
34563 // Start at oper_input_base() and count operands
34564 unsigned idx0 = 1;
34565 unsigned idx1 = 1; // src2
34566 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
34567 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
34568 {
34569 MacroAssembler _masm(&cbuf);
34570
34571#line 9634 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34572
34573 __ andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src2 */);
34574
34575#line 34575 "ad_x86.cpp"
34576 }
34577}
34578
34579void blsiI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34580 cbuf.set_insts_mark();
34581 // Start at oper_input_base() and count operands
34582 unsigned idx0 = 1;
34583 unsigned idx1 = 1; // imm_zero
34584 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34585 {
34586 MacroAssembler _masm(&cbuf);
34587
34588#line 9647 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34589
34590 __ blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
34591
34592#line 34592 "ad_x86.cpp"
34593 }
34594}
34595
34596void blsiI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34597 cbuf.set_insts_mark();
34598 // Start at oper_input_base() and count operands
34599 unsigned idx0 = 1;
34600 unsigned idx1 = 1; // src
34601 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
34602 {
34603 MacroAssembler _masm(&cbuf);
34604
34605#line 9647 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34606
34607 __ blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
34608
34609#line 34609 "ad_x86.cpp"
34610 }
34611}
34612
34613void blsiI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34614 cbuf.set_insts_mark();
34615 // Start at oper_input_base() and count operands
34616 unsigned idx0 = 2;
34617 unsigned idx1 = 2; // imm_zero
34618 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34619 {
34620 MacroAssembler _masm(&cbuf);
34621
34622#line 9661 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34623
34624 __ blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
34625
34626#line 34626 "ad_x86.cpp"
34627 }
34628}
34629
34630void blsiI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34631 cbuf.set_insts_mark();
34632 // Start at oper_input_base() and count operands
34633 unsigned idx0 = 2;
34634 unsigned idx1 = 2; // src
34635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
34636 {
34637 MacroAssembler _masm(&cbuf);
34638
34639#line 9661 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34640
34641 __ blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34642
34643#line 34643 "ad_x86.cpp"
34644 }
34645}
34646
34647void blsmskI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34648 cbuf.set_insts_mark();
34649 // Start at oper_input_base() and count operands
34650 unsigned idx0 = 2;
34651 unsigned idx1 = 2; // src
34652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34653 {
34654 MacroAssembler _masm(&cbuf);
34655
34656#line 9676 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34657
34658 __ blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34659
34660#line 34660 "ad_x86.cpp"
34661 }
34662}
34663
34664void blsmskI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34665 cbuf.set_insts_mark();
34666 // Start at oper_input_base() and count operands
34667 unsigned idx0 = 2;
34668 unsigned idx1 = 2; // src
34669 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34670 {
34671 MacroAssembler _masm(&cbuf);
34672
34673#line 9676 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34674
34675 __ blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34676
34677#line 34677 "ad_x86.cpp"
34678 }
34679}
34680
34681void blsmskI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34682 cbuf.set_insts_mark();
34683 // Start at oper_input_base() and count operands
34684 unsigned idx0 = 1;
34685 unsigned idx1 = 1; // src
34686 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34687 {
34688 MacroAssembler _masm(&cbuf);
34689
34690#line 9690 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34691
34692 __ blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
34693
34694#line 34694 "ad_x86.cpp"
34695 }
34696}
34697
34698void blsmskI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34699 cbuf.set_insts_mark();
34700 // Start at oper_input_base() and count operands
34701 unsigned idx0 = 1;
34702 unsigned idx1 = 1; // src
34703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34704 {
34705 MacroAssembler _masm(&cbuf);
34706
34707#line 9690 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34708
34709 __ blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
34710
34711#line 34711 "ad_x86.cpp"
34712 }
34713}
34714
34715void blsrI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34716 cbuf.set_insts_mark();
34717 // Start at oper_input_base() and count operands
34718 unsigned idx0 = 1;
34719 unsigned idx1 = 1; // src
34720 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34721 {
34722 MacroAssembler _masm(&cbuf);
34723
34724#line 9705 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34725
34726 __ blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
34727
34728#line 34728 "ad_x86.cpp"
34729 }
34730}
34731
34732void blsrI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34733 cbuf.set_insts_mark();
34734 // Start at oper_input_base() and count operands
34735 unsigned idx0 = 1;
34736 unsigned idx1 = 1; // src
34737 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34738 {
34739 MacroAssembler _masm(&cbuf);
34740
34741#line 9705 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34742
34743 __ blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
34744
34745#line 34745 "ad_x86.cpp"
34746 }
34747}
34748
34749void blsrI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34750 cbuf.set_insts_mark();
34751 // Start at oper_input_base() and count operands
34752 unsigned idx0 = 2;
34753 unsigned idx1 = 2; // src
34754 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34755 {
34756 MacroAssembler _masm(&cbuf);
34757
34758#line 9721 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34759
34760 __ blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34761
34762#line 34762 "ad_x86.cpp"
34763 }
34764}
34765
34766void blsrI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34767 cbuf.set_insts_mark();
34768 // Start at oper_input_base() and count operands
34769 unsigned idx0 = 2;
34770 unsigned idx1 = 2; // src
34771 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
34772 {
34773 MacroAssembler _masm(&cbuf);
34774
34775#line 9721 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34776
34777 __ blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
34778
34779#line 34779 "ad_x86.cpp"
34780 }
34781}
34782
34783void orI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34784 cbuf.set_insts_mark();
34785 // Start at oper_input_base() and count operands
34786 unsigned idx0 = 1;
34787 unsigned idx1 = 1; // dst
34788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34789 {
34790
34791#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34792
34793 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
34794 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
34795 emit_opcode(cbuf, Assembler::REX_B);
34796 }
34797 } else {
34798 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
34799 emit_opcode(cbuf, Assembler::REX_R);
34800 } else {
34801 emit_opcode(cbuf, Assembler::REX_RB);
34802 }
34803 }
34804
34805#line 34805 "ad_x86.cpp"
34806 }
34807 {
34808
34809#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34810
34811 emit_opcode(cbuf, (0x0B /*primary()*/));
34812
34813#line 34813 "ad_x86.cpp"
34814 }
34815 {
34816
34817#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34818
34819 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
34820
34821#line 34821 "ad_x86.cpp"
34822 }
34823}
34824
34825void orI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34826 cbuf.set_insts_mark();
34827 // Start at oper_input_base() and count operands
34828 unsigned idx0 = 1;
34829 unsigned idx1 = 1; // dst
34830 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34831 {
34832
34833#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34834
34835 // OpcSEr/m
34836 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
34837 if (dstenc >= 8) {
34838 emit_opcode(cbuf, Assembler::REX_B);
34839 dstenc -= 8;
34840 }
34841 // Emit primary opcode and set sign-extend bit
34842 // Check for 8-bit immediate, and set sign extend bit in opcode
34843 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34844 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
34845 } else {
34846 // 32-bit immediate
34847 emit_opcode(cbuf, (0x81 /*primary()*/));
34848 }
34849 // Emit r/m byte with secondary opcode, after primary opcode.
34850 emit_rm(cbuf, 0x3, (0x01 /*secondary()*/), dstenc);
34851
34852#line 34852 "ad_x86.cpp"
34853 }
34854 {
34855
34856#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34857
34858 // Check for 8-bit immediate, and set sign extend bit in opcode
34859 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
34860 emit_d8(cbuf, opnd_array(2)->constant());
34861 } else {
34862 // 32-bit immediate
34863 emit_d32(cbuf, opnd_array(2)->constant());
34864 }
34865
34866#line 34866 "ad_x86.cpp"
34867 }
34868}
34869
34870void orI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34871 cbuf.set_insts_mark();
34872 // Start at oper_input_base() and count operands
34873 unsigned idx0 = 2;
34874 unsigned idx1 = 2; // dst
34875 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34876 {
34877
34878#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34879
34880 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
34881 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
34882 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
34883 emit_opcode(cbuf, Assembler::REX_X);
34884 }
34885 } else {
34886 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34887 emit_opcode(cbuf, Assembler::REX_B);
34888 } else {
34889 emit_opcode(cbuf, Assembler::REX_XB);
34890 }
34891 }
34892 } else {
34893 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
34894 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34895 emit_opcode(cbuf, Assembler::REX_R);
34896 } else {
34897 emit_opcode(cbuf, Assembler::REX_RX);
34898 }
34899 } else {
34900 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
34901 emit_opcode(cbuf, Assembler::REX_RB);
34902 } else {
34903 emit_opcode(cbuf, Assembler::REX_RXB);
34904 }
34905 }
34906 }
34907
34908#line 34908 "ad_x86.cpp"
34909 }
34910 {
34911
34912#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34913
34914 emit_opcode(cbuf, (0x0B /*primary()*/));
34915
34916#line 34916 "ad_x86.cpp"
34917 }
34918 {
34919
34920#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34921
34922 // High registers handle in encode_RegMem
34923 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
34924 int base = opnd_array(2)->base(ra_,this,idx2);
34925 int index = opnd_array(2)->index(ra_,this,idx2);
34926 int scale = opnd_array(2)->scale();
34927 int disp = opnd_array(2)->disp(ra_,this,idx2);
34928 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
34929
34930 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34931
34932#line 34932 "ad_x86.cpp"
34933 }
34934}
34935
34936void orI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34937 cbuf.set_insts_mark();
34938 // Start at oper_input_base() and count operands
34939 unsigned idx0 = 2;
34940 unsigned idx1 = 2; // src
34941 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
34942 {
34943
34944#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34945
34946 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
34947 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34948 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
34949 emit_opcode(cbuf, Assembler::REX_X);
34950 }
34951 } else {
34952 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34953 emit_opcode(cbuf, Assembler::REX_B);
34954 } else {
34955 emit_opcode(cbuf, Assembler::REX_XB);
34956 }
34957 }
34958 } else {
34959 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
34960 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34961 emit_opcode(cbuf, Assembler::REX_R);
34962 } else {
34963 emit_opcode(cbuf, Assembler::REX_RX);
34964 }
34965 } else {
34966 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
34967 emit_opcode(cbuf, Assembler::REX_RB);
34968 } else {
34969 emit_opcode(cbuf, Assembler::REX_RXB);
34970 }
34971 }
34972 }
34973
34974#line 34974 "ad_x86.cpp"
34975 }
34976 {
34977
34978#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34979
34980 emit_opcode(cbuf, (0x0B /*primary()*/));
34981
34982#line 34982 "ad_x86.cpp"
34983 }
34984 {
34985
34986#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
34987
34988 // High registers handle in encode_RegMem
34989 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
34990 int base = opnd_array(1)->base(ra_,this,idx1);
34991 int index = opnd_array(1)->index(ra_,this,idx1);
34992 int scale = opnd_array(1)->scale();
34993 int disp = opnd_array(1)->disp(ra_,this,idx1);
34994 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
34995
34996 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
34997
34998#line 34998 "ad_x86.cpp"
34999 }
35000}
35001
35002void orB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35003 cbuf.set_insts_mark();
35004 // Start at oper_input_base() and count operands
35005 unsigned idx0 = 2;
35006 unsigned idx1 = 2; // dst
35007 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35008 {
35009
35010#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35011
35012 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35013 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35014 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35015 emit_opcode(cbuf, Assembler::REX_X);
35016 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
35017 emit_opcode(cbuf, Assembler::REX);
35018 }
35019 } else {
35020 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35021 emit_opcode(cbuf, Assembler::REX_B);
35022 } else {
35023 emit_opcode(cbuf, Assembler::REX_XB);
35024 }
35025 }
35026 } else {
35027 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35028 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35029 emit_opcode(cbuf, Assembler::REX_R);
35030 } else {
35031 emit_opcode(cbuf, Assembler::REX_RX);
35032 }
35033 } else {
35034 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35035 emit_opcode(cbuf, Assembler::REX_RB);
35036 } else {
35037 emit_opcode(cbuf, Assembler::REX_RXB);
35038 }
35039 }
35040 }
35041
35042#line 35042 "ad_x86.cpp"
35043 }
35044 {
35045
35046#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35047
35048 emit_opcode(cbuf, (0x08 /*primary()*/));
35049
35050#line 35050 "ad_x86.cpp"
35051 }
35052 {
35053
35054#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35055
35056 // High registers handle in encode_RegMem
35057 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35058 int base = opnd_array(1)->base(ra_,this,idx1);
35059 int index = opnd_array(1)->index(ra_,this,idx1);
35060 int scale = opnd_array(1)->scale();
35061 int disp = opnd_array(1)->disp(ra_,this,idx1);
35062 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35063
35064 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35065
35066#line 35066 "ad_x86.cpp"
35067 }
35068}
35069
35070void orB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35071 cbuf.set_insts_mark();
35072 // Start at oper_input_base() and count operands
35073 unsigned idx0 = 2;
35074 unsigned idx1 = 2; // dst
35075 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35076 {
35077
35078#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35079
35080 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35081 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35082 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35083 emit_opcode(cbuf, Assembler::REX_X);
35084 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
35085 emit_opcode(cbuf, Assembler::REX);
35086 }
35087 } else {
35088 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35089 emit_opcode(cbuf, Assembler::REX_B);
35090 } else {
35091 emit_opcode(cbuf, Assembler::REX_XB);
35092 }
35093 }
35094 } else {
35095 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35096 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35097 emit_opcode(cbuf, Assembler::REX_R);
35098 } else {
35099 emit_opcode(cbuf, Assembler::REX_RX);
35100 }
35101 } else {
35102 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35103 emit_opcode(cbuf, Assembler::REX_RB);
35104 } else {
35105 emit_opcode(cbuf, Assembler::REX_RXB);
35106 }
35107 }
35108 }
35109
35110#line 35110 "ad_x86.cpp"
35111 }
35112 {
35113
35114#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35115
35116 emit_opcode(cbuf, (0x08 /*primary()*/));
35117
35118#line 35118 "ad_x86.cpp"
35119 }
35120 {
35121
35122#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35123
35124 // High registers handle in encode_RegMem
35125 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35126 int base = opnd_array(1)->base(ra_,this,idx1);
35127 int index = opnd_array(1)->index(ra_,this,idx1);
35128 int scale = opnd_array(1)->scale();
35129 int disp = opnd_array(1)->disp(ra_,this,idx1);
35130 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35131
35132 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35133
35134#line 35134 "ad_x86.cpp"
35135 }
35136}
35137
35138void orI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35139 cbuf.set_insts_mark();
35140 // Start at oper_input_base() and count operands
35141 unsigned idx0 = 2;
35142 unsigned idx1 = 2; // dst
35143 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35144 {
35145
35146#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35147
35148 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35149 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35150 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35151 emit_opcode(cbuf, Assembler::REX_X);
35152 }
35153 } else {
35154 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35155 emit_opcode(cbuf, Assembler::REX_B);
35156 } else {
35157 emit_opcode(cbuf, Assembler::REX_XB);
35158 }
35159 }
35160 } else {
35161 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35162 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35163 emit_opcode(cbuf, Assembler::REX_R);
35164 } else {
35165 emit_opcode(cbuf, Assembler::REX_RX);
35166 }
35167 } else {
35168 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35169 emit_opcode(cbuf, Assembler::REX_RB);
35170 } else {
35171 emit_opcode(cbuf, Assembler::REX_RXB);
35172 }
35173 }
35174 }
35175
35176#line 35176 "ad_x86.cpp"
35177 }
35178 {
35179
35180#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35181
35182 emit_opcode(cbuf, (0x09 /*primary()*/));
35183
35184#line 35184 "ad_x86.cpp"
35185 }
35186 {
35187
35188#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35189
35190 // High registers handle in encode_RegMem
35191 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35192 int base = opnd_array(1)->base(ra_,this,idx1);
35193 int index = opnd_array(1)->index(ra_,this,idx1);
35194 int scale = opnd_array(1)->scale();
35195 int disp = opnd_array(1)->disp(ra_,this,idx1);
35196 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35197
35198 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35199
35200#line 35200 "ad_x86.cpp"
35201 }
35202}
35203
35204void orI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35205 cbuf.set_insts_mark();
35206 // Start at oper_input_base() and count operands
35207 unsigned idx0 = 2;
35208 unsigned idx1 = 2; // dst
35209 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35210 {
35211
35212#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35213
35214 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35215 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35216 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35217 emit_opcode(cbuf, Assembler::REX_X);
35218 }
35219 } else {
35220 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35221 emit_opcode(cbuf, Assembler::REX_B);
35222 } else {
35223 emit_opcode(cbuf, Assembler::REX_XB);
35224 }
35225 }
35226 } else {
35227 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35228 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35229 emit_opcode(cbuf, Assembler::REX_R);
35230 } else {
35231 emit_opcode(cbuf, Assembler::REX_RX);
35232 }
35233 } else {
35234 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35235 emit_opcode(cbuf, Assembler::REX_RB);
35236 } else {
35237 emit_opcode(cbuf, Assembler::REX_RXB);
35238 }
35239 }
35240 }
35241
35242#line 35242 "ad_x86.cpp"
35243 }
35244 {
35245
35246#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35247
35248 emit_opcode(cbuf, (0x09 /*primary()*/));
35249
35250#line 35250 "ad_x86.cpp"
35251 }
35252 {
35253
35254#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35255
35256 // High registers handle in encode_RegMem
35257 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35258 int base = opnd_array(1)->base(ra_,this,idx1);
35259 int index = opnd_array(1)->index(ra_,this,idx1);
35260 int scale = opnd_array(1)->scale();
35261 int disp = opnd_array(1)->disp(ra_,this,idx1);
35262 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35263
35264 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35265
35266#line 35266 "ad_x86.cpp"
35267 }
35268}
35269
35270void orI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35271 cbuf.set_insts_mark();
35272 // Start at oper_input_base() and count operands
35273 unsigned idx0 = 2;
35274 unsigned idx1 = 2; // dst
35275 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35276 {
35277
35278#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35279
35280 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
35281 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35282 emit_opcode(cbuf, Assembler::REX_B);
35283 } else {
35284 emit_opcode(cbuf, Assembler::REX_XB);
35285 }
35286 } else {
35287 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35288 emit_opcode(cbuf, Assembler::REX_X);
35289 }
35290 }
35291
35292#line 35292 "ad_x86.cpp"
35293 }
35294 {
35295
35296#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35297
35298 // Emit primary opcode and set sign-extend bit
35299 // Check for 8-bit immediate, and set sign extend bit in opcode
35300 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35301 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
35302 } else {
35303 // 32-bit immediate
35304 emit_opcode(cbuf, (0x81 /*primary()*/));
35305 }
35306
35307#line 35307 "ad_x86.cpp"
35308 }
35309 {
35310
35311#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35312
35313 int rm_byte_opcode = (0x1 /*secondary()*/);
35314
35315 // High registers handle in encode_RegMem
35316 int base = opnd_array(1)->base(ra_,this,idx1);
35317 int index = opnd_array(1)->index(ra_,this,idx1);
35318 int scale = opnd_array(1)->scale();
35319 int displace = opnd_array(1)->disp(ra_,this,idx1);
35320
35321 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
35322 // working with static
35323 // globals
35324 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
35325 disp_reloc);
35326
35327#line 35327 "ad_x86.cpp"
35328 }
35329 {
35330
35331#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35332
35333 // Check for 8-bit immediate, and set sign extend bit in opcode
35334 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35335 emit_d8(cbuf, opnd_array(2)->constant());
35336 } else {
35337 // 32-bit immediate
35338 emit_d32(cbuf, opnd_array(2)->constant());
35339 }
35340
35341#line 35341 "ad_x86.cpp"
35342 }
35343}
35344
35345void xorI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35346 cbuf.set_insts_mark();
35347 // Start at oper_input_base() and count operands
35348 unsigned idx0 = 1;
35349 unsigned idx1 = 1; // dst
35350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35351 {
35352
35353#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35354
35355 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35356 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
35357 emit_opcode(cbuf, Assembler::REX_B);
35358 }
35359 } else {
35360 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35361 emit_opcode(cbuf, Assembler::REX_R);
35362 } else {
35363 emit_opcode(cbuf, Assembler::REX_RB);
35364 }
35365 }
35366
35367#line 35367 "ad_x86.cpp"
35368 }
35369 {
35370
35371#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35372
35373 emit_opcode(cbuf, (0x33 /*primary()*/));
35374
35375#line 35375 "ad_x86.cpp"
35376 }
35377 {
35378
35379#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35380
35381 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
35382
35383#line 35383 "ad_x86.cpp"
35384 }
35385}
35386
35387void xorI_rReg_im1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35388 cbuf.set_insts_mark();
35389 // Start at oper_input_base() and count operands
35390 unsigned idx0 = 1;
35391 unsigned idx1 = 1; // dst
35392 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
35393 {
35394 MacroAssembler _masm(&cbuf);
35395
35396#line 9823 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35397
35398 __ notl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
35399
35400#line 35400 "ad_x86.cpp"
35401 }
35402}
35403
35404void xorI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35405 cbuf.set_insts_mark();
35406 // Start at oper_input_base() and count operands
35407 unsigned idx0 = 1;
35408 unsigned idx1 = 1; // dst
35409 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35410 {
35411
35412#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35413
35414 // OpcSEr/m
35415 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
35416 if (dstenc >= 8) {
35417 emit_opcode(cbuf, Assembler::REX_B);
35418 dstenc -= 8;
35419 }
35420 // Emit primary opcode and set sign-extend bit
35421 // Check for 8-bit immediate, and set sign extend bit in opcode
35422 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35423 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
35424 } else {
35425 // 32-bit immediate
35426 emit_opcode(cbuf, (0x81 /*primary()*/));
35427 }
35428 // Emit r/m byte with secondary opcode, after primary opcode.
35429 emit_rm(cbuf, 0x3, (0x06 /*secondary()*/), dstenc);
35430
35431#line 35431 "ad_x86.cpp"
35432 }
35433 {
35434
35435#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35436
35437 // Check for 8-bit immediate, and set sign extend bit in opcode
35438 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35439 emit_d8(cbuf, opnd_array(2)->constant());
35440 } else {
35441 // 32-bit immediate
35442 emit_d32(cbuf, opnd_array(2)->constant());
35443 }
35444
35445#line 35445 "ad_x86.cpp"
35446 }
35447}
35448
35449void xorI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35450 cbuf.set_insts_mark();
35451 // Start at oper_input_base() and count operands
35452 unsigned idx0 = 2;
35453 unsigned idx1 = 2; // dst
35454 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35455 {
35456
35457#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35458
35459 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35460 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
35461 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
35462 emit_opcode(cbuf, Assembler::REX_X);
35463 }
35464 } else {
35465 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
35466 emit_opcode(cbuf, Assembler::REX_B);
35467 } else {
35468 emit_opcode(cbuf, Assembler::REX_XB);
35469 }
35470 }
35471 } else {
35472 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
35473 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
35474 emit_opcode(cbuf, Assembler::REX_R);
35475 } else {
35476 emit_opcode(cbuf, Assembler::REX_RX);
35477 }
35478 } else {
35479 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
35480 emit_opcode(cbuf, Assembler::REX_RB);
35481 } else {
35482 emit_opcode(cbuf, Assembler::REX_RXB);
35483 }
35484 }
35485 }
35486
35487#line 35487 "ad_x86.cpp"
35488 }
35489 {
35490
35491#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35492
35493 emit_opcode(cbuf, (0x33 /*primary()*/));
35494
35495#line 35495 "ad_x86.cpp"
35496 }
35497 {
35498
35499#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35500
35501 // High registers handle in encode_RegMem
35502 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
35503 int base = opnd_array(2)->base(ra_,this,idx2);
35504 int index = opnd_array(2)->index(ra_,this,idx2);
35505 int scale = opnd_array(2)->scale();
35506 int disp = opnd_array(2)->disp(ra_,this,idx2);
35507 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
35508
35509 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35510
35511#line 35511 "ad_x86.cpp"
35512 }
35513}
35514
35515void xorI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35516 cbuf.set_insts_mark();
35517 // Start at oper_input_base() and count operands
35518 unsigned idx0 = 2;
35519 unsigned idx1 = 2; // src
35520 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
35521 {
35522
35523#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35524
35525 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
35526 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35527 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35528 emit_opcode(cbuf, Assembler::REX_X);
35529 }
35530 } else {
35531 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35532 emit_opcode(cbuf, Assembler::REX_B);
35533 } else {
35534 emit_opcode(cbuf, Assembler::REX_XB);
35535 }
35536 }
35537 } else {
35538 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35539 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35540 emit_opcode(cbuf, Assembler::REX_R);
35541 } else {
35542 emit_opcode(cbuf, Assembler::REX_RX);
35543 }
35544 } else {
35545 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35546 emit_opcode(cbuf, Assembler::REX_RB);
35547 } else {
35548 emit_opcode(cbuf, Assembler::REX_RXB);
35549 }
35550 }
35551 }
35552
35553#line 35553 "ad_x86.cpp"
35554 }
35555 {
35556
35557#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35558
35559 emit_opcode(cbuf, (0x33 /*primary()*/));
35560
35561#line 35561 "ad_x86.cpp"
35562 }
35563 {
35564
35565#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35566
35567 // High registers handle in encode_RegMem
35568 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
35569 int base = opnd_array(1)->base(ra_,this,idx1);
35570 int index = opnd_array(1)->index(ra_,this,idx1);
35571 int scale = opnd_array(1)->scale();
35572 int disp = opnd_array(1)->disp(ra_,this,idx1);
35573 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35574
35575 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35576
35577#line 35577 "ad_x86.cpp"
35578 }
35579}
35580
35581void xorB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35582 cbuf.set_insts_mark();
35583 // Start at oper_input_base() and count operands
35584 unsigned idx0 = 2;
35585 unsigned idx1 = 2; // dst
35586 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35587 {
35588
35589#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35590
35591 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35592 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35593 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35594 emit_opcode(cbuf, Assembler::REX_X);
35595 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
35596 emit_opcode(cbuf, Assembler::REX);
35597 }
35598 } else {
35599 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35600 emit_opcode(cbuf, Assembler::REX_B);
35601 } else {
35602 emit_opcode(cbuf, Assembler::REX_XB);
35603 }
35604 }
35605 } else {
35606 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35607 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35608 emit_opcode(cbuf, Assembler::REX_R);
35609 } else {
35610 emit_opcode(cbuf, Assembler::REX_RX);
35611 }
35612 } else {
35613 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35614 emit_opcode(cbuf, Assembler::REX_RB);
35615 } else {
35616 emit_opcode(cbuf, Assembler::REX_RXB);
35617 }
35618 }
35619 }
35620
35621#line 35621 "ad_x86.cpp"
35622 }
35623 {
35624
35625#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35626
35627 emit_opcode(cbuf, (0x30 /*primary()*/));
35628
35629#line 35629 "ad_x86.cpp"
35630 }
35631 {
35632
35633#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35634
35635 // High registers handle in encode_RegMem
35636 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35637 int base = opnd_array(1)->base(ra_,this,idx1);
35638 int index = opnd_array(1)->index(ra_,this,idx1);
35639 int scale = opnd_array(1)->scale();
35640 int disp = opnd_array(1)->disp(ra_,this,idx1);
35641 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35642
35643 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35644
35645#line 35645 "ad_x86.cpp"
35646 }
35647}
35648
35649void xorB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35650 cbuf.set_insts_mark();
35651 // Start at oper_input_base() and count operands
35652 unsigned idx0 = 2;
35653 unsigned idx1 = 2; // dst
35654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35655 {
35656
35657#line 2393 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35658
35659 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35660 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35661 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35662 emit_opcode(cbuf, Assembler::REX_X);
35663 } else if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 4) {
35664 emit_opcode(cbuf, Assembler::REX);
35665 }
35666 } else {
35667 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35668 emit_opcode(cbuf, Assembler::REX_B);
35669 } else {
35670 emit_opcode(cbuf, Assembler::REX_XB);
35671 }
35672 }
35673 } else {
35674 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35675 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35676 emit_opcode(cbuf, Assembler::REX_R);
35677 } else {
35678 emit_opcode(cbuf, Assembler::REX_RX);
35679 }
35680 } else {
35681 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35682 emit_opcode(cbuf, Assembler::REX_RB);
35683 } else {
35684 emit_opcode(cbuf, Assembler::REX_RXB);
35685 }
35686 }
35687 }
35688
35689#line 35689 "ad_x86.cpp"
35690 }
35691 {
35692
35693#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35694
35695 emit_opcode(cbuf, (0x30 /*primary()*/));
35696
35697#line 35697 "ad_x86.cpp"
35698 }
35699 {
35700
35701#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35702
35703 // High registers handle in encode_RegMem
35704 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35705 int base = opnd_array(1)->base(ra_,this,idx1);
35706 int index = opnd_array(1)->index(ra_,this,idx1);
35707 int scale = opnd_array(1)->scale();
35708 int disp = opnd_array(1)->disp(ra_,this,idx1);
35709 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35710
35711 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35712
35713#line 35713 "ad_x86.cpp"
35714 }
35715}
35716
35717void xorI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35718 cbuf.set_insts_mark();
35719 // Start at oper_input_base() and count operands
35720 unsigned idx0 = 2;
35721 unsigned idx1 = 2; // dst
35722 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35723 {
35724
35725#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35726
35727 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35728 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35729 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35730 emit_opcode(cbuf, Assembler::REX_X);
35731 }
35732 } else {
35733 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35734 emit_opcode(cbuf, Assembler::REX_B);
35735 } else {
35736 emit_opcode(cbuf, Assembler::REX_XB);
35737 }
35738 }
35739 } else {
35740 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35741 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35742 emit_opcode(cbuf, Assembler::REX_R);
35743 } else {
35744 emit_opcode(cbuf, Assembler::REX_RX);
35745 }
35746 } else {
35747 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35748 emit_opcode(cbuf, Assembler::REX_RB);
35749 } else {
35750 emit_opcode(cbuf, Assembler::REX_RXB);
35751 }
35752 }
35753 }
35754
35755#line 35755 "ad_x86.cpp"
35756 }
35757 {
35758
35759#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35760
35761 emit_opcode(cbuf, (0x31 /*primary()*/));
35762
35763#line 35763 "ad_x86.cpp"
35764 }
35765 {
35766
35767#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35768
35769 // High registers handle in encode_RegMem
35770 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35771 int base = opnd_array(1)->base(ra_,this,idx1);
35772 int index = opnd_array(1)->index(ra_,this,idx1);
35773 int scale = opnd_array(1)->scale();
35774 int disp = opnd_array(1)->disp(ra_,this,idx1);
35775 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35776
35777 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35778
35779#line 35779 "ad_x86.cpp"
35780 }
35781}
35782
35783void xorI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35784 cbuf.set_insts_mark();
35785 // Start at oper_input_base() and count operands
35786 unsigned idx0 = 2;
35787 unsigned idx1 = 2; // dst
35788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35789 {
35790
35791#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35792
35793 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35794 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35795 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35796 emit_opcode(cbuf, Assembler::REX_X);
35797 }
35798 } else {
35799 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35800 emit_opcode(cbuf, Assembler::REX_B);
35801 } else {
35802 emit_opcode(cbuf, Assembler::REX_XB);
35803 }
35804 }
35805 } else {
35806 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
35807 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35808 emit_opcode(cbuf, Assembler::REX_R);
35809 } else {
35810 emit_opcode(cbuf, Assembler::REX_RX);
35811 }
35812 } else {
35813 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35814 emit_opcode(cbuf, Assembler::REX_RB);
35815 } else {
35816 emit_opcode(cbuf, Assembler::REX_RXB);
35817 }
35818 }
35819 }
35820
35821#line 35821 "ad_x86.cpp"
35822 }
35823 {
35824
35825#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35826
35827 emit_opcode(cbuf, (0x31 /*primary()*/));
35828
35829#line 35829 "ad_x86.cpp"
35830 }
35831 {
35832
35833#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35834
35835 // High registers handle in encode_RegMem
35836 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
35837 int base = opnd_array(1)->base(ra_,this,idx1);
35838 int index = opnd_array(1)->index(ra_,this,idx1);
35839 int scale = opnd_array(1)->scale();
35840 int disp = opnd_array(1)->disp(ra_,this,idx1);
35841 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
35842
35843 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
35844
35845#line 35845 "ad_x86.cpp"
35846 }
35847}
35848
35849void xorI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35850 cbuf.set_insts_mark();
35851 // Start at oper_input_base() and count operands
35852 unsigned idx0 = 2;
35853 unsigned idx1 = 2; // dst
35854 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35855 {
35856
35857#line 2336 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35858
35859 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
35860 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
35861 emit_opcode(cbuf, Assembler::REX_B);
35862 } else {
35863 emit_opcode(cbuf, Assembler::REX_XB);
35864 }
35865 } else {
35866 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
35867 emit_opcode(cbuf, Assembler::REX_X);
35868 }
35869 }
35870
35871#line 35871 "ad_x86.cpp"
35872 }
35873 {
35874
35875#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35876
35877 // Emit primary opcode and set sign-extend bit
35878 // Check for 8-bit immediate, and set sign extend bit in opcode
35879 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35880 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
35881 } else {
35882 // 32-bit immediate
35883 emit_opcode(cbuf, (0x81 /*primary()*/));
35884 }
35885
35886#line 35886 "ad_x86.cpp"
35887 }
35888 {
35889
35890#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35891
35892 int rm_byte_opcode = (0x6 /*secondary()*/);
35893
35894 // High registers handle in encode_RegMem
35895 int base = opnd_array(1)->base(ra_,this,idx1);
35896 int index = opnd_array(1)->index(ra_,this,idx1);
35897 int scale = opnd_array(1)->scale();
35898 int displace = opnd_array(1)->disp(ra_,this,idx1);
35899
35900 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
35901 // working with static
35902 // globals
35903 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
35904 disp_reloc);
35905
35906#line 35906 "ad_x86.cpp"
35907 }
35908 {
35909
35910#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35911
35912 // Check for 8-bit immediate, and set sign extend bit in opcode
35913 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
35914 emit_d8(cbuf, opnd_array(2)->constant());
35915 } else {
35916 // 32-bit immediate
35917 emit_d32(cbuf, opnd_array(2)->constant());
35918 }
35919
35920#line 35920 "ad_x86.cpp"
35921 }
35922}
35923
35924void andL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35925 cbuf.set_insts_mark();
35926 // Start at oper_input_base() and count operands
35927 unsigned idx0 = 1;
35928 unsigned idx1 = 1; // dst
35929 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35930 {
35931
35932#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35933
35934 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35935 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35936 emit_opcode(cbuf, Assembler::REX_W);
35937 } else {
35938 emit_opcode(cbuf, Assembler::REX_WB);
35939 }
35940 } else {
35941 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
35942 emit_opcode(cbuf, Assembler::REX_WR);
35943 } else {
35944 emit_opcode(cbuf, Assembler::REX_WRB);
35945 }
35946 }
35947
35948#line 35948 "ad_x86.cpp"
35949 }
35950 {
35951
35952#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35953
35954 emit_opcode(cbuf, (0x23 /*primary()*/));
35955
35956#line 35956 "ad_x86.cpp"
35957 }
35958 {
35959
35960#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35961
35962 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
35963
35964#line 35964 "ad_x86.cpp"
35965 }
35966}
35967
35968void andL_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35969 cbuf.set_insts_mark();
35970 // Start at oper_input_base() and count operands
35971 unsigned idx0 = 1;
35972 unsigned idx1 = 1; // dst
35973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35974 {
35975
35976#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35977
35978 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35979 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35980 emit_opcode(cbuf, Assembler::REX_W);
35981 } else {
35982 emit_opcode(cbuf, Assembler::REX_WB);
35983 }
35984 } else {
35985 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
35986 emit_opcode(cbuf, Assembler::REX_WR);
35987 } else {
35988 emit_opcode(cbuf, Assembler::REX_WRB);
35989 }
35990 }
35991
35992#line 35992 "ad_x86.cpp"
35993 }
35994 {
35995
35996#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
35997
35998 emit_opcode(cbuf, (0x0F /*primary()*/));
35999
36000#line 36000 "ad_x86.cpp"
36001 }
36002 {
36003
36004#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36005
36006 emit_opcode(cbuf, (0xB6 /*secondary()*/));
36007
36008#line 36008 "ad_x86.cpp"
36009 }
36010 {
36011
36012#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36013
36014 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
36015
36016#line 36016 "ad_x86.cpp"
36017 }
36018}
36019
36020void andL_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36021 cbuf.set_insts_mark();
36022 // Start at oper_input_base() and count operands
36023 unsigned idx0 = 1;
36024 unsigned idx1 = 1; // dst
36025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36026 {
36027
36028#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36029
36030 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36031 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36032 emit_opcode(cbuf, Assembler::REX_W);
36033 } else {
36034 emit_opcode(cbuf, Assembler::REX_WB);
36035 }
36036 } else {
36037 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36038 emit_opcode(cbuf, Assembler::REX_WR);
36039 } else {
36040 emit_opcode(cbuf, Assembler::REX_WRB);
36041 }
36042 }
36043
36044#line 36044 "ad_x86.cpp"
36045 }
36046 {
36047
36048#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36049
36050 emit_opcode(cbuf, (0x0F /*primary()*/));
36051
36052#line 36052 "ad_x86.cpp"
36053 }
36054 {
36055
36056#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36057
36058 emit_opcode(cbuf, (0xB7 /*secondary()*/));
36059
36060#line 36060 "ad_x86.cpp"
36061 }
36062 {
36063
36064#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36065
36066 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7);
36067
36068#line 36068 "ad_x86.cpp"
36069 }
36070}
36071
36072void andL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36073 cbuf.set_insts_mark();
36074 // Start at oper_input_base() and count operands
36075 unsigned idx0 = 1;
36076 unsigned idx1 = 1; // dst
36077 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36078 {
36079
36080#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36081
36082 // OpcSEr/m
36083 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
36084 if (dstenc < 8) {
36085 emit_opcode(cbuf, Assembler::REX_W);
36086 } else {
36087 emit_opcode(cbuf, Assembler::REX_WB);
36088 dstenc -= 8;
36089 }
36090 // Emit primary opcode and set sign-extend bit
36091 // Check for 8-bit immediate, and set sign extend bit in opcode
36092 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36093 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
36094 } else {
36095 // 32-bit immediate
36096 emit_opcode(cbuf, (0x81 /*primary()*/));
36097 }
36098 // Emit r/m byte with secondary opcode, after primary opcode.
36099 emit_rm(cbuf, 0x3, (0x04 /*secondary()*/), dstenc);
36100
36101#line 36101 "ad_x86.cpp"
36102 }
36103 {
36104
36105#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36106
36107 // Check for 8-bit immediate, and set sign extend bit in opcode
36108 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36109 emit_d8(cbuf, opnd_array(2)->constantL());
36110 } else {
36111 // 32-bit immediate
36112 emit_d32(cbuf, opnd_array(2)->constantL());
36113 }
36114
36115#line 36115 "ad_x86.cpp"
36116 }
36117}
36118
36119void andL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36120 cbuf.set_insts_mark();
36121 // Start at oper_input_base() and count operands
36122 unsigned idx0 = 2;
36123 unsigned idx1 = 2; // dst
36124 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36125 {
36126
36127#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36128
36129 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36130 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
36131 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36132 emit_opcode(cbuf, Assembler::REX_W);
36133 } else {
36134 emit_opcode(cbuf, Assembler::REX_WX);
36135 }
36136 } else {
36137 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36138 emit_opcode(cbuf, Assembler::REX_WB);
36139 } else {
36140 emit_opcode(cbuf, Assembler::REX_WXB);
36141 }
36142 }
36143 } else {
36144 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
36145 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36146 emit_opcode(cbuf, Assembler::REX_WR);
36147 } else {
36148 emit_opcode(cbuf, Assembler::REX_WRX);
36149 }
36150 } else {
36151 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36152 emit_opcode(cbuf, Assembler::REX_WRB);
36153 } else {
36154 emit_opcode(cbuf, Assembler::REX_WRXB);
36155 }
36156 }
36157 }
36158
36159#line 36159 "ad_x86.cpp"
36160 }
36161 {
36162
36163#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36164
36165 emit_opcode(cbuf, (0x23 /*primary()*/));
36166
36167#line 36167 "ad_x86.cpp"
36168 }
36169 {
36170
36171#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36172
36173 // High registers handle in encode_RegMem
36174 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
36175 int base = opnd_array(2)->base(ra_,this,idx2);
36176 int index = opnd_array(2)->index(ra_,this,idx2);
36177 int scale = opnd_array(2)->scale();
36178 int disp = opnd_array(2)->disp(ra_,this,idx2);
36179 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
36180
36181 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
36182
36183#line 36183 "ad_x86.cpp"
36184 }
36185}
36186
36187void andL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36188 cbuf.set_insts_mark();
36189 // Start at oper_input_base() and count operands
36190 unsigned idx0 = 2;
36191 unsigned idx1 = 2; // src
36192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
36193 {
36194
36195#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36196
36197 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
36198 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36199 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36200 emit_opcode(cbuf, Assembler::REX_W);
36201 } else {
36202 emit_opcode(cbuf, Assembler::REX_WX);
36203 }
36204 } else {
36205 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36206 emit_opcode(cbuf, Assembler::REX_WB);
36207 } else {
36208 emit_opcode(cbuf, Assembler::REX_WXB);
36209 }
36210 }
36211 } else {
36212 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36213 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36214 emit_opcode(cbuf, Assembler::REX_WR);
36215 } else {
36216 emit_opcode(cbuf, Assembler::REX_WRX);
36217 }
36218 } else {
36219 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36220 emit_opcode(cbuf, Assembler::REX_WRB);
36221 } else {
36222 emit_opcode(cbuf, Assembler::REX_WRXB);
36223 }
36224 }
36225 }
36226
36227#line 36227 "ad_x86.cpp"
36228 }
36229 {
36230
36231#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36232
36233 emit_opcode(cbuf, (0x23 /*primary()*/));
36234
36235#line 36235 "ad_x86.cpp"
36236 }
36237 {
36238
36239#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36240
36241 // High registers handle in encode_RegMem
36242 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
36243 int base = opnd_array(1)->base(ra_,this,idx1);
36244 int index = opnd_array(1)->index(ra_,this,idx1);
36245 int scale = opnd_array(1)->scale();
36246 int disp = opnd_array(1)->disp(ra_,this,idx1);
36247 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
36248
36249 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
36250
36251#line 36251 "ad_x86.cpp"
36252 }
36253}
36254
36255void andL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36256 cbuf.set_insts_mark();
36257 // Start at oper_input_base() and count operands
36258 unsigned idx0 = 2;
36259 unsigned idx1 = 2; // dst
36260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36261 {
36262
36263#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36264
36265 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36266 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36267 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36268 emit_opcode(cbuf, Assembler::REX_W);
36269 } else {
36270 emit_opcode(cbuf, Assembler::REX_WX);
36271 }
36272 } else {
36273 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36274 emit_opcode(cbuf, Assembler::REX_WB);
36275 } else {
36276 emit_opcode(cbuf, Assembler::REX_WXB);
36277 }
36278 }
36279 } else {
36280 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36281 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36282 emit_opcode(cbuf, Assembler::REX_WR);
36283 } else {
36284 emit_opcode(cbuf, Assembler::REX_WRX);
36285 }
36286 } else {
36287 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36288 emit_opcode(cbuf, Assembler::REX_WRB);
36289 } else {
36290 emit_opcode(cbuf, Assembler::REX_WRXB);
36291 }
36292 }
36293 }
36294
36295#line 36295 "ad_x86.cpp"
36296 }
36297 {
36298
36299#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36300
36301 emit_opcode(cbuf, (0x21 /*primary()*/));
36302
36303#line 36303 "ad_x86.cpp"
36304 }
36305 {
36306
36307#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36308
36309 // High registers handle in encode_RegMem
36310 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
36311 int base = opnd_array(1)->base(ra_,this,idx1);
36312 int index = opnd_array(1)->index(ra_,this,idx1);
36313 int scale = opnd_array(1)->scale();
36314 int disp = opnd_array(1)->disp(ra_,this,idx1);
36315 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
36316
36317 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
36318
36319#line 36319 "ad_x86.cpp"
36320 }
36321}
36322
36323void andL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36324 cbuf.set_insts_mark();
36325 // Start at oper_input_base() and count operands
36326 unsigned idx0 = 2;
36327 unsigned idx1 = 2; // dst
36328 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36329 {
36330
36331#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36332
36333 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36334 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36335 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36336 emit_opcode(cbuf, Assembler::REX_W);
36337 } else {
36338 emit_opcode(cbuf, Assembler::REX_WX);
36339 }
36340 } else {
36341 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36342 emit_opcode(cbuf, Assembler::REX_WB);
36343 } else {
36344 emit_opcode(cbuf, Assembler::REX_WXB);
36345 }
36346 }
36347 } else {
36348 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
36349 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36350 emit_opcode(cbuf, Assembler::REX_WR);
36351 } else {
36352 emit_opcode(cbuf, Assembler::REX_WRX);
36353 }
36354 } else {
36355 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36356 emit_opcode(cbuf, Assembler::REX_WRB);
36357 } else {
36358 emit_opcode(cbuf, Assembler::REX_WRXB);
36359 }
36360 }
36361 }
36362
36363#line 36363 "ad_x86.cpp"
36364 }
36365 {
36366
36367#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36368
36369 emit_opcode(cbuf, (0x21 /*primary()*/));
36370
36371#line 36371 "ad_x86.cpp"
36372 }
36373 {
36374
36375#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36376
36377 // High registers handle in encode_RegMem
36378 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
36379 int base = opnd_array(1)->base(ra_,this,idx1);
36380 int index = opnd_array(1)->index(ra_,this,idx1);
36381 int scale = opnd_array(1)->scale();
36382 int disp = opnd_array(1)->disp(ra_,this,idx1);
36383 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
36384
36385 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
36386
36387#line 36387 "ad_x86.cpp"
36388 }
36389}
36390
36391void andL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36392 cbuf.set_insts_mark();
36393 // Start at oper_input_base() and count operands
36394 unsigned idx0 = 2;
36395 unsigned idx1 = 2; // dst
36396 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36397 {
36398
36399#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36400
36401 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
36402 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36403 emit_opcode(cbuf, Assembler::REX_WB);
36404 } else {
36405 emit_opcode(cbuf, Assembler::REX_WXB);
36406 }
36407 } else {
36408 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
36409 emit_opcode(cbuf, Assembler::REX_W);
36410 } else {
36411 emit_opcode(cbuf, Assembler::REX_WX);
36412 }
36413 }
36414
36415#line 36415 "ad_x86.cpp"
36416 }
36417 {
36418
36419#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36420
36421 // Emit primary opcode and set sign-extend bit
36422 // Check for 8-bit immediate, and set sign extend bit in opcode
36423 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36424 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
36425 } else {
36426 // 32-bit immediate
36427 emit_opcode(cbuf, (0x81 /*primary()*/));
36428 }
36429
36430#line 36430 "ad_x86.cpp"
36431 }
36432 {
36433
36434#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36435
36436 int rm_byte_opcode = (0x4 /*secondary()*/);
36437
36438 // High registers handle in encode_RegMem
36439 int base = opnd_array(1)->base(ra_,this,idx1);
36440 int index = opnd_array(1)->index(ra_,this,idx1);
36441 int scale = opnd_array(1)->scale();
36442 int displace = opnd_array(1)->disp(ra_,this,idx1);
36443
36444 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
36445 // working with static
36446 // globals
36447 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
36448 disp_reloc);
36449
36450#line 36450 "ad_x86.cpp"
36451 }
36452 {
36453
36454#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36455
36456 // Check for 8-bit immediate, and set sign extend bit in opcode
36457 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36458 emit_d8(cbuf, opnd_array(2)->constantL());
36459 } else {
36460 // 32-bit immediate
36461 emit_d32(cbuf, opnd_array(2)->constantL());
36462 }
36463
36464#line 36464 "ad_x86.cpp"
36465 }
36466}
36467
36468void andnL_rReg_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36469 cbuf.set_insts_mark();
36470 // Start at oper_input_base() and count operands
36471 unsigned idx0 = 2;
36472 unsigned idx1 = 2; // src1
36473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36474 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
36475 {
36476 MacroAssembler _masm(&cbuf);
36477
36478#line 9992 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36479
36480 __ andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()));
36481
36482#line 36482 "ad_x86.cpp"
36483 }
36484}
36485
36486void andnL_rReg_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36487 cbuf.set_insts_mark();
36488 // Start at oper_input_base() and count operands
36489 unsigned idx0 = 2;
36490 unsigned idx1 = 2; // src2
36491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
36492 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
36493 {
36494 MacroAssembler _masm(&cbuf);
36495
36496#line 9992 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36497
36498 __ andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36499
36500#line 36500 "ad_x86.cpp"
36501 }
36502}
36503
36504void andnL_rReg_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36505 cbuf.set_insts_mark();
36506 // Start at oper_input_base() and count operands
36507 unsigned idx0 = 1;
36508 unsigned idx1 = 1; // src1
36509 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36510 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
36511 {
36512 MacroAssembler _masm(&cbuf);
36513
36514#line 10005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36515
36516 __ andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* src2 */);
36517
36518#line 36518 "ad_x86.cpp"
36519 }
36520}
36521
36522void andnL_rReg_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36523 cbuf.set_insts_mark();
36524 // Start at oper_input_base() and count operands
36525 unsigned idx0 = 1;
36526 unsigned idx1 = 1; // src2
36527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
36528 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
36529 {
36530 MacroAssembler _masm(&cbuf);
36531
36532#line 10005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36533
36534 __ andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src2 */);
36535
36536#line 36536 "ad_x86.cpp"
36537 }
36538}
36539
36540void blsiL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36541 cbuf.set_insts_mark();
36542 // Start at oper_input_base() and count operands
36543 unsigned idx0 = 1;
36544 unsigned idx1 = 1; // imm_zero
36545 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36546 {
36547 MacroAssembler _masm(&cbuf);
36548
36549#line 10018 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36550
36551 __ blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
36552
36553#line 36553 "ad_x86.cpp"
36554 }
36555}
36556
36557void blsiL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36558 cbuf.set_insts_mark();
36559 // Start at oper_input_base() and count operands
36560 unsigned idx0 = 1;
36561 unsigned idx1 = 1; // src
36562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
36563 {
36564 MacroAssembler _masm(&cbuf);
36565
36566#line 10018 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36567
36568 __ blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
36569
36570#line 36570 "ad_x86.cpp"
36571 }
36572}
36573
36574void blsiL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36575 cbuf.set_insts_mark();
36576 // Start at oper_input_base() and count operands
36577 unsigned idx0 = 2;
36578 unsigned idx1 = 2; // imm_zero
36579 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36580 {
36581 MacroAssembler _masm(&cbuf);
36582
36583#line 10032 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36584
36585 __ blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
36586
36587#line 36587 "ad_x86.cpp"
36588 }
36589}
36590
36591void blsiL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36592 cbuf.set_insts_mark();
36593 // Start at oper_input_base() and count operands
36594 unsigned idx0 = 2;
36595 unsigned idx1 = 2; // src
36596 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
36597 {
36598 MacroAssembler _masm(&cbuf);
36599
36600#line 10032 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36601
36602 __ blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36603
36604#line 36604 "ad_x86.cpp"
36605 }
36606}
36607
36608void blsmskL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36609 cbuf.set_insts_mark();
36610 // Start at oper_input_base() and count operands
36611 unsigned idx0 = 2;
36612 unsigned idx1 = 2; // src
36613 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36614 {
36615 MacroAssembler _masm(&cbuf);
36616
36617#line 10047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36618
36619 __ blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36620
36621#line 36621 "ad_x86.cpp"
36622 }
36623}
36624
36625void blsmskL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36626 cbuf.set_insts_mark();
36627 // Start at oper_input_base() and count operands
36628 unsigned idx0 = 2;
36629 unsigned idx1 = 2; // src
36630 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36631 {
36632 MacroAssembler _masm(&cbuf);
36633
36634#line 10047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36635
36636 __ blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36637
36638#line 36638 "ad_x86.cpp"
36639 }
36640}
36641
36642void blsmskL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36643 cbuf.set_insts_mark();
36644 // Start at oper_input_base() and count operands
36645 unsigned idx0 = 1;
36646 unsigned idx1 = 1; // src
36647 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36648 {
36649 MacroAssembler _masm(&cbuf);
36650
36651#line 10061 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36652
36653 __ blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
36654
36655#line 36655 "ad_x86.cpp"
36656 }
36657}
36658
36659void blsmskL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36660 cbuf.set_insts_mark();
36661 // Start at oper_input_base() and count operands
36662 unsigned idx0 = 1;
36663 unsigned idx1 = 1; // src
36664 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36665 {
36666 MacroAssembler _masm(&cbuf);
36667
36668#line 10061 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36669
36670 __ blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
36671
36672#line 36672 "ad_x86.cpp"
36673 }
36674}
36675
36676void blsrL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36677 cbuf.set_insts_mark();
36678 // Start at oper_input_base() and count operands
36679 unsigned idx0 = 1;
36680 unsigned idx1 = 1; // src
36681 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36682 {
36683 MacroAssembler _masm(&cbuf);
36684
36685#line 10076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36686
36687 __ blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
36688
36689#line 36689 "ad_x86.cpp"
36690 }
36691}
36692
36693void blsrL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36694 cbuf.set_insts_mark();
36695 // Start at oper_input_base() and count operands
36696 unsigned idx0 = 1;
36697 unsigned idx1 = 1; // src
36698 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36699 {
36700 MacroAssembler _masm(&cbuf);
36701
36702#line 10076 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36703
36704 __ blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
36705
36706#line 36706 "ad_x86.cpp"
36707 }
36708}
36709
36710void blsrL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36711 cbuf.set_insts_mark();
36712 // Start at oper_input_base() and count operands
36713 unsigned idx0 = 2;
36714 unsigned idx1 = 2; // src
36715 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36716 {
36717 MacroAssembler _masm(&cbuf);
36718
36719#line 10092 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36720
36721 __ blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36722
36723#line 36723 "ad_x86.cpp"
36724 }
36725}
36726
36727void blsrL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36728 cbuf.set_insts_mark();
36729 // Start at oper_input_base() and count operands
36730 unsigned idx0 = 2;
36731 unsigned idx1 = 2; // src
36732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
36733 {
36734 MacroAssembler _masm(&cbuf);
36735
36736#line 10092 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36737
36738 __ blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
36739
36740#line 36740 "ad_x86.cpp"
36741 }
36742}
36743
36744void orL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36745 cbuf.set_insts_mark();
36746 // Start at oper_input_base() and count operands
36747 unsigned idx0 = 1;
36748 unsigned idx1 = 1; // dst
36749 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36750 {
36751
36752#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36753
36754 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36755 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36756 emit_opcode(cbuf, Assembler::REX_W);
36757 } else {
36758 emit_opcode(cbuf, Assembler::REX_WB);
36759 }
36760 } else {
36761 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36762 emit_opcode(cbuf, Assembler::REX_WR);
36763 } else {
36764 emit_opcode(cbuf, Assembler::REX_WRB);
36765 }
36766 }
36767
36768#line 36768 "ad_x86.cpp"
36769 }
36770 {
36771
36772#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36773
36774 emit_opcode(cbuf, (0x0B /*primary()*/));
36775
36776#line 36776 "ad_x86.cpp"
36777 }
36778 {
36779
36780#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36781
36782 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
36783
36784#line 36784 "ad_x86.cpp"
36785 }
36786}
36787
36788void orL_rReg_castP2XNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36789 cbuf.set_insts_mark();
36790 // Start at oper_input_base() and count operands
36791 unsigned idx0 = 1;
36792 unsigned idx1 = 1; // dst
36793 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36794 {
36795
36796#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36797
36798 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36799 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36800 emit_opcode(cbuf, Assembler::REX_W);
36801 } else {
36802 emit_opcode(cbuf, Assembler::REX_WB);
36803 }
36804 } else {
36805 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
36806 emit_opcode(cbuf, Assembler::REX_WR);
36807 } else {
36808 emit_opcode(cbuf, Assembler::REX_WRB);
36809 }
36810 }
36811
36812#line 36812 "ad_x86.cpp"
36813 }
36814 {
36815
36816#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36817
36818 emit_opcode(cbuf, (0x0B /*primary()*/));
36819
36820#line 36820 "ad_x86.cpp"
36821 }
36822 {
36823
36824#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36825
36826 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
36827
36828#line 36828 "ad_x86.cpp"
36829 }
36830}
36831
36832void orL_rReg_castP2X_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36833 cbuf.set_insts_mark();
36834 // Start at oper_input_base() and count operands
36835 unsigned idx0 = 1;
36836 unsigned idx1 = 1; // src
36837 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
36838 {
36839
36840#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36841
36842 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
36843 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
36844 emit_opcode(cbuf, Assembler::REX_W);
36845 } else {
36846 emit_opcode(cbuf, Assembler::REX_WB);
36847 }
36848 } else {
36849 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
36850 emit_opcode(cbuf, Assembler::REX_WR);
36851 } else {
36852 emit_opcode(cbuf, Assembler::REX_WRB);
36853 }
36854 }
36855
36856#line 36856 "ad_x86.cpp"
36857 }
36858 {
36859
36860#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36861
36862 emit_opcode(cbuf, (0x0B /*primary()*/));
36863
36864#line 36864 "ad_x86.cpp"
36865 }
36866 {
36867
36868#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36869
36870 emit_rm(cbuf, 0x3, opnd_array(2)->reg(ra_,this,idx2)/* dst */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
36871
36872#line 36872 "ad_x86.cpp"
36873 }
36874}
36875
36876void orL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36877 cbuf.set_insts_mark();
36878 // Start at oper_input_base() and count operands
36879 unsigned idx0 = 1;
36880 unsigned idx1 = 1; // dst
36881 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36882 {
36883
36884#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36885
36886 // OpcSEr/m
36887 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
36888 if (dstenc < 8) {
36889 emit_opcode(cbuf, Assembler::REX_W);
36890 } else {
36891 emit_opcode(cbuf, Assembler::REX_WB);
36892 dstenc -= 8;
36893 }
36894 // Emit primary opcode and set sign-extend bit
36895 // Check for 8-bit immediate, and set sign extend bit in opcode
36896 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36897 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
36898 } else {
36899 // 32-bit immediate
36900 emit_opcode(cbuf, (0x81 /*primary()*/));
36901 }
36902 // Emit r/m byte with secondary opcode, after primary opcode.
36903 emit_rm(cbuf, 0x3, (0x01 /*secondary()*/), dstenc);
36904
36905#line 36905 "ad_x86.cpp"
36906 }
36907 {
36908
36909#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36910
36911 // Check for 8-bit immediate, and set sign extend bit in opcode
36912 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
36913 emit_d8(cbuf, opnd_array(2)->constantL());
36914 } else {
36915 // 32-bit immediate
36916 emit_d32(cbuf, opnd_array(2)->constantL());
36917 }
36918
36919#line 36919 "ad_x86.cpp"
36920 }
36921}
36922
36923void orL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36924 cbuf.set_insts_mark();
36925 // Start at oper_input_base() and count operands
36926 unsigned idx0 = 2;
36927 unsigned idx1 = 2; // dst
36928 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36929 {
36930
36931#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36932
36933 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
36934 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
36935 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36936 emit_opcode(cbuf, Assembler::REX_W);
36937 } else {
36938 emit_opcode(cbuf, Assembler::REX_WX);
36939 }
36940 } else {
36941 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36942 emit_opcode(cbuf, Assembler::REX_WB);
36943 } else {
36944 emit_opcode(cbuf, Assembler::REX_WXB);
36945 }
36946 }
36947 } else {
36948 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
36949 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36950 emit_opcode(cbuf, Assembler::REX_WR);
36951 } else {
36952 emit_opcode(cbuf, Assembler::REX_WRX);
36953 }
36954 } else {
36955 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
36956 emit_opcode(cbuf, Assembler::REX_WRB);
36957 } else {
36958 emit_opcode(cbuf, Assembler::REX_WRXB);
36959 }
36960 }
36961 }
36962
36963#line 36963 "ad_x86.cpp"
36964 }
36965 {
36966
36967#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36968
36969 emit_opcode(cbuf, (0x0B /*primary()*/));
36970
36971#line 36971 "ad_x86.cpp"
36972 }
36973 {
36974
36975#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
36976
36977 // High registers handle in encode_RegMem
36978 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
36979 int base = opnd_array(2)->base(ra_,this,idx2);
36980 int index = opnd_array(2)->index(ra_,this,idx2);
36981 int scale = opnd_array(2)->scale();
36982 int disp = opnd_array(2)->disp(ra_,this,idx2);
36983 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
36984
36985 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
36986
36987#line 36987 "ad_x86.cpp"
36988 }
36989}
36990
36991void orL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36992 cbuf.set_insts_mark();
36993 // Start at oper_input_base() and count operands
36994 unsigned idx0 = 2;
36995 unsigned idx1 = 2; // src
36996 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
36997 {
36998
36999#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37000
37001 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
37002 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37003 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37004 emit_opcode(cbuf, Assembler::REX_W);
37005 } else {
37006 emit_opcode(cbuf, Assembler::REX_WX);
37007 }
37008 } else {
37009 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37010 emit_opcode(cbuf, Assembler::REX_WB);
37011 } else {
37012 emit_opcode(cbuf, Assembler::REX_WXB);
37013 }
37014 }
37015 } else {
37016 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37017 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37018 emit_opcode(cbuf, Assembler::REX_WR);
37019 } else {
37020 emit_opcode(cbuf, Assembler::REX_WRX);
37021 }
37022 } else {
37023 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37024 emit_opcode(cbuf, Assembler::REX_WRB);
37025 } else {
37026 emit_opcode(cbuf, Assembler::REX_WRXB);
37027 }
37028 }
37029 }
37030
37031#line 37031 "ad_x86.cpp"
37032 }
37033 {
37034
37035#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37036
37037 emit_opcode(cbuf, (0x0B /*primary()*/));
37038
37039#line 37039 "ad_x86.cpp"
37040 }
37041 {
37042
37043#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37044
37045 // High registers handle in encode_RegMem
37046 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
37047 int base = opnd_array(1)->base(ra_,this,idx1);
37048 int index = opnd_array(1)->index(ra_,this,idx1);
37049 int scale = opnd_array(1)->scale();
37050 int disp = opnd_array(1)->disp(ra_,this,idx1);
37051 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37052
37053 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37054
37055#line 37055 "ad_x86.cpp"
37056 }
37057}
37058
37059void orL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37060 cbuf.set_insts_mark();
37061 // Start at oper_input_base() and count operands
37062 unsigned idx0 = 2;
37063 unsigned idx1 = 2; // dst
37064 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37065 {
37066
37067#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37068
37069 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37070 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37071 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37072 emit_opcode(cbuf, Assembler::REX_W);
37073 } else {
37074 emit_opcode(cbuf, Assembler::REX_WX);
37075 }
37076 } else {
37077 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37078 emit_opcode(cbuf, Assembler::REX_WB);
37079 } else {
37080 emit_opcode(cbuf, Assembler::REX_WXB);
37081 }
37082 }
37083 } else {
37084 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37085 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37086 emit_opcode(cbuf, Assembler::REX_WR);
37087 } else {
37088 emit_opcode(cbuf, Assembler::REX_WRX);
37089 }
37090 } else {
37091 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37092 emit_opcode(cbuf, Assembler::REX_WRB);
37093 } else {
37094 emit_opcode(cbuf, Assembler::REX_WRXB);
37095 }
37096 }
37097 }
37098
37099#line 37099 "ad_x86.cpp"
37100 }
37101 {
37102
37103#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37104
37105 emit_opcode(cbuf, (0x09 /*primary()*/));
37106
37107#line 37107 "ad_x86.cpp"
37108 }
37109 {
37110
37111#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37112
37113 // High registers handle in encode_RegMem
37114 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
37115 int base = opnd_array(1)->base(ra_,this,idx1);
37116 int index = opnd_array(1)->index(ra_,this,idx1);
37117 int scale = opnd_array(1)->scale();
37118 int disp = opnd_array(1)->disp(ra_,this,idx1);
37119 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37120
37121 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37122
37123#line 37123 "ad_x86.cpp"
37124 }
37125}
37126
37127void orL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37128 cbuf.set_insts_mark();
37129 // Start at oper_input_base() and count operands
37130 unsigned idx0 = 2;
37131 unsigned idx1 = 2; // dst
37132 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37133 {
37134
37135#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37136
37137 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37138 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37139 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37140 emit_opcode(cbuf, Assembler::REX_W);
37141 } else {
37142 emit_opcode(cbuf, Assembler::REX_WX);
37143 }
37144 } else {
37145 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37146 emit_opcode(cbuf, Assembler::REX_WB);
37147 } else {
37148 emit_opcode(cbuf, Assembler::REX_WXB);
37149 }
37150 }
37151 } else {
37152 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37153 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37154 emit_opcode(cbuf, Assembler::REX_WR);
37155 } else {
37156 emit_opcode(cbuf, Assembler::REX_WRX);
37157 }
37158 } else {
37159 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37160 emit_opcode(cbuf, Assembler::REX_WRB);
37161 } else {
37162 emit_opcode(cbuf, Assembler::REX_WRXB);
37163 }
37164 }
37165 }
37166
37167#line 37167 "ad_x86.cpp"
37168 }
37169 {
37170
37171#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37172
37173 emit_opcode(cbuf, (0x09 /*primary()*/));
37174
37175#line 37175 "ad_x86.cpp"
37176 }
37177 {
37178
37179#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37180
37181 // High registers handle in encode_RegMem
37182 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
37183 int base = opnd_array(1)->base(ra_,this,idx1);
37184 int index = opnd_array(1)->index(ra_,this,idx1);
37185 int scale = opnd_array(1)->scale();
37186 int disp = opnd_array(1)->disp(ra_,this,idx1);
37187 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37188
37189 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37190
37191#line 37191 "ad_x86.cpp"
37192 }
37193}
37194
37195void orL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37196 cbuf.set_insts_mark();
37197 // Start at oper_input_base() and count operands
37198 unsigned idx0 = 2;
37199 unsigned idx1 = 2; // dst
37200 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37201 {
37202
37203#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37204
37205 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
37206 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37207 emit_opcode(cbuf, Assembler::REX_WB);
37208 } else {
37209 emit_opcode(cbuf, Assembler::REX_WXB);
37210 }
37211 } else {
37212 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37213 emit_opcode(cbuf, Assembler::REX_W);
37214 } else {
37215 emit_opcode(cbuf, Assembler::REX_WX);
37216 }
37217 }
37218
37219#line 37219 "ad_x86.cpp"
37220 }
37221 {
37222
37223#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37224
37225 // Emit primary opcode and set sign-extend bit
37226 // Check for 8-bit immediate, and set sign extend bit in opcode
37227 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37228 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
37229 } else {
37230 // 32-bit immediate
37231 emit_opcode(cbuf, (0x81 /*primary()*/));
37232 }
37233
37234#line 37234 "ad_x86.cpp"
37235 }
37236 {
37237
37238#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37239
37240 int rm_byte_opcode = (0x1 /*secondary()*/);
37241
37242 // High registers handle in encode_RegMem
37243 int base = opnd_array(1)->base(ra_,this,idx1);
37244 int index = opnd_array(1)->index(ra_,this,idx1);
37245 int scale = opnd_array(1)->scale();
37246 int displace = opnd_array(1)->disp(ra_,this,idx1);
37247
37248 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
37249 // working with static
37250 // globals
37251 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
37252 disp_reloc);
37253
37254#line 37254 "ad_x86.cpp"
37255 }
37256 {
37257
37258#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37259
37260 // Check for 8-bit immediate, and set sign extend bit in opcode
37261 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37262 emit_d8(cbuf, opnd_array(2)->constantL());
37263 } else {
37264 // 32-bit immediate
37265 emit_d32(cbuf, opnd_array(2)->constantL());
37266 }
37267
37268#line 37268 "ad_x86.cpp"
37269 }
37270}
37271
37272void xorL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37273 cbuf.set_insts_mark();
37274 // Start at oper_input_base() and count operands
37275 unsigned idx0 = 1;
37276 unsigned idx1 = 1; // dst
37277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37278 {
37279
37280#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37281
37282 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
37283 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37284 emit_opcode(cbuf, Assembler::REX_W);
37285 } else {
37286 emit_opcode(cbuf, Assembler::REX_WB);
37287 }
37288 } else {
37289 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37290 emit_opcode(cbuf, Assembler::REX_WR);
37291 } else {
37292 emit_opcode(cbuf, Assembler::REX_WRB);
37293 }
37294 }
37295
37296#line 37296 "ad_x86.cpp"
37297 }
37298 {
37299
37300#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37301
37302 emit_opcode(cbuf, (0x33 /*primary()*/));
37303
37304#line 37304 "ad_x86.cpp"
37305 }
37306 {
37307
37308#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37309
37310 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
37311
37312#line 37312 "ad_x86.cpp"
37313 }
37314}
37315
37316void xorL_rReg_im1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37317 cbuf.set_insts_mark();
37318 // Start at oper_input_base() and count operands
37319 unsigned idx0 = 1;
37320 unsigned idx1 = 1; // dst
37321 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
37322 {
37323 MacroAssembler _masm(&cbuf);
37324
37325#line 10194 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37326
37327 __ notq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
37328
37329#line 37329 "ad_x86.cpp"
37330 }
37331}
37332
37333void xorL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37334 cbuf.set_insts_mark();
37335 // Start at oper_input_base() and count operands
37336 unsigned idx0 = 1;
37337 unsigned idx1 = 1; // dst
37338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37339 {
37340
37341#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37342
37343 // OpcSEr/m
37344 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
37345 if (dstenc < 8) {
37346 emit_opcode(cbuf, Assembler::REX_W);
37347 } else {
37348 emit_opcode(cbuf, Assembler::REX_WB);
37349 dstenc -= 8;
37350 }
37351 // Emit primary opcode and set sign-extend bit
37352 // Check for 8-bit immediate, and set sign extend bit in opcode
37353 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37354 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
37355 } else {
37356 // 32-bit immediate
37357 emit_opcode(cbuf, (0x81 /*primary()*/));
37358 }
37359 // Emit r/m byte with secondary opcode, after primary opcode.
37360 emit_rm(cbuf, 0x3, (0x06 /*secondary()*/), dstenc);
37361
37362#line 37362 "ad_x86.cpp"
37363 }
37364 {
37365
37366#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37367
37368 // Check for 8-bit immediate, and set sign extend bit in opcode
37369 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37370 emit_d8(cbuf, opnd_array(2)->constantL());
37371 } else {
37372 // 32-bit immediate
37373 emit_d32(cbuf, opnd_array(2)->constantL());
37374 }
37375
37376#line 37376 "ad_x86.cpp"
37377 }
37378}
37379
37380void xorL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37381 cbuf.set_insts_mark();
37382 // Start at oper_input_base() and count operands
37383 unsigned idx0 = 2;
37384 unsigned idx1 = 2; // dst
37385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37386 {
37387
37388#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37389
37390 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
37391 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
37392 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
37393 emit_opcode(cbuf, Assembler::REX_W);
37394 } else {
37395 emit_opcode(cbuf, Assembler::REX_WX);
37396 }
37397 } else {
37398 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
37399 emit_opcode(cbuf, Assembler::REX_WB);
37400 } else {
37401 emit_opcode(cbuf, Assembler::REX_WXB);
37402 }
37403 }
37404 } else {
37405 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
37406 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
37407 emit_opcode(cbuf, Assembler::REX_WR);
37408 } else {
37409 emit_opcode(cbuf, Assembler::REX_WRX);
37410 }
37411 } else {
37412 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
37413 emit_opcode(cbuf, Assembler::REX_WRB);
37414 } else {
37415 emit_opcode(cbuf, Assembler::REX_WRXB);
37416 }
37417 }
37418 }
37419
37420#line 37420 "ad_x86.cpp"
37421 }
37422 {
37423
37424#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37425
37426 emit_opcode(cbuf, (0x33 /*primary()*/));
37427
37428#line 37428 "ad_x86.cpp"
37429 }
37430 {
37431
37432#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37433
37434 // High registers handle in encode_RegMem
37435 int reg = opnd_array(1)->reg(ra_,this,idx1)/* dst */;
37436 int base = opnd_array(2)->base(ra_,this,idx2);
37437 int index = opnd_array(2)->index(ra_,this,idx2);
37438 int scale = opnd_array(2)->scale();
37439 int disp = opnd_array(2)->disp(ra_,this,idx2);
37440 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
37441
37442 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37443
37444#line 37444 "ad_x86.cpp"
37445 }
37446}
37447
37448void xorL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37449 cbuf.set_insts_mark();
37450 // Start at oper_input_base() and count operands
37451 unsigned idx0 = 2;
37452 unsigned idx1 = 2; // src
37453 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
37454 {
37455
37456#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37457
37458 if (opnd_array(2)->reg(ra_,this,idx2)/* dst */ < 8) {
37459 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37460 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37461 emit_opcode(cbuf, Assembler::REX_W);
37462 } else {
37463 emit_opcode(cbuf, Assembler::REX_WX);
37464 }
37465 } else {
37466 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37467 emit_opcode(cbuf, Assembler::REX_WB);
37468 } else {
37469 emit_opcode(cbuf, Assembler::REX_WXB);
37470 }
37471 }
37472 } else {
37473 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37474 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37475 emit_opcode(cbuf, Assembler::REX_WR);
37476 } else {
37477 emit_opcode(cbuf, Assembler::REX_WRX);
37478 }
37479 } else {
37480 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37481 emit_opcode(cbuf, Assembler::REX_WRB);
37482 } else {
37483 emit_opcode(cbuf, Assembler::REX_WRXB);
37484 }
37485 }
37486 }
37487
37488#line 37488 "ad_x86.cpp"
37489 }
37490 {
37491
37492#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37493
37494 emit_opcode(cbuf, (0x33 /*primary()*/));
37495
37496#line 37496 "ad_x86.cpp"
37497 }
37498 {
37499
37500#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37501
37502 // High registers handle in encode_RegMem
37503 int reg = opnd_array(2)->reg(ra_,this,idx2)/* dst */;
37504 int base = opnd_array(1)->base(ra_,this,idx1);
37505 int index = opnd_array(1)->index(ra_,this,idx1);
37506 int scale = opnd_array(1)->scale();
37507 int disp = opnd_array(1)->disp(ra_,this,idx1);
37508 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37509
37510 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37511
37512#line 37512 "ad_x86.cpp"
37513 }
37514}
37515
37516void xorL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37517 cbuf.set_insts_mark();
37518 // Start at oper_input_base() and count operands
37519 unsigned idx0 = 2;
37520 unsigned idx1 = 2; // dst
37521 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37522 {
37523
37524#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37525
37526 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37527 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37528 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37529 emit_opcode(cbuf, Assembler::REX_W);
37530 } else {
37531 emit_opcode(cbuf, Assembler::REX_WX);
37532 }
37533 } else {
37534 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37535 emit_opcode(cbuf, Assembler::REX_WB);
37536 } else {
37537 emit_opcode(cbuf, Assembler::REX_WXB);
37538 }
37539 }
37540 } else {
37541 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37542 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37543 emit_opcode(cbuf, Assembler::REX_WR);
37544 } else {
37545 emit_opcode(cbuf, Assembler::REX_WRX);
37546 }
37547 } else {
37548 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37549 emit_opcode(cbuf, Assembler::REX_WRB);
37550 } else {
37551 emit_opcode(cbuf, Assembler::REX_WRXB);
37552 }
37553 }
37554 }
37555
37556#line 37556 "ad_x86.cpp"
37557 }
37558 {
37559
37560#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37561
37562 emit_opcode(cbuf, (0x31 /*primary()*/));
37563
37564#line 37564 "ad_x86.cpp"
37565 }
37566 {
37567
37568#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37569
37570 // High registers handle in encode_RegMem
37571 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
37572 int base = opnd_array(1)->base(ra_,this,idx1);
37573 int index = opnd_array(1)->index(ra_,this,idx1);
37574 int scale = opnd_array(1)->scale();
37575 int disp = opnd_array(1)->disp(ra_,this,idx1);
37576 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37577
37578 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37579
37580#line 37580 "ad_x86.cpp"
37581 }
37582}
37583
37584void xorL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37585 cbuf.set_insts_mark();
37586 // Start at oper_input_base() and count operands
37587 unsigned idx0 = 2;
37588 unsigned idx1 = 2; // dst
37589 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37590 {
37591
37592#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37593
37594 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
37595 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37596 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37597 emit_opcode(cbuf, Assembler::REX_W);
37598 } else {
37599 emit_opcode(cbuf, Assembler::REX_WX);
37600 }
37601 } else {
37602 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37603 emit_opcode(cbuf, Assembler::REX_WB);
37604 } else {
37605 emit_opcode(cbuf, Assembler::REX_WXB);
37606 }
37607 }
37608 } else {
37609 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
37610 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37611 emit_opcode(cbuf, Assembler::REX_WR);
37612 } else {
37613 emit_opcode(cbuf, Assembler::REX_WRX);
37614 }
37615 } else {
37616 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37617 emit_opcode(cbuf, Assembler::REX_WRB);
37618 } else {
37619 emit_opcode(cbuf, Assembler::REX_WRXB);
37620 }
37621 }
37622 }
37623
37624#line 37624 "ad_x86.cpp"
37625 }
37626 {
37627
37628#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37629
37630 emit_opcode(cbuf, (0x31 /*primary()*/));
37631
37632#line 37632 "ad_x86.cpp"
37633 }
37634 {
37635
37636#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37637
37638 // High registers handle in encode_RegMem
37639 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
37640 int base = opnd_array(1)->base(ra_,this,idx1);
37641 int index = opnd_array(1)->index(ra_,this,idx1);
37642 int scale = opnd_array(1)->scale();
37643 int disp = opnd_array(1)->disp(ra_,this,idx1);
37644 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
37645
37646 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
37647
37648#line 37648 "ad_x86.cpp"
37649 }
37650}
37651
37652void xorL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37653 cbuf.set_insts_mark();
37654 // Start at oper_input_base() and count operands
37655 unsigned idx0 = 2;
37656 unsigned idx1 = 2; // dst
37657 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
37658 {
37659
37660#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37661
37662 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
37663 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37664 emit_opcode(cbuf, Assembler::REX_WB);
37665 } else {
37666 emit_opcode(cbuf, Assembler::REX_WXB);
37667 }
37668 } else {
37669 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
37670 emit_opcode(cbuf, Assembler::REX_W);
37671 } else {
37672 emit_opcode(cbuf, Assembler::REX_WX);
37673 }
37674 }
37675
37676#line 37676 "ad_x86.cpp"
37677 }
37678 {
37679
37680#line 1993 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37681
37682 // Emit primary opcode and set sign-extend bit
37683 // Check for 8-bit immediate, and set sign extend bit in opcode
37684 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37685 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
37686 } else {
37687 // 32-bit immediate
37688 emit_opcode(cbuf, (0x81 /*primary()*/));
37689 }
37690
37691#line 37691 "ad_x86.cpp"
37692 }
37693 {
37694
37695#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37696
37697 int rm_byte_opcode = (0x6 /*secondary()*/);
37698
37699 // High registers handle in encode_RegMem
37700 int base = opnd_array(1)->base(ra_,this,idx1);
37701 int index = opnd_array(1)->index(ra_,this,idx1);
37702 int scale = opnd_array(1)->scale();
37703 int displace = opnd_array(1)->disp(ra_,this,idx1);
37704
37705 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
37706 // working with static
37707 // globals
37708 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
37709 disp_reloc);
37710
37711#line 37711 "ad_x86.cpp"
37712 }
37713 {
37714
37715#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37716
37717 // Check for 8-bit immediate, and set sign extend bit in opcode
37718 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
37719 emit_d8(cbuf, opnd_array(2)->constantL());
37720 } else {
37721 // 32-bit immediate
37722 emit_d32(cbuf, opnd_array(2)->constantL());
37723 }
37724
37725#line 37725 "ad_x86.cpp"
37726 }
37727}
37728
37729void convI2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37730 cbuf.set_insts_mark();
37731 // Start at oper_input_base() and count operands
37732 unsigned idx0 = 1;
37733 unsigned idx1 = 1; // src
37734 {
37735
37736#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37737
37738 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
37739 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
37740 emit_opcode(cbuf, Assembler::REX_B);
37741 }
37742 } else {
37743 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
37744 emit_opcode(cbuf, Assembler::REX_R);
37745 } else {
37746 emit_opcode(cbuf, Assembler::REX_RB);
37747 }
37748 }
37749
37750#line 37750 "ad_x86.cpp"
37751 }
37752 {
37753
37754#line 1851 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37755
37756 emit_opcode(cbuf, (0x85));
37757 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
37758
37759#line 37759 "ad_x86.cpp"
37760 }
37761 {
37762
37763#line 2621 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37764
37765 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
37766 if (dstenc >= 8) {
37767 emit_opcode(cbuf, Assembler::REX_B);
37768 dstenc -= 8;
37769 } else if (dstenc >= 4) {
37770 emit_opcode(cbuf, Assembler::REX);
37771 }
37772 // SETNZ $dst
37773 emit_opcode(cbuf, 0x0F);
37774 emit_opcode(cbuf, 0x95);
37775 emit_rm(cbuf, 0x3, 0x0, dstenc);
37776
37777#line 37777 "ad_x86.cpp"
37778 }
37779 {
37780
37781#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37782
37783 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37784 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 4) {
37785 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* dst */ < 8 ? Assembler::REX : Assembler::REX_B);
37786 }
37787 } else {
37788 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37789 emit_opcode(cbuf, Assembler::REX_R);
37790 } else {
37791 emit_opcode(cbuf, Assembler::REX_RB);
37792 }
37793 }
37794
37795#line 37795 "ad_x86.cpp"
37796 }
37797 {
37798
37799#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37800
37801 emit_opcode(cbuf, (0x0F));
37802
37803#line 37803 "ad_x86.cpp"
37804 }
37805 {
37806
37807#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37808
37809 emit_opcode(cbuf, (0xB6));
37810
37811#line 37811 "ad_x86.cpp"
37812 }
37813 {
37814
37815#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37816
37817 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
37818
37819#line 37819 "ad_x86.cpp"
37820 }
37821}
37822
37823void convP2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37824 cbuf.set_insts_mark();
37825 // Start at oper_input_base() and count operands
37826 unsigned idx0 = 1;
37827 unsigned idx1 = 1; // src
37828 {
37829
37830#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37831
37832 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
37833 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
37834 emit_opcode(cbuf, Assembler::REX_W);
37835 } else {
37836 emit_opcode(cbuf, Assembler::REX_WB);
37837 }
37838 } else {
37839 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
37840 emit_opcode(cbuf, Assembler::REX_WR);
37841 } else {
37842 emit_opcode(cbuf, Assembler::REX_WRB);
37843 }
37844 }
37845
37846#line 37846 "ad_x86.cpp"
37847 }
37848 {
37849
37850#line 1851 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37851
37852 emit_opcode(cbuf, (0x85));
37853 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
37854
37855#line 37855 "ad_x86.cpp"
37856 }
37857 {
37858
37859#line 2621 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37860
37861 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
37862 if (dstenc >= 8) {
37863 emit_opcode(cbuf, Assembler::REX_B);
37864 dstenc -= 8;
37865 } else if (dstenc >= 4) {
37866 emit_opcode(cbuf, Assembler::REX);
37867 }
37868 // SETNZ $dst
37869 emit_opcode(cbuf, 0x0F);
37870 emit_opcode(cbuf, 0x95);
37871 emit_rm(cbuf, 0x3, 0x0, dstenc);
37872
37873#line 37873 "ad_x86.cpp"
37874 }
37875 {
37876
37877#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37878
37879 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37880 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 4) {
37881 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* dst */ < 8 ? Assembler::REX : Assembler::REX_B);
37882 }
37883 } else {
37884 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37885 emit_opcode(cbuf, Assembler::REX_R);
37886 } else {
37887 emit_opcode(cbuf, Assembler::REX_RB);
37888 }
37889 }
37890
37891#line 37891 "ad_x86.cpp"
37892 }
37893 {
37894
37895#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37896
37897 emit_opcode(cbuf, (0x0F));
37898
37899#line 37899 "ad_x86.cpp"
37900 }
37901 {
37902
37903#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37904
37905 emit_opcode(cbuf, (0xB6));
37906
37907#line 37907 "ad_x86.cpp"
37908 }
37909 {
37910
37911#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37912
37913 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
37914
37915#line 37915 "ad_x86.cpp"
37916 }
37917}
37918
37919void cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37920 cbuf.set_insts_mark();
37921 // Start at oper_input_base() and count operands
37922 unsigned idx0 = 1;
37923 unsigned idx1 = 1; // p
37924 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
37925 {
37926
37927#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37928
37929 if (opnd_array(1)->reg(ra_,this,idx1)/* p */ < 8) {
37930 if (opnd_array(2)->reg(ra_,this,idx2)/* q */ >= 8) {
37931 emit_opcode(cbuf, Assembler::REX_B);
37932 }
37933 } else {
37934 if (opnd_array(2)->reg(ra_,this,idx2)/* q */ < 8) {
37935 emit_opcode(cbuf, Assembler::REX_R);
37936 } else {
37937 emit_opcode(cbuf, Assembler::REX_RB);
37938 }
37939 }
37940
37941#line 37941 "ad_x86.cpp"
37942 }
37943 {
37944
37945#line 1851 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37946
37947 emit_opcode(cbuf, (0x3B));
37948 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* p */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* q */ & 7);
37949
37950#line 37950 "ad_x86.cpp"
37951 }
37952 {
37953
37954#line 2606 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37955
37956 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
37957 if (dstenc >= 8) {
37958 emit_opcode(cbuf, Assembler::REX_B);
37959 dstenc -= 8;
37960 } else if (dstenc >= 4) {
37961 emit_opcode(cbuf, Assembler::REX);
37962 }
37963 // SETLT $dst
37964 emit_opcode(cbuf, 0x0F);
37965 emit_opcode(cbuf, 0x9C);
37966 emit_rm(cbuf, 0x3, 0x0, dstenc);
37967
37968#line 37968 "ad_x86.cpp"
37969 }
37970 {
37971
37972#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37973
37974 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37975 if (opnd_array(0)->reg(ra_,this)/* dst */ >= 4) {
37976 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* dst */ < 8 ? Assembler::REX : Assembler::REX_B);
37977 }
37978 } else {
37979 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
37980 emit_opcode(cbuf, Assembler::REX_R);
37981 } else {
37982 emit_opcode(cbuf, Assembler::REX_RB);
37983 }
37984 }
37985
37986#line 37986 "ad_x86.cpp"
37987 }
37988 {
37989
37990#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37991
37992 emit_opcode(cbuf, (0x0F));
37993
37994#line 37994 "ad_x86.cpp"
37995 }
37996 {
37997
37998#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
37999
38000 emit_opcode(cbuf, (0xB6));
38001
38002#line 38002 "ad_x86.cpp"
38003 }
38004 {
38005
38006#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38007
38008 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* dst */ & 7, opnd_array(0)->reg(ra_,this)/* dst */ & 7);
38009
38010#line 38010 "ad_x86.cpp"
38011 }
38012 {
38013
38014#line 2580 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38015
38016 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
38017 if (dstenc >= 8) {
38018 emit_opcode(cbuf, Assembler::REX_B);
38019 dstenc -= 8;
38020 }
38021 // NEG $dst
38022 emit_opcode(cbuf, 0xF7);
38023 emit_rm(cbuf, 0x3, 0x03, dstenc);
38024
38025#line 38025 "ad_x86.cpp"
38026 }
38027}
38028
38029void cmpLTMask0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38030 cbuf.set_insts_mark();
38031 // Start at oper_input_base() and count operands
38032 unsigned idx0 = 1;
38033 unsigned idx1 = 1; // dst
38034 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
38035 {
38036 MacroAssembler _masm(&cbuf);
38037
38038#line 10309 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38039
38040 __ sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 31);
38041
38042#line 38042 "ad_x86.cpp"
38043 }
38044}
38045
38046void cadd_cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38047 cbuf.set_insts_mark();
38048 // Start at oper_input_base() and count operands
38049 unsigned idx0 = 1;
38050 unsigned idx1 = 1; // p
38051 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
38052 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
38053 {
38054 MacroAssembler _masm(&cbuf);
38055
38056#line 10325 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38057
38058 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
38059 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
38060 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
38061 Label done;
38062 __ subl(Rp, Rq);
38063 __ jccb(Assembler::greaterEqual, done);
38064 __ addl(Rp, Ry);
38065 __ bind(done);
38066
38067#line 38067 "ad_x86.cpp"
38068 }
38069}
38070
38071void cadd_cmpLTMask_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38072 cbuf.set_insts_mark();
38073 // Start at oper_input_base() and count operands
38074 unsigned idx0 = 1;
38075 unsigned idx1 = 1; // p
38076 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
38077 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
38078 {
38079 MacroAssembler _masm(&cbuf);
38080
38081#line 10325 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38082
38083 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
38084 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
38085 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
38086 Label done;
38087 __ subl(Rp, Rq);
38088 __ jccb(Assembler::greaterEqual, done);
38089 __ addl(Rp, Ry);
38090 __ bind(done);
38091
38092#line 38092 "ad_x86.cpp"
38093 }
38094}
38095
38096void cadd_cmpLTMask_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38097 cbuf.set_insts_mark();
38098 // Start at oper_input_base() and count operands
38099 unsigned idx0 = 1;
38100 unsigned idx1 = 1; // y
38101 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
38102 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
38103 {
38104 MacroAssembler _masm(&cbuf);
38105
38106#line 10325 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38107
38108 Register Rp = opnd_array(2)->as_Register(ra_,this,idx2)/* p */;
38109 Register Rq = opnd_array(3)->as_Register(ra_,this,idx3)/* q */;
38110 Register Ry = opnd_array(1)->as_Register(ra_,this,idx1)/* y */;
38111 Label done;
38112 __ subl(Rp, Rq);
38113 __ jccb(Assembler::greaterEqual, done);
38114 __ addl(Rp, Ry);
38115 __ bind(done);
38116
38117#line 38117 "ad_x86.cpp"
38118 }
38119}
38120
38121void cadd_cmpLTMask_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38122 cbuf.set_insts_mark();
38123 // Start at oper_input_base() and count operands
38124 unsigned idx0 = 1;
38125 unsigned idx1 = 1; // p
38126 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
38127 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
38128 {
38129 MacroAssembler _masm(&cbuf);
38130
38131#line 10325 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38132
38133 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
38134 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
38135 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
38136 Label done;
38137 __ subl(Rp, Rq);
38138 __ jccb(Assembler::greaterEqual, done);
38139 __ addl(Rp, Ry);
38140 __ bind(done);
38141
38142#line 38142 "ad_x86.cpp"
38143 }
38144}
38145
38146void and_cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38147 cbuf.set_insts_mark();
38148 // Start at oper_input_base() and count operands
38149 unsigned idx0 = 1;
38150 unsigned idx1 = 1; // p
38151 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
38152 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
38153 {
38154 MacroAssembler _masm(&cbuf);
38155
38156#line 10350 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38157
38158 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
38159 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
38160 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
38161 Label done;
38162 __ cmpl(Rp, Rq);
38163 __ jccb(Assembler::less, done);
38164 __ xorl(Ry, Ry);
38165 __ bind(done);
38166
38167#line 38167 "ad_x86.cpp"
38168 }
38169}
38170
38171void and_cmpLTMask_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38172 cbuf.set_insts_mark();
38173 // Start at oper_input_base() and count operands
38174 unsigned idx0 = 1;
38175 unsigned idx1 = 1; // y
38176 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
38177 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
38178 {
38179 MacroAssembler _masm(&cbuf);
38180
38181#line 10350 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38182
38183 Register Rp = opnd_array(2)->as_Register(ra_,this,idx2)/* p */;
38184 Register Rq = opnd_array(3)->as_Register(ra_,this,idx3)/* q */;
38185 Register Ry = opnd_array(1)->as_Register(ra_,this,idx1)/* y */;
38186 Label done;
38187 __ cmpl(Rp, Rq);
38188 __ jccb(Assembler::less, done);
38189 __ xorl(Ry, Ry);
38190 __ bind(done);
38191
38192#line 38192 "ad_x86.cpp"
38193 }
38194}
38195
38196void cmpF_cc_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38197 cbuf.set_insts_mark();
38198 // Start at oper_input_base() and count operands
38199 unsigned idx0 = 1;
38200 unsigned idx1 = 1; // src1
38201 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38202 {
38203 MacroAssembler _masm(&cbuf);
38204
38205#line 10377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38206
38207 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38208 emit_cmpfp_fixup(_masm);
38209
38210#line 38210 "ad_x86.cpp"
38211 }
38212}
38213
38214void cmpF_cc_reg_CFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38215 cbuf.set_insts_mark();
38216 // Start at oper_input_base() and count operands
38217 unsigned idx0 = 1;
38218 unsigned idx1 = 1; // src1
38219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38220 {
38221 MacroAssembler _masm(&cbuf);
38222
38223#line 10389 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38224
38225 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38226
38227#line 38227 "ad_x86.cpp"
38228 }
38229}
38230
38231void cmpF_cc_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38232 cbuf.set_insts_mark();
38233 // Start at oper_input_base() and count operands
38234 unsigned idx0 = 2;
38235 unsigned idx1 = 2; // src1
38236 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38237 {
38238 MacroAssembler _masm(&cbuf);
38239
38240#line 10406 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38241
38242 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38243 emit_cmpfp_fixup(_masm);
38244
38245#line 38245 "ad_x86.cpp"
38246 }
38247}
38248
38249void cmpF_cc_memCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38250 cbuf.set_insts_mark();
38251 // Start at oper_input_base() and count operands
38252 unsigned idx0 = 2;
38253 unsigned idx1 = 2; // src1
38254 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38255 {
38256 MacroAssembler _masm(&cbuf);
38257
38258#line 10418 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38259
38260 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38261
38262#line 38262 "ad_x86.cpp"
38263 }
38264}
38265
38266void cmpF_cc_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38267 cbuf.set_insts_mark();
38268 // Start at oper_input_base() and count operands
38269 unsigned idx0 = 1;
38270 unsigned idx1 = 1; // src
38271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38272 {
38273 MacroAssembler _masm(&cbuf);
38274
38275#line 10434 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38276
38277 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38278 emit_cmpfp_fixup(_masm);
38279
38280#line 38280 "ad_x86.cpp"
38281 }
38282}
38283
38284void cmpF_cc_immNode::eval_constant(Compile* C) {
38285 {
38286
38287#line 10435 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38288 _constant = C->constant_table().add(this, opnd_array(2));
38289#line 38289 "ad_x86.cpp"
38290 }
38291}
38292void cmpF_cc_immCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38293 cbuf.set_insts_mark();
38294 // Start at oper_input_base() and count operands
38295 unsigned idx0 = 1;
38296 unsigned idx1 = 1; // src
38297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38298 {
38299 MacroAssembler _masm(&cbuf);
38300
38301#line 10445 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38302
38303 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38304
38305#line 38305 "ad_x86.cpp"
38306 }
38307}
38308
38309void cmpF_cc_immCFNode::eval_constant(Compile* C) {
38310 {
38311
38312#line 10446 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38313 _constant = C->constant_table().add(this, opnd_array(2));
38314#line 38314 "ad_x86.cpp"
38315 }
38316}
38317void cmpD_cc_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38318 cbuf.set_insts_mark();
38319 // Start at oper_input_base() and count operands
38320 unsigned idx0 = 1;
38321 unsigned idx1 = 1; // src1
38322 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38323 {
38324 MacroAssembler _masm(&cbuf);
38325
38326#line 10462 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38327
38328 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38329 emit_cmpfp_fixup(_masm);
38330
38331#line 38331 "ad_x86.cpp"
38332 }
38333}
38334
38335void cmpD_cc_reg_CFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38336 cbuf.set_insts_mark();
38337 // Start at oper_input_base() and count operands
38338 unsigned idx0 = 1;
38339 unsigned idx1 = 1; // src1
38340 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38341 {
38342 MacroAssembler _masm(&cbuf);
38343
38344#line 10474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38345
38346 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38347
38348#line 38348 "ad_x86.cpp"
38349 }
38350}
38351
38352void cmpD_cc_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38353 cbuf.set_insts_mark();
38354 // Start at oper_input_base() and count operands
38355 unsigned idx0 = 2;
38356 unsigned idx1 = 2; // src1
38357 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38358 {
38359 MacroAssembler _masm(&cbuf);
38360
38361#line 10491 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38362
38363 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38364 emit_cmpfp_fixup(_masm);
38365
38366#line 38366 "ad_x86.cpp"
38367 }
38368}
38369
38370void cmpD_cc_memCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38371 cbuf.set_insts_mark();
38372 // Start at oper_input_base() and count operands
38373 unsigned idx0 = 2;
38374 unsigned idx1 = 2; // src1
38375 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38376 {
38377 MacroAssembler _masm(&cbuf);
38378
38379#line 10503 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38380
38381 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38382
38383#line 38383 "ad_x86.cpp"
38384 }
38385}
38386
38387void cmpD_cc_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38388 cbuf.set_insts_mark();
38389 // Start at oper_input_base() and count operands
38390 unsigned idx0 = 1;
38391 unsigned idx1 = 1; // src
38392 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38393 {
38394 MacroAssembler _masm(&cbuf);
38395
38396#line 10519 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38397
38398 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38399 emit_cmpfp_fixup(_masm);
38400
38401#line 38401 "ad_x86.cpp"
38402 }
38403}
38404
38405void cmpD_cc_immNode::eval_constant(Compile* C) {
38406 {
38407
38408#line 10520 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38409 _constant = C->constant_table().add(this, opnd_array(2));
38410#line 38410 "ad_x86.cpp"
38411 }
38412}
38413void cmpD_cc_immCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38414 cbuf.set_insts_mark();
38415 // Start at oper_input_base() and count operands
38416 unsigned idx0 = 1;
38417 unsigned idx1 = 1; // src
38418 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38419 {
38420 MacroAssembler _masm(&cbuf);
38421
38422#line 10530 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38423
38424 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38425
38426#line 38426 "ad_x86.cpp"
38427 }
38428}
38429
38430void cmpD_cc_immCFNode::eval_constant(Compile* C) {
38431 {
38432
38433#line 10531 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38434 _constant = C->constant_table().add(this, opnd_array(2));
38435#line 38435 "ad_x86.cpp"
38436 }
38437}
38438void cmpF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38439 cbuf.set_insts_mark();
38440 // Start at oper_input_base() and count operands
38441 unsigned idx0 = 1;
38442 unsigned idx1 = 1; // src1
38443 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38444 {
38445 MacroAssembler _masm(&cbuf);
38446
38447#line 10550 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38448
38449 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38450 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38451
38452#line 38452 "ad_x86.cpp"
38453 }
38454}
38455
38456void cmpF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38457 cbuf.set_insts_mark();
38458 // Start at oper_input_base() and count operands
38459 unsigned idx0 = 2;
38460 unsigned idx1 = 2; // src1
38461 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38462 {
38463 MacroAssembler _masm(&cbuf);
38464
38465#line 10571 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38466
38467 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38468 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38469
38470#line 38470 "ad_x86.cpp"
38471 }
38472}
38473
38474void cmpF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38475 cbuf.set_insts_mark();
38476 // Start at oper_input_base() and count operands
38477 unsigned idx0 = 1;
38478 unsigned idx1 = 1; // src
38479 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38480 {
38481 MacroAssembler _masm(&cbuf);
38482
38483#line 10591 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38484
38485 __ ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38486 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38487
38488#line 38488 "ad_x86.cpp"
38489 }
38490}
38491
38492void cmpF_immNode::eval_constant(Compile* C) {
38493 {
38494
38495#line 10592 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38496 _constant = C->constant_table().add(this, opnd_array(2));
38497#line 38497 "ad_x86.cpp"
38498 }
38499}
38500void cmpD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38501 cbuf.set_insts_mark();
38502 // Start at oper_input_base() and count operands
38503 unsigned idx0 = 1;
38504 unsigned idx1 = 1; // src1
38505 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38506 {
38507 MacroAssembler _masm(&cbuf);
38508
38509#line 10612 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38510
38511 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
38512 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38513
38514#line 38514 "ad_x86.cpp"
38515 }
38516}
38517
38518void cmpD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38519 cbuf.set_insts_mark();
38520 // Start at oper_input_base() and count operands
38521 unsigned idx0 = 2;
38522 unsigned idx1 = 2; // src1
38523 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38524 {
38525 MacroAssembler _masm(&cbuf);
38526
38527#line 10633 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38528
38529 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
38530 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38531
38532#line 38532 "ad_x86.cpp"
38533 }
38534}
38535
38536void cmpD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38537 cbuf.set_insts_mark();
38538 // Start at oper_input_base() and count operands
38539 unsigned idx0 = 1;
38540 unsigned idx1 = 1; // src
38541 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
38542 {
38543 MacroAssembler _masm(&cbuf);
38544
38545#line 10653 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38546
38547 __ ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
38548 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
38549
38550#line 38550 "ad_x86.cpp"
38551 }
38552}
38553
38554void cmpD_immNode::eval_constant(Compile* C) {
38555 {
38556
38557#line 10654 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38558 _constant = C->constant_table().add(this, opnd_array(2));
38559#line 38559 "ad_x86.cpp"
38560 }
38561}
38562void roundFloat_nopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38563 cbuf.set_insts_mark();
38564 // Start at oper_input_base() and count operands
38565 unsigned idx0 = 1;
38566 unsigned idx1 = 1; // dst
38567 // User did not define which encode class to use.
38568}
38569
38570void roundDouble_nopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38571 cbuf.set_insts_mark();
38572 // Start at oper_input_base() and count operands
38573 unsigned idx0 = 1;
38574 unsigned idx1 = 1; // dst
38575 // User did not define which encode class to use.
38576}
38577
38578void convF2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38579 cbuf.set_insts_mark();
38580 // Start at oper_input_base() and count operands
38581 unsigned idx0 = 1;
38582 unsigned idx1 = 1; // src
38583 {
38584 MacroAssembler _masm(&cbuf);
38585
38586#line 10685 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38587
38588 __ cvtss2sd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38589
38590#line 38590 "ad_x86.cpp"
38591 }
38592}
38593
38594void convF2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38595 cbuf.set_insts_mark();
38596 // Start at oper_input_base() and count operands
38597 unsigned idx0 = 2;
38598 unsigned idx1 = 2; // src
38599 {
38600 MacroAssembler _masm(&cbuf);
38601
38602#line 10696 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38603
38604 __ cvtss2sd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38605
38606#line 38606 "ad_x86.cpp"
38607 }
38608}
38609
38610void convD2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38611 cbuf.set_insts_mark();
38612 // Start at oper_input_base() and count operands
38613 unsigned idx0 = 1;
38614 unsigned idx1 = 1; // src
38615 {
38616 MacroAssembler _masm(&cbuf);
38617
38618#line 10707 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38619
38620 __ cvtsd2ss (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38621
38622#line 38622 "ad_x86.cpp"
38623 }
38624}
38625
38626void convD2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38627 cbuf.set_insts_mark();
38628 // Start at oper_input_base() and count operands
38629 unsigned idx0 = 2;
38630 unsigned idx1 = 2; // src
38631 {
38632 MacroAssembler _masm(&cbuf);
38633
38634#line 10718 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38635
38636 __ cvtsd2ss (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38637
38638#line 38638 "ad_x86.cpp"
38639 }
38640}
38641
38642void convF2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38643 cbuf.set_insts_mark();
38644 // Start at oper_input_base() and count operands
38645 unsigned idx0 = 1;
38646 unsigned idx1 = 1; // src
38647 {
38648 MacroAssembler _masm(&cbuf);
38649
38650#line 10738 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38651
38652 Label done;
38653 __ cvttss2sil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38654 __ cmpl(opnd_array(0)->as_Register(ra_,this)/* dst */, 0x80000000);
38655 __ jccb(Assembler::notEqual, done);
38656 __ subptr(rsp, 8);
38657 __ movflt(Address(rsp, 0), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38658 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
38659 __ pop(opnd_array(0)->as_Register(ra_,this)/* dst */);
38660 __ bind(done);
38661
38662#line 38662 "ad_x86.cpp"
38663 }
38664}
38665
38666void convF2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38667 cbuf.set_insts_mark();
38668 // Start at oper_input_base() and count operands
38669 unsigned idx0 = 1;
38670 unsigned idx1 = 1; // src
38671 {
38672 MacroAssembler _masm(&cbuf);
38673
38674#line 10765 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38675
38676 Label done;
38677 __ cvttss2siq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38678 __ cmp64(opnd_array(0)->as_Register(ra_,this)/* dst */,
38679 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
38680 __ jccb(Assembler::notEqual, done);
38681 __ subptr(rsp, 8);
38682 __ movflt(Address(rsp, 0), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38683 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
38684 __ pop(opnd_array(0)->as_Register(ra_,this)/* dst */);
38685 __ bind(done);
38686
38687#line 38687 "ad_x86.cpp"
38688 }
38689}
38690
38691void convD2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38692 cbuf.set_insts_mark();
38693 // Start at oper_input_base() and count operands
38694 unsigned idx0 = 1;
38695 unsigned idx1 = 1; // src
38696 {
38697 MacroAssembler _masm(&cbuf);
38698
38699#line 10793 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38700
38701 Label done;
38702 __ cvttsd2sil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38703 __ cmpl(opnd_array(0)->as_Register(ra_,this)/* dst */, 0x80000000);
38704 __ jccb(Assembler::notEqual, done);
38705 __ subptr(rsp, 8);
38706 __ movdbl(Address(rsp, 0), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38707 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
38708 __ pop(opnd_array(0)->as_Register(ra_,this)/* dst */);
38709 __ bind(done);
38710
38711#line 38711 "ad_x86.cpp"
38712 }
38713}
38714
38715void convD2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38716 cbuf.set_insts_mark();
38717 // Start at oper_input_base() and count operands
38718 unsigned idx0 = 1;
38719 unsigned idx1 = 1; // src
38720 {
38721 MacroAssembler _masm(&cbuf);
38722
38723#line 10820 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38724
38725 Label done;
38726 __ cvttsd2siq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38727 __ cmp64(opnd_array(0)->as_Register(ra_,this)/* dst */,
38728 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
38729 __ jccb(Assembler::notEqual, done);
38730 __ subptr(rsp, 8);
38731 __ movdbl(Address(rsp, 0), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38732 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
38733 __ pop(opnd_array(0)->as_Register(ra_,this)/* dst */);
38734 __ bind(done);
38735
38736#line 38736 "ad_x86.cpp"
38737 }
38738}
38739
38740void convI2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38741 cbuf.set_insts_mark();
38742 // Start at oper_input_base() and count operands
38743 unsigned idx0 = 1;
38744 unsigned idx1 = 1; // src
38745 {
38746 MacroAssembler _masm(&cbuf);
38747
38748#line 10841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38749
38750 __ cvtsi2ssl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38751
38752#line 38752 "ad_x86.cpp"
38753 }
38754}
38755
38756void convI2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38757 cbuf.set_insts_mark();
38758 // Start at oper_input_base() and count operands
38759 unsigned idx0 = 2;
38760 unsigned idx1 = 2; // src
38761 {
38762 MacroAssembler _masm(&cbuf);
38763
38764#line 10852 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38765
38766 __ cvtsi2ssl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38767
38768#line 38768 "ad_x86.cpp"
38769 }
38770}
38771
38772void convI2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38773 cbuf.set_insts_mark();
38774 // Start at oper_input_base() and count operands
38775 unsigned idx0 = 1;
38776 unsigned idx1 = 1; // src
38777 {
38778 MacroAssembler _masm(&cbuf);
38779
38780#line 10864 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38781
38782 __ cvtsi2sdl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38783
38784#line 38784 "ad_x86.cpp"
38785 }
38786}
38787
38788void convI2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38789 cbuf.set_insts_mark();
38790 // Start at oper_input_base() and count operands
38791 unsigned idx0 = 2;
38792 unsigned idx1 = 2; // src
38793 {
38794 MacroAssembler _masm(&cbuf);
38795
38796#line 10875 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38797
38798 __ cvtsi2sdl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38799
38800#line 38800 "ad_x86.cpp"
38801 }
38802}
38803
38804void convXI2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38805 cbuf.set_insts_mark();
38806 // Start at oper_input_base() and count operands
38807 unsigned idx0 = 1;
38808 unsigned idx1 = 1; // src
38809 {
38810 MacroAssembler _masm(&cbuf);
38811
38812#line 10888 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38813
38814 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38815 __ cvtdq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
38816
38817#line 38817 "ad_x86.cpp"
38818 }
38819}
38820
38821void convXI2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38822 cbuf.set_insts_mark();
38823 // Start at oper_input_base() and count operands
38824 unsigned idx0 = 1;
38825 unsigned idx1 = 1; // src
38826 {
38827 MacroAssembler _masm(&cbuf);
38828
38829#line 10902 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38830
38831 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38832 __ cvtdq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
38833
38834#line 38834 "ad_x86.cpp"
38835 }
38836}
38837
38838void convL2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38839 cbuf.set_insts_mark();
38840 // Start at oper_input_base() and count operands
38841 unsigned idx0 = 1;
38842 unsigned idx1 = 1; // src
38843 {
38844 MacroAssembler _masm(&cbuf);
38845
38846#line 10914 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38847
38848 __ cvtsi2ssq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38849
38850#line 38850 "ad_x86.cpp"
38851 }
38852}
38853
38854void convL2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38855 cbuf.set_insts_mark();
38856 // Start at oper_input_base() and count operands
38857 unsigned idx0 = 2;
38858 unsigned idx1 = 2; // src
38859 {
38860 MacroAssembler _masm(&cbuf);
38861
38862#line 10925 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38863
38864 __ cvtsi2ssq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38865
38866#line 38866 "ad_x86.cpp"
38867 }
38868}
38869
38870void convL2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38871 cbuf.set_insts_mark();
38872 // Start at oper_input_base() and count operands
38873 unsigned idx0 = 1;
38874 unsigned idx1 = 1; // src
38875 {
38876 MacroAssembler _masm(&cbuf);
38877
38878#line 10936 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38879
38880 __ cvtsi2sdq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38881
38882#line 38882 "ad_x86.cpp"
38883 }
38884}
38885
38886void convL2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38887 cbuf.set_insts_mark();
38888 // Start at oper_input_base() and count operands
38889 unsigned idx0 = 2;
38890 unsigned idx1 = 2; // src
38891 {
38892 MacroAssembler _masm(&cbuf);
38893
38894#line 10947 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38895
38896 __ cvtsi2sdq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38897
38898#line 38898 "ad_x86.cpp"
38899 }
38900}
38901
38902void convI2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38903 cbuf.set_insts_mark();
38904 // Start at oper_input_base() and count operands
38905 unsigned idx0 = 1;
38906 unsigned idx1 = 1; // src
38907 {
38908 MacroAssembler _masm(&cbuf);
38909
38910#line 10959 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38911
38912 __ movslq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38913
38914#line 38914 "ad_x86.cpp"
38915 }
38916}
38917
38918void convI2L_reg_reg_zexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38919 cbuf.set_insts_mark();
38920 // Start at oper_input_base() and count operands
38921 unsigned idx0 = 1;
38922 unsigned idx1 = 1; // src
38923 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
38924 {
38925 MacroAssembler _masm(&cbuf);
38926
38927#line 10988 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38928
38929 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
38930 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38931 }
38932
38933#line 38933 "ad_x86.cpp"
38934 }
38935}
38936
38937void convI2L_reg_mem_zexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38938 cbuf.set_insts_mark();
38939 // Start at oper_input_base() and count operands
38940 unsigned idx0 = 2;
38941 unsigned idx1 = 2; // src
38942 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
38943 {
38944 MacroAssembler _masm(&cbuf);
38945
38946#line 11002 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38947
38948 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
38949
38950#line 38950 "ad_x86.cpp"
38951 }
38952}
38953
38954void zerox_long_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38955 cbuf.set_insts_mark();
38956 // Start at oper_input_base() and count operands
38957 unsigned idx0 = 1;
38958 unsigned idx1 = 1; // src
38959 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
38960 {
38961 MacroAssembler _masm(&cbuf);
38962
38963#line 11013 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38964
38965 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38966
38967#line 38967 "ad_x86.cpp"
38968 }
38969}
38970
38971void convL2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38972 cbuf.set_insts_mark();
38973 // Start at oper_input_base() and count operands
38974 unsigned idx0 = 1;
38975 unsigned idx1 = 1; // src
38976 {
38977 MacroAssembler _masm(&cbuf);
38978
38979#line 11024 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38980
38981 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
38982
38983#line 38983 "ad_x86.cpp"
38984 }
38985}
38986
38987void MoveF2I_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38988 cbuf.set_insts_mark();
38989 // Start at oper_input_base() and count operands
38990 unsigned idx0 = 1;
38991 unsigned idx1 = 1; // src
38992 {
38993 MacroAssembler _masm(&cbuf);
38994
38995#line 11037 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
38996
38997 __ movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
38998
38999#line 38999 "ad_x86.cpp"
39000 }
39001}
39002
39003void MoveI2F_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39004 cbuf.set_insts_mark();
39005 // Start at oper_input_base() and count operands
39006 unsigned idx0 = 1;
39007 unsigned idx1 = 1; // src
39008 {
39009 MacroAssembler _masm(&cbuf);
39010
39011#line 11049 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39012
39013 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
39014
39015#line 39015 "ad_x86.cpp"
39016 }
39017}
39018
39019void MoveD2L_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39020 cbuf.set_insts_mark();
39021 // Start at oper_input_base() and count operands
39022 unsigned idx0 = 1;
39023 unsigned idx1 = 1; // src
39024 {
39025 MacroAssembler _masm(&cbuf);
39026
39027#line 11061 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39028
39029 __ movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
39030
39031#line 39031 "ad_x86.cpp"
39032 }
39033}
39034
39035void MoveL2D_stack_reg_partialNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39036 cbuf.set_insts_mark();
39037 // Start at oper_input_base() and count operands
39038 unsigned idx0 = 1;
39039 unsigned idx1 = 1; // src
39040 {
39041 MacroAssembler _masm(&cbuf);
39042
39043#line 11074 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39044
39045 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
39046
39047#line 39047 "ad_x86.cpp"
39048 }
39049}
39050
39051void MoveL2D_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39052 cbuf.set_insts_mark();
39053 // Start at oper_input_base() and count operands
39054 unsigned idx0 = 1;
39055 unsigned idx1 = 1; // src
39056 {
39057 MacroAssembler _masm(&cbuf);
39058
39059#line 11087 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39060
39061 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
39062
39063#line 39063 "ad_x86.cpp"
39064 }
39065}
39066
39067void MoveF2I_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39068 cbuf.set_insts_mark();
39069 // Start at oper_input_base() and count operands
39070 unsigned idx0 = 1;
39071 unsigned idx1 = 1; // src
39072 {
39073 MacroAssembler _masm(&cbuf);
39074
39075#line 11100 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39076
39077 __ movflt(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
39078
39079#line 39079 "ad_x86.cpp"
39080 }
39081}
39082
39083void MoveI2F_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39084 cbuf.set_insts_mark();
39085 // Start at oper_input_base() and count operands
39086 unsigned idx0 = 1;
39087 unsigned idx1 = 1; // src
39088 {
39089 MacroAssembler _masm(&cbuf);
39090
39091#line 11112 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39092
39093 __ movl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
39094
39095#line 39095 "ad_x86.cpp"
39096 }
39097}
39098
39099void MoveD2L_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39100 cbuf.set_insts_mark();
39101 // Start at oper_input_base() and count operands
39102 unsigned idx0 = 1;
39103 unsigned idx1 = 1; // src
39104 {
39105 MacroAssembler _masm(&cbuf);
39106
39107#line 11124 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39108
39109 __ movdbl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
39110
39111#line 39111 "ad_x86.cpp"
39112 }
39113}
39114
39115void MoveL2D_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39116 cbuf.set_insts_mark();
39117 // Start at oper_input_base() and count operands
39118 unsigned idx0 = 1;
39119 unsigned idx1 = 1; // src
39120 {
39121 MacroAssembler _masm(&cbuf);
39122
39123#line 11136 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39124
39125 __ movq(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
39126
39127#line 39127 "ad_x86.cpp"
39128 }
39129}
39130
39131void MoveF2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39132 cbuf.set_insts_mark();
39133 // Start at oper_input_base() and count operands
39134 unsigned idx0 = 1;
39135 unsigned idx1 = 1; // src
39136 {
39137 MacroAssembler _masm(&cbuf);
39138
39139#line 11147 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39140
39141 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
39142
39143#line 39143 "ad_x86.cpp"
39144 }
39145}
39146
39147void MoveD2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39148 cbuf.set_insts_mark();
39149 // Start at oper_input_base() and count operands
39150 unsigned idx0 = 1;
39151 unsigned idx1 = 1; // src
39152 {
39153 MacroAssembler _masm(&cbuf);
39154
39155#line 11158 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39156
39157 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
39158
39159#line 39159 "ad_x86.cpp"
39160 }
39161}
39162
39163void MoveI2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39164 cbuf.set_insts_mark();
39165 // Start at oper_input_base() and count operands
39166 unsigned idx0 = 1;
39167 unsigned idx1 = 1; // src
39168 {
39169 MacroAssembler _masm(&cbuf);
39170
39171#line 11169 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39172
39173 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
39174
39175#line 39175 "ad_x86.cpp"
39176 }
39177}
39178
39179void MoveL2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39180 cbuf.set_insts_mark();
39181 // Start at oper_input_base() and count operands
39182 unsigned idx0 = 1;
39183 unsigned idx1 = 1; // src
39184 {
39185 MacroAssembler _masm(&cbuf);
39186
39187#line 11180 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39188
39189 __ movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
39190
39191#line 39191 "ad_x86.cpp"
39192 }
39193}
39194
39195void rep_stosNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39196 cbuf.set_insts_mark();
39197 // Start at oper_input_base() and count operands
39198 unsigned idx0 = 2;
39199 unsigned idx1 = 2; // cnt
39200 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
39201 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
39202 {
39203 MacroAssembler _masm(&cbuf);
39204
39205#line 11241 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39206
39207 __ clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
39208 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, false);
39209
39210#line 39210 "ad_x86.cpp"
39211 }
39212}
39213
39214void rep_stos_largeNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39215 cbuf.set_insts_mark();
39216 // Start at oper_input_base() and count operands
39217 unsigned idx0 = 2;
39218 unsigned idx1 = 2; // cnt
39219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
39220 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
39221 {
39222 MacroAssembler _masm(&cbuf);
39223
39224#line 11291 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39225
39226 __ clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
39227 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, true);
39228
39229#line 39229 "ad_x86.cpp"
39230 }
39231}
39232
39233void string_compareLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39234 cbuf.set_insts_mark();
39235 // Start at oper_input_base() and count operands
39236 unsigned idx0 = 2;
39237 unsigned idx1 = 2; // str1
39238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39239 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39240 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39241 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
39242 {
39243 MacroAssembler _masm(&cbuf);
39244
39245#line 11306 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39246
39247 __ string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39248 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
39249 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LL);
39250
39251#line 39251 "ad_x86.cpp"
39252 }
39253}
39254
39255void string_compareUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39256 cbuf.set_insts_mark();
39257 // Start at oper_input_base() and count operands
39258 unsigned idx0 = 2;
39259 unsigned idx1 = 2; // str1
39260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39261 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39262 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39263 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
39264 {
39265 MacroAssembler _masm(&cbuf);
39266
39267#line 11322 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39268
39269 __ string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39270 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
39271 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UU);
39272
39273#line 39273 "ad_x86.cpp"
39274 }
39275}
39276
39277void string_compareLUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39278 cbuf.set_insts_mark();
39279 // Start at oper_input_base() and count operands
39280 unsigned idx0 = 2;
39281 unsigned idx1 = 2; // str1
39282 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39283 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39284 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39285 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
39286 {
39287 MacroAssembler _masm(&cbuf);
39288
39289#line 11338 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39290
39291 __ string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39292 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
39293 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LU);
39294
39295#line 39295 "ad_x86.cpp"
39296 }
39297}
39298
39299void string_compareULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39300 cbuf.set_insts_mark();
39301 // Start at oper_input_base() and count operands
39302 unsigned idx0 = 2;
39303 unsigned idx1 = 2; // str1
39304 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39305 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39306 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39307 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
39308 {
39309 MacroAssembler _masm(&cbuf);
39310
39311#line 11354 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39312
39313 __ string_compare(opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */,
39314 opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(0)->as_Register(ra_,this)/* result */,
39315 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UL);
39316
39317#line 39317 "ad_x86.cpp"
39318 }
39319}
39320
39321void string_indexof_conLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39322 cbuf.set_insts_mark();
39323 // Start at oper_input_base() and count operands
39324 unsigned idx0 = 2;
39325 unsigned idx1 = 2; // str1
39326 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39327 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39328 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
39329 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39330 {
39331 MacroAssembler _masm(&cbuf);
39332
39333#line 11371 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39334
39335 int icnt2 = (int)opnd_array(4)->constant();
39336 if (icnt2 >= 16) {
39337 // IndexOf for constant substrings with size >= 16 elements
39338 // which don't need to be loaded through stack.
39339 __ string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39340 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39341 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39342 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
39343 } else {
39344 // Small strings are loaded through stack if they cross page boundary.
39345 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39346 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39347 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39348 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
39349 }
39350
39351#line 39351 "ad_x86.cpp"
39352 }
39353}
39354
39355void string_indexof_conUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39356 cbuf.set_insts_mark();
39357 // Start at oper_input_base() and count operands
39358 unsigned idx0 = 2;
39359 unsigned idx1 = 2; // str1
39360 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39361 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39362 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
39363 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39364 {
39365 MacroAssembler _masm(&cbuf);
39366
39367#line 11400 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39368
39369 int icnt2 = (int)opnd_array(4)->constant();
39370 if (icnt2 >= 8) {
39371 // IndexOf for constant substrings with size >= 8 elements
39372 // which don't need to be loaded through stack.
39373 __ string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39374 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39375 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39376 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
39377 } else {
39378 // Small strings are loaded through stack if they cross page boundary.
39379 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39380 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39381 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39382 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
39383 }
39384
39385#line 39385 "ad_x86.cpp"
39386 }
39387}
39388
39389void string_indexof_conULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39390 cbuf.set_insts_mark();
39391 // Start at oper_input_base() and count operands
39392 unsigned idx0 = 2;
39393 unsigned idx1 = 2; // str1
39394 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39395 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39396 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
39397 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39398 {
39399 MacroAssembler _masm(&cbuf);
39400
39401#line 11429 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39402
39403 int icnt2 = (int)opnd_array(4)->constant();
39404 if (icnt2 >= 8) {
39405 // IndexOf for constant substrings with size >= 8 elements
39406 // which don't need to be loaded through stack.
39407 __ string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39408 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39409 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39410 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
39411 } else {
39412 // Small strings are loaded through stack if they cross page boundary.
39413 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39414 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
39415 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
39416 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
39417 }
39418
39419#line 39419 "ad_x86.cpp"
39420 }
39421}
39422
39423void string_indexofLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39424 cbuf.set_insts_mark();
39425 // Start at oper_input_base() and count operands
39426 unsigned idx0 = 2;
39427 unsigned idx1 = 2; // str1
39428 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39429 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39430 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39431 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39432 {
39433 MacroAssembler _masm(&cbuf);
39434
39435#line 11457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39436
39437 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39438 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
39439 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
39440 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
39441
39442#line 39442 "ad_x86.cpp"
39443 }
39444}
39445
39446void string_indexofUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39447 cbuf.set_insts_mark();
39448 // Start at oper_input_base() and count operands
39449 unsigned idx0 = 2;
39450 unsigned idx1 = 2; // str1
39451 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39452 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39453 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39454 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39455 {
39456 MacroAssembler _masm(&cbuf);
39457
39458#line 11474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39459
39460 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39461 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
39462 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
39463 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
39464
39465#line 39465 "ad_x86.cpp"
39466 }
39467}
39468
39469void string_indexofULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39470 cbuf.set_insts_mark();
39471 // Start at oper_input_base() and count operands
39472 unsigned idx0 = 2;
39473 unsigned idx1 = 2; // str1
39474 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39475 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
39476 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
39477 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
39478 {
39479 MacroAssembler _masm(&cbuf);
39480
39481#line 11491 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39482
39483 __ string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
39484 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
39485 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
39486 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
39487
39488#line 39488 "ad_x86.cpp"
39489 }
39490}
39491
39492void string_indexofU_charNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39493 cbuf.set_insts_mark();
39494 // Start at oper_input_base() and count operands
39495 unsigned idx0 = 2;
39496 unsigned idx1 = 2; // str1
39497 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
39498 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch
39499 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vec1
39500 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec2
39501 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vec3
39502 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp
39503 {
39504 MacroAssembler _masm(&cbuf);
39505
39506#line 11507 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39507
39508 __ string_indexof_char(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* ch */, opnd_array(0)->as_Register(ra_,this)/* result */,
39509 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vec1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vec2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vec3 */, opnd_array(7)->as_Register(ra_,this,idx7)/* tmp */);
39510
39511#line 39511 "ad_x86.cpp"
39512 }
39513}
39514
39515void string_equalsNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39516 cbuf.set_insts_mark();
39517 // Start at oper_input_base() and count operands
39518 unsigned idx0 = 2;
39519 unsigned idx1 = 2; // str1
39520 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2
39521 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt
39522 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
39523 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
39524 {
39525 MacroAssembler _masm(&cbuf);
39526
39527#line 11522 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39528
39529 __ arrays_equals(false, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* str2 */,
39530 opnd_array(3)->as_Register(ra_,this,idx3)/* cnt */, opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
39531 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, false /* char */);
39532
39533#line 39533 "ad_x86.cpp"
39534 }
39535}
39536
39537void array_equalsBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39538 cbuf.set_insts_mark();
39539 // Start at oper_input_base() and count operands
39540 unsigned idx0 = 2;
39541 unsigned idx1 = 2; // ary1
39542 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
39543 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
39544 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
39545 {
39546 MacroAssembler _masm(&cbuf);
39547
39548#line 11539 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39549
39550 __ arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
39551 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
39552 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, false /* char */);
39553
39554#line 39554 "ad_x86.cpp"
39555 }
39556}
39557
39558void array_equalsCNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39559 cbuf.set_insts_mark();
39560 // Start at oper_input_base() and count operands
39561 unsigned idx0 = 2;
39562 unsigned idx1 = 2; // ary1
39563 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
39564 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
39565 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
39566 {
39567 MacroAssembler _masm(&cbuf);
39568
39569#line 11555 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39570
39571 __ arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
39572 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
39573 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, true /* char */);
39574
39575#line 39575 "ad_x86.cpp"
39576 }
39577}
39578
39579void has_negativesNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39580 cbuf.set_insts_mark();
39581 // Start at oper_input_base() and count operands
39582 unsigned idx0 = 2;
39583 unsigned idx1 = 2; // ary1
39584 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len
39585 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
39586 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
39587 {
39588 MacroAssembler _masm(&cbuf);
39589
39590#line 11570 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39591
39592 __ has_negatives(opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* len */,
39593 opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
39594 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
39595
39596#line 39596 "ad_x86.cpp"
39597 }
39598}
39599
39600void string_compressNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39601 cbuf.set_insts_mark();
39602 // Start at oper_input_base() and count operands
39603 unsigned idx0 = 2;
39604 unsigned idx1 = 2; // src
39605 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39606 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
39607 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
39608 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
39609 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
39610 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
39611 {
39612 MacroAssembler _masm(&cbuf);
39613
39614#line 11585 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39615
39616 __ char_array_compress(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
39617 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
39618 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */);
39619
39620#line 39620 "ad_x86.cpp"
39621 }
39622}
39623
39624void string_inflateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39625 cbuf.set_insts_mark();
39626 // Start at oper_input_base() and count operands
39627 unsigned idx0 = 2;
39628 unsigned idx1 = 2; // src
39629 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39630 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
39631 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
39632 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
39633 {
39634 MacroAssembler _masm(&cbuf);
39635
39636#line 11600 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39637
39638 __ byte_array_inflate(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
39639 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
39640
39641#line 39641 "ad_x86.cpp"
39642 }
39643}
39644
39645void encode_iso_arrayNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39646 cbuf.set_insts_mark();
39647 // Start at oper_input_base() and count operands
39648 unsigned idx0 = 2;
39649 unsigned idx1 = 2; // src
39650 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39651 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
39652 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
39653 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
39654 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
39655 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
39656 {
39657 MacroAssembler _masm(&cbuf);
39658
39659#line 11615 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39660
39661 __ encode_iso_array(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
39662 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
39663 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */);
39664
39665#line 39665 "ad_x86.cpp"
39666 }
39667}
39668
39669void overflowAddI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39670 cbuf.set_insts_mark();
39671 // Start at oper_input_base() and count operands
39672 unsigned idx0 = 1;
39673 unsigned idx1 = 1; // op1
39674 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39675 {
39676 MacroAssembler _masm(&cbuf);
39677
39678#line 11632 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39679
39680 __ addl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39681
39682#line 39682 "ad_x86.cpp"
39683 }
39684}
39685
39686void overflowAddI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39687 cbuf.set_insts_mark();
39688 // Start at oper_input_base() and count operands
39689 unsigned idx0 = 1;
39690 unsigned idx1 = 1; // op1
39691 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39692 {
39693 MacroAssembler _masm(&cbuf);
39694
39695#line 11645 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39696
39697 __ addl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
39698
39699#line 39699 "ad_x86.cpp"
39700 }
39701}
39702
39703void overflowAddL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39704 cbuf.set_insts_mark();
39705 // Start at oper_input_base() and count operands
39706 unsigned idx0 = 1;
39707 unsigned idx1 = 1; // op1
39708 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39709 {
39710 MacroAssembler _masm(&cbuf);
39711
39712#line 11657 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39713
39714 __ addq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39715
39716#line 39716 "ad_x86.cpp"
39717 }
39718}
39719
39720void overflowAddL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39721 cbuf.set_insts_mark();
39722 // Start at oper_input_base() and count operands
39723 unsigned idx0 = 1;
39724 unsigned idx1 = 1; // op1
39725 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39726 {
39727 MacroAssembler _masm(&cbuf);
39728
39729#line 11669 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39730
39731 __ addq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
39732
39733#line 39733 "ad_x86.cpp"
39734 }
39735}
39736
39737void overflowSubI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39738 cbuf.set_insts_mark();
39739 // Start at oper_input_base() and count operands
39740 unsigned idx0 = 1;
39741 unsigned idx1 = 1; // op1
39742 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39743 {
39744 MacroAssembler _masm(&cbuf);
39745
39746#line 11680 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39747
39748 __ cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39749
39750#line 39750 "ad_x86.cpp"
39751 }
39752}
39753
39754void overflowSubI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39755 cbuf.set_insts_mark();
39756 // Start at oper_input_base() and count operands
39757 unsigned idx0 = 1;
39758 unsigned idx1 = 1; // op1
39759 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39760 {
39761 MacroAssembler _masm(&cbuf);
39762
39763#line 11691 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39764
39765 __ cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
39766
39767#line 39767 "ad_x86.cpp"
39768 }
39769}
39770
39771void overflowSubL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39772 cbuf.set_insts_mark();
39773 // Start at oper_input_base() and count operands
39774 unsigned idx0 = 1;
39775 unsigned idx1 = 1; // op1
39776 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39777 {
39778 MacroAssembler _masm(&cbuf);
39779
39780#line 11702 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39781
39782 __ cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39783
39784#line 39784 "ad_x86.cpp"
39785 }
39786}
39787
39788void overflowSubL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39789 cbuf.set_insts_mark();
39790 // Start at oper_input_base() and count operands
39791 unsigned idx0 = 1;
39792 unsigned idx1 = 1; // op1
39793 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39794 {
39795 MacroAssembler _masm(&cbuf);
39796
39797#line 11713 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39798
39799 __ cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
39800
39801#line 39801 "ad_x86.cpp"
39802 }
39803}
39804
39805void overflowNegI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39806 cbuf.set_insts_mark();
39807 // Start at oper_input_base() and count operands
39808 unsigned idx0 = 1;
39809 unsigned idx1 = 1; // zero
39810 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39811 {
39812 MacroAssembler _masm(&cbuf);
39813
39814#line 11725 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39815
39816 __ negl(opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39817
39818#line 39818 "ad_x86.cpp"
39819 }
39820}
39821
39822void overflowNegL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39823 cbuf.set_insts_mark();
39824 // Start at oper_input_base() and count operands
39825 unsigned idx0 = 1;
39826 unsigned idx1 = 1; // zero
39827 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39828 {
39829 MacroAssembler _masm(&cbuf);
39830
39831#line 11737 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39832
39833 __ negq(opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39834
39835#line 39835 "ad_x86.cpp"
39836 }
39837}
39838
39839void overflowMulI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39840 cbuf.set_insts_mark();
39841 // Start at oper_input_base() and count operands
39842 unsigned idx0 = 1;
39843 unsigned idx1 = 1; // op1
39844 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39845 {
39846 MacroAssembler _masm(&cbuf);
39847
39848#line 11749 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39849
39850 __ imull(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39851
39852#line 39852 "ad_x86.cpp"
39853 }
39854}
39855
39856void overflowMulI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39857 cbuf.set_insts_mark();
39858 // Start at oper_input_base() and count operands
39859 unsigned idx0 = 1;
39860 unsigned idx1 = 1; // op1
39861 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39862 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
39863 {
39864 MacroAssembler _masm(&cbuf);
39865
39866#line 11761 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39867
39868 __ imull(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
39869
39870#line 39870 "ad_x86.cpp"
39871 }
39872}
39873
39874void overflowMulL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39875 cbuf.set_insts_mark();
39876 // Start at oper_input_base() and count operands
39877 unsigned idx0 = 1;
39878 unsigned idx1 = 1; // op1
39879 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39880 {
39881 MacroAssembler _masm(&cbuf);
39882
39883#line 11773 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39884
39885 __ imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
39886
39887#line 39887 "ad_x86.cpp"
39888 }
39889}
39890
39891void overflowMulL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39892 cbuf.set_insts_mark();
39893 // Start at oper_input_base() and count operands
39894 unsigned idx0 = 1;
39895 unsigned idx1 = 1; // op1
39896 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39897 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
39898 {
39899 MacroAssembler _masm(&cbuf);
39900
39901#line 11785 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39902
39903 __ imulq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
39904
39905#line 39905 "ad_x86.cpp"
39906 }
39907}
39908
39909void compI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39910 cbuf.set_insts_mark();
39911 // Start at oper_input_base() and count operands
39912 unsigned idx0 = 1;
39913 unsigned idx1 = 1; // op1
39914 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39915 {
39916
39917#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39918
39919 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
39920 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ >= 8) {
39921 emit_opcode(cbuf, Assembler::REX_B);
39922 }
39923 } else {
39924 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
39925 emit_opcode(cbuf, Assembler::REX_R);
39926 } else {
39927 emit_opcode(cbuf, Assembler::REX_RB);
39928 }
39929 }
39930
39931#line 39931 "ad_x86.cpp"
39932 }
39933 {
39934
39935#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39936
39937 emit_opcode(cbuf, (0x3B /*primary()*/));
39938
39939#line 39939 "ad_x86.cpp"
39940 }
39941 {
39942
39943#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39944
39945 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* op1 */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* op2 */ & 7);
39946
39947#line 39947 "ad_x86.cpp"
39948 }
39949}
39950
39951void compI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39952 cbuf.set_insts_mark();
39953 // Start at oper_input_base() and count operands
39954 unsigned idx0 = 1;
39955 unsigned idx1 = 1; // op1
39956 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
39957 {
39958
39959#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39960
39961 // OpcSEr/m
39962 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
39963 if (dstenc >= 8) {
39964 emit_opcode(cbuf, Assembler::REX_B);
39965 dstenc -= 8;
39966 }
39967 // Emit primary opcode and set sign-extend bit
39968 // Check for 8-bit immediate, and set sign extend bit in opcode
39969 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
39970 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
39971 } else {
39972 // 32-bit immediate
39973 emit_opcode(cbuf, (0x81 /*primary()*/));
39974 }
39975 // Emit r/m byte with secondary opcode, after primary opcode.
39976 emit_rm(cbuf, 0x3, (0x07 /*secondary()*/), dstenc);
39977
39978#line 39978 "ad_x86.cpp"
39979 }
39980 {
39981
39982#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
39983
39984 // Check for 8-bit immediate, and set sign extend bit in opcode
39985 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
39986 emit_d8(cbuf, opnd_array(2)->constant());
39987 } else {
39988 // 32-bit immediate
39989 emit_d32(cbuf, opnd_array(2)->constant());
39990 }
39991
39992#line 39992 "ad_x86.cpp"
39993 }
39994}
39995
39996void compI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39997 cbuf.set_insts_mark();
39998 // Start at oper_input_base() and count operands
39999 unsigned idx0 = 2;
40000 unsigned idx1 = 2; // op1
40001 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40002 {
40003
40004#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40005
40006 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40007 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40008 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
40009 emit_opcode(cbuf, Assembler::REX_X);
40010 }
40011 } else {
40012 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40013 emit_opcode(cbuf, Assembler::REX_B);
40014 } else {
40015 emit_opcode(cbuf, Assembler::REX_XB);
40016 }
40017 }
40018 } else {
40019 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40020 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40021 emit_opcode(cbuf, Assembler::REX_R);
40022 } else {
40023 emit_opcode(cbuf, Assembler::REX_RX);
40024 }
40025 } else {
40026 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40027 emit_opcode(cbuf, Assembler::REX_RB);
40028 } else {
40029 emit_opcode(cbuf, Assembler::REX_RXB);
40030 }
40031 }
40032 }
40033
40034#line 40034 "ad_x86.cpp"
40035 }
40036 {
40037
40038#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40039
40040 emit_opcode(cbuf, (0x3B /*primary()*/));
40041
40042#line 40042 "ad_x86.cpp"
40043 }
40044 {
40045
40046#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40047
40048 // High registers handle in encode_RegMem
40049 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40050 int base = opnd_array(2)->base(ra_,this,idx2);
40051 int index = opnd_array(2)->index(ra_,this,idx2);
40052 int scale = opnd_array(2)->scale();
40053 int disp = opnd_array(2)->disp(ra_,this,idx2);
40054 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
40055
40056 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40057
40058#line 40058 "ad_x86.cpp"
40059 }
40060}
40061
40062void testI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40063 cbuf.set_insts_mark();
40064 // Start at oper_input_base() and count operands
40065 unsigned idx0 = 1;
40066 unsigned idx1 = 1; // src
40067 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40068 {
40069
40070#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40071
40072 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40073 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
40074 emit_opcode(cbuf, Assembler::REX_B);
40075 }
40076 } else {
40077 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40078 emit_opcode(cbuf, Assembler::REX_R);
40079 } else {
40080 emit_opcode(cbuf, Assembler::REX_RB);
40081 }
40082 }
40083
40084#line 40084 "ad_x86.cpp"
40085 }
40086 {
40087
40088#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40089
40090 emit_opcode(cbuf, (0x85 /*primary()*/));
40091
40092#line 40092 "ad_x86.cpp"
40093 }
40094 {
40095
40096#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40097
40098 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
40099
40100#line 40100 "ad_x86.cpp"
40101 }
40102}
40103
40104void testI_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40105 cbuf.set_insts_mark();
40106 // Start at oper_input_base() and count operands
40107 unsigned idx0 = 1;
40108 unsigned idx1 = 1; // src
40109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
40110 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40111 {
40112
40113#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40114
40115 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
40116 emit_opcode(cbuf, Assembler::REX_B);
40117 }
40118
40119#line 40119 "ad_x86.cpp"
40120 }
40121 {
40122
40123#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40124
40125 emit_opcode(cbuf, (0xF7 /*primary()*/));
40126
40127#line 40127 "ad_x86.cpp"
40128 }
40129 {
40130
40131#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40132
40133 // INC, DEC, IDIV, IMOD, JMP indirect, ...
40134 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
40135
40136#line 40136 "ad_x86.cpp"
40137 }
40138 {
40139
40140#line 2299 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40141
40142 // Output immediate
40143 emit_d32(cbuf, opnd_array(2)->constant());
40144
40145#line 40145 "ad_x86.cpp"
40146 }
40147}
40148
40149void testI_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40150 cbuf.set_insts_mark();
40151 // Start at oper_input_base() and count operands
40152 unsigned idx0 = 2;
40153 unsigned idx1 = 2; // src
40154 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
40155 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40156 {
40157
40158#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40159
40160 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40161 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40162 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
40163 emit_opcode(cbuf, Assembler::REX_X);
40164 }
40165 } else {
40166 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40167 emit_opcode(cbuf, Assembler::REX_B);
40168 } else {
40169 emit_opcode(cbuf, Assembler::REX_XB);
40170 }
40171 }
40172 } else {
40173 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40174 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40175 emit_opcode(cbuf, Assembler::REX_R);
40176 } else {
40177 emit_opcode(cbuf, Assembler::REX_RX);
40178 }
40179 } else {
40180 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40181 emit_opcode(cbuf, Assembler::REX_RB);
40182 } else {
40183 emit_opcode(cbuf, Assembler::REX_RXB);
40184 }
40185 }
40186 }
40187
40188#line 40188 "ad_x86.cpp"
40189 }
40190 {
40191
40192#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40193
40194 emit_opcode(cbuf, (0x85 /*primary()*/));
40195
40196#line 40196 "ad_x86.cpp"
40197 }
40198 {
40199
40200#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40201
40202 // High registers handle in encode_RegMem
40203 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
40204 int base = opnd_array(2)->base(ra_,this,idx2);
40205 int index = opnd_array(2)->index(ra_,this,idx2);
40206 int scale = opnd_array(2)->scale();
40207 int disp = opnd_array(2)->disp(ra_,this,idx2);
40208 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
40209
40210 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40211
40212#line 40212 "ad_x86.cpp"
40213 }
40214}
40215
40216void testI_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40217 cbuf.set_insts_mark();
40218 // Start at oper_input_base() and count operands
40219 unsigned idx0 = 2;
40220 unsigned idx1 = 2; // mem
40221 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
40222 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40223 {
40224
40225#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40226
40227 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
40228 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
40229 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
40230 emit_opcode(cbuf, Assembler::REX_X);
40231 }
40232 } else {
40233 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
40234 emit_opcode(cbuf, Assembler::REX_B);
40235 } else {
40236 emit_opcode(cbuf, Assembler::REX_XB);
40237 }
40238 }
40239 } else {
40240 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
40241 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
40242 emit_opcode(cbuf, Assembler::REX_R);
40243 } else {
40244 emit_opcode(cbuf, Assembler::REX_RX);
40245 }
40246 } else {
40247 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
40248 emit_opcode(cbuf, Assembler::REX_RB);
40249 } else {
40250 emit_opcode(cbuf, Assembler::REX_RXB);
40251 }
40252 }
40253 }
40254
40255#line 40255 "ad_x86.cpp"
40256 }
40257 {
40258
40259#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40260
40261 emit_opcode(cbuf, (0x85 /*primary()*/));
40262
40263#line 40263 "ad_x86.cpp"
40264 }
40265 {
40266
40267#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40268
40269 // High registers handle in encode_RegMem
40270 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
40271 int base = opnd_array(1)->base(ra_,this,idx1);
40272 int index = opnd_array(1)->index(ra_,this,idx1);
40273 int scale = opnd_array(1)->scale();
40274 int disp = opnd_array(1)->disp(ra_,this,idx1);
40275 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
40276
40277 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40278
40279#line 40279 "ad_x86.cpp"
40280 }
40281}
40282
40283void compU_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40284 cbuf.set_insts_mark();
40285 // Start at oper_input_base() and count operands
40286 unsigned idx0 = 1;
40287 unsigned idx1 = 1; // op1
40288 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40289 {
40290
40291#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40292
40293 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40294 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ >= 8) {
40295 emit_opcode(cbuf, Assembler::REX_B);
40296 }
40297 } else {
40298 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
40299 emit_opcode(cbuf, Assembler::REX_R);
40300 } else {
40301 emit_opcode(cbuf, Assembler::REX_RB);
40302 }
40303 }
40304
40305#line 40305 "ad_x86.cpp"
40306 }
40307 {
40308
40309#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40310
40311 emit_opcode(cbuf, (0x3B /*primary()*/));
40312
40313#line 40313 "ad_x86.cpp"
40314 }
40315 {
40316
40317#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40318
40319 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* op1 */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* op2 */ & 7);
40320
40321#line 40321 "ad_x86.cpp"
40322 }
40323}
40324
40325void compU_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40326 cbuf.set_insts_mark();
40327 // Start at oper_input_base() and count operands
40328 unsigned idx0 = 1;
40329 unsigned idx1 = 1; // op1
40330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40331 {
40332
40333#line 2005 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40334
40335 // OpcSEr/m
40336 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40337 if (dstenc >= 8) {
40338 emit_opcode(cbuf, Assembler::REX_B);
40339 dstenc -= 8;
40340 }
40341 // Emit primary opcode and set sign-extend bit
40342 // Check for 8-bit immediate, and set sign extend bit in opcode
40343 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
40344 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
40345 } else {
40346 // 32-bit immediate
40347 emit_opcode(cbuf, (0x81 /*primary()*/));
40348 }
40349 // Emit r/m byte with secondary opcode, after primary opcode.
40350 emit_rm(cbuf, 0x3, (0x07 /*secondary()*/), dstenc);
40351
40352#line 40352 "ad_x86.cpp"
40353 }
40354 {
40355
40356#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40357
40358 // Check for 8-bit immediate, and set sign extend bit in opcode
40359 if (-0x80 <= opnd_array(2)->constant() && opnd_array(2)->constant() < 0x80) {
40360 emit_d8(cbuf, opnd_array(2)->constant());
40361 } else {
40362 // 32-bit immediate
40363 emit_d32(cbuf, opnd_array(2)->constant());
40364 }
40365
40366#line 40366 "ad_x86.cpp"
40367 }
40368}
40369
40370void compU_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40371 cbuf.set_insts_mark();
40372 // Start at oper_input_base() and count operands
40373 unsigned idx0 = 2;
40374 unsigned idx1 = 2; // op1
40375 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40376 {
40377
40378#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40379
40380 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40381 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40382 if (opnd_array(2)->index(ra_,this,idx2) >= 8) {
40383 emit_opcode(cbuf, Assembler::REX_X);
40384 }
40385 } else {
40386 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40387 emit_opcode(cbuf, Assembler::REX_B);
40388 } else {
40389 emit_opcode(cbuf, Assembler::REX_XB);
40390 }
40391 }
40392 } else {
40393 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40394 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40395 emit_opcode(cbuf, Assembler::REX_R);
40396 } else {
40397 emit_opcode(cbuf, Assembler::REX_RX);
40398 }
40399 } else {
40400 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40401 emit_opcode(cbuf, Assembler::REX_RB);
40402 } else {
40403 emit_opcode(cbuf, Assembler::REX_RXB);
40404 }
40405 }
40406 }
40407
40408#line 40408 "ad_x86.cpp"
40409 }
40410 {
40411
40412#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40413
40414 emit_opcode(cbuf, (0x3B /*primary()*/));
40415
40416#line 40416 "ad_x86.cpp"
40417 }
40418 {
40419
40420#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40421
40422 // High registers handle in encode_RegMem
40423 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40424 int base = opnd_array(2)->base(ra_,this,idx2);
40425 int index = opnd_array(2)->index(ra_,this,idx2);
40426 int scale = opnd_array(2)->scale();
40427 int disp = opnd_array(2)->disp(ra_,this,idx2);
40428 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
40429
40430 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40431
40432#line 40432 "ad_x86.cpp"
40433 }
40434}
40435
40436void testU_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40437 cbuf.set_insts_mark();
40438 // Start at oper_input_base() and count operands
40439 unsigned idx0 = 1;
40440 unsigned idx1 = 1; // src
40441 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40442 {
40443
40444#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40445
40446 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40447 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ >= 8) {
40448 emit_opcode(cbuf, Assembler::REX_B);
40449 }
40450 } else {
40451 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40452 emit_opcode(cbuf, Assembler::REX_R);
40453 } else {
40454 emit_opcode(cbuf, Assembler::REX_RB);
40455 }
40456 }
40457
40458#line 40458 "ad_x86.cpp"
40459 }
40460 {
40461
40462#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40463
40464 emit_opcode(cbuf, (0x85 /*primary()*/));
40465
40466#line 40466 "ad_x86.cpp"
40467 }
40468 {
40469
40470#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40471
40472 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
40473
40474#line 40474 "ad_x86.cpp"
40475 }
40476}
40477
40478void compP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40479 cbuf.set_insts_mark();
40480 // Start at oper_input_base() and count operands
40481 unsigned idx0 = 1;
40482 unsigned idx1 = 1; // op1
40483 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40484 {
40485
40486#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40487
40488 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40489 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
40490 emit_opcode(cbuf, Assembler::REX_W);
40491 } else {
40492 emit_opcode(cbuf, Assembler::REX_WB);
40493 }
40494 } else {
40495 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
40496 emit_opcode(cbuf, Assembler::REX_WR);
40497 } else {
40498 emit_opcode(cbuf, Assembler::REX_WRB);
40499 }
40500 }
40501
40502#line 40502 "ad_x86.cpp"
40503 }
40504 {
40505
40506#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40507
40508 emit_opcode(cbuf, (0x3B /*primary()*/));
40509
40510#line 40510 "ad_x86.cpp"
40511 }
40512 {
40513
40514#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40515
40516 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* op1 */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* op2 */ & 7);
40517
40518#line 40518 "ad_x86.cpp"
40519 }
40520}
40521
40522void compP_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40523 cbuf.set_insts_mark();
40524 // Start at oper_input_base() and count operands
40525 unsigned idx0 = 2;
40526 unsigned idx1 = 2; // op1
40527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40528 {
40529
40530#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40531
40532 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40533 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40534 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40535 emit_opcode(cbuf, Assembler::REX_W);
40536 } else {
40537 emit_opcode(cbuf, Assembler::REX_WX);
40538 }
40539 } else {
40540 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40541 emit_opcode(cbuf, Assembler::REX_WB);
40542 } else {
40543 emit_opcode(cbuf, Assembler::REX_WXB);
40544 }
40545 }
40546 } else {
40547 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40548 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40549 emit_opcode(cbuf, Assembler::REX_WR);
40550 } else {
40551 emit_opcode(cbuf, Assembler::REX_WRX);
40552 }
40553 } else {
40554 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40555 emit_opcode(cbuf, Assembler::REX_WRB);
40556 } else {
40557 emit_opcode(cbuf, Assembler::REX_WRXB);
40558 }
40559 }
40560 }
40561
40562#line 40562 "ad_x86.cpp"
40563 }
40564 {
40565
40566#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40567
40568 emit_opcode(cbuf, (0x3B /*primary()*/));
40569
40570#line 40570 "ad_x86.cpp"
40571 }
40572 {
40573
40574#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40575
40576 // High registers handle in encode_RegMem
40577 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40578 int base = opnd_array(2)->base(ra_,this,idx2);
40579 int index = opnd_array(2)->index(ra_,this,idx2);
40580 int scale = opnd_array(2)->scale();
40581 int disp = opnd_array(2)->disp(ra_,this,idx2);
40582 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
40583
40584 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40585
40586#line 40586 "ad_x86.cpp"
40587 }
40588}
40589
40590void compP_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40591 cbuf.set_insts_mark();
40592 // Start at oper_input_base() and count operands
40593 unsigned idx0 = 2;
40594 unsigned idx1 = 2; // op1
40595 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40596 {
40597
40598#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40599
40600 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40601 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40602 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40603 emit_opcode(cbuf, Assembler::REX_W);
40604 } else {
40605 emit_opcode(cbuf, Assembler::REX_WX);
40606 }
40607 } else {
40608 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40609 emit_opcode(cbuf, Assembler::REX_WB);
40610 } else {
40611 emit_opcode(cbuf, Assembler::REX_WXB);
40612 }
40613 }
40614 } else {
40615 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
40616 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40617 emit_opcode(cbuf, Assembler::REX_WR);
40618 } else {
40619 emit_opcode(cbuf, Assembler::REX_WRX);
40620 }
40621 } else {
40622 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
40623 emit_opcode(cbuf, Assembler::REX_WRB);
40624 } else {
40625 emit_opcode(cbuf, Assembler::REX_WRXB);
40626 }
40627 }
40628 }
40629
40630#line 40630 "ad_x86.cpp"
40631 }
40632 {
40633
40634#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40635
40636 emit_opcode(cbuf, (0x3B /*primary()*/));
40637
40638#line 40638 "ad_x86.cpp"
40639 }
40640 {
40641
40642#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40643
40644 // High registers handle in encode_RegMem
40645 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40646 int base = opnd_array(2)->base(ra_,this,idx2);
40647 int index = opnd_array(2)->index(ra_,this,idx2);
40648 int scale = opnd_array(2)->scale();
40649 int disp = opnd_array(2)->disp(ra_,this,idx2);
40650 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
40651
40652 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
40653
40654#line 40654 "ad_x86.cpp"
40655 }
40656}
40657
40658void testP_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40659 cbuf.set_insts_mark();
40660 // Start at oper_input_base() and count operands
40661 unsigned idx0 = 1;
40662 unsigned idx1 = 1; // src
40663 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40664 {
40665
40666#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40667
40668 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40669 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40670 emit_opcode(cbuf, Assembler::REX_W);
40671 } else {
40672 emit_opcode(cbuf, Assembler::REX_WB);
40673 }
40674 } else {
40675 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
40676 emit_opcode(cbuf, Assembler::REX_WR);
40677 } else {
40678 emit_opcode(cbuf, Assembler::REX_WRB);
40679 }
40680 }
40681
40682#line 40682 "ad_x86.cpp"
40683 }
40684 {
40685
40686#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40687
40688 emit_opcode(cbuf, (0x85 /*primary()*/));
40689
40690#line 40690 "ad_x86.cpp"
40691 }
40692 {
40693
40694#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40695
40696 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
40697
40698#line 40698 "ad_x86.cpp"
40699 }
40700}
40701
40702void testP_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40703 cbuf.set_insts_mark();
40704 // Start at oper_input_base() and count operands
40705 unsigned idx0 = 2;
40706 unsigned idx1 = 2; // op
40707 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40708 {
40709
40710#line 2351 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40711
40712 if (opnd_array(1)->base(ra_,this,idx1) >= 8) {
40713 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
40714 emit_opcode(cbuf, Assembler::REX_WB);
40715 } else {
40716 emit_opcode(cbuf, Assembler::REX_WXB);
40717 }
40718 } else {
40719 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
40720 emit_opcode(cbuf, Assembler::REX_W);
40721 } else {
40722 emit_opcode(cbuf, Assembler::REX_WX);
40723 }
40724 }
40725
40726#line 40726 "ad_x86.cpp"
40727 }
40728 {
40729
40730#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40731
40732 emit_opcode(cbuf, (0xF7 /*primary()*/));
40733
40734#line 40734 "ad_x86.cpp"
40735 }
40736 {
40737
40738#line 2551 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40739
40740 int rm_byte_opcode = (0x00);
40741
40742 // High registers handle in encode_RegMem
40743 int base = opnd_array(1)->base(ra_,this,idx1);
40744 int index = opnd_array(1)->index(ra_,this,idx1);
40745 int scale = opnd_array(1)->scale();
40746 int displace = opnd_array(1)->disp(ra_,this,idx1);
40747
40748 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc(); // disp-as-oop when
40749 // working with static
40750 // globals
40751 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
40752 disp_reloc);
40753
40754#line 40754 "ad_x86.cpp"
40755 }
40756 {
40757
40758#line 2320 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40759
40760 emit_d32(cbuf,(0xFFFFFFFF));
40761
40762#line 40762 "ad_x86.cpp"
40763 }
40764}
40765
40766void testP_mem_reg0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40767 cbuf.set_insts_mark();
40768 // Start at oper_input_base() and count operands
40769 unsigned idx0 = 2;
40770 unsigned idx1 = 2; // mem
40771 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40772 {
40773 MacroAssembler _masm(&cbuf);
40774
40775#line 11992 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40776
40777 __ cmpq(r12, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
40778
40779#line 40779 "ad_x86.cpp"
40780 }
40781}
40782
40783void compN_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40784 cbuf.set_insts_mark();
40785 // Start at oper_input_base() and count operands
40786 unsigned idx0 = 1;
40787 unsigned idx1 = 1; // op1
40788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40789 {
40790 MacroAssembler _masm(&cbuf);
40791
40792#line 12003 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40793__ cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
40794#line 40794 "ad_x86.cpp"
40795 }
40796}
40797
40798void compN_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40799 cbuf.set_insts_mark();
40800 // Start at oper_input_base() and count operands
40801 unsigned idx0 = 2;
40802 unsigned idx1 = 2; // src
40803 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
40804 {
40805 MacroAssembler _masm(&cbuf);
40806
40807#line 12012 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40808
40809 __ cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
40810
40811#line 40811 "ad_x86.cpp"
40812 }
40813}
40814
40815void compN_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40816 cbuf.set_insts_mark();
40817 // Start at oper_input_base() and count operands
40818 unsigned idx0 = 1;
40819 unsigned idx1 = 1; // op1
40820 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40821 {
40822 MacroAssembler _masm(&cbuf);
40823
40824#line 12022 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40825
40826 __ cmp_narrow_oop(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, (jobject)opnd_array(2)->constant());
40827
40828#line 40828 "ad_x86.cpp"
40829 }
40830}
40831
40832void compN_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40833 cbuf.set_insts_mark();
40834 // Start at oper_input_base() and count operands
40835 unsigned idx0 = 2;
40836 unsigned idx1 = 2; // src
40837 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
40838 {
40839 MacroAssembler _masm(&cbuf);
40840
40841#line 12033 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40842
40843 __ cmp_narrow_oop(Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), (jobject)opnd_array(1)->constant());
40844
40845#line 40845 "ad_x86.cpp"
40846 }
40847}
40848
40849void compN_rReg_imm_klassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40850 cbuf.set_insts_mark();
40851 // Start at oper_input_base() and count operands
40852 unsigned idx0 = 1;
40853 unsigned idx1 = 1; // op1
40854 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40855 {
40856 MacroAssembler _masm(&cbuf);
40857
40858#line 12043 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40859
40860 __ cmp_narrow_klass(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, (Klass*)opnd_array(2)->constant());
40861
40862#line 40862 "ad_x86.cpp"
40863 }
40864}
40865
40866void compN_mem_imm_klassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40867 cbuf.set_insts_mark();
40868 // Start at oper_input_base() and count operands
40869 unsigned idx0 = 2;
40870 unsigned idx1 = 2; // src
40871 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
40872 {
40873 MacroAssembler _masm(&cbuf);
40874
40875#line 12054 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40876
40877 __ cmp_narrow_klass(Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), (Klass*)opnd_array(1)->constant());
40878
40879#line 40879 "ad_x86.cpp"
40880 }
40881}
40882
40883void testN_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40884 cbuf.set_insts_mark();
40885 // Start at oper_input_base() and count operands
40886 unsigned idx0 = 1;
40887 unsigned idx1 = 1; // src
40888 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40889 {
40890 MacroAssembler _masm(&cbuf);
40891
40892#line 12064 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40893__ testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
40894#line 40894 "ad_x86.cpp"
40895 }
40896}
40897
40898void testN_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40899 cbuf.set_insts_mark();
40900 // Start at oper_input_base() and count operands
40901 unsigned idx0 = 2;
40902 unsigned idx1 = 2; // mem
40903 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40904 {
40905 MacroAssembler _masm(&cbuf);
40906
40907#line 12075 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40908
40909 __ cmpl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (int)0xFFFFFFFF);
40910
40911#line 40911 "ad_x86.cpp"
40912 }
40913}
40914
40915void testN_mem_reg0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40916 cbuf.set_insts_mark();
40917 // Start at oper_input_base() and count operands
40918 unsigned idx0 = 2;
40919 unsigned idx1 = 2; // mem
40920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
40921 {
40922 MacroAssembler _masm(&cbuf);
40923
40924#line 12087 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40925
40926 __ cmpl(r12, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
40927
40928#line 40928 "ad_x86.cpp"
40929 }
40930}
40931
40932void compL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40933 cbuf.set_insts_mark();
40934 // Start at oper_input_base() and count operands
40935 unsigned idx0 = 1;
40936 unsigned idx1 = 1; // op1
40937 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40938 {
40939
40940#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40941
40942 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
40943 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
40944 emit_opcode(cbuf, Assembler::REX_W);
40945 } else {
40946 emit_opcode(cbuf, Assembler::REX_WB);
40947 }
40948 } else {
40949 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
40950 emit_opcode(cbuf, Assembler::REX_WR);
40951 } else {
40952 emit_opcode(cbuf, Assembler::REX_WRB);
40953 }
40954 }
40955
40956#line 40956 "ad_x86.cpp"
40957 }
40958 {
40959
40960#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40961
40962 emit_opcode(cbuf, (0x3B /*primary()*/));
40963
40964#line 40964 "ad_x86.cpp"
40965 }
40966 {
40967
40968#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40969
40970 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* op1 */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* op2 */ & 7);
40971
40972#line 40972 "ad_x86.cpp"
40973 }
40974}
40975
40976void compL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40977 cbuf.set_insts_mark();
40978 // Start at oper_input_base() and count operands
40979 unsigned idx0 = 1;
40980 unsigned idx1 = 1; // op1
40981 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
40982 {
40983
40984#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
40985
40986 // OpcSEr/m
40987 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
40988 if (dstenc < 8) {
40989 emit_opcode(cbuf, Assembler::REX_W);
40990 } else {
40991 emit_opcode(cbuf, Assembler::REX_WB);
40992 dstenc -= 8;
40993 }
40994 // Emit primary opcode and set sign-extend bit
40995 // Check for 8-bit immediate, and set sign extend bit in opcode
40996 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
40997 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
40998 } else {
40999 // 32-bit immediate
41000 emit_opcode(cbuf, (0x81 /*primary()*/));
41001 }
41002 // Emit r/m byte with secondary opcode, after primary opcode.
41003 emit_rm(cbuf, 0x3, (0x07 /*secondary()*/), dstenc);
41004
41005#line 41005 "ad_x86.cpp"
41006 }
41007 {
41008
41009#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41010
41011 // Check for 8-bit immediate, and set sign extend bit in opcode
41012 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
41013 emit_d8(cbuf, opnd_array(2)->constantL());
41014 } else {
41015 // 32-bit immediate
41016 emit_d32(cbuf, opnd_array(2)->constantL());
41017 }
41018
41019#line 41019 "ad_x86.cpp"
41020 }
41021}
41022
41023void compL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41024 cbuf.set_insts_mark();
41025 // Start at oper_input_base() and count operands
41026 unsigned idx0 = 2;
41027 unsigned idx1 = 2; // op1
41028 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
41029 {
41030
41031#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41032
41033 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
41034 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41035 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41036 emit_opcode(cbuf, Assembler::REX_W);
41037 } else {
41038 emit_opcode(cbuf, Assembler::REX_WX);
41039 }
41040 } else {
41041 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41042 emit_opcode(cbuf, Assembler::REX_WB);
41043 } else {
41044 emit_opcode(cbuf, Assembler::REX_WXB);
41045 }
41046 }
41047 } else {
41048 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41049 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41050 emit_opcode(cbuf, Assembler::REX_WR);
41051 } else {
41052 emit_opcode(cbuf, Assembler::REX_WRX);
41053 }
41054 } else {
41055 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41056 emit_opcode(cbuf, Assembler::REX_WRB);
41057 } else {
41058 emit_opcode(cbuf, Assembler::REX_WRXB);
41059 }
41060 }
41061 }
41062
41063#line 41063 "ad_x86.cpp"
41064 }
41065 {
41066
41067#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41068
41069 emit_opcode(cbuf, (0x3B /*primary()*/));
41070
41071#line 41071 "ad_x86.cpp"
41072 }
41073 {
41074
41075#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41076
41077 // High registers handle in encode_RegMem
41078 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
41079 int base = opnd_array(2)->base(ra_,this,idx2);
41080 int index = opnd_array(2)->index(ra_,this,idx2);
41081 int scale = opnd_array(2)->scale();
41082 int disp = opnd_array(2)->disp(ra_,this,idx2);
41083 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
41084
41085 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41086
41087#line 41087 "ad_x86.cpp"
41088 }
41089}
41090
41091void testL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41092 cbuf.set_insts_mark();
41093 // Start at oper_input_base() and count operands
41094 unsigned idx0 = 1;
41095 unsigned idx1 = 1; // src
41096 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
41097 {
41098
41099#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41100
41101 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41102 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41103 emit_opcode(cbuf, Assembler::REX_W);
41104 } else {
41105 emit_opcode(cbuf, Assembler::REX_WB);
41106 }
41107 } else {
41108 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41109 emit_opcode(cbuf, Assembler::REX_WR);
41110 } else {
41111 emit_opcode(cbuf, Assembler::REX_WRB);
41112 }
41113 }
41114
41115#line 41115 "ad_x86.cpp"
41116 }
41117 {
41118
41119#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41120
41121 emit_opcode(cbuf, (0x85 /*primary()*/));
41122
41123#line 41123 "ad_x86.cpp"
41124 }
41125 {
41126
41127#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41128
41129 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
41130
41131#line 41131 "ad_x86.cpp"
41132 }
41133}
41134
41135void testL_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41136 cbuf.set_insts_mark();
41137 // Start at oper_input_base() and count operands
41138 unsigned idx0 = 1;
41139 unsigned idx1 = 1; // src
41140 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
41141 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41142 {
41143
41144#line 2433 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41145
41146 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41147 emit_opcode(cbuf, Assembler::REX_W);
41148 } else {
41149 emit_opcode(cbuf, Assembler::REX_WB);
41150 }
41151
41152#line 41152 "ad_x86.cpp"
41153 }
41154 {
41155
41156#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41157
41158 emit_opcode(cbuf, (0xF7 /*primary()*/));
41159
41160#line 41160 "ad_x86.cpp"
41161 }
41162 {
41163
41164#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41165
41166 // INC, DEC, IDIV, IMOD, JMP indirect, ...
41167 emit_rm(cbuf, 0x3, (0x00 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
41168
41169#line 41169 "ad_x86.cpp"
41170 }
41171 {
41172
41173#line 2299 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41174
41175 // Output immediate
41176 emit_d32(cbuf, opnd_array(2)->constantL());
41177
41178#line 41178 "ad_x86.cpp"
41179 }
41180}
41181
41182void testL_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41183 cbuf.set_insts_mark();
41184 // Start at oper_input_base() and count operands
41185 unsigned idx0 = 2;
41186 unsigned idx1 = 2; // src
41187 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
41188 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41189 {
41190
41191#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41192
41193 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41194 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41195 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41196 emit_opcode(cbuf, Assembler::REX_W);
41197 } else {
41198 emit_opcode(cbuf, Assembler::REX_WX);
41199 }
41200 } else {
41201 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41202 emit_opcode(cbuf, Assembler::REX_WB);
41203 } else {
41204 emit_opcode(cbuf, Assembler::REX_WXB);
41205 }
41206 }
41207 } else {
41208 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41209 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41210 emit_opcode(cbuf, Assembler::REX_WR);
41211 } else {
41212 emit_opcode(cbuf, Assembler::REX_WRX);
41213 }
41214 } else {
41215 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41216 emit_opcode(cbuf, Assembler::REX_WRB);
41217 } else {
41218 emit_opcode(cbuf, Assembler::REX_WRXB);
41219 }
41220 }
41221 }
41222
41223#line 41223 "ad_x86.cpp"
41224 }
41225 {
41226
41227#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41228
41229 emit_opcode(cbuf, (0x85 /*primary()*/));
41230
41231#line 41231 "ad_x86.cpp"
41232 }
41233 {
41234
41235#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41236
41237 // High registers handle in encode_RegMem
41238 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
41239 int base = opnd_array(2)->base(ra_,this,idx2);
41240 int index = opnd_array(2)->index(ra_,this,idx2);
41241 int scale = opnd_array(2)->scale();
41242 int disp = opnd_array(2)->disp(ra_,this,idx2);
41243 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
41244
41245 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41246
41247#line 41247 "ad_x86.cpp"
41248 }
41249}
41250
41251void testL_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41252 cbuf.set_insts_mark();
41253 // Start at oper_input_base() and count operands
41254 unsigned idx0 = 2;
41255 unsigned idx1 = 2; // mem
41256 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
41257 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41258 {
41259
41260#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41261
41262 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
41263 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
41264 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41265 emit_opcode(cbuf, Assembler::REX_W);
41266 } else {
41267 emit_opcode(cbuf, Assembler::REX_WX);
41268 }
41269 } else {
41270 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41271 emit_opcode(cbuf, Assembler::REX_WB);
41272 } else {
41273 emit_opcode(cbuf, Assembler::REX_WXB);
41274 }
41275 }
41276 } else {
41277 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
41278 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41279 emit_opcode(cbuf, Assembler::REX_WR);
41280 } else {
41281 emit_opcode(cbuf, Assembler::REX_WRX);
41282 }
41283 } else {
41284 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41285 emit_opcode(cbuf, Assembler::REX_WRB);
41286 } else {
41287 emit_opcode(cbuf, Assembler::REX_WRXB);
41288 }
41289 }
41290 }
41291
41292#line 41292 "ad_x86.cpp"
41293 }
41294 {
41295
41296#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41297
41298 emit_opcode(cbuf, (0x85 /*primary()*/));
41299
41300#line 41300 "ad_x86.cpp"
41301 }
41302 {
41303
41304#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41305
41306 // High registers handle in encode_RegMem
41307 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
41308 int base = opnd_array(1)->base(ra_,this,idx1);
41309 int index = opnd_array(1)->index(ra_,this,idx1);
41310 int scale = opnd_array(1)->scale();
41311 int disp = opnd_array(1)->disp(ra_,this,idx1);
41312 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
41313
41314 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41315
41316#line 41316 "ad_x86.cpp"
41317 }
41318}
41319
41320void testL_reg_mem2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41321 cbuf.set_insts_mark();
41322 // Start at oper_input_base() and count operands
41323 unsigned idx0 = 2;
41324 unsigned idx1 = 2; // src
41325 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
41326 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41327 {
41328
41329#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41330
41331 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41332 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41333 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41334 emit_opcode(cbuf, Assembler::REX_W);
41335 } else {
41336 emit_opcode(cbuf, Assembler::REX_WX);
41337 }
41338 } else {
41339 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41340 emit_opcode(cbuf, Assembler::REX_WB);
41341 } else {
41342 emit_opcode(cbuf, Assembler::REX_WXB);
41343 }
41344 }
41345 } else {
41346 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41347 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41348 emit_opcode(cbuf, Assembler::REX_WR);
41349 } else {
41350 emit_opcode(cbuf, Assembler::REX_WRX);
41351 }
41352 } else {
41353 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41354 emit_opcode(cbuf, Assembler::REX_WRB);
41355 } else {
41356 emit_opcode(cbuf, Assembler::REX_WRXB);
41357 }
41358 }
41359 }
41360
41361#line 41361 "ad_x86.cpp"
41362 }
41363 {
41364
41365#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41366
41367 emit_opcode(cbuf, (0x85 /*primary()*/));
41368
41369#line 41369 "ad_x86.cpp"
41370 }
41371 {
41372
41373#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41374
41375 // High registers handle in encode_RegMem
41376 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
41377 int base = opnd_array(2)->base(ra_,this,idx2);
41378 int index = opnd_array(2)->index(ra_,this,idx2);
41379 int scale = opnd_array(2)->scale();
41380 int disp = opnd_array(2)->disp(ra_,this,idx2);
41381 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
41382
41383 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41384
41385#line 41385 "ad_x86.cpp"
41386 }
41387}
41388
41389void testL_reg_mem2_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41390 cbuf.set_insts_mark();
41391 // Start at oper_input_base() and count operands
41392 unsigned idx0 = 2;
41393 unsigned idx1 = 2; // mem
41394 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
41395 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41396 {
41397
41398#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41399
41400 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
41401 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
41402 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41403 emit_opcode(cbuf, Assembler::REX_W);
41404 } else {
41405 emit_opcode(cbuf, Assembler::REX_WX);
41406 }
41407 } else {
41408 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41409 emit_opcode(cbuf, Assembler::REX_WB);
41410 } else {
41411 emit_opcode(cbuf, Assembler::REX_WXB);
41412 }
41413 }
41414 } else {
41415 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
41416 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41417 emit_opcode(cbuf, Assembler::REX_WR);
41418 } else {
41419 emit_opcode(cbuf, Assembler::REX_WRX);
41420 }
41421 } else {
41422 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
41423 emit_opcode(cbuf, Assembler::REX_WRB);
41424 } else {
41425 emit_opcode(cbuf, Assembler::REX_WRXB);
41426 }
41427 }
41428 }
41429
41430#line 41430 "ad_x86.cpp"
41431 }
41432 {
41433
41434#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41435
41436 emit_opcode(cbuf, (0x85 /*primary()*/));
41437
41438#line 41438 "ad_x86.cpp"
41439 }
41440 {
41441
41442#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41443
41444 // High registers handle in encode_RegMem
41445 int reg = opnd_array(2)->reg(ra_,this,idx2)/* src */;
41446 int base = opnd_array(1)->base(ra_,this,idx1);
41447 int index = opnd_array(1)->index(ra_,this,idx1);
41448 int scale = opnd_array(1)->scale();
41449 int disp = opnd_array(1)->disp(ra_,this,idx1);
41450 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
41451
41452 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41453
41454#line 41454 "ad_x86.cpp"
41455 }
41456}
41457
41458void cmpL3_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41459 cbuf.set_insts_mark();
41460 // Start at oper_input_base() and count operands
41461 unsigned idx0 = 1;
41462 unsigned idx1 = 1; // src1
41463 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41464 {
41465
41466#line 2638 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41467
41468 int src1enc = opnd_array(1)->reg(ra_,this,idx1)/* src1 */;
41469 int src2enc = opnd_array(2)->reg(ra_,this,idx2)/* src2 */;
41470 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
41471
41472 // cmpq $src1, $src2
41473 if (src1enc < 8) {
41474 if (src2enc < 8) {
41475 emit_opcode(cbuf, Assembler::REX_W);
41476 } else {
41477 emit_opcode(cbuf, Assembler::REX_WB);
41478 }
41479 } else {
41480 if (src2enc < 8) {
41481 emit_opcode(cbuf, Assembler::REX_WR);
41482 } else {
41483 emit_opcode(cbuf, Assembler::REX_WRB);
41484 }
41485 }
41486 emit_opcode(cbuf, 0x3B);
41487 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
41488
41489 // movl $dst, -1
41490 if (dstenc >= 8) {
41491 emit_opcode(cbuf, Assembler::REX_B);
41492 }
41493 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
41494 emit_d32(cbuf, -1);
41495
41496 // jl,s done
41497 emit_opcode(cbuf, 0x7C);
41498 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
41499
41500 // setne $dst
41501 if (dstenc >= 4) {
41502 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
41503 }
41504 emit_opcode(cbuf, 0x0F);
41505 emit_opcode(cbuf, 0x95);
41506 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
41507
41508 // movzbl $dst, $dst
41509 if (dstenc >= 4) {
41510 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
41511 }
41512 emit_opcode(cbuf, 0x0F);
41513 emit_opcode(cbuf, 0xB6);
41514 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
41515
41516#line 41516 "ad_x86.cpp"
41517 }
41518}
41519
41520void compUL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41521 cbuf.set_insts_mark();
41522 // Start at oper_input_base() and count operands
41523 unsigned idx0 = 1;
41524 unsigned idx1 = 1; // op1
41525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
41526 {
41527
41528#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41529
41530 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
41531 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
41532 emit_opcode(cbuf, Assembler::REX_W);
41533 } else {
41534 emit_opcode(cbuf, Assembler::REX_WB);
41535 }
41536 } else {
41537 if (opnd_array(2)->reg(ra_,this,idx2)/* op2 */ < 8) {
41538 emit_opcode(cbuf, Assembler::REX_WR);
41539 } else {
41540 emit_opcode(cbuf, Assembler::REX_WRB);
41541 }
41542 }
41543
41544#line 41544 "ad_x86.cpp"
41545 }
41546 {
41547
41548#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41549
41550 emit_opcode(cbuf, (0x3B /*primary()*/));
41551
41552#line 41552 "ad_x86.cpp"
41553 }
41554 {
41555
41556#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41557
41558 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* op1 */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* op2 */ & 7);
41559
41560#line 41560 "ad_x86.cpp"
41561 }
41562}
41563
41564void compUL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41565 cbuf.set_insts_mark();
41566 // Start at oper_input_base() and count operands
41567 unsigned idx0 = 1;
41568 unsigned idx1 = 1; // op1
41569 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
41570 {
41571
41572#line 2025 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41573
41574 // OpcSEr/m
41575 int dstenc = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
41576 if (dstenc < 8) {
41577 emit_opcode(cbuf, Assembler::REX_W);
41578 } else {
41579 emit_opcode(cbuf, Assembler::REX_WB);
41580 dstenc -= 8;
41581 }
41582 // Emit primary opcode and set sign-extend bit
41583 // Check for 8-bit immediate, and set sign extend bit in opcode
41584 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
41585 emit_opcode(cbuf, (0x81 /*primary()*/) | 0x02);
41586 } else {
41587 // 32-bit immediate
41588 emit_opcode(cbuf, (0x81 /*primary()*/));
41589 }
41590 // Emit r/m byte with secondary opcode, after primary opcode.
41591 emit_rm(cbuf, 0x3, (0x07 /*secondary()*/), dstenc);
41592
41593#line 41593 "ad_x86.cpp"
41594 }
41595 {
41596
41597#line 2047 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41598
41599 // Check for 8-bit immediate, and set sign extend bit in opcode
41600 if (-0x80 <= opnd_array(2)->constantL() && opnd_array(2)->constantL() < 0x80) {
41601 emit_d8(cbuf, opnd_array(2)->constantL());
41602 } else {
41603 // 32-bit immediate
41604 emit_d32(cbuf, opnd_array(2)->constantL());
41605 }
41606
41607#line 41607 "ad_x86.cpp"
41608 }
41609}
41610
41611void compUL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41612 cbuf.set_insts_mark();
41613 // Start at oper_input_base() and count operands
41614 unsigned idx0 = 2;
41615 unsigned idx1 = 2; // op1
41616 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
41617 {
41618
41619#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41620
41621 if (opnd_array(1)->reg(ra_,this,idx1)/* op1 */ < 8) {
41622 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41623 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41624 emit_opcode(cbuf, Assembler::REX_W);
41625 } else {
41626 emit_opcode(cbuf, Assembler::REX_WX);
41627 }
41628 } else {
41629 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41630 emit_opcode(cbuf, Assembler::REX_WB);
41631 } else {
41632 emit_opcode(cbuf, Assembler::REX_WXB);
41633 }
41634 }
41635 } else {
41636 if (opnd_array(2)->base(ra_,this,idx2) < 8) {
41637 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41638 emit_opcode(cbuf, Assembler::REX_WR);
41639 } else {
41640 emit_opcode(cbuf, Assembler::REX_WRX);
41641 }
41642 } else {
41643 if (opnd_array(2)->index(ra_,this,idx2) < 8) {
41644 emit_opcode(cbuf, Assembler::REX_WRB);
41645 } else {
41646 emit_opcode(cbuf, Assembler::REX_WRXB);
41647 }
41648 }
41649 }
41650
41651#line 41651 "ad_x86.cpp"
41652 }
41653 {
41654
41655#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41656
41657 emit_opcode(cbuf, (0x3B /*primary()*/));
41658
41659#line 41659 "ad_x86.cpp"
41660 }
41661 {
41662
41663#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41664
41665 // High registers handle in encode_RegMem
41666 int reg = opnd_array(1)->reg(ra_,this,idx1)/* op1 */;
41667 int base = opnd_array(2)->base(ra_,this,idx2);
41668 int index = opnd_array(2)->index(ra_,this,idx2);
41669 int scale = opnd_array(2)->scale();
41670 int disp = opnd_array(2)->disp(ra_,this,idx2);
41671 relocInfo::relocType disp_reloc = opnd_array(2)->disp_reloc();
41672
41673 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
41674
41675#line 41675 "ad_x86.cpp"
41676 }
41677}
41678
41679void testUL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41680 cbuf.set_insts_mark();
41681 // Start at oper_input_base() and count operands
41682 unsigned idx0 = 1;
41683 unsigned idx1 = 1; // src
41684 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
41685 {
41686
41687#line 2457 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41688
41689 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41690 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41691 emit_opcode(cbuf, Assembler::REX_W);
41692 } else {
41693 emit_opcode(cbuf, Assembler::REX_WB);
41694 }
41695 } else {
41696 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
41697 emit_opcode(cbuf, Assembler::REX_WR);
41698 } else {
41699 emit_opcode(cbuf, Assembler::REX_WRB);
41700 }
41701 }
41702
41703#line 41703 "ad_x86.cpp"
41704 }
41705 {
41706
41707#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41708
41709 emit_opcode(cbuf, (0x85 /*primary()*/));
41710
41711#line 41711 "ad_x86.cpp"
41712 }
41713 {
41714
41715#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41716
41717 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7, opnd_array(1)->reg(ra_,this,idx1)/* src */ & 7);
41718
41719#line 41719 "ad_x86.cpp"
41720 }
41721}
41722
41723void compB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41724 cbuf.set_insts_mark();
41725 // Start at oper_input_base() and count operands
41726 unsigned idx0 = 2;
41727 unsigned idx1 = 2; // mem
41728 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
41729 {
41730 MacroAssembler _masm(&cbuf);
41731
41732#line 12232 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41733__ cmpb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
41734#line 41734 "ad_x86.cpp"
41735 }
41736}
41737
41738void testUB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41739 cbuf.set_insts_mark();
41740 // Start at oper_input_base() and count operands
41741 unsigned idx0 = 2;
41742 unsigned idx1 = 2; // mem
41743 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
41744 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41745 {
41746 MacroAssembler _masm(&cbuf);
41747
41748#line 12242 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41749__ testb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
41750#line 41750 "ad_x86.cpp"
41751 }
41752}
41753
41754void testB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41755 cbuf.set_insts_mark();
41756 // Start at oper_input_base() and count operands
41757 unsigned idx0 = 2;
41758 unsigned idx1 = 2; // mem
41759 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
41760 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
41761 {
41762 MacroAssembler _masm(&cbuf);
41763
41764#line 12252 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41765__ testb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
41766#line 41766 "ad_x86.cpp"
41767 }
41768}
41769
41770void cmovI_reg_gNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41771 cbuf.set_insts_mark();
41772 // Start at oper_input_base() and count operands
41773 unsigned idx0 = 1;
41774 unsigned idx1 = 1; // src
41775 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
41776 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41777 {
41778
41779#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41780
41781 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
41782 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
41783 emit_opcode(cbuf, Assembler::REX_B);
41784 }
41785 } else {
41786 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
41787 emit_opcode(cbuf, Assembler::REX_R);
41788 } else {
41789 emit_opcode(cbuf, Assembler::REX_RB);
41790 }
41791 }
41792
41793#line 41793 "ad_x86.cpp"
41794 }
41795 {
41796
41797#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41798
41799 emit_opcode(cbuf, (0x0F /*primary()*/));
41800
41801#line 41801 "ad_x86.cpp"
41802 }
41803 {
41804
41805#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41806
41807 emit_opcode(cbuf, (0x4F /*secondary()*/));
41808
41809#line 41809 "ad_x86.cpp"
41810 }
41811 {
41812
41813#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41814
41815 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
41816
41817#line 41817 "ad_x86.cpp"
41818 }
41819}
41820
41821void cmovI_reg_lNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41822 cbuf.set_insts_mark();
41823 // Start at oper_input_base() and count operands
41824 unsigned idx0 = 1;
41825 unsigned idx1 = 1; // src
41826 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
41827 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41828 {
41829
41830#line 2442 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41831
41832 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
41833 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ >= 8) {
41834 emit_opcode(cbuf, Assembler::REX_B);
41835 }
41836 } else {
41837 if (opnd_array(2)->reg(ra_,this,idx2)/* src */ < 8) {
41838 emit_opcode(cbuf, Assembler::REX_R);
41839 } else {
41840 emit_opcode(cbuf, Assembler::REX_RB);
41841 }
41842 }
41843
41844#line 41844 "ad_x86.cpp"
41845 }
41846 {
41847
41848#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41849
41850 emit_opcode(cbuf, (0x0F /*primary()*/));
41851
41852#line 41852 "ad_x86.cpp"
41853 }
41854 {
41855
41856#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41857
41858 emit_opcode(cbuf, (0x4C /*secondary()*/));
41859
41860#line 41860 "ad_x86.cpp"
41861 }
41862 {
41863
41864#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41865
41866 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(2)->reg(ra_,this,idx2)/* src */ & 7);
41867
41868#line 41868 "ad_x86.cpp"
41869 }
41870}
41871
41872void jmpDirNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41873 cbuf.set_insts_mark();
41874 // Start at oper_input_base() and count operands
41875 unsigned idx0 = 1;
41876 unsigned idx1 = 1; //
41877 {
41878 MacroAssembler _masm(&cbuf);
41879
41880#line 12317 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41881
41882 Label* L = opnd_array(1)->label();
41883 __ jmp(*L, false); // Always long jump
41884
41885#line 41885 "ad_x86.cpp"
41886 }
41887}
41888
41889uint jmpDirNode::size(PhaseRegAlloc *ra_) const {
41890 assert(VerifyOops || MachNode::size(ra_) <= 5, "bad fixed size");
41891 return (VerifyOops ? MachNode::size(ra_) : 5);
41892}
41893
41894void jmpConNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41895 cbuf.set_insts_mark();
41896 // Start at oper_input_base() and count operands
41897 unsigned idx0 = 1;
41898 unsigned idx1 = 1; // cr
41899 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
41900 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41901 {
41902 MacroAssembler _masm(&cbuf);
41903
41904#line 12333 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41905
41906 Label* L = opnd_array(3)->label();
41907 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
41908
41909#line 41909 "ad_x86.cpp"
41910 }
41911}
41912
41913uint jmpConNode::size(PhaseRegAlloc *ra_) const {
41914 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
41915 return (VerifyOops ? MachNode::size(ra_) : 6);
41916}
41917
41918void jmpLoopEndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41919 cbuf.set_insts_mark();
41920 // Start at oper_input_base() and count operands
41921 unsigned idx0 = 1;
41922 unsigned idx1 = 1; // cr
41923 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
41924 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41925 {
41926 MacroAssembler _masm(&cbuf);
41927
41928#line 12350 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41929
41930 Label* L = opnd_array(3)->label();
41931 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
41932
41933#line 41933 "ad_x86.cpp"
41934 }
41935}
41936
41937uint jmpLoopEndNode::size(PhaseRegAlloc *ra_) const {
41938 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
41939 return (VerifyOops ? MachNode::size(ra_) : 6);
41940}
41941
41942void jmpLoopEndUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41943 cbuf.set_insts_mark();
41944 // Start at oper_input_base() and count operands
41945 unsigned idx0 = 1;
41946 unsigned idx1 = 1; // cmp
41947 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
41948 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41949 {
41950 MacroAssembler _masm(&cbuf);
41951
41952#line 12366 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41953
41954 Label* L = opnd_array(3)->label();
41955 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
41956
41957#line 41957 "ad_x86.cpp"
41958 }
41959}
41960
41961uint jmpLoopEndUNode::size(PhaseRegAlloc *ra_) const {
41962 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
41963 return (VerifyOops ? MachNode::size(ra_) : 6);
41964}
41965
41966void jmpLoopEndUCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41967 cbuf.set_insts_mark();
41968 // Start at oper_input_base() and count operands
41969 unsigned idx0 = 1;
41970 unsigned idx1 = 1; // cmp
41971 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
41972 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41973 {
41974 MacroAssembler _masm(&cbuf);
41975
41976#line 12381 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
41977
41978 Label* L = opnd_array(3)->label();
41979 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
41980
41981#line 41981 "ad_x86.cpp"
41982 }
41983}
41984
41985uint jmpLoopEndUCFNode::size(PhaseRegAlloc *ra_) const {
41986 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
41987 return (VerifyOops ? MachNode::size(ra_) : 6);
41988}
41989
41990void jmpLoopEnd_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41991 cbuf.set_insts_mark();
41992 // Start at oper_input_base() and count operands
41993 unsigned idx0 = 1;
41994 unsigned idx1 = 1; // cr
41995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
41996 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
41997 {
41998 MacroAssembler _masm(&cbuf);
41999
42000#line 12400 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42001
42002 Label* L = opnd_array(3)->label();
42003 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
42004 __ restorevectmask();
42005
42006#line 42006 "ad_x86.cpp"
42007 }
42008}
42009
42010uint jmpLoopEnd_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
42011 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size");
42012 return (VerifyOops ? MachNode::size(ra_) : 10);
42013}
42014
42015void jmpLoopEndU_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42016 cbuf.set_insts_mark();
42017 // Start at oper_input_base() and count operands
42018 unsigned idx0 = 1;
42019 unsigned idx1 = 1; // cmp
42020 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42021 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42022 {
42023 MacroAssembler _masm(&cbuf);
42024
42025#line 12418 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42026
42027 Label* L = opnd_array(3)->label();
42028 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
42029 __ restorevectmask();
42030
42031#line 42031 "ad_x86.cpp"
42032 }
42033}
42034
42035uint jmpLoopEndU_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
42036 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size");
42037 return (VerifyOops ? MachNode::size(ra_) : 10);
42038}
42039
42040void jmpLoopEndUCF_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42041 cbuf.set_insts_mark();
42042 // Start at oper_input_base() and count operands
42043 unsigned idx0 = 1;
42044 unsigned idx1 = 1; // cmp
42045 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42046 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42047 {
42048 MacroAssembler _masm(&cbuf);
42049
42050#line 12435 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42051
42052 Label* L = opnd_array(3)->label();
42053 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
42054 __ restorevectmask();
42055
42056#line 42056 "ad_x86.cpp"
42057 }
42058}
42059
42060uint jmpLoopEndUCF_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
42061 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size");
42062 return (VerifyOops ? MachNode::size(ra_) : 10);
42063}
42064
42065void jmpConUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42066 cbuf.set_insts_mark();
42067 // Start at oper_input_base() and count operands
42068 unsigned idx0 = 1;
42069 unsigned idx1 = 1; // cmp
42070 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42071 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42072 {
42073 MacroAssembler _masm(&cbuf);
42074
42075#line 12451 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42076
42077 Label* L = opnd_array(3)->label();
42078 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
42079
42080#line 42080 "ad_x86.cpp"
42081 }
42082}
42083
42084uint jmpConUNode::size(PhaseRegAlloc *ra_) const {
42085 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
42086 return (VerifyOops ? MachNode::size(ra_) : 6);
42087}
42088
42089void jmpConUCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42090 cbuf.set_insts_mark();
42091 // Start at oper_input_base() and count operands
42092 unsigned idx0 = 1;
42093 unsigned idx1 = 1; // cmp
42094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42095 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42096 {
42097 MacroAssembler _masm(&cbuf);
42098
42099#line 12465 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42100
42101 Label* L = opnd_array(3)->label();
42102 __ jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
42103
42104#line 42104 "ad_x86.cpp"
42105 }
42106}
42107
42108uint jmpConUCFNode::size(PhaseRegAlloc *ra_) const {
42109 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size");
42110 return (VerifyOops ? MachNode::size(ra_) : 6);
42111}
42112
42113void jmpConUCF2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42114 cbuf.set_insts_mark();
42115 // Start at oper_input_base() and count operands
42116 unsigned idx0 = 1;
42117 unsigned idx1 = 1; // cmp
42118 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42119 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42120 {
42121 MacroAssembler _masm(&cbuf);
42122
42123#line 12487 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42124
42125 Label* l = opnd_array(3)->label();
42126 if (opnd_array(1)->ccode()== Assembler::notEqual) {
42127 __ jcc(Assembler::parity, *l, false);
42128 __ jcc(Assembler::notEqual, *l, false);
42129 } else if (opnd_array(1)->ccode()== Assembler::equal) {
42130 Label done;
42131 __ jccb(Assembler::parity, done);
42132 __ jcc(Assembler::equal, *l, false);
42133 __ bind(done);
42134 } else {
42135 ShouldNotReachHere();
42136 }
42137
42138#line 42138 "ad_x86.cpp"
42139 }
42140}
42141
42142void partialSubtypeCheckNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42143 cbuf.set_insts_mark();
42144 // Start at oper_input_base() and count operands
42145 unsigned idx0 = 1;
42146 unsigned idx1 = 1; // sub
42147 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
42148 {
42149
42150#line 2083 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42151
42152 Register Rrdi = as_Register(RDI_enc); // result register
42153 Register Rrax = as_Register(RAX_enc); // super class
42154 Register Rrcx = as_Register(RCX_enc); // killed
42155 Register Rrsi = as_Register(RSI_enc); // sub class
42156 Label miss;
42157 const bool set_cond_codes = true;
42158
42159 MacroAssembler _masm(&cbuf);
42160 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
42161 NULL, &miss,
42162 /*set_cond_codes:*/ true);
42163 if ((0x1 /*primary()*/)) {
42164 __ xorptr(Rrdi, Rrdi);
42165 }
42166 __ bind(miss);
42167
42168#line 42168 "ad_x86.cpp"
42169 }
42170}
42171
42172void partialSubtypeCheck_vs_ZeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42173 cbuf.set_insts_mark();
42174 // Start at oper_input_base() and count operands
42175 unsigned idx0 = 1;
42176 unsigned idx1 = 1; // sub
42177 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
42178 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
42179 {
42180
42181#line 2083 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42182
42183 Register Rrdi = as_Register(RDI_enc); // result register
42184 Register Rrax = as_Register(RAX_enc); // super class
42185 Register Rrcx = as_Register(RCX_enc); // killed
42186 Register Rrsi = as_Register(RSI_enc); // sub class
42187 Label miss;
42188 const bool set_cond_codes = true;
42189
42190 MacroAssembler _masm(&cbuf);
42191 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
42192 NULL, &miss,
42193 /*set_cond_codes:*/ true);
42194 if ((0x0 /*primary()*/)) {
42195 __ xorptr(Rrdi, Rrdi);
42196 }
42197 __ bind(miss);
42198
42199#line 42199 "ad_x86.cpp"
42200 }
42201}
42202
42203void jmpDir_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42204 cbuf.set_insts_mark();
42205 // Start at oper_input_base() and count operands
42206 unsigned idx0 = 1;
42207 unsigned idx1 = 1; //
42208 {
42209 MacroAssembler _masm(&cbuf);
42210
42211#line 12575 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42212
42213 Label* L = opnd_array(1)->label();
42214 __ jmpb(*L);
42215
42216#line 42216 "ad_x86.cpp"
42217 }
42218}
42219
42220uint jmpDir_shortNode::size(PhaseRegAlloc *ra_) const {
42221 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42222 return (VerifyOops ? MachNode::size(ra_) : 2);
42223}
42224
42225void jmpCon_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42226 cbuf.set_insts_mark();
42227 // Start at oper_input_base() and count operands
42228 unsigned idx0 = 1;
42229 unsigned idx1 = 1; // cr
42230 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42231 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42232 {
42233 MacroAssembler _masm(&cbuf);
42234
42235#line 12591 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42236
42237 Label* L = opnd_array(3)->label();
42238 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42239
42240#line 42240 "ad_x86.cpp"
42241 }
42242}
42243
42244uint jmpCon_shortNode::size(PhaseRegAlloc *ra_) const {
42245 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42246 return (VerifyOops ? MachNode::size(ra_) : 2);
42247}
42248
42249void jmpLoopEnd_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42250 cbuf.set_insts_mark();
42251 // Start at oper_input_base() and count operands
42252 unsigned idx0 = 1;
42253 unsigned idx1 = 1; // cr
42254 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42255 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42256 {
42257 MacroAssembler _masm(&cbuf);
42258
42259#line 12607 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42260
42261 Label* L = opnd_array(3)->label();
42262 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42263
42264#line 42264 "ad_x86.cpp"
42265 }
42266}
42267
42268uint jmpLoopEnd_shortNode::size(PhaseRegAlloc *ra_) const {
42269 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42270 return (VerifyOops ? MachNode::size(ra_) : 2);
42271}
42272
42273void jmpLoopEndU_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42274 cbuf.set_insts_mark();
42275 // Start at oper_input_base() and count operands
42276 unsigned idx0 = 1;
42277 unsigned idx1 = 1; // cmp
42278 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42279 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42280 {
42281 MacroAssembler _masm(&cbuf);
42282
42283#line 12623 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42284
42285 Label* L = opnd_array(3)->label();
42286 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42287
42288#line 42288 "ad_x86.cpp"
42289 }
42290}
42291
42292uint jmpLoopEndU_shortNode::size(PhaseRegAlloc *ra_) const {
42293 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42294 return (VerifyOops ? MachNode::size(ra_) : 2);
42295}
42296
42297void jmpLoopEndUCF_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42298 cbuf.set_insts_mark();
42299 // Start at oper_input_base() and count operands
42300 unsigned idx0 = 1;
42301 unsigned idx1 = 1; // cmp
42302 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42303 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42304 {
42305 MacroAssembler _masm(&cbuf);
42306
42307#line 12638 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42308
42309 Label* L = opnd_array(3)->label();
42310 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42311
42312#line 42312 "ad_x86.cpp"
42313 }
42314}
42315
42316uint jmpLoopEndUCF_shortNode::size(PhaseRegAlloc *ra_) const {
42317 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42318 return (VerifyOops ? MachNode::size(ra_) : 2);
42319}
42320
42321void jmpConU_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42322 cbuf.set_insts_mark();
42323 // Start at oper_input_base() and count operands
42324 unsigned idx0 = 1;
42325 unsigned idx1 = 1; // cmp
42326 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42327 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42328 {
42329 MacroAssembler _masm(&cbuf);
42330
42331#line 12654 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42332
42333 Label* L = opnd_array(3)->label();
42334 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42335
42336#line 42336 "ad_x86.cpp"
42337 }
42338}
42339
42340uint jmpConU_shortNode::size(PhaseRegAlloc *ra_) const {
42341 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42342 return (VerifyOops ? MachNode::size(ra_) : 2);
42343}
42344
42345void jmpConUCF_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42346 cbuf.set_insts_mark();
42347 // Start at oper_input_base() and count operands
42348 unsigned idx0 = 1;
42349 unsigned idx1 = 1; // cmp
42350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42351 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42352 {
42353 MacroAssembler _masm(&cbuf);
42354
42355#line 12669 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42356
42357 Label* L = opnd_array(3)->label();
42358 __ jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L);
42359
42360#line 42360 "ad_x86.cpp"
42361 }
42362}
42363
42364uint jmpConUCF_shortNode::size(PhaseRegAlloc *ra_) const {
42365 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size");
42366 return (VerifyOops ? MachNode::size(ra_) : 2);
42367}
42368
42369void jmpConUCF2_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42370 cbuf.set_insts_mark();
42371 // Start at oper_input_base() and count operands
42372 unsigned idx0 = 1;
42373 unsigned idx1 = 1; // cmp
42374 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
42375 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
42376 {
42377 MacroAssembler _masm(&cbuf);
42378
42379#line 12693 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42380
42381 Label* l = opnd_array(3)->label();
42382 if (opnd_array(1)->ccode()== Assembler::notEqual) {
42383 __ jccb(Assembler::parity, *l);
42384 __ jccb(Assembler::notEqual, *l);
42385 } else if (opnd_array(1)->ccode()== Assembler::equal) {
42386 Label done;
42387 __ jccb(Assembler::parity, done);
42388 __ jccb(Assembler::equal, *l);
42389 __ bind(done);
42390 } else {
42391 ShouldNotReachHere();
42392 }
42393
42394#line 42394 "ad_x86.cpp"
42395 }
42396}
42397
42398uint jmpConUCF2_shortNode::size(PhaseRegAlloc *ra_) const {
42399 assert(VerifyOops || MachNode::size(ra_) <= 4, "bad fixed size");
42400 return (VerifyOops ? MachNode::size(ra_) : 4);
42401}
42402
42403void cmpFastLockRTMNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42404 cbuf.set_insts_mark();
42405 // Start at oper_input_base() and count operands
42406 unsigned idx0 = 1;
42407 unsigned idx1 = 1; // object
42408 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
42409 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
42410 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
42411 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1
42412 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // cx2
42413 {
42414 MacroAssembler _masm(&cbuf);
42415
42416#line 12720 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42417
42418 __ fast_lock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */,
42419 opnd_array(4)->as_Register(ra_,this,idx4)/* scr */, opnd_array(5)->as_Register(ra_,this,idx5)/* cx1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* cx2 */,
42420 _counters, _rtm_counters, _stack_rtm_counters,
42421 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
42422 true, ra_->C->profile_rtm());
42423
42424#line 42424 "ad_x86.cpp"
42425 }
42426}
42427
42428void cmpFastLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42429 cbuf.set_insts_mark();
42430 // Start at oper_input_base() and count operands
42431 unsigned idx0 = 1;
42432 unsigned idx1 = 1; // object
42433 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
42434 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
42435 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
42436 {
42437 MacroAssembler _masm(&cbuf);
42438
42439#line 12736 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42440
42441 __ fast_lock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */,
42442 opnd_array(4)->as_Register(ra_,this,idx4)/* scr */, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
42443
42444#line 42444 "ad_x86.cpp"
42445 }
42446}
42447
42448void cmpFastUnlockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42449 cbuf.set_insts_mark();
42450 // Start at oper_input_base() and count operands
42451 unsigned idx0 = 1;
42452 unsigned idx1 = 1; // object
42453 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
42454 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
42455 {
42456 MacroAssembler _masm(&cbuf);
42457
42458#line 12748 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42459
42460 __ fast_unlock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, ra_->C->use_rtm());
42461
42462#line 42462 "ad_x86.cpp"
42463 }
42464}
42465
42466void safePoint_pollNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42467 cbuf.set_insts_mark();
42468 // Start at oper_input_base() and count operands
42469 unsigned idx0 = 5;
42470 unsigned idx1 = 5; //
42471 {
42472 MacroAssembler _masm(&cbuf);
42473
42474#line 12766 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42475
42476 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
42477 __ testl(rax, addr);
42478
42479#line 42479 "ad_x86.cpp"
42480 }
42481}
42482
42483void safePoint_poll_farNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42484 cbuf.set_insts_mark();
42485 // Start at oper_input_base() and count operands
42486 unsigned idx0 = 5;
42487 unsigned idx1 = 5; // cr
42488 {
42489 MacroAssembler _masm(&cbuf);
42490
42491#line 12782 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42492
42493 __ relocate(relocInfo::poll_type);
42494 __ testl(rax, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* poll */, 0));
42495
42496#line 42496 "ad_x86.cpp"
42497 }
42498}
42499
42500void safePoint_poll_tlsNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42501 cbuf.set_insts_mark();
42502 // Start at oper_input_base() and count operands
42503 unsigned idx0 = 5;
42504 unsigned idx1 = 5; // cr
42505 {
42506 MacroAssembler _masm(&cbuf);
42507
42508#line 12799 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42509
42510 __ relocate(relocInfo::poll_type);
42511 address pre_pc = __ pc();
42512 __ testl(rax, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* poll */, 0));
42513 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
42514
42515#line 42515 "ad_x86.cpp"
42516 }
42517}
42518
42519uint safePoint_poll_tlsNode::size(PhaseRegAlloc *ra_) const {
42520 assert(VerifyOops || MachNode::size(ra_) <= 4, "bad fixed size");
42521 return (VerifyOops ? MachNode::size(ra_) : 4);
42522}
42523
42524void CallStaticJavaDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42525 cbuf.set_insts_mark();
42526 // Start at oper_input_base() and count operands
42527 unsigned idx0 = 1;
42528 unsigned idx1 = 1; //
42529 {
42530
42531#line 2101 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42532
42533 debug_only(int off0 = cbuf.insts_size());
42534 if (generate_vzeroupper(Compile::current())) {
42535 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
42536 // Clear upper bits of YMM registers when current compiled code uses
42537 // wide vectors to avoid AVX <-> SSE transition penalty during call.
42538 MacroAssembler _masm(&cbuf);
42539 __ vzeroupper();
42540 }
42541 debug_only(int off1 = cbuf.insts_size());
42542 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
42543
42544#line 42544 "ad_x86.cpp"
42545 }
42546 {
42547
42548#line 2135 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42549
42550 // JAVA STATIC CALL
42551 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
42552 // determine who we intended to call.
42553 cbuf.set_insts_mark();
42554 emit_d8(cbuf, (0xE8 /*primary()*/));
42555
42556 if (!_method) {
42557 emit_d32_reloc(cbuf, (int) (opnd_array(1)->method() - ((intptr_t) cbuf.insts_end()) - 4),
42558 runtime_call_Relocation::spec(),
42559 RELOC_DISP32);
42560 } else {
42561 int method_index = resolved_method_index(cbuf);
42562 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
42563 : static_call_Relocation::spec(method_index);
42564 emit_d32_reloc(cbuf, (int) (opnd_array(1)->method() - ((intptr_t) cbuf.insts_end()) - 4),
42565 rspec, RELOC_DISP32);
42566 // Emit stubs for static call.
42567 address mark = cbuf.insts_mark();
42568 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
42569 if (stub == NULL) {
42570 ciEnv::current()->record_failure("CodeCache is full");
42571 return;
42572 }
42573#if INCLUDE_AOT
42574 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
42575#endif
42576 }
42577
42578#line 42578 "ad_x86.cpp"
42579 }
42580 {
42581
42582#line 2024 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42583
42584 if (VerifyStackAtCalls) {
42585 // Check that stack depth is unchanged: find majik cookie on stack
42586 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
42587 MacroAssembler _masm(&cbuf);
42588 Label L;
42589 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
42590 __ jccb(Assembler::equal, L);
42591 // Die if stack mismatch
42592 __ int3();
42593 __ bind(L);
42594 }
42595
42596#line 42596 "ad_x86.cpp"
42597 }
42598}
42599
42600void CallDynamicJavaDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42601 cbuf.set_insts_mark();
42602 // Start at oper_input_base() and count operands
42603 unsigned idx0 = 1;
42604 unsigned idx1 = 1; //
42605 {
42606
42607#line 2101 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42608
42609 debug_only(int off0 = cbuf.insts_size());
42610 if (generate_vzeroupper(Compile::current())) {
42611 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
42612 // Clear upper bits of YMM registers when current compiled code uses
42613 // wide vectors to avoid AVX <-> SSE transition penalty during call.
42614 MacroAssembler _masm(&cbuf);
42615 __ vzeroupper();
42616 }
42617 debug_only(int off1 = cbuf.insts_size());
42618 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
42619
42620#line 42620 "ad_x86.cpp"
42621 }
42622 {
42623
42624#line 2165 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42625
42626 MacroAssembler _masm(&cbuf);
42627 __ ic_call((address)opnd_array(1)->method(), resolved_method_index(cbuf));
42628
42629#line 42629 "ad_x86.cpp"
42630 }
42631 {
42632
42633#line 2024 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42634
42635 if (VerifyStackAtCalls) {
42636 // Check that stack depth is unchanged: find majik cookie on stack
42637 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
42638 MacroAssembler _masm(&cbuf);
42639 Label L;
42640 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
42641 __ jccb(Assembler::equal, L);
42642 // Die if stack mismatch
42643 __ int3();
42644 __ bind(L);
42645 }
42646
42647#line 42647 "ad_x86.cpp"
42648 }
42649}
42650
42651void CallRuntimeDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42652 cbuf.set_insts_mark();
42653 // Start at oper_input_base() and count operands
42654 unsigned idx0 = 1;
42655 unsigned idx1 = 1; //
42656 {
42657
42658#line 2101 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42659
42660 debug_only(int off0 = cbuf.insts_size());
42661 if (generate_vzeroupper(Compile::current())) {
42662 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
42663 // Clear upper bits of YMM registers when current compiled code uses
42664 // wide vectors to avoid AVX <-> SSE transition penalty during call.
42665 MacroAssembler _masm(&cbuf);
42666 __ vzeroupper();
42667 }
42668 debug_only(int off1 = cbuf.insts_size());
42669 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
42670
42671#line 42671 "ad_x86.cpp"
42672 }
42673 {
42674
42675#line 2114 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42676
42677 // No relocation needed
42678 MacroAssembler _masm(&cbuf);
42679 __ mov64(r10, (int64_t) opnd_array(1)->method());
42680 __ call(r10);
42681
42682#line 42682 "ad_x86.cpp"
42683 }
42684}
42685
42686void CallLeafDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42687 cbuf.set_insts_mark();
42688 // Start at oper_input_base() and count operands
42689 unsigned idx0 = 1;
42690 unsigned idx1 = 1; //
42691 {
42692
42693#line 2101 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42694
42695 debug_only(int off0 = cbuf.insts_size());
42696 if (generate_vzeroupper(Compile::current())) {
42697 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
42698 // Clear upper bits of YMM registers when current compiled code uses
42699 // wide vectors to avoid AVX <-> SSE transition penalty during call.
42700 MacroAssembler _masm(&cbuf);
42701 __ vzeroupper();
42702 }
42703 debug_only(int off1 = cbuf.insts_size());
42704 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
42705
42706#line 42706 "ad_x86.cpp"
42707 }
42708 {
42709
42710#line 2114 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42711
42712 // No relocation needed
42713 MacroAssembler _masm(&cbuf);
42714 __ mov64(r10, (int64_t) opnd_array(1)->method());
42715 __ call(r10);
42716
42717#line 42717 "ad_x86.cpp"
42718 }
42719}
42720
42721void CallLeafNoFPDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42722 cbuf.set_insts_mark();
42723 // Start at oper_input_base() and count operands
42724 unsigned idx0 = 1;
42725 unsigned idx1 = 1; //
42726 {
42727
42728#line 2101 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42729
42730 debug_only(int off0 = cbuf.insts_size());
42731 if (generate_vzeroupper(Compile::current())) {
42732 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
42733 // Clear upper bits of YMM registers when current compiled code uses
42734 // wide vectors to avoid AVX <-> SSE transition penalty during call.
42735 MacroAssembler _masm(&cbuf);
42736 __ vzeroupper();
42737 }
42738 debug_only(int off1 = cbuf.insts_size());
42739 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
42740
42741#line 42741 "ad_x86.cpp"
42742 }
42743 {
42744
42745#line 2114 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42746
42747 // No relocation needed
42748 MacroAssembler _masm(&cbuf);
42749 __ mov64(r10, (int64_t) opnd_array(1)->method());
42750 __ call(r10);
42751
42752#line 42752 "ad_x86.cpp"
42753 }
42754}
42755
42756void RetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42757 cbuf.set_insts_mark();
42758 // Start at oper_input_base() and count operands
42759 unsigned idx0 = 5;
42760 unsigned idx1 = 5; //
42761 {
42762
42763#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42764
42765 emit_opcode(cbuf, (0xC3 /*primary()*/));
42766
42767#line 42767 "ad_x86.cpp"
42768 }
42769}
42770
42771void TailCalljmpIndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42772 cbuf.set_insts_mark();
42773 // Start at oper_input_base() and count operands
42774 unsigned idx0 = 5;
42775 unsigned idx1 = 5; // method_oop
42776 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
42777 {
42778
42779#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42780
42781 if (opnd_array(1)->reg(ra_,this,idx1)/* jump_target */ >= 8) {
42782 emit_opcode(cbuf, Assembler::REX_B);
42783 }
42784
42785#line 42785 "ad_x86.cpp"
42786 }
42787 {
42788
42789#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42790
42791 emit_opcode(cbuf, (0xFF /*primary()*/));
42792
42793#line 42793 "ad_x86.cpp"
42794 }
42795 {
42796
42797#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42798
42799 // INC, DEC, IDIV, IMOD, JMP indirect, ...
42800 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* jump_target */ & 7);
42801
42802#line 42802 "ad_x86.cpp"
42803 }
42804}
42805
42806void tailjmpIndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42807 cbuf.set_insts_mark();
42808 // Start at oper_input_base() and count operands
42809 unsigned idx0 = 5;
42810 unsigned idx1 = 5; // ex_oop
42811 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
42812 {
42813
42814#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42815
42816 emit_opcode(cbuf, (0x5a));
42817
42818#line 42818 "ad_x86.cpp"
42819 }
42820 {
42821
42822#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42823
42824 if (opnd_array(1)->reg(ra_,this,idx1)/* jump_target */ >= 8) {
42825 emit_opcode(cbuf, Assembler::REX_B);
42826 }
42827
42828#line 42828 "ad_x86.cpp"
42829 }
42830 {
42831
42832#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42833
42834 emit_opcode(cbuf, (0xFF /*primary()*/));
42835
42836#line 42836 "ad_x86.cpp"
42837 }
42838 {
42839
42840#line 2070 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42841
42842 // INC, DEC, IDIV, IMOD, JMP indirect, ...
42843 emit_rm(cbuf, 0x3, (0x4 /*secondary()*/), opnd_array(1)->reg(ra_,this,idx1)/* jump_target */ & 7);
42844
42845#line 42845 "ad_x86.cpp"
42846 }
42847}
42848
42849void CreateExceptionNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42850 cbuf.set_insts_mark();
42851 // Start at oper_input_base() and count operands
42852 unsigned idx0 = 1;
42853 unsigned idx1 = 1; //
42854 // User did not define which encode class to use.
42855}
42856
42857uint CreateExceptionNode::size(PhaseRegAlloc *ra_) const {
42858 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
42859 return (VerifyOops ? MachNode::size(ra_) : 0);
42860}
42861
42862void RethrowExceptionNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42863 cbuf.set_insts_mark();
42864 // Start at oper_input_base() and count operands
42865 unsigned idx0 = 5;
42866 unsigned idx1 = 5; //
42867 {
42868
42869#line 2704 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
42870
42871 cbuf.set_insts_mark();
42872 emit_opcode(cbuf, 0xE9); // jmp entry
42873 emit_d32_reloc(cbuf,
42874 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
42875 runtime_call_Relocation::spec(),
42876 RELOC_DISP32);
42877
42878#line 42878 "ad_x86.cpp"
42879 }
42880}
42881
42882void tlsLoadPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42883 cbuf.set_insts_mark();
42884 // Start at oper_input_base() and count operands
42885 unsigned idx0 = 1;
42886 unsigned idx1 = 1; //
42887 // User did not define which encode class to use.
42888}
42889
42890uint tlsLoadPNode::size(PhaseRegAlloc *ra_) const {
42891 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size");
42892 return (VerifyOops ? MachNode::size(ra_) : 0);
42893}
42894
42895void ShouldNotReachHereNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42896 cbuf.set_insts_mark();
42897 // Start at oper_input_base() and count operands
42898 unsigned idx0 = 5;
42899 unsigned idx1 = 5; //
42900 {
42901 MacroAssembler _masm(&cbuf);
42902
42903#line 2092 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42904
42905 __ ud2();
42906
42907#line 42907 "ad_x86.cpp"
42908 }
42909}
42910
42911void setMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42912 cbuf.set_insts_mark();
42913 // Start at oper_input_base() and count operands
42914 unsigned idx0 = 1;
42915 unsigned idx1 = 1; // src
42916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
42917 {
42918 MacroAssembler _masm(&cbuf);
42919
42920#line 2105 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42921
42922 __ setvectmask(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
42923
42924#line 42924 "ad_x86.cpp"
42925 }
42926}
42927
42928void addF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42929 cbuf.set_insts_mark();
42930 // Start at oper_input_base() and count operands
42931 unsigned idx0 = 1;
42932 unsigned idx1 = 1; // dst
42933 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
42934 {
42935 MacroAssembler _masm(&cbuf);
42936
42937#line 2119 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42938
42939 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
42940
42941#line 42941 "ad_x86.cpp"
42942 }
42943}
42944
42945void addF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42946 cbuf.set_insts_mark();
42947 // Start at oper_input_base() and count operands
42948 unsigned idx0 = 2;
42949 unsigned idx1 = 2; // dst
42950 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
42951 {
42952 MacroAssembler _masm(&cbuf);
42953
42954#line 2131 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42955
42956 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
42957
42958#line 42958 "ad_x86.cpp"
42959 }
42960}
42961
42962void addF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42963 cbuf.set_insts_mark();
42964 // Start at oper_input_base() and count operands
42965 unsigned idx0 = 2;
42966 unsigned idx1 = 2; // src
42967 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
42968 {
42969 MacroAssembler _masm(&cbuf);
42970
42971#line 2131 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42972
42973 __ addss(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
42974
42975#line 42975 "ad_x86.cpp"
42976 }
42977}
42978
42979void addF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42980 cbuf.set_insts_mark();
42981 // Start at oper_input_base() and count operands
42982 unsigned idx0 = 1;
42983 unsigned idx1 = 1; // dst
42984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
42985 {
42986 MacroAssembler _masm(&cbuf);
42987
42988#line 2142 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
42989
42990 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
42991
42992#line 42992 "ad_x86.cpp"
42993 }
42994}
42995
42996void addF_immNode::eval_constant(Compile* C) {
42997 {
42998
42999#line 2143 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43000 _constant = C->constant_table().add(this, opnd_array(2));
43001#line 43001 "ad_x86.cpp"
43002 }
43003}
43004void addF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43005 cbuf.set_insts_mark();
43006 // Start at oper_input_base() and count operands
43007 unsigned idx0 = 1;
43008 unsigned idx1 = 1; // src1
43009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43010 {
43011 MacroAssembler _masm(&cbuf);
43012
43013#line 2154 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43014
43015 __ vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43016
43017#line 43017 "ad_x86.cpp"
43018 }
43019}
43020
43021void addF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43022 cbuf.set_insts_mark();
43023 // Start at oper_input_base() and count operands
43024 unsigned idx0 = 2;
43025 unsigned idx1 = 2; // src1
43026 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43027 {
43028 MacroAssembler _masm(&cbuf);
43029
43030#line 2166 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43031
43032 __ vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43033
43034#line 43034 "ad_x86.cpp"
43035 }
43036}
43037
43038void addF_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43039 cbuf.set_insts_mark();
43040 // Start at oper_input_base() and count operands
43041 unsigned idx0 = 2;
43042 unsigned idx1 = 2; // src2
43043 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
43044 {
43045 MacroAssembler _masm(&cbuf);
43046
43047#line 2166 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43048
43049 __ vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43050
43051#line 43051 "ad_x86.cpp"
43052 }
43053}
43054
43055void addF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43056 cbuf.set_insts_mark();
43057 // Start at oper_input_base() and count operands
43058 unsigned idx0 = 1;
43059 unsigned idx1 = 1; // src
43060 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43061 {
43062 MacroAssembler _masm(&cbuf);
43063
43064#line 2178 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43065
43066 __ vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43067
43068#line 43068 "ad_x86.cpp"
43069 }
43070}
43071
43072void addF_reg_immNode::eval_constant(Compile* C) {
43073 {
43074
43075#line 2179 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43076 _constant = C->constant_table().add(this, opnd_array(2));
43077#line 43077 "ad_x86.cpp"
43078 }
43079}
43080void addD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43081 cbuf.set_insts_mark();
43082 // Start at oper_input_base() and count operands
43083 unsigned idx0 = 1;
43084 unsigned idx1 = 1; // dst
43085 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43086 {
43087 MacroAssembler _masm(&cbuf);
43088
43089#line 2190 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43090
43091 __ addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43092
43093#line 43093 "ad_x86.cpp"
43094 }
43095}
43096
43097void addD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43098 cbuf.set_insts_mark();
43099 // Start at oper_input_base() and count operands
43100 unsigned idx0 = 2;
43101 unsigned idx1 = 2; // dst
43102 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43103 {
43104 MacroAssembler _masm(&cbuf);
43105
43106#line 2202 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43107
43108 __ addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43109
43110#line 43110 "ad_x86.cpp"
43111 }
43112}
43113
43114void addD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43115 cbuf.set_insts_mark();
43116 // Start at oper_input_base() and count operands
43117 unsigned idx0 = 2;
43118 unsigned idx1 = 2; // src
43119 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
43120 {
43121 MacroAssembler _masm(&cbuf);
43122
43123#line 2202 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43124
43125 __ addsd(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43126
43127#line 43127 "ad_x86.cpp"
43128 }
43129}
43130
43131void addD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43132 cbuf.set_insts_mark();
43133 // Start at oper_input_base() and count operands
43134 unsigned idx0 = 1;
43135 unsigned idx1 = 1; // dst
43136 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43137 {
43138 MacroAssembler _masm(&cbuf);
43139
43140#line 2213 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43141
43142 __ addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43143
43144#line 43144 "ad_x86.cpp"
43145 }
43146}
43147
43148void addD_immNode::eval_constant(Compile* C) {
43149 {
43150
43151#line 2214 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43152 _constant = C->constant_table().add(this, opnd_array(2));
43153#line 43153 "ad_x86.cpp"
43154 }
43155}
43156void addD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43157 cbuf.set_insts_mark();
43158 // Start at oper_input_base() and count operands
43159 unsigned idx0 = 1;
43160 unsigned idx1 = 1; // src1
43161 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43162 {
43163 MacroAssembler _masm(&cbuf);
43164
43165#line 2225 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43166
43167 __ vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43168
43169#line 43169 "ad_x86.cpp"
43170 }
43171}
43172
43173void addD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43174 cbuf.set_insts_mark();
43175 // Start at oper_input_base() and count operands
43176 unsigned idx0 = 2;
43177 unsigned idx1 = 2; // src1
43178 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43179 {
43180 MacroAssembler _masm(&cbuf);
43181
43182#line 2237 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43183
43184 __ vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43185
43186#line 43186 "ad_x86.cpp"
43187 }
43188}
43189
43190void addD_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43191 cbuf.set_insts_mark();
43192 // Start at oper_input_base() and count operands
43193 unsigned idx0 = 2;
43194 unsigned idx1 = 2; // src2
43195 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
43196 {
43197 MacroAssembler _masm(&cbuf);
43198
43199#line 2237 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43200
43201 __ vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43202
43203#line 43203 "ad_x86.cpp"
43204 }
43205}
43206
43207void addD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43208 cbuf.set_insts_mark();
43209 // Start at oper_input_base() and count operands
43210 unsigned idx0 = 1;
43211 unsigned idx1 = 1; // src
43212 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43213 {
43214 MacroAssembler _masm(&cbuf);
43215
43216#line 2249 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43217
43218 __ vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43219
43220#line 43220 "ad_x86.cpp"
43221 }
43222}
43223
43224void addD_reg_immNode::eval_constant(Compile* C) {
43225 {
43226
43227#line 2250 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43228 _constant = C->constant_table().add(this, opnd_array(2));
43229#line 43229 "ad_x86.cpp"
43230 }
43231}
43232void subF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43233 cbuf.set_insts_mark();
43234 // Start at oper_input_base() and count operands
43235 unsigned idx0 = 1;
43236 unsigned idx1 = 1; // dst
43237 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43238 {
43239 MacroAssembler _masm(&cbuf);
43240
43241#line 2261 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43242
43243 __ subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43244
43245#line 43245 "ad_x86.cpp"
43246 }
43247}
43248
43249void subF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43250 cbuf.set_insts_mark();
43251 // Start at oper_input_base() and count operands
43252 unsigned idx0 = 2;
43253 unsigned idx1 = 2; // dst
43254 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43255 {
43256 MacroAssembler _masm(&cbuf);
43257
43258#line 2273 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43259
43260 __ subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43261
43262#line 43262 "ad_x86.cpp"
43263 }
43264}
43265
43266void subF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43267 cbuf.set_insts_mark();
43268 // Start at oper_input_base() and count operands
43269 unsigned idx0 = 1;
43270 unsigned idx1 = 1; // dst
43271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43272 {
43273 MacroAssembler _masm(&cbuf);
43274
43275#line 2284 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43276
43277 __ subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43278
43279#line 43279 "ad_x86.cpp"
43280 }
43281}
43282
43283void subF_immNode::eval_constant(Compile* C) {
43284 {
43285
43286#line 2285 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43287 _constant = C->constant_table().add(this, opnd_array(2));
43288#line 43288 "ad_x86.cpp"
43289 }
43290}
43291void subF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43292 cbuf.set_insts_mark();
43293 // Start at oper_input_base() and count operands
43294 unsigned idx0 = 1;
43295 unsigned idx1 = 1; // src1
43296 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43297 {
43298 MacroAssembler _masm(&cbuf);
43299
43300#line 2296 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43301
43302 __ vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43303
43304#line 43304 "ad_x86.cpp"
43305 }
43306}
43307
43308void subF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43309 cbuf.set_insts_mark();
43310 // Start at oper_input_base() and count operands
43311 unsigned idx0 = 2;
43312 unsigned idx1 = 2; // src1
43313 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43314 {
43315 MacroAssembler _masm(&cbuf);
43316
43317#line 2308 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43318
43319 __ vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43320
43321#line 43321 "ad_x86.cpp"
43322 }
43323}
43324
43325void subF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43326 cbuf.set_insts_mark();
43327 // Start at oper_input_base() and count operands
43328 unsigned idx0 = 1;
43329 unsigned idx1 = 1; // src
43330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43331 {
43332 MacroAssembler _masm(&cbuf);
43333
43334#line 2320 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43335
43336 __ vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43337
43338#line 43338 "ad_x86.cpp"
43339 }
43340}
43341
43342void subF_reg_immNode::eval_constant(Compile* C) {
43343 {
43344
43345#line 2321 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43346 _constant = C->constant_table().add(this, opnd_array(2));
43347#line 43347 "ad_x86.cpp"
43348 }
43349}
43350void subD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43351 cbuf.set_insts_mark();
43352 // Start at oper_input_base() and count operands
43353 unsigned idx0 = 1;
43354 unsigned idx1 = 1; // dst
43355 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43356 {
43357 MacroAssembler _masm(&cbuf);
43358
43359#line 2332 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43360
43361 __ subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43362
43363#line 43363 "ad_x86.cpp"
43364 }
43365}
43366
43367void subD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43368 cbuf.set_insts_mark();
43369 // Start at oper_input_base() and count operands
43370 unsigned idx0 = 2;
43371 unsigned idx1 = 2; // dst
43372 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43373 {
43374 MacroAssembler _masm(&cbuf);
43375
43376#line 2344 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43377
43378 __ subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43379
43380#line 43380 "ad_x86.cpp"
43381 }
43382}
43383
43384void subD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43385 cbuf.set_insts_mark();
43386 // Start at oper_input_base() and count operands
43387 unsigned idx0 = 1;
43388 unsigned idx1 = 1; // dst
43389 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43390 {
43391 MacroAssembler _masm(&cbuf);
43392
43393#line 2355 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43394
43395 __ subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43396
43397#line 43397 "ad_x86.cpp"
43398 }
43399}
43400
43401void subD_immNode::eval_constant(Compile* C) {
43402 {
43403
43404#line 2356 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43405 _constant = C->constant_table().add(this, opnd_array(2));
43406#line 43406 "ad_x86.cpp"
43407 }
43408}
43409void subD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43410 cbuf.set_insts_mark();
43411 // Start at oper_input_base() and count operands
43412 unsigned idx0 = 1;
43413 unsigned idx1 = 1; // src1
43414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43415 {
43416 MacroAssembler _masm(&cbuf);
43417
43418#line 2367 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43419
43420 __ vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43421
43422#line 43422 "ad_x86.cpp"
43423 }
43424}
43425
43426void subD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43427 cbuf.set_insts_mark();
43428 // Start at oper_input_base() and count operands
43429 unsigned idx0 = 2;
43430 unsigned idx1 = 2; // src1
43431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43432 {
43433 MacroAssembler _masm(&cbuf);
43434
43435#line 2379 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43436
43437 __ vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43438
43439#line 43439 "ad_x86.cpp"
43440 }
43441}
43442
43443void subD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43444 cbuf.set_insts_mark();
43445 // Start at oper_input_base() and count operands
43446 unsigned idx0 = 1;
43447 unsigned idx1 = 1; // src
43448 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43449 {
43450 MacroAssembler _masm(&cbuf);
43451
43452#line 2391 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43453
43454 __ vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43455
43456#line 43456 "ad_x86.cpp"
43457 }
43458}
43459
43460void subD_reg_immNode::eval_constant(Compile* C) {
43461 {
43462
43463#line 2392 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43464 _constant = C->constant_table().add(this, opnd_array(2));
43465#line 43465 "ad_x86.cpp"
43466 }
43467}
43468void mulF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43469 cbuf.set_insts_mark();
43470 // Start at oper_input_base() and count operands
43471 unsigned idx0 = 1;
43472 unsigned idx1 = 1; // dst
43473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43474 {
43475 MacroAssembler _masm(&cbuf);
43476
43477#line 2403 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43478
43479 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43480
43481#line 43481 "ad_x86.cpp"
43482 }
43483}
43484
43485void mulF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43486 cbuf.set_insts_mark();
43487 // Start at oper_input_base() and count operands
43488 unsigned idx0 = 2;
43489 unsigned idx1 = 2; // dst
43490 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43491 {
43492 MacroAssembler _masm(&cbuf);
43493
43494#line 2415 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43495
43496 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43497
43498#line 43498 "ad_x86.cpp"
43499 }
43500}
43501
43502void mulF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43503 cbuf.set_insts_mark();
43504 // Start at oper_input_base() and count operands
43505 unsigned idx0 = 2;
43506 unsigned idx1 = 2; // src
43507 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
43508 {
43509 MacroAssembler _masm(&cbuf);
43510
43511#line 2415 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43512
43513 __ mulss(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43514
43515#line 43515 "ad_x86.cpp"
43516 }
43517}
43518
43519void mulF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43520 cbuf.set_insts_mark();
43521 // Start at oper_input_base() and count operands
43522 unsigned idx0 = 1;
43523 unsigned idx1 = 1; // dst
43524 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43525 {
43526 MacroAssembler _masm(&cbuf);
43527
43528#line 2426 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43529
43530 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43531
43532#line 43532 "ad_x86.cpp"
43533 }
43534}
43535
43536void mulF_immNode::eval_constant(Compile* C) {
43537 {
43538
43539#line 2427 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43540 _constant = C->constant_table().add(this, opnd_array(2));
43541#line 43541 "ad_x86.cpp"
43542 }
43543}
43544void mulF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43545 cbuf.set_insts_mark();
43546 // Start at oper_input_base() and count operands
43547 unsigned idx0 = 1;
43548 unsigned idx1 = 1; // src1
43549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43550 {
43551 MacroAssembler _masm(&cbuf);
43552
43553#line 2438 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43554
43555 __ vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43556
43557#line 43557 "ad_x86.cpp"
43558 }
43559}
43560
43561void mulF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43562 cbuf.set_insts_mark();
43563 // Start at oper_input_base() and count operands
43564 unsigned idx0 = 2;
43565 unsigned idx1 = 2; // src1
43566 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43567 {
43568 MacroAssembler _masm(&cbuf);
43569
43570#line 2450 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43571
43572 __ vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43573
43574#line 43574 "ad_x86.cpp"
43575 }
43576}
43577
43578void mulF_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43579 cbuf.set_insts_mark();
43580 // Start at oper_input_base() and count operands
43581 unsigned idx0 = 2;
43582 unsigned idx1 = 2; // src2
43583 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
43584 {
43585 MacroAssembler _masm(&cbuf);
43586
43587#line 2450 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43588
43589 __ vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43590
43591#line 43591 "ad_x86.cpp"
43592 }
43593}
43594
43595void mulF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43596 cbuf.set_insts_mark();
43597 // Start at oper_input_base() and count operands
43598 unsigned idx0 = 1;
43599 unsigned idx1 = 1; // src
43600 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43601 {
43602 MacroAssembler _masm(&cbuf);
43603
43604#line 2462 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43605
43606 __ vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43607
43608#line 43608 "ad_x86.cpp"
43609 }
43610}
43611
43612void mulF_reg_immNode::eval_constant(Compile* C) {
43613 {
43614
43615#line 2463 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43616 _constant = C->constant_table().add(this, opnd_array(2));
43617#line 43617 "ad_x86.cpp"
43618 }
43619}
43620void mulD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43621 cbuf.set_insts_mark();
43622 // Start at oper_input_base() and count operands
43623 unsigned idx0 = 1;
43624 unsigned idx1 = 1; // dst
43625 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43626 {
43627 MacroAssembler _masm(&cbuf);
43628
43629#line 2474 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43630
43631 __ mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43632
43633#line 43633 "ad_x86.cpp"
43634 }
43635}
43636
43637void mulD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43638 cbuf.set_insts_mark();
43639 // Start at oper_input_base() and count operands
43640 unsigned idx0 = 2;
43641 unsigned idx1 = 2; // dst
43642 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43643 {
43644 MacroAssembler _masm(&cbuf);
43645
43646#line 2486 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43647
43648 __ mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43649
43650#line 43650 "ad_x86.cpp"
43651 }
43652}
43653
43654void mulD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43655 cbuf.set_insts_mark();
43656 // Start at oper_input_base() and count operands
43657 unsigned idx0 = 2;
43658 unsigned idx1 = 2; // src
43659 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
43660 {
43661 MacroAssembler _masm(&cbuf);
43662
43663#line 2486 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43664
43665 __ mulsd(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43666
43667#line 43667 "ad_x86.cpp"
43668 }
43669}
43670
43671void mulD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43672 cbuf.set_insts_mark();
43673 // Start at oper_input_base() and count operands
43674 unsigned idx0 = 1;
43675 unsigned idx1 = 1; // dst
43676 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43677 {
43678 MacroAssembler _masm(&cbuf);
43679
43680#line 2497 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43681
43682 __ mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43683
43684#line 43684 "ad_x86.cpp"
43685 }
43686}
43687
43688void mulD_immNode::eval_constant(Compile* C) {
43689 {
43690
43691#line 2498 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43692 _constant = C->constant_table().add(this, opnd_array(2));
43693#line 43693 "ad_x86.cpp"
43694 }
43695}
43696void mulD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43697 cbuf.set_insts_mark();
43698 // Start at oper_input_base() and count operands
43699 unsigned idx0 = 1;
43700 unsigned idx1 = 1; // src1
43701 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43702 {
43703 MacroAssembler _masm(&cbuf);
43704
43705#line 2509 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43706
43707 __ vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43708
43709#line 43709 "ad_x86.cpp"
43710 }
43711}
43712
43713void mulD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43714 cbuf.set_insts_mark();
43715 // Start at oper_input_base() and count operands
43716 unsigned idx0 = 2;
43717 unsigned idx1 = 2; // src1
43718 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43719 {
43720 MacroAssembler _masm(&cbuf);
43721
43722#line 2521 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43723
43724 __ vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43725
43726#line 43726 "ad_x86.cpp"
43727 }
43728}
43729
43730void mulD_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43731 cbuf.set_insts_mark();
43732 // Start at oper_input_base() and count operands
43733 unsigned idx0 = 2;
43734 unsigned idx1 = 2; // src2
43735 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
43736 {
43737 MacroAssembler _masm(&cbuf);
43738
43739#line 2521 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43740
43741 __ vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
43742
43743#line 43743 "ad_x86.cpp"
43744 }
43745}
43746
43747void mulD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43748 cbuf.set_insts_mark();
43749 // Start at oper_input_base() and count operands
43750 unsigned idx0 = 1;
43751 unsigned idx1 = 1; // src
43752 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43753 {
43754 MacroAssembler _masm(&cbuf);
43755
43756#line 2533 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43757
43758 __ vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43759
43760#line 43760 "ad_x86.cpp"
43761 }
43762}
43763
43764void mulD_reg_immNode::eval_constant(Compile* C) {
43765 {
43766
43767#line 2534 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43768 _constant = C->constant_table().add(this, opnd_array(2));
43769#line 43769 "ad_x86.cpp"
43770 }
43771}
43772void divF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43773 cbuf.set_insts_mark();
43774 // Start at oper_input_base() and count operands
43775 unsigned idx0 = 1;
43776 unsigned idx1 = 1; // dst
43777 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43778 {
43779 MacroAssembler _masm(&cbuf);
43780
43781#line 2545 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43782
43783 __ divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43784
43785#line 43785 "ad_x86.cpp"
43786 }
43787}
43788
43789void divF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43790 cbuf.set_insts_mark();
43791 // Start at oper_input_base() and count operands
43792 unsigned idx0 = 2;
43793 unsigned idx1 = 2; // dst
43794 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43795 {
43796 MacroAssembler _masm(&cbuf);
43797
43798#line 2557 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43799
43800 __ divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43801
43802#line 43802 "ad_x86.cpp"
43803 }
43804}
43805
43806void divF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43807 cbuf.set_insts_mark();
43808 // Start at oper_input_base() and count operands
43809 unsigned idx0 = 1;
43810 unsigned idx1 = 1; // dst
43811 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43812 {
43813 MacroAssembler _masm(&cbuf);
43814
43815#line 2568 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43816
43817 __ divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43818
43819#line 43819 "ad_x86.cpp"
43820 }
43821}
43822
43823void divF_immNode::eval_constant(Compile* C) {
43824 {
43825
43826#line 2569 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43827 _constant = C->constant_table().add(this, opnd_array(2));
43828#line 43828 "ad_x86.cpp"
43829 }
43830}
43831void divF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43832 cbuf.set_insts_mark();
43833 // Start at oper_input_base() and count operands
43834 unsigned idx0 = 1;
43835 unsigned idx1 = 1; // src1
43836 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43837 {
43838 MacroAssembler _masm(&cbuf);
43839
43840#line 2580 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43841
43842 __ vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43843
43844#line 43844 "ad_x86.cpp"
43845 }
43846}
43847
43848void divF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43849 cbuf.set_insts_mark();
43850 // Start at oper_input_base() and count operands
43851 unsigned idx0 = 2;
43852 unsigned idx1 = 2; // src1
43853 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43854 {
43855 MacroAssembler _masm(&cbuf);
43856
43857#line 2592 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43858
43859 __ vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43860
43861#line 43861 "ad_x86.cpp"
43862 }
43863}
43864
43865void divF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43866 cbuf.set_insts_mark();
43867 // Start at oper_input_base() and count operands
43868 unsigned idx0 = 1;
43869 unsigned idx1 = 1; // src
43870 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43871 {
43872 MacroAssembler _masm(&cbuf);
43873
43874#line 2604 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43875
43876 __ vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43877
43878#line 43878 "ad_x86.cpp"
43879 }
43880}
43881
43882void divF_reg_immNode::eval_constant(Compile* C) {
43883 {
43884
43885#line 2605 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43886 _constant = C->constant_table().add(this, opnd_array(2));
43887#line 43887 "ad_x86.cpp"
43888 }
43889}
43890void divD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43891 cbuf.set_insts_mark();
43892 // Start at oper_input_base() and count operands
43893 unsigned idx0 = 1;
43894 unsigned idx1 = 1; // dst
43895 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43896 {
43897 MacroAssembler _masm(&cbuf);
43898
43899#line 2616 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43900
43901 __ divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
43902
43903#line 43903 "ad_x86.cpp"
43904 }
43905}
43906
43907void divD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43908 cbuf.set_insts_mark();
43909 // Start at oper_input_base() and count operands
43910 unsigned idx0 = 2;
43911 unsigned idx1 = 2; // dst
43912 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
43913 {
43914 MacroAssembler _masm(&cbuf);
43915
43916#line 2628 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43917
43918 __ divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43919
43920#line 43920 "ad_x86.cpp"
43921 }
43922}
43923
43924void divD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43925 cbuf.set_insts_mark();
43926 // Start at oper_input_base() and count operands
43927 unsigned idx0 = 1;
43928 unsigned idx1 = 1; // dst
43929 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43930 {
43931 MacroAssembler _masm(&cbuf);
43932
43933#line 2639 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43934
43935 __ divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43936
43937#line 43937 "ad_x86.cpp"
43938 }
43939}
43940
43941void divD_immNode::eval_constant(Compile* C) {
43942 {
43943
43944#line 2640 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43945 _constant = C->constant_table().add(this, opnd_array(2));
43946#line 43946 "ad_x86.cpp"
43947 }
43948}
43949void divD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43950 cbuf.set_insts_mark();
43951 // Start at oper_input_base() and count operands
43952 unsigned idx0 = 1;
43953 unsigned idx1 = 1; // src1
43954 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43955 {
43956 MacroAssembler _masm(&cbuf);
43957
43958#line 2651 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43959
43960 __ vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
43961
43962#line 43962 "ad_x86.cpp"
43963 }
43964}
43965
43966void divD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43967 cbuf.set_insts_mark();
43968 // Start at oper_input_base() and count operands
43969 unsigned idx0 = 2;
43970 unsigned idx1 = 2; // src1
43971 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43972 {
43973 MacroAssembler _masm(&cbuf);
43974
43975#line 2663 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43976
43977 __ vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
43978
43979#line 43979 "ad_x86.cpp"
43980 }
43981}
43982
43983void divD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43984 cbuf.set_insts_mark();
43985 // Start at oper_input_base() and count operands
43986 unsigned idx0 = 1;
43987 unsigned idx1 = 1; // src
43988 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
43989 {
43990 MacroAssembler _masm(&cbuf);
43991
43992#line 2675 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
43993
43994 __ vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(__ code()->consts()->start() + constant_offset()));
43995
43996#line 43996 "ad_x86.cpp"
43997 }
43998}
43999
44000void divD_reg_immNode::eval_constant(Compile* C) {
44001 {
44002
44003#line 2676 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44004 _constant = C->constant_table().add(this, opnd_array(2));
44005#line 44005 "ad_x86.cpp"
44006 }
44007}
44008void absF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44009 cbuf.set_insts_mark();
44010 // Start at oper_input_base() and count operands
44011 unsigned idx0 = 1;
44012 unsigned idx1 = 1; // dst
44013 {
44014 MacroAssembler _masm(&cbuf);
44015
44016#line 2686 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44017
44018 __ andps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(float_signmask()));
44019
44020#line 44020 "ad_x86.cpp"
44021 }
44022}
44023
44024void absF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44025 cbuf.set_insts_mark();
44026 // Start at oper_input_base() and count operands
44027 unsigned idx0 = 1;
44028 unsigned idx1 = 1; // src
44029 {
44030 MacroAssembler _masm(&cbuf);
44031
44032#line 2697 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44033
44034 int vector_len = 0;
44035 __ vandps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
44036 ExternalAddress(float_signmask()), vector_len);
44037
44038#line 44038 "ad_x86.cpp"
44039 }
44040}
44041
44042void absD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44043 cbuf.set_insts_mark();
44044 // Start at oper_input_base() and count operands
44045 unsigned idx0 = 1;
44046 unsigned idx1 = 1; // dst
44047 {
44048 MacroAssembler _masm(&cbuf);
44049
44050#line 2711 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44051
44052 __ andpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(double_signmask()));
44053
44054#line 44054 "ad_x86.cpp"
44055 }
44056}
44057
44058void absD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44059 cbuf.set_insts_mark();
44060 // Start at oper_input_base() and count operands
44061 unsigned idx0 = 1;
44062 unsigned idx1 = 1; // src
44063 {
44064 MacroAssembler _masm(&cbuf);
44065
44066#line 2723 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44067
44068 int vector_len = 0;
44069 __ vandpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
44070 ExternalAddress(double_signmask()), vector_len);
44071
44072#line 44072 "ad_x86.cpp"
44073 }
44074}
44075
44076void negF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44077 cbuf.set_insts_mark();
44078 // Start at oper_input_base() and count operands
44079 unsigned idx0 = 1;
44080 unsigned idx1 = 1; // dst
44081 {
44082 MacroAssembler _masm(&cbuf);
44083
44084#line 2736 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44085
44086 __ xorps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(float_signflip()));
44087
44088#line 44088 "ad_x86.cpp"
44089 }
44090}
44091
44092void negF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44093 cbuf.set_insts_mark();
44094 // Start at oper_input_base() and count operands
44095 unsigned idx0 = 1;
44096 unsigned idx1 = 1; // src
44097 {
44098 MacroAssembler _masm(&cbuf);
44099
44100#line 2747 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44101
44102 __ vnegatess(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
44103 ExternalAddress(float_signflip()));
44104
44105#line 44105 "ad_x86.cpp"
44106 }
44107}
44108
44109void negD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44110 cbuf.set_insts_mark();
44111 // Start at oper_input_base() and count operands
44112 unsigned idx0 = 1;
44113 unsigned idx1 = 1; // dst
44114 {
44115 MacroAssembler _masm(&cbuf);
44116
44117#line 2760 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44118
44119 __ xorpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(double_signflip()));
44120
44121#line 44121 "ad_x86.cpp"
44122 }
44123}
44124
44125void negD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44126 cbuf.set_insts_mark();
44127 // Start at oper_input_base() and count operands
44128 unsigned idx0 = 1;
44129 unsigned idx1 = 1; // src
44130 {
44131 MacroAssembler _masm(&cbuf);
44132
44133#line 2772 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44134
44135 __ vnegatesd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
44136 ExternalAddress(double_signflip()));
44137
44138#line 44138 "ad_x86.cpp"
44139 }
44140}
44141
44142void sqrtF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44143 cbuf.set_insts_mark();
44144 // Start at oper_input_base() and count operands
44145 unsigned idx0 = 1;
44146 unsigned idx1 = 1; // src
44147 {
44148 MacroAssembler _masm(&cbuf);
44149
44150#line 2785 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44151
44152 __ sqrtss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44153
44154#line 44154 "ad_x86.cpp"
44155 }
44156}
44157
44158void sqrtF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44159 cbuf.set_insts_mark();
44160 // Start at oper_input_base() and count operands
44161 unsigned idx0 = 2;
44162 unsigned idx1 = 2; // src
44163 {
44164 MacroAssembler _masm(&cbuf);
44165
44166#line 2797 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44167
44168 __ sqrtss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44169
44170#line 44170 "ad_x86.cpp"
44171 }
44172}
44173
44174void sqrtF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44175 cbuf.set_insts_mark();
44176 // Start at oper_input_base() and count operands
44177 unsigned idx0 = 1;
44178 unsigned idx1 = 1; // con
44179 {
44180 MacroAssembler _masm(&cbuf);
44181
44182#line 2809 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44183
44184 __ sqrtss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44185
44186#line 44186 "ad_x86.cpp"
44187 }
44188}
44189
44190void sqrtF_immNode::eval_constant(Compile* C) {
44191 {
44192
44193#line 2810 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44194 _constant = C->constant_table().add(this, opnd_array(1));
44195#line 44195 "ad_x86.cpp"
44196 }
44197}
44198void sqrtD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44199 cbuf.set_insts_mark();
44200 // Start at oper_input_base() and count operands
44201 unsigned idx0 = 1;
44202 unsigned idx1 = 1; // src
44203 {
44204 MacroAssembler _masm(&cbuf);
44205
44206#line 2821 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44207
44208 __ sqrtsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44209
44210#line 44210 "ad_x86.cpp"
44211 }
44212}
44213
44214void sqrtD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44215 cbuf.set_insts_mark();
44216 // Start at oper_input_base() and count operands
44217 unsigned idx0 = 2;
44218 unsigned idx1 = 2; // src
44219 {
44220 MacroAssembler _masm(&cbuf);
44221
44222#line 2833 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44223
44224 __ sqrtsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44225
44226#line 44226 "ad_x86.cpp"
44227 }
44228}
44229
44230void sqrtD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44231 cbuf.set_insts_mark();
44232 // Start at oper_input_base() and count operands
44233 unsigned idx0 = 1;
44234 unsigned idx1 = 1; // con
44235 {
44236 MacroAssembler _masm(&cbuf);
44237
44238#line 2844 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44239
44240 __ sqrtsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44241
44242#line 44242 "ad_x86.cpp"
44243 }
44244}
44245
44246void sqrtD_immNode::eval_constant(Compile* C) {
44247 {
44248
44249#line 2845 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44250 _constant = C->constant_table().add(this, opnd_array(1));
44251#line 44251 "ad_x86.cpp"
44252 }
44253}
44254void onspinwaitNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44255 cbuf.set_insts_mark();
44256 // Start at oper_input_base() and count operands
44257 unsigned idx0 = 1;
44258 unsigned idx1 = 1; //
44259 {
44260 MacroAssembler _masm(&cbuf);
44261
44262#line 2858 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44263
44264 __ pause();
44265
44266#line 44266 "ad_x86.cpp"
44267 }
44268}
44269
44270void fmaD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44271 cbuf.set_insts_mark();
44272 // Start at oper_input_base() and count operands
44273 unsigned idx0 = 1;
44274 unsigned idx1 = 1; // c
44275 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
44276 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
44277 {
44278 MacroAssembler _masm(&cbuf);
44279
44280#line 2870 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44281
44282 __ fmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */);
44283
44284#line 44284 "ad_x86.cpp"
44285 }
44286}
44287
44288void fmaF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44289 cbuf.set_insts_mark();
44290 // Start at oper_input_base() and count operands
44291 unsigned idx0 = 1;
44292 unsigned idx1 = 1; // c
44293 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
44294 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
44295 {
44296 MacroAssembler _masm(&cbuf);
44297
44298#line 2882 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44299
44300 __ fmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */);
44301
44302#line 44302 "ad_x86.cpp"
44303 }
44304}
44305
44306void loadV4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44307 cbuf.set_insts_mark();
44308 // Start at oper_input_base() and count operands
44309 unsigned idx0 = 2;
44310 unsigned idx1 = 2; // mem
44311 {
44312 MacroAssembler _masm(&cbuf);
44313
44314#line 2897 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44315
44316 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44317
44318#line 44318 "ad_x86.cpp"
44319 }
44320}
44321
44322void MoveVecS2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44323 cbuf.set_insts_mark();
44324 // Start at oper_input_base() and count operands
44325 unsigned idx0 = 1;
44326 unsigned idx1 = 1; // src
44327 {
44328 MacroAssembler _masm(&cbuf);
44329
44330#line 2907 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44331
44332 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44333
44334#line 44334 "ad_x86.cpp"
44335 }
44336}
44337
44338void MoveLeg2VecSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44339 cbuf.set_insts_mark();
44340 // Start at oper_input_base() and count operands
44341 unsigned idx0 = 1;
44342 unsigned idx1 = 1; // src
44343 {
44344 MacroAssembler _masm(&cbuf);
44345
44346#line 2917 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44347
44348 __ movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44349
44350#line 44350 "ad_x86.cpp"
44351 }
44352}
44353
44354void loadV8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44355 cbuf.set_insts_mark();
44356 // Start at oper_input_base() and count operands
44357 unsigned idx0 = 2;
44358 unsigned idx1 = 2; // mem
44359 {
44360 MacroAssembler _masm(&cbuf);
44361
44362#line 2929 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44363
44364 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44365
44366#line 44366 "ad_x86.cpp"
44367 }
44368}
44369
44370void MoveVecD2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44371 cbuf.set_insts_mark();
44372 // Start at oper_input_base() and count operands
44373 unsigned idx0 = 1;
44374 unsigned idx1 = 1; // src
44375 {
44376 MacroAssembler _masm(&cbuf);
44377
44378#line 2939 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44379
44380 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44381
44382#line 44382 "ad_x86.cpp"
44383 }
44384}
44385
44386void MoveLeg2VecDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44387 cbuf.set_insts_mark();
44388 // Start at oper_input_base() and count operands
44389 unsigned idx0 = 1;
44390 unsigned idx1 = 1; // src
44391 {
44392 MacroAssembler _masm(&cbuf);
44393
44394#line 2949 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44395
44396 __ movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44397
44398#line 44398 "ad_x86.cpp"
44399 }
44400}
44401
44402void loadV16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44403 cbuf.set_insts_mark();
44404 // Start at oper_input_base() and count operands
44405 unsigned idx0 = 2;
44406 unsigned idx1 = 2; // mem
44407 {
44408 MacroAssembler _masm(&cbuf);
44409
44410#line 2961 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44411
44412 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44413
44414#line 44414 "ad_x86.cpp"
44415 }
44416}
44417
44418void MoveVecX2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44419 cbuf.set_insts_mark();
44420 // Start at oper_input_base() and count operands
44421 unsigned idx0 = 1;
44422 unsigned idx1 = 1; // src
44423 {
44424 MacroAssembler _masm(&cbuf);
44425
44426#line 2971 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44427
44428 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
44429 int vector_len = 2;
44430 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44431 } else {
44432 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44433 }
44434
44435#line 44435 "ad_x86.cpp"
44436 }
44437}
44438
44439void MoveLeg2VecXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44440 cbuf.set_insts_mark();
44441 // Start at oper_input_base() and count operands
44442 unsigned idx0 = 1;
44443 unsigned idx1 = 1; // src
44444 {
44445 MacroAssembler _masm(&cbuf);
44446
44447#line 2986 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44448
44449 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
44450 int vector_len = 2;
44451 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44452 } else {
44453 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44454 }
44455
44456#line 44456 "ad_x86.cpp"
44457 }
44458}
44459
44460void loadV32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44461 cbuf.set_insts_mark();
44462 // Start at oper_input_base() and count operands
44463 unsigned idx0 = 2;
44464 unsigned idx1 = 2; // mem
44465 {
44466 MacroAssembler _masm(&cbuf);
44467
44468#line 3003 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44469
44470 __ vmovdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44471
44472#line 44472 "ad_x86.cpp"
44473 }
44474}
44475
44476void MoveVecY2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44477 cbuf.set_insts_mark();
44478 // Start at oper_input_base() and count operands
44479 unsigned idx0 = 1;
44480 unsigned idx1 = 1; // src
44481 {
44482 MacroAssembler _masm(&cbuf);
44483
44484#line 3013 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44485
44486 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
44487 int vector_len = 2;
44488 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44489 } else {
44490 __ vmovdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44491 }
44492
44493#line 44493 "ad_x86.cpp"
44494 }
44495}
44496
44497void MoveLeg2VecYNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44498 cbuf.set_insts_mark();
44499 // Start at oper_input_base() and count operands
44500 unsigned idx0 = 1;
44501 unsigned idx1 = 1; // src
44502 {
44503 MacroAssembler _masm(&cbuf);
44504
44505#line 3028 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44506
44507 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
44508 int vector_len = 2;
44509 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44510 } else {
44511 __ vmovdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
44512 }
44513
44514#line 44514 "ad_x86.cpp"
44515 }
44516}
44517
44518void loadV64_dwordNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44519 cbuf.set_insts_mark();
44520 // Start at oper_input_base() and count operands
44521 unsigned idx0 = 2;
44522 unsigned idx1 = 2; // mem
44523 {
44524 MacroAssembler _masm(&cbuf);
44525
44526#line 3045 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44527
44528 int vector_len = 2;
44529 __ evmovdqul(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
44530
44531#line 44531 "ad_x86.cpp"
44532 }
44533}
44534
44535void loadV64_qwordNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44536 cbuf.set_insts_mark();
44537 // Start at oper_input_base() and count operands
44538 unsigned idx0 = 2;
44539 unsigned idx1 = 2; // mem
44540 {
44541 MacroAssembler _masm(&cbuf);
44542
44543#line 3058 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44544
44545 int vector_len = 2;
44546 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
44547
44548#line 44548 "ad_x86.cpp"
44549 }
44550}
44551
44552void MoveVecZ2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44553 cbuf.set_insts_mark();
44554 // Start at oper_input_base() and count operands
44555 unsigned idx0 = 1;
44556 unsigned idx1 = 1; // src
44557 {
44558 MacroAssembler _masm(&cbuf);
44559
44560#line 3068 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44561
44562 int vector_len = 2;
44563 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44564
44565#line 44565 "ad_x86.cpp"
44566 }
44567}
44568
44569void MoveLeg2VecZNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44570 cbuf.set_insts_mark();
44571 // Start at oper_input_base() and count operands
44572 unsigned idx0 = 1;
44573 unsigned idx1 = 1; // src
44574 {
44575 MacroAssembler _masm(&cbuf);
44576
44577#line 3078 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44578
44579 int vector_len = 2;
44580 __ evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
44581
44582#line 44582 "ad_x86.cpp"
44583 }
44584}
44585
44586void storeV4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44587 cbuf.set_insts_mark();
44588 // Start at oper_input_base() and count operands
44589 unsigned idx0 = 2;
44590 unsigned idx1 = 2; // mem
44591 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44592 {
44593 MacroAssembler _masm(&cbuf);
44594
44595#line 3091 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44596
44597 __ movdl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
44598
44599#line 44599 "ad_x86.cpp"
44600 }
44601}
44602
44603void storeV8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44604 cbuf.set_insts_mark();
44605 // Start at oper_input_base() and count operands
44606 unsigned idx0 = 2;
44607 unsigned idx1 = 2; // mem
44608 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44609 {
44610 MacroAssembler _masm(&cbuf);
44611
44612#line 3102 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44613
44614 __ movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
44615
44616#line 44616 "ad_x86.cpp"
44617 }
44618}
44619
44620void storeV16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44621 cbuf.set_insts_mark();
44622 // Start at oper_input_base() and count operands
44623 unsigned idx0 = 2;
44624 unsigned idx1 = 2; // mem
44625 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44626 {
44627 MacroAssembler _masm(&cbuf);
44628
44629#line 3113 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44630
44631 __ movdqu(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
44632
44633#line 44633 "ad_x86.cpp"
44634 }
44635}
44636
44637void storeV32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44638 cbuf.set_insts_mark();
44639 // Start at oper_input_base() and count operands
44640 unsigned idx0 = 2;
44641 unsigned idx1 = 2; // mem
44642 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44643 {
44644 MacroAssembler _masm(&cbuf);
44645
44646#line 3124 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44647
44648 __ vmovdqu(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
44649
44650#line 44650 "ad_x86.cpp"
44651 }
44652}
44653
44654void storeV64_dwordNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44655 cbuf.set_insts_mark();
44656 // Start at oper_input_base() and count operands
44657 unsigned idx0 = 2;
44658 unsigned idx1 = 2; // mem
44659 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44660 {
44661 MacroAssembler _masm(&cbuf);
44662
44663#line 3135 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44664
44665 int vector_len = 2;
44666 __ evmovdqul(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, vector_len);
44667
44668#line 44668 "ad_x86.cpp"
44669 }
44670}
44671
44672void storeV64_qwordNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44673 cbuf.set_insts_mark();
44674 // Start at oper_input_base() and count operands
44675 unsigned idx0 = 2;
44676 unsigned idx1 = 2; // mem
44677 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
44678 {
44679 MacroAssembler _masm(&cbuf);
44680
44681#line 3147 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44682
44683 int vector_len = 2;
44684 __ evmovdquq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, vector_len);
44685
44686#line 44686 "ad_x86.cpp"
44687 }
44688}
44689
44690void Repl16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44691 cbuf.set_insts_mark();
44692 // Start at oper_input_base() and count operands
44693 unsigned idx0 = 1;
44694 unsigned idx1 = 1; // src
44695 {
44696 MacroAssembler _masm(&cbuf);
44697
44698#line 3163 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44699
44700 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44701 __ punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44702 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44703 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44704
44705#line 44705 "ad_x86.cpp"
44706 }
44707}
44708
44709void Repl32BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44710 cbuf.set_insts_mark();
44711 // Start at oper_input_base() and count operands
44712 unsigned idx0 = 1;
44713 unsigned idx1 = 1; // src
44714 {
44715 MacroAssembler _masm(&cbuf);
44716
44717#line 3180 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44718
44719 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44720 __ punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44721 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44722 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44723 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44724
44725#line 44725 "ad_x86.cpp"
44726 }
44727}
44728
44729void Repl64BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44730 cbuf.set_insts_mark();
44731 // Start at oper_input_base() and count operands
44732 unsigned idx0 = 1;
44733 unsigned idx1 = 1; // src
44734 {
44735 MacroAssembler _masm(&cbuf);
44736
44737#line 3199 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44738
44739 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44740 __ punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44741 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44742 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44743 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44744 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
44745
44746#line 44746 "ad_x86.cpp"
44747 }
44748}
44749
44750void Repl16B_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44751 cbuf.set_insts_mark();
44752 // Start at oper_input_base() and count operands
44753 unsigned idx0 = 1;
44754 unsigned idx1 = 1; // con
44755 {
44756 MacroAssembler _masm(&cbuf);
44757
44758#line 3215 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44759
44760 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44761 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44762
44763#line 44763 "ad_x86.cpp"
44764 }
44765}
44766
44767void Repl16B_immNode::eval_constant(Compile* C) {
44768 {
44769
44770#line 3216 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44771 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
44772#line 44772 "ad_x86.cpp"
44773 }
44774}
44775void Repl32B_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44776 cbuf.set_insts_mark();
44777 // Start at oper_input_base() and count operands
44778 unsigned idx0 = 1;
44779 unsigned idx1 = 1; // con
44780 {
44781 MacroAssembler _masm(&cbuf);
44782
44783#line 3228 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44784
44785 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44786 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44787 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44788
44789#line 44789 "ad_x86.cpp"
44790 }
44791}
44792
44793void Repl32B_immNode::eval_constant(Compile* C) {
44794 {
44795
44796#line 3229 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44797 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
44798#line 44798 "ad_x86.cpp"
44799 }
44800}
44801void Repl64B_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44802 cbuf.set_insts_mark();
44803 // Start at oper_input_base() and count operands
44804 unsigned idx0 = 1;
44805 unsigned idx1 = 1; // con
44806 {
44807 MacroAssembler _masm(&cbuf);
44808
44809#line 3243 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44810
44811 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44812 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44813 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44814 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
44815
44816#line 44816 "ad_x86.cpp"
44817 }
44818}
44819
44820void Repl64B_immNode::eval_constant(Compile* C) {
44821 {
44822
44823#line 3244 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44824 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
44825#line 44825 "ad_x86.cpp"
44826 }
44827}
44828void Repl4SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44829 cbuf.set_insts_mark();
44830 // Start at oper_input_base() and count operands
44831 unsigned idx0 = 1;
44832 unsigned idx1 = 1; // src
44833 {
44834 MacroAssembler _masm(&cbuf);
44835
44836#line 3257 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44837
44838 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44839 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44840
44841#line 44841 "ad_x86.cpp"
44842 }
44843}
44844
44845void Repl4S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44846 cbuf.set_insts_mark();
44847 // Start at oper_input_base() and count operands
44848 unsigned idx0 = 2;
44849 unsigned idx1 = 2; // mem
44850 {
44851 MacroAssembler _masm(&cbuf);
44852
44853#line 3268 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44854
44855 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
44856
44857#line 44857 "ad_x86.cpp"
44858 }
44859}
44860
44861void Repl8SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44862 cbuf.set_insts_mark();
44863 // Start at oper_input_base() and count operands
44864 unsigned idx0 = 1;
44865 unsigned idx1 = 1; // src
44866 {
44867 MacroAssembler _masm(&cbuf);
44868
44869#line 3280 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44870
44871 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44872 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44873 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44874
44875#line 44875 "ad_x86.cpp"
44876 }
44877}
44878
44879void Repl8S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44880 cbuf.set_insts_mark();
44881 // Start at oper_input_base() and count operands
44882 unsigned idx0 = 2;
44883 unsigned idx1 = 2; // mem
44884 {
44885 MacroAssembler _masm(&cbuf);
44886
44887#line 3293 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44888
44889 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
44890 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44891
44892#line 44892 "ad_x86.cpp"
44893 }
44894}
44895
44896void Repl8S_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44897 cbuf.set_insts_mark();
44898 // Start at oper_input_base() and count operands
44899 unsigned idx0 = 1;
44900 unsigned idx1 = 1; // con
44901 {
44902 MacroAssembler _masm(&cbuf);
44903
44904#line 3305 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44905
44906 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44907 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44908
44909#line 44909 "ad_x86.cpp"
44910 }
44911}
44912
44913void Repl8S_immNode::eval_constant(Compile* C) {
44914 {
44915
44916#line 3306 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44917 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
44918#line 44918 "ad_x86.cpp"
44919 }
44920}
44921void Repl16SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44922 cbuf.set_insts_mark();
44923 // Start at oper_input_base() and count operands
44924 unsigned idx0 = 1;
44925 unsigned idx1 = 1; // src
44926 {
44927 MacroAssembler _masm(&cbuf);
44928
44929#line 3319 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44930
44931 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44932 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44933 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44934 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44935
44936#line 44936 "ad_x86.cpp"
44937 }
44938}
44939
44940void Repl16S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44941 cbuf.set_insts_mark();
44942 // Start at oper_input_base() and count operands
44943 unsigned idx0 = 2;
44944 unsigned idx1 = 2; // mem
44945 {
44946 MacroAssembler _masm(&cbuf);
44947
44948#line 3334 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44949
44950 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
44951 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44952 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44953
44954#line 44954 "ad_x86.cpp"
44955 }
44956}
44957
44958void Repl16S_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44959 cbuf.set_insts_mark();
44960 // Start at oper_input_base() and count operands
44961 unsigned idx0 = 1;
44962 unsigned idx1 = 1; // con
44963 {
44964 MacroAssembler _masm(&cbuf);
44965
44966#line 3348 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44967
44968 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
44969 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44970 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44971
44972#line 44972 "ad_x86.cpp"
44973 }
44974}
44975
44976void Repl16S_immNode::eval_constant(Compile* C) {
44977 {
44978
44979#line 3349 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44980 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
44981#line 44981 "ad_x86.cpp"
44982 }
44983}
44984void Repl32SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44985 cbuf.set_insts_mark();
44986 // Start at oper_input_base() and count operands
44987 unsigned idx0 = 1;
44988 unsigned idx1 = 1; // src
44989 {
44990 MacroAssembler _masm(&cbuf);
44991
44992#line 3364 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
44993
44994 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44995 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
44996 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44997 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
44998 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
44999
45000#line 45000 "ad_x86.cpp"
45001 }
45002}
45003
45004void Repl32S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45005 cbuf.set_insts_mark();
45006 // Start at oper_input_base() and count operands
45007 unsigned idx0 = 2;
45008 unsigned idx1 = 2; // mem
45009 {
45010 MacroAssembler _masm(&cbuf);
45011
45012#line 3381 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45013
45014 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45015 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45016 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45017 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45018
45019#line 45019 "ad_x86.cpp"
45020 }
45021}
45022
45023void Repl32S_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45024 cbuf.set_insts_mark();
45025 // Start at oper_input_base() and count operands
45026 unsigned idx0 = 1;
45027 unsigned idx1 = 1; // con
45028 {
45029 MacroAssembler _masm(&cbuf);
45030
45031#line 3397 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45032
45033 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45034 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45035 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45036 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45037
45038#line 45038 "ad_x86.cpp"
45039 }
45040}
45041
45042void Repl32S_immNode::eval_constant(Compile* C) {
45043 {
45044
45045#line 3398 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45046 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
45047#line 45047 "ad_x86.cpp"
45048 }
45049}
45050void Repl4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45051 cbuf.set_insts_mark();
45052 // Start at oper_input_base() and count operands
45053 unsigned idx0 = 1;
45054 unsigned idx1 = 1; // src
45055 {
45056 MacroAssembler _masm(&cbuf);
45057
45058#line 3411 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45059
45060 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45061 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45062
45063#line 45063 "ad_x86.cpp"
45064 }
45065}
45066
45067void Repl4I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45068 cbuf.set_insts_mark();
45069 // Start at oper_input_base() and count operands
45070 unsigned idx0 = 2;
45071 unsigned idx1 = 2; // mem
45072 {
45073 MacroAssembler _masm(&cbuf);
45074
45075#line 3422 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45076
45077 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45078
45079#line 45079 "ad_x86.cpp"
45080 }
45081}
45082
45083void Repl8INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45084 cbuf.set_insts_mark();
45085 // Start at oper_input_base() and count operands
45086 unsigned idx0 = 1;
45087 unsigned idx1 = 1; // src
45088 {
45089 MacroAssembler _masm(&cbuf);
45090
45091#line 3434 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45092
45093 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45094 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45095 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45096
45097#line 45097 "ad_x86.cpp"
45098 }
45099}
45100
45101void Repl8I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45102 cbuf.set_insts_mark();
45103 // Start at oper_input_base() and count operands
45104 unsigned idx0 = 2;
45105 unsigned idx1 = 2; // mem
45106 {
45107 MacroAssembler _masm(&cbuf);
45108
45109#line 3447 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45110
45111 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45112 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45113
45114#line 45114 "ad_x86.cpp"
45115 }
45116}
45117
45118void Repl16INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45119 cbuf.set_insts_mark();
45120 // Start at oper_input_base() and count operands
45121 unsigned idx0 = 1;
45122 unsigned idx1 = 1; // src
45123 {
45124 MacroAssembler _masm(&cbuf);
45125
45126#line 3461 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45127
45128 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45129 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45130 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45131 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45132
45133#line 45133 "ad_x86.cpp"
45134 }
45135}
45136
45137void Repl16I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45138 cbuf.set_insts_mark();
45139 // Start at oper_input_base() and count operands
45140 unsigned idx0 = 2;
45141 unsigned idx1 = 2; // mem
45142 {
45143 MacroAssembler _masm(&cbuf);
45144
45145#line 3476 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45146
45147 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45148 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45149 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45150
45151#line 45151 "ad_x86.cpp"
45152 }
45153}
45154
45155void Repl4I_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45156 cbuf.set_insts_mark();
45157 // Start at oper_input_base() and count operands
45158 unsigned idx0 = 1;
45159 unsigned idx1 = 1; // con
45160 {
45161 MacroAssembler _masm(&cbuf);
45162
45163#line 3489 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45164
45165 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45166 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45167
45168#line 45168 "ad_x86.cpp"
45169 }
45170}
45171
45172void Repl4I_immNode::eval_constant(Compile* C) {
45173 {
45174
45175#line 3490 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45176 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
45177#line 45177 "ad_x86.cpp"
45178 }
45179}
45180void Repl8I_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45181 cbuf.set_insts_mark();
45182 // Start at oper_input_base() and count operands
45183 unsigned idx0 = 1;
45184 unsigned idx1 = 1; // con
45185 {
45186 MacroAssembler _masm(&cbuf);
45187
45188#line 3502 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45189
45190 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45191 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45192 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45193
45194#line 45194 "ad_x86.cpp"
45195 }
45196}
45197
45198void Repl8I_immNode::eval_constant(Compile* C) {
45199 {
45200
45201#line 3503 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45202 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
45203#line 45203 "ad_x86.cpp"
45204 }
45205}
45206void Repl16I_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45207 cbuf.set_insts_mark();
45208 // Start at oper_input_base() and count operands
45209 unsigned idx0 = 1;
45210 unsigned idx1 = 1; // con
45211 {
45212 MacroAssembler _masm(&cbuf);
45213
45214#line 3517 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45215
45216 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45217 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45218 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45219 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45220
45221#line 45221 "ad_x86.cpp"
45222 }
45223}
45224
45225void Repl16I_immNode::eval_constant(Compile* C) {
45226 {
45227
45228#line 3518 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45229 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
45230#line 45230 "ad_x86.cpp"
45231 }
45232}
45233void Repl2L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45234 cbuf.set_insts_mark();
45235 // Start at oper_input_base() and count operands
45236 unsigned idx0 = 2;
45237 unsigned idx1 = 2; // mem
45238 {
45239 MacroAssembler _masm(&cbuf);
45240
45241#line 3532 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45242
45243 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
45244 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45245
45246#line 45246 "ad_x86.cpp"
45247 }
45248}
45249
45250void Repl4LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45251 cbuf.set_insts_mark();
45252 // Start at oper_input_base() and count operands
45253 unsigned idx0 = 1;
45254 unsigned idx1 = 1; // src
45255 {
45256 MacroAssembler _masm(&cbuf);
45257
45258#line 3547 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45259
45260 __ movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45261 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45262 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45263
45264#line 45264 "ad_x86.cpp"
45265 }
45266}
45267
45268void Repl8LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45269 cbuf.set_insts_mark();
45270 // Start at oper_input_base() and count operands
45271 unsigned idx0 = 1;
45272 unsigned idx1 = 1; // src
45273 {
45274 MacroAssembler _masm(&cbuf);
45275
45276#line 3562 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45277
45278 __ movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45279 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45280 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45281 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45282
45283#line 45283 "ad_x86.cpp"
45284 }
45285}
45286
45287void Repl4L_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45288 cbuf.set_insts_mark();
45289 // Start at oper_input_base() and count operands
45290 unsigned idx0 = 1;
45291 unsigned idx1 = 1; // con
45292 {
45293 MacroAssembler _masm(&cbuf);
45294
45295#line 3618 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45296
45297 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45298 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45299 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45300
45301#line 45301 "ad_x86.cpp"
45302 }
45303}
45304
45305void Repl4L_immNode::eval_constant(Compile* C) {
45306 {
45307
45308#line 3619 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45309 _constant = C->constant_table().add(this, opnd_array(1));
45310#line 45310 "ad_x86.cpp"
45311 }
45312}
45313void Repl8L_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45314 cbuf.set_insts_mark();
45315 // Start at oper_input_base() and count operands
45316 unsigned idx0 = 1;
45317 unsigned idx1 = 1; // con
45318 {
45319 MacroAssembler _masm(&cbuf);
45320
45321#line 3633 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45322
45323 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45324 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45325 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45326 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45327
45328#line 45328 "ad_x86.cpp"
45329 }
45330}
45331
45332void Repl8L_immNode::eval_constant(Compile* C) {
45333 {
45334
45335#line 3634 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45336 _constant = C->constant_table().add(this, opnd_array(1));
45337#line 45337 "ad_x86.cpp"
45338 }
45339}
45340void Repl4L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45341 cbuf.set_insts_mark();
45342 // Start at oper_input_base() and count operands
45343 unsigned idx0 = 2;
45344 unsigned idx1 = 2; // mem
45345 {
45346 MacroAssembler _masm(&cbuf);
45347
45348#line 3648 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45349
45350 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
45351 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45352 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45353
45354#line 45354 "ad_x86.cpp"
45355 }
45356}
45357
45358void Repl8L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45359 cbuf.set_insts_mark();
45360 // Start at oper_input_base() and count operands
45361 unsigned idx0 = 2;
45362 unsigned idx1 = 2; // mem
45363 {
45364 MacroAssembler _masm(&cbuf);
45365
45366#line 3663 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45367
45368 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
45369 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45370 __ vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45371 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45372
45373#line 45373 "ad_x86.cpp"
45374 }
45375}
45376
45377void Repl2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45378 cbuf.set_insts_mark();
45379 // Start at oper_input_base() and count operands
45380 unsigned idx0 = 2;
45381 unsigned idx1 = 2; // mem
45382 {
45383 MacroAssembler _masm(&cbuf);
45384
45385#line 3676 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45386
45387 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45388
45389#line 45389 "ad_x86.cpp"
45390 }
45391}
45392
45393void Repl4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45394 cbuf.set_insts_mark();
45395 // Start at oper_input_base() and count operands
45396 unsigned idx0 = 2;
45397 unsigned idx1 = 2; // mem
45398 {
45399 MacroAssembler _masm(&cbuf);
45400
45401#line 3686 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45402
45403 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45404
45405#line 45405 "ad_x86.cpp"
45406 }
45407}
45408
45409void Repl8FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45410 cbuf.set_insts_mark();
45411 // Start at oper_input_base() and count operands
45412 unsigned idx0 = 1;
45413 unsigned idx1 = 1; // src
45414 {
45415 MacroAssembler _masm(&cbuf);
45416
45417#line 3697 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45418
45419 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
45420 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45421
45422#line 45422 "ad_x86.cpp"
45423 }
45424}
45425
45426void Repl8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45427 cbuf.set_insts_mark();
45428 // Start at oper_input_base() and count operands
45429 unsigned idx0 = 2;
45430 unsigned idx1 = 2; // mem
45431 {
45432 MacroAssembler _masm(&cbuf);
45433
45434#line 3709 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45435
45436 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45437 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45438
45439#line 45439 "ad_x86.cpp"
45440 }
45441}
45442
45443void Repl16FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45444 cbuf.set_insts_mark();
45445 // Start at oper_input_base() and count operands
45446 unsigned idx0 = 1;
45447 unsigned idx1 = 1; // src
45448 {
45449 MacroAssembler _masm(&cbuf);
45450
45451#line 3722 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45452
45453 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
45454 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45455 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45456
45457#line 45457 "ad_x86.cpp"
45458 }
45459}
45460
45461void Repl16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45462 cbuf.set_insts_mark();
45463 // Start at oper_input_base() and count operands
45464 unsigned idx0 = 2;
45465 unsigned idx1 = 2; // mem
45466 {
45467 MacroAssembler _masm(&cbuf);
45468
45469#line 3736 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45470
45471 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x00);
45472 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45473 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45474
45475#line 45475 "ad_x86.cpp"
45476 }
45477}
45478
45479void Repl2F_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45480 cbuf.set_insts_mark();
45481 // Start at oper_input_base() and count operands
45482 unsigned idx0 = 1;
45483 unsigned idx1 = 1; // zero
45484 {
45485 MacroAssembler _masm(&cbuf);
45486
45487#line 3748 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45488
45489 __ xorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45490
45491#line 45491 "ad_x86.cpp"
45492 }
45493}
45494
45495void Repl4F_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45496 cbuf.set_insts_mark();
45497 // Start at oper_input_base() and count operands
45498 unsigned idx0 = 1;
45499 unsigned idx1 = 1; // zero
45500 {
45501 MacroAssembler _masm(&cbuf);
45502
45503#line 3758 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45504
45505 __ xorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45506
45507#line 45507 "ad_x86.cpp"
45508 }
45509}
45510
45511void Repl8F_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45512 cbuf.set_insts_mark();
45513 // Start at oper_input_base() and count operands
45514 unsigned idx0 = 1;
45515 unsigned idx1 = 1; // zero
45516 {
45517 MacroAssembler _masm(&cbuf);
45518
45519#line 3768 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45520
45521 int vector_len = 1;
45522 __ vxorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
45523
45524#line 45524 "ad_x86.cpp"
45525 }
45526}
45527
45528void Repl2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45529 cbuf.set_insts_mark();
45530 // Start at oper_input_base() and count operands
45531 unsigned idx0 = 2;
45532 unsigned idx1 = 2; // mem
45533 {
45534 MacroAssembler _masm(&cbuf);
45535
45536#line 3779 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45537
45538 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x44);
45539
45540#line 45540 "ad_x86.cpp"
45541 }
45542}
45543
45544void Repl4DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45545 cbuf.set_insts_mark();
45546 // Start at oper_input_base() and count operands
45547 unsigned idx0 = 1;
45548 unsigned idx1 = 1; // src
45549 {
45550 MacroAssembler _masm(&cbuf);
45551
45552#line 3790 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45553
45554 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x44);
45555 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45556
45557#line 45557 "ad_x86.cpp"
45558 }
45559}
45560
45561void Repl4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45562 cbuf.set_insts_mark();
45563 // Start at oper_input_base() and count operands
45564 unsigned idx0 = 2;
45565 unsigned idx1 = 2; // mem
45566 {
45567 MacroAssembler _masm(&cbuf);
45568
45569#line 3802 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45570
45571 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x44);
45572 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45573
45574#line 45574 "ad_x86.cpp"
45575 }
45576}
45577
45578void Repl8DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45579 cbuf.set_insts_mark();
45580 // Start at oper_input_base() and count operands
45581 unsigned idx0 = 1;
45582 unsigned idx1 = 1; // src
45583 {
45584 MacroAssembler _masm(&cbuf);
45585
45586#line 3815 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45587
45588 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x44);
45589 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45590 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45591
45592#line 45592 "ad_x86.cpp"
45593 }
45594}
45595
45596void Repl8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45597 cbuf.set_insts_mark();
45598 // Start at oper_input_base() and count operands
45599 unsigned idx0 = 2;
45600 unsigned idx1 = 2; // mem
45601 {
45602 MacroAssembler _masm(&cbuf);
45603
45604#line 3829 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45605
45606 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0x44);
45607 __ vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45608 __ vinserti64x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x1);
45609
45610#line 45610 "ad_x86.cpp"
45611 }
45612}
45613
45614void Repl2D_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45615 cbuf.set_insts_mark();
45616 // Start at oper_input_base() and count operands
45617 unsigned idx0 = 1;
45618 unsigned idx1 = 1; // zero
45619 {
45620 MacroAssembler _masm(&cbuf);
45621
45622#line 3842 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45623
45624 __ xorpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45625
45626#line 45626 "ad_x86.cpp"
45627 }
45628}
45629
45630void Repl4D_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45631 cbuf.set_insts_mark();
45632 // Start at oper_input_base() and count operands
45633 unsigned idx0 = 1;
45634 unsigned idx1 = 1; // zero
45635 {
45636 MacroAssembler _masm(&cbuf);
45637
45638#line 3852 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45639
45640 int vector_len = 1;
45641 __ vxorpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
45642
45643#line 45643 "ad_x86.cpp"
45644 }
45645}
45646
45647void Repl4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45648 cbuf.set_insts_mark();
45649 // Start at oper_input_base() and count operands
45650 unsigned idx0 = 1;
45651 unsigned idx1 = 1; // src
45652 {
45653 MacroAssembler _masm(&cbuf);
45654
45655#line 3868 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45656
45657 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45658 __ punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45659 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45660
45661#line 45661 "ad_x86.cpp"
45662 }
45663}
45664
45665void Repl8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45666 cbuf.set_insts_mark();
45667 // Start at oper_input_base() and count operands
45668 unsigned idx0 = 1;
45669 unsigned idx1 = 1; // src
45670 {
45671 MacroAssembler _masm(&cbuf);
45672
45673#line 3882 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45674
45675 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45676 __ punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45677 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45678
45679#line 45679 "ad_x86.cpp"
45680 }
45681}
45682
45683void Repl4B_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45684 cbuf.set_insts_mark();
45685 // Start at oper_input_base() and count operands
45686 unsigned idx0 = 1;
45687 unsigned idx1 = 1; // con
45688 {
45689 MacroAssembler _masm(&cbuf);
45690
45691#line 3895 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45692
45693 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45694
45695#line 45695 "ad_x86.cpp"
45696 }
45697}
45698
45699void Repl4B_immNode::eval_constant(Compile* C) {
45700 {
45701
45702#line 3896 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45703 _constant = C->constant_table().add(this, replicate4_imm(opnd_array(1)->constant(), 1));
45704#line 45704 "ad_x86.cpp"
45705 }
45706}
45707void Repl8B_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45708 cbuf.set_insts_mark();
45709 // Start at oper_input_base() and count operands
45710 unsigned idx0 = 1;
45711 unsigned idx1 = 1; // con
45712 {
45713 MacroAssembler _masm(&cbuf);
45714
45715#line 3905 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45716
45717 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45718
45719#line 45719 "ad_x86.cpp"
45720 }
45721}
45722
45723void Repl8B_immNode::eval_constant(Compile* C) {
45724 {
45725
45726#line 3906 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45727 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
45728#line 45728 "ad_x86.cpp"
45729 }
45730}
45731void Repl4B_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45732 cbuf.set_insts_mark();
45733 // Start at oper_input_base() and count operands
45734 unsigned idx0 = 1;
45735 unsigned idx1 = 1; // zero
45736 {
45737 MacroAssembler _masm(&cbuf);
45738
45739#line 3916 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45740
45741 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45742
45743#line 45743 "ad_x86.cpp"
45744 }
45745}
45746
45747void Repl8B_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45748 cbuf.set_insts_mark();
45749 // Start at oper_input_base() and count operands
45750 unsigned idx0 = 1;
45751 unsigned idx1 = 1; // zero
45752 {
45753 MacroAssembler _masm(&cbuf);
45754
45755#line 3926 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45756
45757 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45758
45759#line 45759 "ad_x86.cpp"
45760 }
45761}
45762
45763void Repl16B_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45764 cbuf.set_insts_mark();
45765 // Start at oper_input_base() and count operands
45766 unsigned idx0 = 1;
45767 unsigned idx1 = 1; // zero
45768 {
45769 MacroAssembler _masm(&cbuf);
45770
45771#line 3936 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45772
45773 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45774
45775#line 45775 "ad_x86.cpp"
45776 }
45777}
45778
45779void Repl32B_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45780 cbuf.set_insts_mark();
45781 // Start at oper_input_base() and count operands
45782 unsigned idx0 = 1;
45783 unsigned idx1 = 1; // zero
45784 {
45785 MacroAssembler _masm(&cbuf);
45786
45787#line 3946 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45788
45789 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
45790 int vector_len = 1;
45791 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
45792
45793#line 45793 "ad_x86.cpp"
45794 }
45795}
45796
45797void Repl2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45798 cbuf.set_insts_mark();
45799 // Start at oper_input_base() and count operands
45800 unsigned idx0 = 1;
45801 unsigned idx1 = 1; // src
45802 {
45803 MacroAssembler _masm(&cbuf);
45804
45805#line 3960 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45806
45807 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45808 __ pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45809
45810#line 45810 "ad_x86.cpp"
45811 }
45812}
45813
45814void Repl2S_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45815 cbuf.set_insts_mark();
45816 // Start at oper_input_base() and count operands
45817 unsigned idx0 = 1;
45818 unsigned idx1 = 1; // con
45819 {
45820 MacroAssembler _masm(&cbuf);
45821
45822#line 3972 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45823
45824 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45825
45826#line 45826 "ad_x86.cpp"
45827 }
45828}
45829
45830void Repl2S_immNode::eval_constant(Compile* C) {
45831 {
45832
45833#line 3973 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45834 _constant = C->constant_table().add(this, replicate4_imm(opnd_array(1)->constant(), 2));
45835#line 45835 "ad_x86.cpp"
45836 }
45837}
45838void Repl4S_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45839 cbuf.set_insts_mark();
45840 // Start at oper_input_base() and count operands
45841 unsigned idx0 = 1;
45842 unsigned idx1 = 1; // con
45843 {
45844 MacroAssembler _masm(&cbuf);
45845
45846#line 3982 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45847
45848 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45849
45850#line 45850 "ad_x86.cpp"
45851 }
45852}
45853
45854void Repl4S_immNode::eval_constant(Compile* C) {
45855 {
45856
45857#line 3983 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45858 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
45859#line 45859 "ad_x86.cpp"
45860 }
45861}
45862void Repl2S_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45863 cbuf.set_insts_mark();
45864 // Start at oper_input_base() and count operands
45865 unsigned idx0 = 1;
45866 unsigned idx1 = 1; // zero
45867 {
45868 MacroAssembler _masm(&cbuf);
45869
45870#line 3993 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45871
45872 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45873
45874#line 45874 "ad_x86.cpp"
45875 }
45876}
45877
45878void Repl4S_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45879 cbuf.set_insts_mark();
45880 // Start at oper_input_base() and count operands
45881 unsigned idx0 = 1;
45882 unsigned idx1 = 1; // zero
45883 {
45884 MacroAssembler _masm(&cbuf);
45885
45886#line 4003 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45887
45888 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45889
45890#line 45890 "ad_x86.cpp"
45891 }
45892}
45893
45894void Repl8S_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45895 cbuf.set_insts_mark();
45896 // Start at oper_input_base() and count operands
45897 unsigned idx0 = 1;
45898 unsigned idx1 = 1; // zero
45899 {
45900 MacroAssembler _masm(&cbuf);
45901
45902#line 4013 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45903
45904 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45905
45906#line 45906 "ad_x86.cpp"
45907 }
45908}
45909
45910void Repl16S_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45911 cbuf.set_insts_mark();
45912 // Start at oper_input_base() and count operands
45913 unsigned idx0 = 1;
45914 unsigned idx1 = 1; // zero
45915 {
45916 MacroAssembler _masm(&cbuf);
45917
45918#line 4023 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45919
45920 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
45921 int vector_len = 1;
45922 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
45923
45924#line 45924 "ad_x86.cpp"
45925 }
45926}
45927
45928void Repl2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45929 cbuf.set_insts_mark();
45930 // Start at oper_input_base() and count operands
45931 unsigned idx0 = 1;
45932 unsigned idx1 = 1; // src
45933 {
45934 MacroAssembler _masm(&cbuf);
45935
45936#line 4037 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45937
45938 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
45939 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45940
45941#line 45941 "ad_x86.cpp"
45942 }
45943}
45944
45945void Repl2I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45946 cbuf.set_insts_mark();
45947 // Start at oper_input_base() and count operands
45948 unsigned idx0 = 2;
45949 unsigned idx1 = 2; // mem
45950 {
45951 MacroAssembler _masm(&cbuf);
45952
45953#line 4050 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45954
45955 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
45956 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
45957
45958#line 45958 "ad_x86.cpp"
45959 }
45960}
45961
45962void Repl2I_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45963 cbuf.set_insts_mark();
45964 // Start at oper_input_base() and count operands
45965 unsigned idx0 = 1;
45966 unsigned idx1 = 1; // con
45967 {
45968 MacroAssembler _masm(&cbuf);
45969
45970#line 4062 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45971
45972 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
45973
45974#line 45974 "ad_x86.cpp"
45975 }
45976}
45977
45978void Repl2I_immNode::eval_constant(Compile* C) {
45979 {
45980
45981#line 4063 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45982 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
45983#line 45983 "ad_x86.cpp"
45984 }
45985}
45986void Repl2I_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
45987 cbuf.set_insts_mark();
45988 // Start at oper_input_base() and count operands
45989 unsigned idx0 = 1;
45990 unsigned idx1 = 1; // zero
45991 {
45992 MacroAssembler _masm(&cbuf);
45993
45994#line 4073 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
45995
45996 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
45997
45998#line 45998 "ad_x86.cpp"
45999 }
46000}
46001
46002void Repl4I_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46003 cbuf.set_insts_mark();
46004 // Start at oper_input_base() and count operands
46005 unsigned idx0 = 1;
46006 unsigned idx1 = 1; // zero
46007 {
46008 MacroAssembler _masm(&cbuf);
46009
46010#line 4083 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46011
46012 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
46013
46014#line 46014 "ad_x86.cpp"
46015 }
46016}
46017
46018void Repl8I_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46019 cbuf.set_insts_mark();
46020 // Start at oper_input_base() and count operands
46021 unsigned idx0 = 1;
46022 unsigned idx1 = 1; // zero
46023 {
46024 MacroAssembler _masm(&cbuf);
46025
46026#line 4093 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46027
46028 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
46029 int vector_len = 1;
46030 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46031
46032#line 46032 "ad_x86.cpp"
46033 }
46034}
46035
46036void Repl2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46037 cbuf.set_insts_mark();
46038 // Start at oper_input_base() and count operands
46039 unsigned idx0 = 1;
46040 unsigned idx1 = 1; // src
46041 {
46042 MacroAssembler _masm(&cbuf);
46043
46044#line 4108 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46045
46046 __ movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
46047 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
46048
46049#line 46049 "ad_x86.cpp"
46050 }
46051}
46052
46053void Repl2L_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46054 cbuf.set_insts_mark();
46055 // Start at oper_input_base() and count operands
46056 unsigned idx0 = 1;
46057 unsigned idx1 = 1; // con
46058 {
46059 MacroAssembler _masm(&cbuf);
46060
46061#line 4139 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46062
46063 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46064 __ punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
46065
46066#line 46066 "ad_x86.cpp"
46067 }
46068}
46069
46070void Repl2L_immNode::eval_constant(Compile* C) {
46071 {
46072
46073#line 4140 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46074 _constant = C->constant_table().add(this, opnd_array(1));
46075#line 46075 "ad_x86.cpp"
46076 }
46077}
46078void Repl2L_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46079 cbuf.set_insts_mark();
46080 // Start at oper_input_base() and count operands
46081 unsigned idx0 = 1;
46082 unsigned idx1 = 1; // zero
46083 {
46084 MacroAssembler _masm(&cbuf);
46085
46086#line 4151 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46087
46088 __ pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
46089
46090#line 46090 "ad_x86.cpp"
46091 }
46092}
46093
46094void Repl4L_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46095 cbuf.set_insts_mark();
46096 // Start at oper_input_base() and count operands
46097 unsigned idx0 = 1;
46098 unsigned idx1 = 1; // zero
46099 {
46100 MacroAssembler _masm(&cbuf);
46101
46102#line 4161 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46103
46104 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
46105 int vector_len = 1;
46106 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46107
46108#line 46108 "ad_x86.cpp"
46109 }
46110}
46111
46112void Repl2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46113 cbuf.set_insts_mark();
46114 // Start at oper_input_base() and count operands
46115 unsigned idx0 = 1;
46116 unsigned idx1 = 1; // src
46117 {
46118 MacroAssembler _masm(&cbuf);
46119
46120#line 4174 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46121
46122 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
46123
46124#line 46124 "ad_x86.cpp"
46125 }
46126}
46127
46128void Repl4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46129 cbuf.set_insts_mark();
46130 // Start at oper_input_base() and count operands
46131 unsigned idx0 = 1;
46132 unsigned idx1 = 1; // src
46133 {
46134 MacroAssembler _masm(&cbuf);
46135
46136#line 4184 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46137
46138 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
46139
46140#line 46140 "ad_x86.cpp"
46141 }
46142}
46143
46144void Repl2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46145 cbuf.set_insts_mark();
46146 // Start at oper_input_base() and count operands
46147 unsigned idx0 = 1;
46148 unsigned idx1 = 1; // src
46149 {
46150 MacroAssembler _masm(&cbuf);
46151
46152#line 4195 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46153
46154 __ pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x44);
46155
46156#line 46156 "ad_x86.cpp"
46157 }
46158}
46159
46160void Repl4B_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46161 cbuf.set_insts_mark();
46162 // Start at oper_input_base() and count operands
46163 unsigned idx0 = 2;
46164 unsigned idx1 = 2; // mem
46165 {
46166 MacroAssembler _masm(&cbuf);
46167
46168#line 4207 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46169
46170 int vector_len = 0;
46171 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46172
46173#line 46173 "ad_x86.cpp"
46174 }
46175}
46176
46177void Repl8B_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46178 cbuf.set_insts_mark();
46179 // Start at oper_input_base() and count operands
46180 unsigned idx0 = 2;
46181 unsigned idx1 = 2; // mem
46182 {
46183 MacroAssembler _masm(&cbuf);
46184
46185#line 4218 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46186
46187 int vector_len = 0;
46188 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46189
46190#line 46190 "ad_x86.cpp"
46191 }
46192}
46193
46194void Repl16B_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46195 cbuf.set_insts_mark();
46196 // Start at oper_input_base() and count operands
46197 unsigned idx0 = 1;
46198 unsigned idx1 = 1; // src
46199 {
46200 MacroAssembler _masm(&cbuf);
46201
46202#line 4229 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46203
46204 int vector_len = 0;
46205 __ evpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46206
46207#line 46207 "ad_x86.cpp"
46208 }
46209}
46210
46211void Repl16B_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46212 cbuf.set_insts_mark();
46213 // Start at oper_input_base() and count operands
46214 unsigned idx0 = 2;
46215 unsigned idx1 = 2; // mem
46216 {
46217 MacroAssembler _masm(&cbuf);
46218
46219#line 4240 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46220
46221 int vector_len = 0;
46222 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46223
46224#line 46224 "ad_x86.cpp"
46225 }
46226}
46227
46228void Repl32B_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46229 cbuf.set_insts_mark();
46230 // Start at oper_input_base() and count operands
46231 unsigned idx0 = 1;
46232 unsigned idx1 = 1; // src
46233 {
46234 MacroAssembler _masm(&cbuf);
46235
46236#line 4251 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46237
46238 int vector_len = 1;
46239 __ evpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46240
46241#line 46241 "ad_x86.cpp"
46242 }
46243}
46244
46245void Repl32B_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46246 cbuf.set_insts_mark();
46247 // Start at oper_input_base() and count operands
46248 unsigned idx0 = 2;
46249 unsigned idx1 = 2; // mem
46250 {
46251 MacroAssembler _masm(&cbuf);
46252
46253#line 4262 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46254
46255 int vector_len = 1;
46256 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46257
46258#line 46258 "ad_x86.cpp"
46259 }
46260}
46261
46262void Repl64B_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46263 cbuf.set_insts_mark();
46264 // Start at oper_input_base() and count operands
46265 unsigned idx0 = 1;
46266 unsigned idx1 = 1; // src
46267 {
46268 MacroAssembler _masm(&cbuf);
46269
46270#line 4273 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46271
46272 int vector_len = 2;
46273 __ evpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46274
46275#line 46275 "ad_x86.cpp"
46276 }
46277}
46278
46279void Repl64B_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46280 cbuf.set_insts_mark();
46281 // Start at oper_input_base() and count operands
46282 unsigned idx0 = 2;
46283 unsigned idx1 = 2; // mem
46284 {
46285 MacroAssembler _masm(&cbuf);
46286
46287#line 4284 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46288
46289 int vector_len = 2;
46290 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46291
46292#line 46292 "ad_x86.cpp"
46293 }
46294}
46295
46296void Repl16B_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46297 cbuf.set_insts_mark();
46298 // Start at oper_input_base() and count operands
46299 unsigned idx0 = 1;
46300 unsigned idx1 = 1; // con
46301 {
46302 MacroAssembler _masm(&cbuf);
46303
46304#line 4296 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46305
46306 int vector_len = 0;
46307 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46308 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46309
46310#line 46310 "ad_x86.cpp"
46311 }
46312}
46313
46314void Repl16B_imm_evexNode::eval_constant(Compile* C) {
46315 {
46316
46317#line 4298 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46318 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
46319#line 46319 "ad_x86.cpp"
46320 }
46321}
46322void Repl32B_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46323 cbuf.set_insts_mark();
46324 // Start at oper_input_base() and count operands
46325 unsigned idx0 = 1;
46326 unsigned idx1 = 1; // con
46327 {
46328 MacroAssembler _masm(&cbuf);
46329
46330#line 4309 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46331
46332 int vector_len = 1;
46333 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46334 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46335
46336#line 46336 "ad_x86.cpp"
46337 }
46338}
46339
46340void Repl32B_imm_evexNode::eval_constant(Compile* C) {
46341 {
46342
46343#line 4311 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46344 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
46345#line 46345 "ad_x86.cpp"
46346 }
46347}
46348void Repl64B_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46349 cbuf.set_insts_mark();
46350 // Start at oper_input_base() and count operands
46351 unsigned idx0 = 1;
46352 unsigned idx1 = 1; // con
46353 {
46354 MacroAssembler _masm(&cbuf);
46355
46356#line 4322 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46357
46358 int vector_len = 2;
46359 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46360 __ vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46361
46362#line 46362 "ad_x86.cpp"
46363 }
46364}
46365
46366void Repl64B_imm_evexNode::eval_constant(Compile* C) {
46367 {
46368
46369#line 4324 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46370 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
46371#line 46371 "ad_x86.cpp"
46372 }
46373}
46374void Repl64B_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46375 cbuf.set_insts_mark();
46376 // Start at oper_input_base() and count operands
46377 unsigned idx0 = 1;
46378 unsigned idx1 = 1; // zero
46379 {
46380 MacroAssembler _masm(&cbuf);
46381
46382#line 4334 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46383
46384 // Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it).
46385 int vector_len = 2;
46386 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46387
46388#line 46388 "ad_x86.cpp"
46389 }
46390}
46391
46392void Repl4S_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46393 cbuf.set_insts_mark();
46394 // Start at oper_input_base() and count operands
46395 unsigned idx0 = 1;
46396 unsigned idx1 = 1; // src
46397 {
46398 MacroAssembler _masm(&cbuf);
46399
46400#line 4346 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46401
46402 int vector_len = 0;
46403 __ evpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46404
46405#line 46405 "ad_x86.cpp"
46406 }
46407}
46408
46409void Repl4S_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46410 cbuf.set_insts_mark();
46411 // Start at oper_input_base() and count operands
46412 unsigned idx0 = 2;
46413 unsigned idx1 = 2; // mem
46414 {
46415 MacroAssembler _masm(&cbuf);
46416
46417#line 4357 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46418
46419 int vector_len = 0;
46420 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46421
46422#line 46422 "ad_x86.cpp"
46423 }
46424}
46425
46426void Repl8S_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46427 cbuf.set_insts_mark();
46428 // Start at oper_input_base() and count operands
46429 unsigned idx0 = 1;
46430 unsigned idx1 = 1; // src
46431 {
46432 MacroAssembler _masm(&cbuf);
46433
46434#line 4368 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46435
46436 int vector_len = 0;
46437 __ evpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46438
46439#line 46439 "ad_x86.cpp"
46440 }
46441}
46442
46443void Repl8S_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46444 cbuf.set_insts_mark();
46445 // Start at oper_input_base() and count operands
46446 unsigned idx0 = 2;
46447 unsigned idx1 = 2; // mem
46448 {
46449 MacroAssembler _masm(&cbuf);
46450
46451#line 4379 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46452
46453 int vector_len = 0;
46454 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46455
46456#line 46456 "ad_x86.cpp"
46457 }
46458}
46459
46460void Repl16S_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46461 cbuf.set_insts_mark();
46462 // Start at oper_input_base() and count operands
46463 unsigned idx0 = 1;
46464 unsigned idx1 = 1; // src
46465 {
46466 MacroAssembler _masm(&cbuf);
46467
46468#line 4390 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46469
46470 int vector_len = 1;
46471 __ evpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46472
46473#line 46473 "ad_x86.cpp"
46474 }
46475}
46476
46477void Repl16S_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46478 cbuf.set_insts_mark();
46479 // Start at oper_input_base() and count operands
46480 unsigned idx0 = 2;
46481 unsigned idx1 = 2; // mem
46482 {
46483 MacroAssembler _masm(&cbuf);
46484
46485#line 4401 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46486
46487 int vector_len = 1;
46488 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46489
46490#line 46490 "ad_x86.cpp"
46491 }
46492}
46493
46494void Repl32S_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46495 cbuf.set_insts_mark();
46496 // Start at oper_input_base() and count operands
46497 unsigned idx0 = 1;
46498 unsigned idx1 = 1; // src
46499 {
46500 MacroAssembler _masm(&cbuf);
46501
46502#line 4412 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46503
46504 int vector_len = 2;
46505 __ evpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46506
46507#line 46507 "ad_x86.cpp"
46508 }
46509}
46510
46511void Repl32S_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46512 cbuf.set_insts_mark();
46513 // Start at oper_input_base() and count operands
46514 unsigned idx0 = 2;
46515 unsigned idx1 = 2; // mem
46516 {
46517 MacroAssembler _masm(&cbuf);
46518
46519#line 4423 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46520
46521 int vector_len = 2;
46522 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46523
46524#line 46524 "ad_x86.cpp"
46525 }
46526}
46527
46528void Repl8S_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46529 cbuf.set_insts_mark();
46530 // Start at oper_input_base() and count operands
46531 unsigned idx0 = 1;
46532 unsigned idx1 = 1; // con
46533 {
46534 MacroAssembler _masm(&cbuf);
46535
46536#line 4435 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46537
46538 int vector_len = 0;
46539 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46540 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46541
46542#line 46542 "ad_x86.cpp"
46543 }
46544}
46545
46546void Repl8S_imm_evexNode::eval_constant(Compile* C) {
46547 {
46548
46549#line 4437 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46550 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
46551#line 46551 "ad_x86.cpp"
46552 }
46553}
46554void Repl16S_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46555 cbuf.set_insts_mark();
46556 // Start at oper_input_base() and count operands
46557 unsigned idx0 = 1;
46558 unsigned idx1 = 1; // con
46559 {
46560 MacroAssembler _masm(&cbuf);
46561
46562#line 4448 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46563
46564 int vector_len = 1;
46565 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46566 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46567
46568#line 46568 "ad_x86.cpp"
46569 }
46570}
46571
46572void Repl16S_imm_evexNode::eval_constant(Compile* C) {
46573 {
46574
46575#line 4450 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46576 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
46577#line 46577 "ad_x86.cpp"
46578 }
46579}
46580void Repl32S_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46581 cbuf.set_insts_mark();
46582 // Start at oper_input_base() and count operands
46583 unsigned idx0 = 1;
46584 unsigned idx1 = 1; // con
46585 {
46586 MacroAssembler _masm(&cbuf);
46587
46588#line 4461 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46589
46590 int vector_len = 2;
46591 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46592 __ vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46593
46594#line 46594 "ad_x86.cpp"
46595 }
46596}
46597
46598void Repl32S_imm_evexNode::eval_constant(Compile* C) {
46599 {
46600
46601#line 4463 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46602 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
46603#line 46603 "ad_x86.cpp"
46604 }
46605}
46606void Repl32S_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46607 cbuf.set_insts_mark();
46608 // Start at oper_input_base() and count operands
46609 unsigned idx0 = 1;
46610 unsigned idx1 = 1; // zero
46611 {
46612 MacroAssembler _masm(&cbuf);
46613
46614#line 4473 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46615
46616 // Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it).
46617 int vector_len = 2;
46618 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46619
46620#line 46620 "ad_x86.cpp"
46621 }
46622}
46623
46624void Repl4I_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46625 cbuf.set_insts_mark();
46626 // Start at oper_input_base() and count operands
46627 unsigned idx0 = 1;
46628 unsigned idx1 = 1; // src
46629 {
46630 MacroAssembler _masm(&cbuf);
46631
46632#line 4485 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46633
46634 int vector_len = 0;
46635 __ evpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46636
46637#line 46637 "ad_x86.cpp"
46638 }
46639}
46640
46641void Repl4I_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46642 cbuf.set_insts_mark();
46643 // Start at oper_input_base() and count operands
46644 unsigned idx0 = 2;
46645 unsigned idx1 = 2; // mem
46646 {
46647 MacroAssembler _masm(&cbuf);
46648
46649#line 4496 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46650
46651 int vector_len = 0;
46652 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46653
46654#line 46654 "ad_x86.cpp"
46655 }
46656}
46657
46658void Repl8I_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46659 cbuf.set_insts_mark();
46660 // Start at oper_input_base() and count operands
46661 unsigned idx0 = 1;
46662 unsigned idx1 = 1; // src
46663 {
46664 MacroAssembler _masm(&cbuf);
46665
46666#line 4507 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46667
46668 int vector_len = 1;
46669 __ evpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46670
46671#line 46671 "ad_x86.cpp"
46672 }
46673}
46674
46675void Repl8I_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46676 cbuf.set_insts_mark();
46677 // Start at oper_input_base() and count operands
46678 unsigned idx0 = 2;
46679 unsigned idx1 = 2; // mem
46680 {
46681 MacroAssembler _masm(&cbuf);
46682
46683#line 4518 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46684
46685 int vector_len = 1;
46686 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46687
46688#line 46688 "ad_x86.cpp"
46689 }
46690}
46691
46692void Repl16I_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46693 cbuf.set_insts_mark();
46694 // Start at oper_input_base() and count operands
46695 unsigned idx0 = 1;
46696 unsigned idx1 = 1; // src
46697 {
46698 MacroAssembler _masm(&cbuf);
46699
46700#line 4529 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46701
46702 int vector_len = 2;
46703 __ evpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46704
46705#line 46705 "ad_x86.cpp"
46706 }
46707}
46708
46709void Repl16I_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46710 cbuf.set_insts_mark();
46711 // Start at oper_input_base() and count operands
46712 unsigned idx0 = 2;
46713 unsigned idx1 = 2; // mem
46714 {
46715 MacroAssembler _masm(&cbuf);
46716
46717#line 4540 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46718
46719 int vector_len = 2;
46720 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46721
46722#line 46722 "ad_x86.cpp"
46723 }
46724}
46725
46726void Repl4I_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46727 cbuf.set_insts_mark();
46728 // Start at oper_input_base() and count operands
46729 unsigned idx0 = 1;
46730 unsigned idx1 = 1; // con
46731 {
46732 MacroAssembler _masm(&cbuf);
46733
46734#line 4552 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46735
46736 int vector_len = 0;
46737 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46738 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46739
46740#line 46740 "ad_x86.cpp"
46741 }
46742}
46743
46744void Repl4I_imm_evexNode::eval_constant(Compile* C) {
46745 {
46746
46747#line 4554 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46748 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
46749#line 46749 "ad_x86.cpp"
46750 }
46751}
46752void Repl8I_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46753 cbuf.set_insts_mark();
46754 // Start at oper_input_base() and count operands
46755 unsigned idx0 = 1;
46756 unsigned idx1 = 1; // con
46757 {
46758 MacroAssembler _masm(&cbuf);
46759
46760#line 4565 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46761
46762 int vector_len = 1;
46763 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46764 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46765
46766#line 46766 "ad_x86.cpp"
46767 }
46768}
46769
46770void Repl8I_imm_evexNode::eval_constant(Compile* C) {
46771 {
46772
46773#line 4567 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46774 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
46775#line 46775 "ad_x86.cpp"
46776 }
46777}
46778void Repl16I_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46779 cbuf.set_insts_mark();
46780 // Start at oper_input_base() and count operands
46781 unsigned idx0 = 1;
46782 unsigned idx1 = 1; // con
46783 {
46784 MacroAssembler _masm(&cbuf);
46785
46786#line 4578 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46787
46788 int vector_len = 2;
46789 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46790 __ vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46791
46792#line 46792 "ad_x86.cpp"
46793 }
46794}
46795
46796void Repl16I_imm_evexNode::eval_constant(Compile* C) {
46797 {
46798
46799#line 4580 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46800 _constant = C->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
46801#line 46801 "ad_x86.cpp"
46802 }
46803}
46804void Repl16I_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46805 cbuf.set_insts_mark();
46806 // Start at oper_input_base() and count operands
46807 unsigned idx0 = 1;
46808 unsigned idx1 = 1; // zero
46809 {
46810 MacroAssembler _masm(&cbuf);
46811
46812#line 4590 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46813
46814 // Use vxorpd since AVX does not have vpxor for 512-bit (AVX2 will have it).
46815 int vector_len = 2;
46816 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46817
46818#line 46818 "ad_x86.cpp"
46819 }
46820}
46821
46822void Repl4L_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46823 cbuf.set_insts_mark();
46824 // Start at oper_input_base() and count operands
46825 unsigned idx0 = 1;
46826 unsigned idx1 = 1; // src
46827 {
46828 MacroAssembler _masm(&cbuf);
46829
46830#line 4604 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46831
46832 int vector_len = 1;
46833 __ evpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46834
46835#line 46835 "ad_x86.cpp"
46836 }
46837}
46838
46839void Repl8L_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46840 cbuf.set_insts_mark();
46841 // Start at oper_input_base() and count operands
46842 unsigned idx0 = 1;
46843 unsigned idx1 = 1; // src
46844 {
46845 MacroAssembler _masm(&cbuf);
46846
46847#line 4615 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46848
46849 int vector_len = 2;
46850 __ evpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vector_len);
46851
46852#line 46852 "ad_x86.cpp"
46853 }
46854}
46855
46856void Repl4L_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46857 cbuf.set_insts_mark();
46858 // Start at oper_input_base() and count operands
46859 unsigned idx0 = 1;
46860 unsigned idx1 = 1; // con
46861 {
46862 MacroAssembler _masm(&cbuf);
46863
46864#line 4664 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46865
46866 int vector_len = 1;
46867 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46868 __ vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46869
46870#line 46870 "ad_x86.cpp"
46871 }
46872}
46873
46874void Repl4L_imm_evexNode::eval_constant(Compile* C) {
46875 {
46876
46877#line 4666 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46878 _constant = C->constant_table().add(this, opnd_array(1));
46879#line 46879 "ad_x86.cpp"
46880 }
46881}
46882void Repl8L_imm_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46883 cbuf.set_insts_mark();
46884 // Start at oper_input_base() and count operands
46885 unsigned idx0 = 1;
46886 unsigned idx1 = 1; // con
46887 {
46888 MacroAssembler _masm(&cbuf);
46889
46890#line 4677 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46891
46892 int vector_len = 2;
46893 __ movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(__ code()->consts()->start() + constant_offset()));
46894 __ vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46895
46896#line 46896 "ad_x86.cpp"
46897 }
46898}
46899
46900void Repl8L_imm_evexNode::eval_constant(Compile* C) {
46901 {
46902
46903#line 4679 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46904 _constant = C->constant_table().add(this, opnd_array(1));
46905#line 46905 "ad_x86.cpp"
46906 }
46907}
46908void Repl2L_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46909 cbuf.set_insts_mark();
46910 // Start at oper_input_base() and count operands
46911 unsigned idx0 = 2;
46912 unsigned idx1 = 2; // mem
46913 {
46914 MacroAssembler _masm(&cbuf);
46915
46916#line 4689 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46917
46918 int vector_len = 0;
46919 __ vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46920
46921#line 46921 "ad_x86.cpp"
46922 }
46923}
46924
46925void Repl4L_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46926 cbuf.set_insts_mark();
46927 // Start at oper_input_base() and count operands
46928 unsigned idx0 = 2;
46929 unsigned idx1 = 2; // mem
46930 {
46931 MacroAssembler _masm(&cbuf);
46932
46933#line 4700 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46934
46935 int vector_len = 1;
46936 __ vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46937
46938#line 46938 "ad_x86.cpp"
46939 }
46940}
46941
46942void Repl8L_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46943 cbuf.set_insts_mark();
46944 // Start at oper_input_base() and count operands
46945 unsigned idx0 = 2;
46946 unsigned idx1 = 2; // mem
46947 {
46948 MacroAssembler _masm(&cbuf);
46949
46950#line 4711 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46951
46952 int vector_len = 2;
46953 __ vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
46954
46955#line 46955 "ad_x86.cpp"
46956 }
46957}
46958
46959void Repl8L_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46960 cbuf.set_insts_mark();
46961 // Start at oper_input_base() and count operands
46962 unsigned idx0 = 1;
46963 unsigned idx1 = 1; // zero
46964 {
46965 MacroAssembler _masm(&cbuf);
46966
46967#line 4722 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46968
46969 // Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it).
46970 int vector_len = 2;
46971 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
46972
46973#line 46973 "ad_x86.cpp"
46974 }
46975}
46976
46977void Repl8F_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46978 cbuf.set_insts_mark();
46979 // Start at oper_input_base() and count operands
46980 unsigned idx0 = 1;
46981 unsigned idx1 = 1; // src
46982 {
46983 MacroAssembler _masm(&cbuf);
46984
46985#line 4734 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
46986
46987 int vector_len = 1;
46988 __ vpbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
46989
46990#line 46990 "ad_x86.cpp"
46991 }
46992}
46993
46994void Repl8F_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
46995 cbuf.set_insts_mark();
46996 // Start at oper_input_base() and count operands
46997 unsigned idx0 = 2;
46998 unsigned idx1 = 2; // mem
46999 {
47000 MacroAssembler _masm(&cbuf);
47001
47002#line 4745 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47003
47004 int vector_len = 1;
47005 __ vpbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
47006
47007#line 47007 "ad_x86.cpp"
47008 }
47009}
47010
47011void Repl16F_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47012 cbuf.set_insts_mark();
47013 // Start at oper_input_base() and count operands
47014 unsigned idx0 = 1;
47015 unsigned idx1 = 1; // src
47016 {
47017 MacroAssembler _masm(&cbuf);
47018
47019#line 4756 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47020
47021 int vector_len = 2;
47022 __ vpbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
47023
47024#line 47024 "ad_x86.cpp"
47025 }
47026}
47027
47028void Repl16F_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47029 cbuf.set_insts_mark();
47030 // Start at oper_input_base() and count operands
47031 unsigned idx0 = 2;
47032 unsigned idx1 = 2; // mem
47033 {
47034 MacroAssembler _masm(&cbuf);
47035
47036#line 4767 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47037
47038 int vector_len = 2;
47039 __ vpbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
47040
47041#line 47041 "ad_x86.cpp"
47042 }
47043}
47044
47045void Repl2F_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47046 cbuf.set_insts_mark();
47047 // Start at oper_input_base() and count operands
47048 unsigned idx0 = 1;
47049 unsigned idx1 = 1; // zero
47050 {
47051 MacroAssembler _masm(&cbuf);
47052
47053#line 4778 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47054
47055 // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
47056 int vector_len = 2;
47057 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47058
47059#line 47059 "ad_x86.cpp"
47060 }
47061}
47062
47063void Repl4F_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47064 cbuf.set_insts_mark();
47065 // Start at oper_input_base() and count operands
47066 unsigned idx0 = 1;
47067 unsigned idx1 = 1; // zero
47068 {
47069 MacroAssembler _masm(&cbuf);
47070
47071#line 4790 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47072
47073 // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
47074 int vector_len = 2;
47075 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47076
47077#line 47077 "ad_x86.cpp"
47078 }
47079}
47080
47081void Repl8F_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47082 cbuf.set_insts_mark();
47083 // Start at oper_input_base() and count operands
47084 unsigned idx0 = 1;
47085 unsigned idx1 = 1; // zero
47086 {
47087 MacroAssembler _masm(&cbuf);
47088
47089#line 4802 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47090
47091 // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
47092 int vector_len = 2;
47093 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47094
47095#line 47095 "ad_x86.cpp"
47096 }
47097}
47098
47099void Repl16F_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47100 cbuf.set_insts_mark();
47101 // Start at oper_input_base() and count operands
47102 unsigned idx0 = 1;
47103 unsigned idx1 = 1; // zero
47104 {
47105 MacroAssembler _masm(&cbuf);
47106
47107#line 4814 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47108
47109 // Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
47110 int vector_len = 2;
47111 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47112
47113#line 47113 "ad_x86.cpp"
47114 }
47115}
47116
47117void Repl4D_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47118 cbuf.set_insts_mark();
47119 // Start at oper_input_base() and count operands
47120 unsigned idx0 = 1;
47121 unsigned idx1 = 1; // src
47122 {
47123 MacroAssembler _masm(&cbuf);
47124
47125#line 4826 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47126
47127 int vector_len = 1;
47128 __ vpbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
47129
47130#line 47130 "ad_x86.cpp"
47131 }
47132}
47133
47134void Repl4D_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47135 cbuf.set_insts_mark();
47136 // Start at oper_input_base() and count operands
47137 unsigned idx0 = 2;
47138 unsigned idx1 = 2; // mem
47139 {
47140 MacroAssembler _masm(&cbuf);
47141
47142#line 4837 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47143
47144 int vector_len = 1;
47145 __ vpbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
47146
47147#line 47147 "ad_x86.cpp"
47148 }
47149}
47150
47151void Repl8D_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47152 cbuf.set_insts_mark();
47153 // Start at oper_input_base() and count operands
47154 unsigned idx0 = 1;
47155 unsigned idx1 = 1; // src
47156 {
47157 MacroAssembler _masm(&cbuf);
47158
47159#line 4848 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47160
47161 int vector_len = 2;
47162 __ vpbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
47163
47164#line 47164 "ad_x86.cpp"
47165 }
47166}
47167
47168void Repl8D_mem_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47169 cbuf.set_insts_mark();
47170 // Start at oper_input_base() and count operands
47171 unsigned idx0 = 2;
47172 unsigned idx1 = 2; // mem
47173 {
47174 MacroAssembler _masm(&cbuf);
47175
47176#line 4859 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47177
47178 int vector_len = 2;
47179 __ vpbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
47180
47181#line 47181 "ad_x86.cpp"
47182 }
47183}
47184
47185void Repl2D_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47186 cbuf.set_insts_mark();
47187 // Start at oper_input_base() and count operands
47188 unsigned idx0 = 1;
47189 unsigned idx1 = 1; // zero
47190 {
47191 MacroAssembler _masm(&cbuf);
47192
47193#line 4870 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47194
47195 // Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation
47196 int vector_len = 2;
47197 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47198
47199#line 47199 "ad_x86.cpp"
47200 }
47201}
47202
47203void Repl4D_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47204 cbuf.set_insts_mark();
47205 // Start at oper_input_base() and count operands
47206 unsigned idx0 = 1;
47207 unsigned idx1 = 1; // zero
47208 {
47209 MacroAssembler _masm(&cbuf);
47210
47211#line 4882 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47212
47213 // Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation
47214 int vector_len = 2;
47215 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47216
47217#line 47217 "ad_x86.cpp"
47218 }
47219}
47220
47221void Repl8D_zero_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47222 cbuf.set_insts_mark();
47223 // Start at oper_input_base() and count operands
47224 unsigned idx0 = 1;
47225 unsigned idx1 = 1; // zero
47226 {
47227 MacroAssembler _masm(&cbuf);
47228
47229#line 4894 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47230
47231 // Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation
47232 int vector_len = 2;
47233 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vector_len);
47234
47235#line 47235 "ad_x86.cpp"
47236 }
47237}
47238
47239void rsadd2I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47240 cbuf.set_insts_mark();
47241 // Start at oper_input_base() and count operands
47242 unsigned idx0 = 1;
47243 unsigned idx1 = 1; // src1
47244 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47245 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47246 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47247 {
47248 MacroAssembler _masm(&cbuf);
47249
47250#line 4913 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47251
47252 __ movdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47253 __ phaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47254 __ movdl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47255 __ paddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47256 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47257
47258#line 47258 "ad_x86.cpp"
47259 }
47260}
47261
47262void rvadd2I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47263 cbuf.set_insts_mark();
47264 // Start at oper_input_base() and count operands
47265 unsigned idx0 = 1;
47266 unsigned idx1 = 1; // src1
47267 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47268 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47269 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47270 {
47271 MacroAssembler _masm(&cbuf);
47272
47273#line 4931 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47274
47275 int vector_len = 0;
47276 __ vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
47277 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47278 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, vector_len);
47279 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47280
47281#line 47281 "ad_x86.cpp"
47282 }
47283}
47284
47285void rvadd2I_reduction_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47286 cbuf.set_insts_mark();
47287 // Start at oper_input_base() and count operands
47288 unsigned idx0 = 1;
47289 unsigned idx1 = 1; // src1
47290 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47291 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47292 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47293 {
47294 MacroAssembler _masm(&cbuf);
47295
47296#line 4950 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47297
47298 int vector_len = 0;
47299 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47300 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47301 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47302 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47303 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47304
47305#line 47305 "ad_x86.cpp"
47306 }
47307}
47308
47309void rsadd4I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47310 cbuf.set_insts_mark();
47311 // Start at oper_input_base() and count operands
47312 unsigned idx0 = 1;
47313 unsigned idx1 = 1; // src1
47314 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47315 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47316 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47317 {
47318 MacroAssembler _masm(&cbuf);
47319
47320#line 4971 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47321
47322 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47323 __ phaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47324 __ phaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47325 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47326 __ paddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47327 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47328
47329#line 47329 "ad_x86.cpp"
47330 }
47331}
47332
47333void rvadd4I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47334 cbuf.set_insts_mark();
47335 // Start at oper_input_base() and count operands
47336 unsigned idx0 = 1;
47337 unsigned idx1 = 1; // src1
47338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47339 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47340 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47341 {
47342 MacroAssembler _masm(&cbuf);
47343
47344#line 4991 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47345
47346 int vector_len = 0;
47347 __ vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
47348 __ vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, vector_len);
47349 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47350 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, vector_len);
47351 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47352
47353#line 47353 "ad_x86.cpp"
47354 }
47355}
47356
47357void rvadd4I_reduction_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47358 cbuf.set_insts_mark();
47359 // Start at oper_input_base() and count operands
47360 unsigned idx0 = 1;
47361 unsigned idx1 = 1; // src1
47362 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47363 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47364 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47365 {
47366 MacroAssembler _masm(&cbuf);
47367
47368#line 5013 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47369
47370 int vector_len = 0;
47371 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47372 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47373 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47374 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47375 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47376 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47377 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47378
47379#line 47379 "ad_x86.cpp"
47380 }
47381}
47382
47383void rvadd8I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47384 cbuf.set_insts_mark();
47385 // Start at oper_input_base() and count operands
47386 unsigned idx0 = 1;
47387 unsigned idx1 = 1; // src1
47388 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47389 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47390 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47391 {
47392 MacroAssembler _masm(&cbuf);
47393
47394#line 5037 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47395
47396 int vector_len = 1;
47397 __ vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
47398 __ vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47399 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47400 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47401 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47402 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47403 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47404
47405#line 47405 "ad_x86.cpp"
47406 }
47407}
47408
47409void rvadd8I_reduction_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47410 cbuf.set_insts_mark();
47411 // Start at oper_input_base() and count operands
47412 unsigned idx0 = 1;
47413 unsigned idx1 = 1; // src1
47414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47415 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47416 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47417 {
47418 MacroAssembler _masm(&cbuf);
47419
47420#line 5063 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47421
47422 int vector_len = 0;
47423 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47424 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
47425 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0xE);
47426 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47427 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47428 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47429 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47430 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47431 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47432
47433#line 47433 "ad_x86.cpp"
47434 }
47435}
47436
47437void rvadd16I_reduction_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47438 cbuf.set_insts_mark();
47439 // Start at oper_input_base() and count operands
47440 unsigned idx0 = 1;
47441 unsigned idx1 = 1; // src1
47442 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47443 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47444 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47445 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
47446 {
47447 MacroAssembler _masm(&cbuf);
47448
47449#line 5093 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47450
47451 __ vextracti64x4_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47452 __ vpaddd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 1);
47453 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */);
47454 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, 0);
47455 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0xE);
47456 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47457 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47458 __ vpaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47459 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47460 __ vpaddd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47461 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47462
47463#line 47463 "ad_x86.cpp"
47464 }
47465}
47466
47467void rvadd2L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47468 cbuf.set_insts_mark();
47469 // Start at oper_input_base() and count operands
47470 unsigned idx0 = 1;
47471 unsigned idx1 = 1; // src1
47472 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47473 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47474 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47475 {
47476 MacroAssembler _masm(&cbuf);
47477
47478#line 5119 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47479
47480 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47481 __ vpaddq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47482 __ movdq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47483 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47484 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47485
47486#line 47486 "ad_x86.cpp"
47487 }
47488}
47489
47490void rvadd4L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47491 cbuf.set_insts_mark();
47492 // Start at oper_input_base() and count operands
47493 unsigned idx0 = 1;
47494 unsigned idx1 = 1; // src1
47495 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47496 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47497 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47498 {
47499 MacroAssembler _masm(&cbuf);
47500
47501#line 5140 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47502
47503 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47504 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0);
47505 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47506 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47507 __ movdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47508 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47509 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47510
47511#line 47511 "ad_x86.cpp"
47512 }
47513}
47514
47515void rvadd8L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47516 cbuf.set_insts_mark();
47517 // Start at oper_input_base() and count operands
47518 unsigned idx0 = 1;
47519 unsigned idx1 = 1; // src1
47520 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47521 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47522 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47523 {
47524 MacroAssembler _masm(&cbuf);
47525
47526#line 5165 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47527
47528 __ vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47529 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 1);
47530 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47531 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47532 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47533 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47534 __ movdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47535 __ vpaddq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
47536 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47537
47538#line 47538 "ad_x86.cpp"
47539 }
47540}
47541
47542void rsadd2F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47543 cbuf.set_insts_mark();
47544 // Start at oper_input_base() and count operands
47545 unsigned idx0 = 1;
47546 unsigned idx1 = 1; // dst
47547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47548 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47549 {
47550 MacroAssembler _masm(&cbuf);
47551
47552#line 5187 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47553
47554 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47555 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47556 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47557
47558#line 47558 "ad_x86.cpp"
47559 }
47560}
47561
47562void rvadd2F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47563 cbuf.set_insts_mark();
47564 // Start at oper_input_base() and count operands
47565 unsigned idx0 = 1;
47566 unsigned idx1 = 1; // dst
47567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47568 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47569 {
47570 MacroAssembler _masm(&cbuf);
47571
47572#line 5202 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47573
47574 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47575 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47576 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47577
47578#line 47578 "ad_x86.cpp"
47579 }
47580}
47581
47582void rsadd4F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47583 cbuf.set_insts_mark();
47584 // Start at oper_input_base() and count operands
47585 unsigned idx0 = 1;
47586 unsigned idx1 = 1; // dst
47587 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47588 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47589 {
47590 MacroAssembler _masm(&cbuf);
47591
47592#line 5221 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47593
47594 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47595 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47596 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47597 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
47598 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47599 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
47600 __ addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47601
47602#line 47602 "ad_x86.cpp"
47603 }
47604}
47605
47606void rvadd4F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47607 cbuf.set_insts_mark();
47608 // Start at oper_input_base() and count operands
47609 unsigned idx0 = 1;
47610 unsigned idx1 = 1; // dst
47611 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47612 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47613 {
47614 MacroAssembler _masm(&cbuf);
47615
47616#line 5244 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47617
47618 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47619 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47620 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47621 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
47622 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47623 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
47624 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47625
47626#line 47626 "ad_x86.cpp"
47627 }
47628}
47629
47630void radd8F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47631 cbuf.set_insts_mark();
47632 // Start at oper_input_base() and count operands
47633 unsigned idx0 = 1;
47634 unsigned idx1 = 1; // dst
47635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47636 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47637 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47638 {
47639 MacroAssembler _masm(&cbuf);
47640
47641#line 5275 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47642
47643 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47644 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47645 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47646 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
47647 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47648 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
47649 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47650 __ vextractf128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47651 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47652 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
47653 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47654 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
47655 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47656 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
47657 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47658
47659#line 47659 "ad_x86.cpp"
47660 }
47661}
47662
47663void radd16F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47664 cbuf.set_insts_mark();
47665 // Start at oper_input_base() and count operands
47666 unsigned idx0 = 1;
47667 unsigned idx1 = 1; // dst
47668 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47669 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47670 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47671 {
47672 MacroAssembler _masm(&cbuf);
47673
47674#line 5330 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47675
47676 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47677 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
47678 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47679 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
47680 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47681 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
47682 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47683 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47684 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47685 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
47686 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47687 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
47688 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47689 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
47690 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47691 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x2);
47692 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47693 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
47694 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47695 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
47696 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47697 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
47698 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47699 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x3);
47700 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47701 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
47702 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47703 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
47704 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47705 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
47706 __ vaddss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47707
47708#line 47708 "ad_x86.cpp"
47709 }
47710}
47711
47712void rsadd2D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47713 cbuf.set_insts_mark();
47714 // Start at oper_input_base() and count operands
47715 unsigned idx0 = 1;
47716 unsigned idx1 = 1; // dst
47717 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47718 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47719 {
47720 MacroAssembler _masm(&cbuf);
47721
47722#line 5373 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47723
47724 __ addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47725 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47726 __ addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47727
47728#line 47728 "ad_x86.cpp"
47729 }
47730}
47731
47732void rvadd2D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47733 cbuf.set_insts_mark();
47734 // Start at oper_input_base() and count operands
47735 unsigned idx0 = 1;
47736 unsigned idx1 = 1; // dst
47737 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47738 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47739 {
47740 MacroAssembler _masm(&cbuf);
47741
47742#line 5388 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47743
47744 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47745 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47746 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47747
47748#line 47748 "ad_x86.cpp"
47749 }
47750}
47751
47752void rvadd4D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47753 cbuf.set_insts_mark();
47754 // Start at oper_input_base() and count operands
47755 unsigned idx0 = 1;
47756 unsigned idx1 = 1; // dst
47757 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47758 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47759 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47760 {
47761 MacroAssembler _masm(&cbuf);
47762
47763#line 5407 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47764
47765 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47766 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47767 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47768 __ vextractf128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47769 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47770 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47771 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47772
47773#line 47773 "ad_x86.cpp"
47774 }
47775}
47776
47777void rvadd8D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47778 cbuf.set_insts_mark();
47779 // Start at oper_input_base() and count operands
47780 unsigned idx0 = 1;
47781 unsigned idx1 = 1; // dst
47782 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47783 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47784 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47785 {
47786 MacroAssembler _masm(&cbuf);
47787
47788#line 5438 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47789
47790 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47791 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47792 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47793 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47794 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47795 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47796 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47797 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x2);
47798 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47799 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47800 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47801 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x3);
47802 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47803 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
47804 __ vaddsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47805
47806#line 47806 "ad_x86.cpp"
47807 }
47808}
47809
47810void rsmul2I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47811 cbuf.set_insts_mark();
47812 // Start at oper_input_base() and count operands
47813 unsigned idx0 = 1;
47814 unsigned idx1 = 1; // src1
47815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47816 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47817 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47818 {
47819 MacroAssembler _masm(&cbuf);
47820
47821#line 5467 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47822
47823 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47824 __ pmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47825 __ movdl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47826 __ pmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47827 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47828
47829#line 47829 "ad_x86.cpp"
47830 }
47831}
47832
47833void rvmul2I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47834 cbuf.set_insts_mark();
47835 // Start at oper_input_base() and count operands
47836 unsigned idx0 = 1;
47837 unsigned idx1 = 1; // src1
47838 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47839 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47840 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47841 {
47842 MacroAssembler _masm(&cbuf);
47843
47844#line 5486 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47845
47846 int vector_len = 0;
47847 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
47848 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47849 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47850 __ vpmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47851 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47852
47853#line 47853 "ad_x86.cpp"
47854 }
47855}
47856
47857void rsmul4I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47858 cbuf.set_insts_mark();
47859 // Start at oper_input_base() and count operands
47860 unsigned idx0 = 1;
47861 unsigned idx1 = 1; // src1
47862 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47863 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47864 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47865 {
47866 MacroAssembler _masm(&cbuf);
47867
47868#line 5508 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47869
47870 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47871 __ pmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47872 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x1);
47873 __ pmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47874 __ movdl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47875 __ pmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
47876 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47877
47878#line 47878 "ad_x86.cpp"
47879 }
47880}
47881
47882void rvmul4I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47883 cbuf.set_insts_mark();
47884 // Start at oper_input_base() and count operands
47885 unsigned idx0 = 1;
47886 unsigned idx1 = 1; // src1
47887 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47888 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47889 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47890 {
47891 MacroAssembler _masm(&cbuf);
47892
47893#line 5531 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47894
47895 int vector_len = 0;
47896 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47897 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47898 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47899 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47900 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47901 __ vpmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47902 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47903
47904#line 47904 "ad_x86.cpp"
47905 }
47906}
47907
47908void rvmul8I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47909 cbuf.set_insts_mark();
47910 // Start at oper_input_base() and count operands
47911 unsigned idx0 = 1;
47912 unsigned idx1 = 1; // src1
47913 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47914 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47915 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47916 {
47917 MacroAssembler _masm(&cbuf);
47918
47919#line 5557 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47920
47921 int vector_len = 0;
47922 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47923 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
47924 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0xE);
47925 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47926 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47927 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47928 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47929 __ vpmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, vector_len);
47930 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47931
47932#line 47932 "ad_x86.cpp"
47933 }
47934}
47935
47936void rvmul16I_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47937 cbuf.set_insts_mark();
47938 // Start at oper_input_base() and count operands
47939 unsigned idx0 = 1;
47940 unsigned idx1 = 1; // src1
47941 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47942 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47943 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47944 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
47945 {
47946 MacroAssembler _masm(&cbuf);
47947
47948#line 5587 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47949
47950 __ vextracti64x4_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
47951 __ vpmulld(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 1);
47952 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */);
47953 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, 0);
47954 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0xE);
47955 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47956 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0x1);
47957 __ vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47958 __ movdl(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47959 __ vpmulld(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47960 __ movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47961
47962#line 47962 "ad_x86.cpp"
47963 }
47964}
47965
47966void rvmul2L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47967 cbuf.set_insts_mark();
47968 // Start at oper_input_base() and count operands
47969 unsigned idx0 = 1;
47970 unsigned idx1 = 1; // src1
47971 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47972 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47973 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47974 {
47975 MacroAssembler _masm(&cbuf);
47976
47977#line 5613 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
47978
47979 __ pshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
47980 __ vpmullq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47981 __ movdq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
47982 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0);
47983 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
47984
47985#line 47985 "ad_x86.cpp"
47986 }
47987}
47988
47989void rvmul4L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
47990 cbuf.set_insts_mark();
47991 // Start at oper_input_base() and count operands
47992 unsigned idx0 = 1;
47993 unsigned idx1 = 1; // src1
47994 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
47995 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
47996 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
47997 {
47998 MacroAssembler _masm(&cbuf);
47999
48000#line 5634 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48001
48002 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48003 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0);
48004 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48005 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
48006 __ movdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
48007 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
48008 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48009
48010#line 48010 "ad_x86.cpp"
48011 }
48012}
48013
48014void rvmul8L_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48015 cbuf.set_insts_mark();
48016 // Start at oper_input_base() and count operands
48017 unsigned idx0 = 1;
48018 unsigned idx1 = 1; // src1
48019 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48020 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48021 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
48022 {
48023 MacroAssembler _masm(&cbuf);
48024
48025#line 5659 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48026
48027 __ vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48028 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 1);
48029 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48030 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
48031 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48032 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
48033 __ movdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */);
48034 __ vpmullq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 0);
48035 __ movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48036
48037#line 48037 "ad_x86.cpp"
48038 }
48039}
48040
48041void rsmul2F_reductionNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48042 cbuf.set_insts_mark();
48043 // Start at oper_input_base() and count operands
48044 unsigned idx0 = 1;
48045 unsigned idx1 = 1; // dst
48046 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48047 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48048 {
48049 MacroAssembler _masm(&cbuf);
48050
48051#line 5681 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48052
48053 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48054 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48055 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48056
48057#line 48057 "ad_x86.cpp"
48058 }
48059}
48060
48061void rvmul2F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48062 cbuf.set_insts_mark();
48063 // Start at oper_input_base() and count operands
48064 unsigned idx0 = 1;
48065 unsigned idx1 = 1; // dst
48066 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48067 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48068 {
48069 MacroAssembler _masm(&cbuf);
48070
48071#line 5696 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48072
48073 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48074 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48075 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48076
48077#line 48077 "ad_x86.cpp"
48078 }
48079}
48080
48081void rsmul4F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48082 cbuf.set_insts_mark();
48083 // Start at oper_input_base() and count operands
48084 unsigned idx0 = 1;
48085 unsigned idx1 = 1; // dst
48086 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48087 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48088 {
48089 MacroAssembler _masm(&cbuf);
48090
48091#line 5715 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48092
48093 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48094 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48095 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48096 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
48097 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48098 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
48099 __ mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48100
48101#line 48101 "ad_x86.cpp"
48102 }
48103}
48104
48105void rvmul4F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48106 cbuf.set_insts_mark();
48107 // Start at oper_input_base() and count operands
48108 unsigned idx0 = 1;
48109 unsigned idx1 = 1; // dst
48110 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48111 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48112 {
48113 MacroAssembler _masm(&cbuf);
48114
48115#line 5738 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48116
48117 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48118 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48119 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48120 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
48121 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48122 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
48123 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48124
48125#line 48125 "ad_x86.cpp"
48126 }
48127}
48128
48129void rvmul8F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48130 cbuf.set_insts_mark();
48131 // Start at oper_input_base() and count operands
48132 unsigned idx0 = 1;
48133 unsigned idx1 = 1; // dst
48134 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48135 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48136 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
48137 {
48138 MacroAssembler _masm(&cbuf);
48139
48140#line 5769 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48141
48142 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48143 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48144 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48145 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
48146 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48147 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
48148 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48149 __ vextractf128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48150 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48151 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
48152 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48153 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
48154 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48155 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
48156 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48157
48158#line 48158 "ad_x86.cpp"
48159 }
48160}
48161
48162void rvmul16F_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48163 cbuf.set_insts_mark();
48164 // Start at oper_input_base() and count operands
48165 unsigned idx0 = 1;
48166 unsigned idx1 = 1; // dst
48167 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48168 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48169 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
48170 {
48171 MacroAssembler _masm(&cbuf);
48172
48173#line 5824 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48174
48175 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48176 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x01);
48177 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48178 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x02);
48179 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48180 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x03);
48181 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48182 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
48183 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48184 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
48185 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48186 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
48187 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48188 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
48189 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48190 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x2);
48191 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48192 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
48193 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48194 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
48195 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48196 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
48197 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48198 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x3);
48199 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48200 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x01);
48201 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48202 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x02);
48203 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48204 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0x03);
48205 __ vmulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48206
48207#line 48207 "ad_x86.cpp"
48208 }
48209}
48210
48211void rsmul2D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48212 cbuf.set_insts_mark();
48213 // Start at oper_input_base() and count operands
48214 unsigned idx0 = 1;
48215 unsigned idx1 = 1; // dst
48216 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48217 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48218 {
48219 MacroAssembler _masm(&cbuf);
48220
48221#line 5867 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48222
48223 __ mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48224 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
48225 __ mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48226
48227#line 48227 "ad_x86.cpp"
48228 }
48229}
48230
48231void rvmul2D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48232 cbuf.set_insts_mark();
48233 // Start at oper_input_base() and count operands
48234 unsigned idx0 = 1;
48235 unsigned idx1 = 1; // dst
48236 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48237 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48238 {
48239 MacroAssembler _masm(&cbuf);
48240
48241#line 5882 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48242
48243 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48244 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
48245 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48246
48247#line 48247 "ad_x86.cpp"
48248 }
48249}
48250
48251void rvmul4D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48252 cbuf.set_insts_mark();
48253 // Start at oper_input_base() and count operands
48254 unsigned idx0 = 1;
48255 unsigned idx1 = 1; // dst
48256 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48257 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48258 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
48259 {
48260 MacroAssembler _masm(&cbuf);
48261
48262#line 5901 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48263
48264 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48265 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
48266 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48267 __ vextractf128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48268 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48269 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48270 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48271
48272#line 48272 "ad_x86.cpp"
48273 }
48274}
48275
48276void rvmul8D_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48277 cbuf.set_insts_mark();
48278 // Start at oper_input_base() and count operands
48279 unsigned idx0 = 1;
48280 unsigned idx1 = 1; // dst
48281 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48282 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
48283 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
48284 {
48285 MacroAssembler _masm(&cbuf);
48286
48287#line 5932 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48288
48289 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
48290 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xE);
48291 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48292 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x1);
48293 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48294 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48295 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48296 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x2);
48297 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48298 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48299 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48300 __ vextractf32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0x3);
48301 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */);
48302 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, 0xE);
48303 __ vmulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
48304
48305#line 48305 "ad_x86.cpp"
48306 }
48307}
48308
48309void vadd4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48310 cbuf.set_insts_mark();
48311 // Start at oper_input_base() and count operands
48312 unsigned idx0 = 1;
48313 unsigned idx1 = 1; // dst
48314 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48315 {
48316 MacroAssembler _masm(&cbuf);
48317
48318#line 5961 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48319
48320 __ paddb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48321
48322#line 48322 "ad_x86.cpp"
48323 }
48324}
48325
48326void vadd4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48327 cbuf.set_insts_mark();
48328 // Start at oper_input_base() and count operands
48329 unsigned idx0 = 1;
48330 unsigned idx1 = 1; // src1
48331 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48332 {
48333 MacroAssembler _masm(&cbuf);
48334
48335#line 5971 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48336
48337 int vector_len = 0;
48338 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48339
48340#line 48340 "ad_x86.cpp"
48341 }
48342}
48343
48344void vadd4B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48345 cbuf.set_insts_mark();
48346 // Start at oper_input_base() and count operands
48347 unsigned idx0 = 2;
48348 unsigned idx1 = 2; // src
48349 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48350 {
48351 MacroAssembler _masm(&cbuf);
48352
48353#line 5983 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48354
48355 int vector_len = 0;
48356 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48357
48358#line 48358 "ad_x86.cpp"
48359 }
48360}
48361
48362void vadd4B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48363 cbuf.set_insts_mark();
48364 // Start at oper_input_base() and count operands
48365 unsigned idx0 = 2;
48366 unsigned idx1 = 2; // mem
48367 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48368 {
48369 MacroAssembler _masm(&cbuf);
48370
48371#line 5983 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48372
48373 int vector_len = 0;
48374 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48375
48376#line 48376 "ad_x86.cpp"
48377 }
48378}
48379
48380void vadd8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48381 cbuf.set_insts_mark();
48382 // Start at oper_input_base() and count operands
48383 unsigned idx0 = 1;
48384 unsigned idx1 = 1; // dst
48385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48386 {
48387 MacroAssembler _masm(&cbuf);
48388
48389#line 5994 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48390
48391 __ paddb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48392
48393#line 48393 "ad_x86.cpp"
48394 }
48395}
48396
48397void vadd8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48398 cbuf.set_insts_mark();
48399 // Start at oper_input_base() and count operands
48400 unsigned idx0 = 1;
48401 unsigned idx1 = 1; // src1
48402 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48403 {
48404 MacroAssembler _masm(&cbuf);
48405
48406#line 6004 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48407
48408 int vector_len = 0;
48409 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48410
48411#line 48411 "ad_x86.cpp"
48412 }
48413}
48414
48415void vadd8B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48416 cbuf.set_insts_mark();
48417 // Start at oper_input_base() and count operands
48418 unsigned idx0 = 2;
48419 unsigned idx1 = 2; // src
48420 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48421 {
48422 MacroAssembler _masm(&cbuf);
48423
48424#line 6016 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48425
48426 int vector_len = 0;
48427 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48428
48429#line 48429 "ad_x86.cpp"
48430 }
48431}
48432
48433void vadd8B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48434 cbuf.set_insts_mark();
48435 // Start at oper_input_base() and count operands
48436 unsigned idx0 = 2;
48437 unsigned idx1 = 2; // mem
48438 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48439 {
48440 MacroAssembler _masm(&cbuf);
48441
48442#line 6016 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48443
48444 int vector_len = 0;
48445 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48446
48447#line 48447 "ad_x86.cpp"
48448 }
48449}
48450
48451void vadd16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48452 cbuf.set_insts_mark();
48453 // Start at oper_input_base() and count operands
48454 unsigned idx0 = 1;
48455 unsigned idx1 = 1; // dst
48456 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48457 {
48458 MacroAssembler _masm(&cbuf);
48459
48460#line 6027 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48461
48462 __ paddb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48463
48464#line 48464 "ad_x86.cpp"
48465 }
48466}
48467
48468void vadd16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48469 cbuf.set_insts_mark();
48470 // Start at oper_input_base() and count operands
48471 unsigned idx0 = 1;
48472 unsigned idx1 = 1; // src1
48473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48474 {
48475 MacroAssembler _masm(&cbuf);
48476
48477#line 6037 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48478
48479 int vector_len = 0;
48480 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48481
48482#line 48482 "ad_x86.cpp"
48483 }
48484}
48485
48486void vadd16B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48487 cbuf.set_insts_mark();
48488 // Start at oper_input_base() and count operands
48489 unsigned idx0 = 2;
48490 unsigned idx1 = 2; // src
48491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48492 {
48493 MacroAssembler _masm(&cbuf);
48494
48495#line 6048 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48496
48497 int vector_len = 0;
48498 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48499
48500#line 48500 "ad_x86.cpp"
48501 }
48502}
48503
48504void vadd16B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48505 cbuf.set_insts_mark();
48506 // Start at oper_input_base() and count operands
48507 unsigned idx0 = 2;
48508 unsigned idx1 = 2; // mem
48509 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48510 {
48511 MacroAssembler _masm(&cbuf);
48512
48513#line 6048 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48514
48515 int vector_len = 0;
48516 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48517
48518#line 48518 "ad_x86.cpp"
48519 }
48520}
48521
48522void vadd32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48523 cbuf.set_insts_mark();
48524 // Start at oper_input_base() and count operands
48525 unsigned idx0 = 1;
48526 unsigned idx1 = 1; // src1
48527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48528 {
48529 MacroAssembler _masm(&cbuf);
48530
48531#line 6059 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48532
48533 int vector_len = 1;
48534 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48535
48536#line 48536 "ad_x86.cpp"
48537 }
48538}
48539
48540void vadd32B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48541 cbuf.set_insts_mark();
48542 // Start at oper_input_base() and count operands
48543 unsigned idx0 = 2;
48544 unsigned idx1 = 2; // src
48545 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48546 {
48547 MacroAssembler _masm(&cbuf);
48548
48549#line 6070 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48550
48551 int vector_len = 1;
48552 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48553
48554#line 48554 "ad_x86.cpp"
48555 }
48556}
48557
48558void vadd32B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48559 cbuf.set_insts_mark();
48560 // Start at oper_input_base() and count operands
48561 unsigned idx0 = 2;
48562 unsigned idx1 = 2; // mem
48563 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48564 {
48565 MacroAssembler _masm(&cbuf);
48566
48567#line 6070 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48568
48569 int vector_len = 1;
48570 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48571
48572#line 48572 "ad_x86.cpp"
48573 }
48574}
48575
48576void vadd64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48577 cbuf.set_insts_mark();
48578 // Start at oper_input_base() and count operands
48579 unsigned idx0 = 1;
48580 unsigned idx1 = 1; // src1
48581 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48582 {
48583 MacroAssembler _masm(&cbuf);
48584
48585#line 6081 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48586
48587 int vector_len = 2;
48588 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48589
48590#line 48590 "ad_x86.cpp"
48591 }
48592}
48593
48594void vadd64B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48595 cbuf.set_insts_mark();
48596 // Start at oper_input_base() and count operands
48597 unsigned idx0 = 2;
48598 unsigned idx1 = 2; // src
48599 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48600 {
48601 MacroAssembler _masm(&cbuf);
48602
48603#line 6092 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48604
48605 int vector_len = 2;
48606 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48607
48608#line 48608 "ad_x86.cpp"
48609 }
48610}
48611
48612void vadd64B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48613 cbuf.set_insts_mark();
48614 // Start at oper_input_base() and count operands
48615 unsigned idx0 = 2;
48616 unsigned idx1 = 2; // mem
48617 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48618 {
48619 MacroAssembler _masm(&cbuf);
48620
48621#line 6092 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48622
48623 int vector_len = 2;
48624 __ vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48625
48626#line 48626 "ad_x86.cpp"
48627 }
48628}
48629
48630void vadd2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48631 cbuf.set_insts_mark();
48632 // Start at oper_input_base() and count operands
48633 unsigned idx0 = 1;
48634 unsigned idx1 = 1; // dst
48635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48636 {
48637 MacroAssembler _masm(&cbuf);
48638
48639#line 6104 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48640
48641 __ paddw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48642
48643#line 48643 "ad_x86.cpp"
48644 }
48645}
48646
48647void vadd2S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48648 cbuf.set_insts_mark();
48649 // Start at oper_input_base() and count operands
48650 unsigned idx0 = 1;
48651 unsigned idx1 = 1; // src1
48652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48653 {
48654 MacroAssembler _masm(&cbuf);
48655
48656#line 6114 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48657
48658 int vector_len = 0;
48659 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48660
48661#line 48661 "ad_x86.cpp"
48662 }
48663}
48664
48665void vadd2S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48666 cbuf.set_insts_mark();
48667 // Start at oper_input_base() and count operands
48668 unsigned idx0 = 2;
48669 unsigned idx1 = 2; // src
48670 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48671 {
48672 MacroAssembler _masm(&cbuf);
48673
48674#line 6125 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48675
48676 int vector_len = 0;
48677 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48678
48679#line 48679 "ad_x86.cpp"
48680 }
48681}
48682
48683void vadd2S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48684 cbuf.set_insts_mark();
48685 // Start at oper_input_base() and count operands
48686 unsigned idx0 = 2;
48687 unsigned idx1 = 2; // mem
48688 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48689 {
48690 MacroAssembler _masm(&cbuf);
48691
48692#line 6125 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48693
48694 int vector_len = 0;
48695 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48696
48697#line 48697 "ad_x86.cpp"
48698 }
48699}
48700
48701void vadd4SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48702 cbuf.set_insts_mark();
48703 // Start at oper_input_base() and count operands
48704 unsigned idx0 = 1;
48705 unsigned idx1 = 1; // dst
48706 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48707 {
48708 MacroAssembler _masm(&cbuf);
48709
48710#line 6136 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48711
48712 __ paddw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48713
48714#line 48714 "ad_x86.cpp"
48715 }
48716}
48717
48718void vadd4S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48719 cbuf.set_insts_mark();
48720 // Start at oper_input_base() and count operands
48721 unsigned idx0 = 1;
48722 unsigned idx1 = 1; // src1
48723 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48724 {
48725 MacroAssembler _masm(&cbuf);
48726
48727#line 6146 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48728
48729 int vector_len = 0;
48730 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48731
48732#line 48732 "ad_x86.cpp"
48733 }
48734}
48735
48736void vadd4S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48737 cbuf.set_insts_mark();
48738 // Start at oper_input_base() and count operands
48739 unsigned idx0 = 2;
48740 unsigned idx1 = 2; // src
48741 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48742 {
48743 MacroAssembler _masm(&cbuf);
48744
48745#line 6157 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48746
48747 int vector_len = 0;
48748 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48749
48750#line 48750 "ad_x86.cpp"
48751 }
48752}
48753
48754void vadd4S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48755 cbuf.set_insts_mark();
48756 // Start at oper_input_base() and count operands
48757 unsigned idx0 = 2;
48758 unsigned idx1 = 2; // mem
48759 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48760 {
48761 MacroAssembler _masm(&cbuf);
48762
48763#line 6157 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48764
48765 int vector_len = 0;
48766 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48767
48768#line 48768 "ad_x86.cpp"
48769 }
48770}
48771
48772void vadd8SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48773 cbuf.set_insts_mark();
48774 // Start at oper_input_base() and count operands
48775 unsigned idx0 = 1;
48776 unsigned idx1 = 1; // dst
48777 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48778 {
48779 MacroAssembler _masm(&cbuf);
48780
48781#line 6168 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48782
48783 __ paddw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48784
48785#line 48785 "ad_x86.cpp"
48786 }
48787}
48788
48789void vadd8S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48790 cbuf.set_insts_mark();
48791 // Start at oper_input_base() and count operands
48792 unsigned idx0 = 1;
48793 unsigned idx1 = 1; // src1
48794 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48795 {
48796 MacroAssembler _masm(&cbuf);
48797
48798#line 6178 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48799
48800 int vector_len = 0;
48801 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48802
48803#line 48803 "ad_x86.cpp"
48804 }
48805}
48806
48807void vadd8S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48808 cbuf.set_insts_mark();
48809 // Start at oper_input_base() and count operands
48810 unsigned idx0 = 2;
48811 unsigned idx1 = 2; // src
48812 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48813 {
48814 MacroAssembler _masm(&cbuf);
48815
48816#line 6189 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48817
48818 int vector_len = 0;
48819 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48820
48821#line 48821 "ad_x86.cpp"
48822 }
48823}
48824
48825void vadd8S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48826 cbuf.set_insts_mark();
48827 // Start at oper_input_base() and count operands
48828 unsigned idx0 = 2;
48829 unsigned idx1 = 2; // mem
48830 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48831 {
48832 MacroAssembler _masm(&cbuf);
48833
48834#line 6189 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48835
48836 int vector_len = 0;
48837 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48838
48839#line 48839 "ad_x86.cpp"
48840 }
48841}
48842
48843void vadd16S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48844 cbuf.set_insts_mark();
48845 // Start at oper_input_base() and count operands
48846 unsigned idx0 = 1;
48847 unsigned idx1 = 1; // src1
48848 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48849 {
48850 MacroAssembler _masm(&cbuf);
48851
48852#line 6200 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48853
48854 int vector_len = 1;
48855 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48856
48857#line 48857 "ad_x86.cpp"
48858 }
48859}
48860
48861void vadd16S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48862 cbuf.set_insts_mark();
48863 // Start at oper_input_base() and count operands
48864 unsigned idx0 = 2;
48865 unsigned idx1 = 2; // src
48866 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48867 {
48868 MacroAssembler _masm(&cbuf);
48869
48870#line 6211 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48871
48872 int vector_len = 1;
48873 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48874
48875#line 48875 "ad_x86.cpp"
48876 }
48877}
48878
48879void vadd16S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48880 cbuf.set_insts_mark();
48881 // Start at oper_input_base() and count operands
48882 unsigned idx0 = 2;
48883 unsigned idx1 = 2; // mem
48884 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48885 {
48886 MacroAssembler _masm(&cbuf);
48887
48888#line 6211 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48889
48890 int vector_len = 1;
48891 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48892
48893#line 48893 "ad_x86.cpp"
48894 }
48895}
48896
48897void vadd32S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48898 cbuf.set_insts_mark();
48899 // Start at oper_input_base() and count operands
48900 unsigned idx0 = 1;
48901 unsigned idx1 = 1; // src1
48902 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48903 {
48904 MacroAssembler _masm(&cbuf);
48905
48906#line 6222 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48907
48908 int vector_len = 2;
48909 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48910
48911#line 48911 "ad_x86.cpp"
48912 }
48913}
48914
48915void vadd32S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48916 cbuf.set_insts_mark();
48917 // Start at oper_input_base() and count operands
48918 unsigned idx0 = 2;
48919 unsigned idx1 = 2; // src
48920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48921 {
48922 MacroAssembler _masm(&cbuf);
48923
48924#line 6233 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48925
48926 int vector_len = 2;
48927 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48928
48929#line 48929 "ad_x86.cpp"
48930 }
48931}
48932
48933void vadd32S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48934 cbuf.set_insts_mark();
48935 // Start at oper_input_base() and count operands
48936 unsigned idx0 = 2;
48937 unsigned idx1 = 2; // mem
48938 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48939 {
48940 MacroAssembler _masm(&cbuf);
48941
48942#line 6233 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48943
48944 int vector_len = 2;
48945 __ vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
48946
48947#line 48947 "ad_x86.cpp"
48948 }
48949}
48950
48951void vadd2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48952 cbuf.set_insts_mark();
48953 // Start at oper_input_base() and count operands
48954 unsigned idx0 = 1;
48955 unsigned idx1 = 1; // dst
48956 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
48957 {
48958 MacroAssembler _masm(&cbuf);
48959
48960#line 6245 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48961
48962 __ paddd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
48963
48964#line 48964 "ad_x86.cpp"
48965 }
48966}
48967
48968void vadd2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48969 cbuf.set_insts_mark();
48970 // Start at oper_input_base() and count operands
48971 unsigned idx0 = 1;
48972 unsigned idx1 = 1; // src1
48973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
48974 {
48975 MacroAssembler _masm(&cbuf);
48976
48977#line 6255 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48978
48979 int vector_len = 0;
48980 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
48981
48982#line 48982 "ad_x86.cpp"
48983 }
48984}
48985
48986void vadd2I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
48987 cbuf.set_insts_mark();
48988 // Start at oper_input_base() and count operands
48989 unsigned idx0 = 2;
48990 unsigned idx1 = 2; // src
48991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
48992 {
48993 MacroAssembler _masm(&cbuf);
48994
48995#line 6266 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
48996
48997 int vector_len = 0;
48998 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
48999
49000#line 49000 "ad_x86.cpp"
49001 }
49002}
49003
49004void vadd2I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49005 cbuf.set_insts_mark();
49006 // Start at oper_input_base() and count operands
49007 unsigned idx0 = 2;
49008 unsigned idx1 = 2; // mem
49009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49010 {
49011 MacroAssembler _masm(&cbuf);
49012
49013#line 6266 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49014
49015 int vector_len = 0;
49016 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49017
49018#line 49018 "ad_x86.cpp"
49019 }
49020}
49021
49022void vadd4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49023 cbuf.set_insts_mark();
49024 // Start at oper_input_base() and count operands
49025 unsigned idx0 = 1;
49026 unsigned idx1 = 1; // dst
49027 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49028 {
49029 MacroAssembler _masm(&cbuf);
49030
49031#line 6277 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49032
49033 __ paddd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49034
49035#line 49035 "ad_x86.cpp"
49036 }
49037}
49038
49039void vadd4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49040 cbuf.set_insts_mark();
49041 // Start at oper_input_base() and count operands
49042 unsigned idx0 = 1;
49043 unsigned idx1 = 1; // src1
49044 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49045 {
49046 MacroAssembler _masm(&cbuf);
49047
49048#line 6287 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49049
49050 int vector_len = 0;
49051 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49052
49053#line 49053 "ad_x86.cpp"
49054 }
49055}
49056
49057void vadd4I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49058 cbuf.set_insts_mark();
49059 // Start at oper_input_base() and count operands
49060 unsigned idx0 = 2;
49061 unsigned idx1 = 2; // src
49062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49063 {
49064 MacroAssembler _masm(&cbuf);
49065
49066#line 6298 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49067
49068 int vector_len = 0;
49069 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49070
49071#line 49071 "ad_x86.cpp"
49072 }
49073}
49074
49075void vadd4I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49076 cbuf.set_insts_mark();
49077 // Start at oper_input_base() and count operands
49078 unsigned idx0 = 2;
49079 unsigned idx1 = 2; // mem
49080 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49081 {
49082 MacroAssembler _masm(&cbuf);
49083
49084#line 6298 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49085
49086 int vector_len = 0;
49087 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49088
49089#line 49089 "ad_x86.cpp"
49090 }
49091}
49092
49093void vadd8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49094 cbuf.set_insts_mark();
49095 // Start at oper_input_base() and count operands
49096 unsigned idx0 = 1;
49097 unsigned idx1 = 1; // src1
49098 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49099 {
49100 MacroAssembler _masm(&cbuf);
49101
49102#line 6309 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49103
49104 int vector_len = 1;
49105 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49106
49107#line 49107 "ad_x86.cpp"
49108 }
49109}
49110
49111void vadd8I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49112 cbuf.set_insts_mark();
49113 // Start at oper_input_base() and count operands
49114 unsigned idx0 = 2;
49115 unsigned idx1 = 2; // src
49116 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49117 {
49118 MacroAssembler _masm(&cbuf);
49119
49120#line 6320 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49121
49122 int vector_len = 1;
49123 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49124
49125#line 49125 "ad_x86.cpp"
49126 }
49127}
49128
49129void vadd8I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49130 cbuf.set_insts_mark();
49131 // Start at oper_input_base() and count operands
49132 unsigned idx0 = 2;
49133 unsigned idx1 = 2; // mem
49134 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49135 {
49136 MacroAssembler _masm(&cbuf);
49137
49138#line 6320 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49139
49140 int vector_len = 1;
49141 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49142
49143#line 49143 "ad_x86.cpp"
49144 }
49145}
49146
49147void vadd16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49148 cbuf.set_insts_mark();
49149 // Start at oper_input_base() and count operands
49150 unsigned idx0 = 1;
49151 unsigned idx1 = 1; // src1
49152 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49153 {
49154 MacroAssembler _masm(&cbuf);
49155
49156#line 6331 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49157
49158 int vector_len = 2;
49159 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49160
49161#line 49161 "ad_x86.cpp"
49162 }
49163}
49164
49165void vadd16I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49166 cbuf.set_insts_mark();
49167 // Start at oper_input_base() and count operands
49168 unsigned idx0 = 2;
49169 unsigned idx1 = 2; // src
49170 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49171 {
49172 MacroAssembler _masm(&cbuf);
49173
49174#line 6342 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49175
49176 int vector_len = 2;
49177 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49178
49179#line 49179 "ad_x86.cpp"
49180 }
49181}
49182
49183void vadd16I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49184 cbuf.set_insts_mark();
49185 // Start at oper_input_base() and count operands
49186 unsigned idx0 = 2;
49187 unsigned idx1 = 2; // mem
49188 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49189 {
49190 MacroAssembler _masm(&cbuf);
49191
49192#line 6342 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49193
49194 int vector_len = 2;
49195 __ vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49196
49197#line 49197 "ad_x86.cpp"
49198 }
49199}
49200
49201void vadd2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49202 cbuf.set_insts_mark();
49203 // Start at oper_input_base() and count operands
49204 unsigned idx0 = 1;
49205 unsigned idx1 = 1; // dst
49206 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49207 {
49208 MacroAssembler _masm(&cbuf);
49209
49210#line 6354 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49211
49212 __ paddq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49213
49214#line 49214 "ad_x86.cpp"
49215 }
49216}
49217
49218void vadd2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49219 cbuf.set_insts_mark();
49220 // Start at oper_input_base() and count operands
49221 unsigned idx0 = 1;
49222 unsigned idx1 = 1; // src1
49223 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49224 {
49225 MacroAssembler _masm(&cbuf);
49226
49227#line 6364 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49228
49229 int vector_len = 0;
49230 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49231
49232#line 49232 "ad_x86.cpp"
49233 }
49234}
49235
49236void vadd2L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49237 cbuf.set_insts_mark();
49238 // Start at oper_input_base() and count operands
49239 unsigned idx0 = 2;
49240 unsigned idx1 = 2; // src
49241 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49242 {
49243 MacroAssembler _masm(&cbuf);
49244
49245#line 6375 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49246
49247 int vector_len = 0;
49248 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49249
49250#line 49250 "ad_x86.cpp"
49251 }
49252}
49253
49254void vadd2L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49255 cbuf.set_insts_mark();
49256 // Start at oper_input_base() and count operands
49257 unsigned idx0 = 2;
49258 unsigned idx1 = 2; // mem
49259 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49260 {
49261 MacroAssembler _masm(&cbuf);
49262
49263#line 6375 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49264
49265 int vector_len = 0;
49266 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49267
49268#line 49268 "ad_x86.cpp"
49269 }
49270}
49271
49272void vadd4L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49273 cbuf.set_insts_mark();
49274 // Start at oper_input_base() and count operands
49275 unsigned idx0 = 1;
49276 unsigned idx1 = 1; // src1
49277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49278 {
49279 MacroAssembler _masm(&cbuf);
49280
49281#line 6386 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49282
49283 int vector_len = 1;
49284 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49285
49286#line 49286 "ad_x86.cpp"
49287 }
49288}
49289
49290void vadd4L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49291 cbuf.set_insts_mark();
49292 // Start at oper_input_base() and count operands
49293 unsigned idx0 = 2;
49294 unsigned idx1 = 2; // src
49295 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49296 {
49297 MacroAssembler _masm(&cbuf);
49298
49299#line 6397 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49300
49301 int vector_len = 1;
49302 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49303
49304#line 49304 "ad_x86.cpp"
49305 }
49306}
49307
49308void vadd4L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49309 cbuf.set_insts_mark();
49310 // Start at oper_input_base() and count operands
49311 unsigned idx0 = 2;
49312 unsigned idx1 = 2; // mem
49313 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49314 {
49315 MacroAssembler _masm(&cbuf);
49316
49317#line 6397 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49318
49319 int vector_len = 1;
49320 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49321
49322#line 49322 "ad_x86.cpp"
49323 }
49324}
49325
49326void vadd8L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49327 cbuf.set_insts_mark();
49328 // Start at oper_input_base() and count operands
49329 unsigned idx0 = 1;
49330 unsigned idx1 = 1; // src1
49331 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49332 {
49333 MacroAssembler _masm(&cbuf);
49334
49335#line 6408 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49336
49337 int vector_len = 2;
49338 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49339
49340#line 49340 "ad_x86.cpp"
49341 }
49342}
49343
49344void vadd8L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49345 cbuf.set_insts_mark();
49346 // Start at oper_input_base() and count operands
49347 unsigned idx0 = 2;
49348 unsigned idx1 = 2; // src
49349 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49350 {
49351 MacroAssembler _masm(&cbuf);
49352
49353#line 6419 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49354
49355 int vector_len = 2;
49356 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49357
49358#line 49358 "ad_x86.cpp"
49359 }
49360}
49361
49362void vadd8L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49363 cbuf.set_insts_mark();
49364 // Start at oper_input_base() and count operands
49365 unsigned idx0 = 2;
49366 unsigned idx1 = 2; // mem
49367 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49368 {
49369 MacroAssembler _masm(&cbuf);
49370
49371#line 6419 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49372
49373 int vector_len = 2;
49374 __ vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49375
49376#line 49376 "ad_x86.cpp"
49377 }
49378}
49379
49380void vadd2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49381 cbuf.set_insts_mark();
49382 // Start at oper_input_base() and count operands
49383 unsigned idx0 = 1;
49384 unsigned idx1 = 1; // dst
49385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49386 {
49387 MacroAssembler _masm(&cbuf);
49388
49389#line 6431 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49390
49391 __ addps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49392
49393#line 49393 "ad_x86.cpp"
49394 }
49395}
49396
49397void vadd2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49398 cbuf.set_insts_mark();
49399 // Start at oper_input_base() and count operands
49400 unsigned idx0 = 1;
49401 unsigned idx1 = 1; // src1
49402 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49403 {
49404 MacroAssembler _masm(&cbuf);
49405
49406#line 6441 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49407
49408 int vector_len = 0;
49409 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49410
49411#line 49411 "ad_x86.cpp"
49412 }
49413}
49414
49415void vadd2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49416 cbuf.set_insts_mark();
49417 // Start at oper_input_base() and count operands
49418 unsigned idx0 = 2;
49419 unsigned idx1 = 2; // src
49420 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49421 {
49422 MacroAssembler _masm(&cbuf);
49423
49424#line 6452 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49425
49426 int vector_len = 0;
49427 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49428
49429#line 49429 "ad_x86.cpp"
49430 }
49431}
49432
49433void vadd2F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49434 cbuf.set_insts_mark();
49435 // Start at oper_input_base() and count operands
49436 unsigned idx0 = 2;
49437 unsigned idx1 = 2; // mem
49438 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49439 {
49440 MacroAssembler _masm(&cbuf);
49441
49442#line 6452 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49443
49444 int vector_len = 0;
49445 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49446
49447#line 49447 "ad_x86.cpp"
49448 }
49449}
49450
49451void vadd4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49452 cbuf.set_insts_mark();
49453 // Start at oper_input_base() and count operands
49454 unsigned idx0 = 1;
49455 unsigned idx1 = 1; // dst
49456 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49457 {
49458 MacroAssembler _masm(&cbuf);
49459
49460#line 6463 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49461
49462 __ addps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49463
49464#line 49464 "ad_x86.cpp"
49465 }
49466}
49467
49468void vadd4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49469 cbuf.set_insts_mark();
49470 // Start at oper_input_base() and count operands
49471 unsigned idx0 = 1;
49472 unsigned idx1 = 1; // src1
49473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49474 {
49475 MacroAssembler _masm(&cbuf);
49476
49477#line 6473 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49478
49479 int vector_len = 0;
49480 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49481
49482#line 49482 "ad_x86.cpp"
49483 }
49484}
49485
49486void vadd4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49487 cbuf.set_insts_mark();
49488 // Start at oper_input_base() and count operands
49489 unsigned idx0 = 2;
49490 unsigned idx1 = 2; // src
49491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49492 {
49493 MacroAssembler _masm(&cbuf);
49494
49495#line 6484 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49496
49497 int vector_len = 0;
49498 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49499
49500#line 49500 "ad_x86.cpp"
49501 }
49502}
49503
49504void vadd4F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49505 cbuf.set_insts_mark();
49506 // Start at oper_input_base() and count operands
49507 unsigned idx0 = 2;
49508 unsigned idx1 = 2; // mem
49509 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49510 {
49511 MacroAssembler _masm(&cbuf);
49512
49513#line 6484 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49514
49515 int vector_len = 0;
49516 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49517
49518#line 49518 "ad_x86.cpp"
49519 }
49520}
49521
49522void vadd8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49523 cbuf.set_insts_mark();
49524 // Start at oper_input_base() and count operands
49525 unsigned idx0 = 1;
49526 unsigned idx1 = 1; // src1
49527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49528 {
49529 MacroAssembler _masm(&cbuf);
49530
49531#line 6495 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49532
49533 int vector_len = 1;
49534 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49535
49536#line 49536 "ad_x86.cpp"
49537 }
49538}
49539
49540void vadd8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49541 cbuf.set_insts_mark();
49542 // Start at oper_input_base() and count operands
49543 unsigned idx0 = 2;
49544 unsigned idx1 = 2; // src
49545 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49546 {
49547 MacroAssembler _masm(&cbuf);
49548
49549#line 6506 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49550
49551 int vector_len = 1;
49552 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49553
49554#line 49554 "ad_x86.cpp"
49555 }
49556}
49557
49558void vadd8F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49559 cbuf.set_insts_mark();
49560 // Start at oper_input_base() and count operands
49561 unsigned idx0 = 2;
49562 unsigned idx1 = 2; // mem
49563 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49564 {
49565 MacroAssembler _masm(&cbuf);
49566
49567#line 6506 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49568
49569 int vector_len = 1;
49570 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49571
49572#line 49572 "ad_x86.cpp"
49573 }
49574}
49575
49576void vadd16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49577 cbuf.set_insts_mark();
49578 // Start at oper_input_base() and count operands
49579 unsigned idx0 = 1;
49580 unsigned idx1 = 1; // src1
49581 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49582 {
49583 MacroAssembler _masm(&cbuf);
49584
49585#line 6517 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49586
49587 int vector_len = 2;
49588 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49589
49590#line 49590 "ad_x86.cpp"
49591 }
49592}
49593
49594void vadd16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49595 cbuf.set_insts_mark();
49596 // Start at oper_input_base() and count operands
49597 unsigned idx0 = 2;
49598 unsigned idx1 = 2; // src
49599 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49600 {
49601 MacroAssembler _masm(&cbuf);
49602
49603#line 6528 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49604
49605 int vector_len = 2;
49606 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49607
49608#line 49608 "ad_x86.cpp"
49609 }
49610}
49611
49612void vadd16F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49613 cbuf.set_insts_mark();
49614 // Start at oper_input_base() and count operands
49615 unsigned idx0 = 2;
49616 unsigned idx1 = 2; // mem
49617 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49618 {
49619 MacroAssembler _masm(&cbuf);
49620
49621#line 6528 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49622
49623 int vector_len = 2;
49624 __ vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49625
49626#line 49626 "ad_x86.cpp"
49627 }
49628}
49629
49630void vadd2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49631 cbuf.set_insts_mark();
49632 // Start at oper_input_base() and count operands
49633 unsigned idx0 = 1;
49634 unsigned idx1 = 1; // dst
49635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49636 {
49637 MacroAssembler _masm(&cbuf);
49638
49639#line 6540 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49640
49641 __ addpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49642
49643#line 49643 "ad_x86.cpp"
49644 }
49645}
49646
49647void vadd2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49648 cbuf.set_insts_mark();
49649 // Start at oper_input_base() and count operands
49650 unsigned idx0 = 1;
49651 unsigned idx1 = 1; // src1
49652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49653 {
49654 MacroAssembler _masm(&cbuf);
49655
49656#line 6550 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49657
49658 int vector_len = 0;
49659 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49660
49661#line 49661 "ad_x86.cpp"
49662 }
49663}
49664
49665void vadd2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49666 cbuf.set_insts_mark();
49667 // Start at oper_input_base() and count operands
49668 unsigned idx0 = 2;
49669 unsigned idx1 = 2; // src
49670 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49671 {
49672 MacroAssembler _masm(&cbuf);
49673
49674#line 6561 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49675
49676 int vector_len = 0;
49677 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49678
49679#line 49679 "ad_x86.cpp"
49680 }
49681}
49682
49683void vadd2D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49684 cbuf.set_insts_mark();
49685 // Start at oper_input_base() and count operands
49686 unsigned idx0 = 2;
49687 unsigned idx1 = 2; // mem
49688 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49689 {
49690 MacroAssembler _masm(&cbuf);
49691
49692#line 6561 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49693
49694 int vector_len = 0;
49695 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49696
49697#line 49697 "ad_x86.cpp"
49698 }
49699}
49700
49701void vadd4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49702 cbuf.set_insts_mark();
49703 // Start at oper_input_base() and count operands
49704 unsigned idx0 = 1;
49705 unsigned idx1 = 1; // src1
49706 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49707 {
49708 MacroAssembler _masm(&cbuf);
49709
49710#line 6572 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49711
49712 int vector_len = 1;
49713 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49714
49715#line 49715 "ad_x86.cpp"
49716 }
49717}
49718
49719void vadd4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49720 cbuf.set_insts_mark();
49721 // Start at oper_input_base() and count operands
49722 unsigned idx0 = 2;
49723 unsigned idx1 = 2; // src
49724 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49725 {
49726 MacroAssembler _masm(&cbuf);
49727
49728#line 6583 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49729
49730 int vector_len = 1;
49731 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49732
49733#line 49733 "ad_x86.cpp"
49734 }
49735}
49736
49737void vadd4D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49738 cbuf.set_insts_mark();
49739 // Start at oper_input_base() and count operands
49740 unsigned idx0 = 2;
49741 unsigned idx1 = 2; // mem
49742 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49743 {
49744 MacroAssembler _masm(&cbuf);
49745
49746#line 6583 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49747
49748 int vector_len = 1;
49749 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49750
49751#line 49751 "ad_x86.cpp"
49752 }
49753}
49754
49755void vadd8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49756 cbuf.set_insts_mark();
49757 // Start at oper_input_base() and count operands
49758 unsigned idx0 = 1;
49759 unsigned idx1 = 1; // src1
49760 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49761 {
49762 MacroAssembler _masm(&cbuf);
49763
49764#line 6594 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49765
49766 int vector_len = 2;
49767 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49768
49769#line 49769 "ad_x86.cpp"
49770 }
49771}
49772
49773void vadd8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49774 cbuf.set_insts_mark();
49775 // Start at oper_input_base() and count operands
49776 unsigned idx0 = 2;
49777 unsigned idx1 = 2; // src
49778 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49779 {
49780 MacroAssembler _masm(&cbuf);
49781
49782#line 6605 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49783
49784 int vector_len = 2;
49785 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49786
49787#line 49787 "ad_x86.cpp"
49788 }
49789}
49790
49791void vadd8D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49792 cbuf.set_insts_mark();
49793 // Start at oper_input_base() and count operands
49794 unsigned idx0 = 2;
49795 unsigned idx1 = 2; // mem
49796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49797 {
49798 MacroAssembler _masm(&cbuf);
49799
49800#line 6605 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49801
49802 int vector_len = 2;
49803 __ vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
49804
49805#line 49805 "ad_x86.cpp"
49806 }
49807}
49808
49809void vsub4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49810 cbuf.set_insts_mark();
49811 // Start at oper_input_base() and count operands
49812 unsigned idx0 = 1;
49813 unsigned idx1 = 1; // dst
49814 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49815 {
49816 MacroAssembler _masm(&cbuf);
49817
49818#line 6619 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49819
49820 __ psubb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49821
49822#line 49822 "ad_x86.cpp"
49823 }
49824}
49825
49826void vsub4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49827 cbuf.set_insts_mark();
49828 // Start at oper_input_base() and count operands
49829 unsigned idx0 = 1;
49830 unsigned idx1 = 1; // src1
49831 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49832 {
49833 MacroAssembler _masm(&cbuf);
49834
49835#line 6629 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49836
49837 int vector_len = 0;
49838 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49839
49840#line 49840 "ad_x86.cpp"
49841 }
49842}
49843
49844void vsub4B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49845 cbuf.set_insts_mark();
49846 // Start at oper_input_base() and count operands
49847 unsigned idx0 = 2;
49848 unsigned idx1 = 2; // src
49849 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49850 {
49851 MacroAssembler _masm(&cbuf);
49852
49853#line 6640 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49854
49855 int vector_len = 0;
49856 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49857
49858#line 49858 "ad_x86.cpp"
49859 }
49860}
49861
49862void vsub8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49863 cbuf.set_insts_mark();
49864 // Start at oper_input_base() and count operands
49865 unsigned idx0 = 1;
49866 unsigned idx1 = 1; // dst
49867 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49868 {
49869 MacroAssembler _masm(&cbuf);
49870
49871#line 6651 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49872
49873 __ psubb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49874
49875#line 49875 "ad_x86.cpp"
49876 }
49877}
49878
49879void vsub8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49880 cbuf.set_insts_mark();
49881 // Start at oper_input_base() and count operands
49882 unsigned idx0 = 1;
49883 unsigned idx1 = 1; // src1
49884 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49885 {
49886 MacroAssembler _masm(&cbuf);
49887
49888#line 6661 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49889
49890 int vector_len = 0;
49891 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49892
49893#line 49893 "ad_x86.cpp"
49894 }
49895}
49896
49897void vsub8B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49898 cbuf.set_insts_mark();
49899 // Start at oper_input_base() and count operands
49900 unsigned idx0 = 2;
49901 unsigned idx1 = 2; // src
49902 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49903 {
49904 MacroAssembler _masm(&cbuf);
49905
49906#line 6672 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49907
49908 int vector_len = 0;
49909 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49910
49911#line 49911 "ad_x86.cpp"
49912 }
49913}
49914
49915void vsub16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49916 cbuf.set_insts_mark();
49917 // Start at oper_input_base() and count operands
49918 unsigned idx0 = 1;
49919 unsigned idx1 = 1; // dst
49920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
49921 {
49922 MacroAssembler _masm(&cbuf);
49923
49924#line 6683 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49925
49926 __ psubb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
49927
49928#line 49928 "ad_x86.cpp"
49929 }
49930}
49931
49932void vsub16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49933 cbuf.set_insts_mark();
49934 // Start at oper_input_base() and count operands
49935 unsigned idx0 = 1;
49936 unsigned idx1 = 1; // src1
49937 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49938 {
49939 MacroAssembler _masm(&cbuf);
49940
49941#line 6693 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49942
49943 int vector_len = 0;
49944 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49945
49946#line 49946 "ad_x86.cpp"
49947 }
49948}
49949
49950void vsub16B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49951 cbuf.set_insts_mark();
49952 // Start at oper_input_base() and count operands
49953 unsigned idx0 = 2;
49954 unsigned idx1 = 2; // src
49955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49956 {
49957 MacroAssembler _masm(&cbuf);
49958
49959#line 6704 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49960
49961 int vector_len = 0;
49962 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49963
49964#line 49964 "ad_x86.cpp"
49965 }
49966}
49967
49968void vsub32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49969 cbuf.set_insts_mark();
49970 // Start at oper_input_base() and count operands
49971 unsigned idx0 = 1;
49972 unsigned idx1 = 1; // src1
49973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
49974 {
49975 MacroAssembler _masm(&cbuf);
49976
49977#line 6715 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49978
49979 int vector_len = 1;
49980 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
49981
49982#line 49982 "ad_x86.cpp"
49983 }
49984}
49985
49986void vsub32B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
49987 cbuf.set_insts_mark();
49988 // Start at oper_input_base() and count operands
49989 unsigned idx0 = 2;
49990 unsigned idx1 = 2; // src
49991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
49992 {
49993 MacroAssembler _masm(&cbuf);
49994
49995#line 6726 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
49996
49997 int vector_len = 1;
49998 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
49999
50000#line 50000 "ad_x86.cpp"
50001 }
50002}
50003
50004void vsub64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50005 cbuf.set_insts_mark();
50006 // Start at oper_input_base() and count operands
50007 unsigned idx0 = 1;
50008 unsigned idx1 = 1; // src1
50009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50010 {
50011 MacroAssembler _masm(&cbuf);
50012
50013#line 6737 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50014
50015 int vector_len = 2;
50016 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50017
50018#line 50018 "ad_x86.cpp"
50019 }
50020}
50021
50022void vsub64B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50023 cbuf.set_insts_mark();
50024 // Start at oper_input_base() and count operands
50025 unsigned idx0 = 2;
50026 unsigned idx1 = 2; // src
50027 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50028 {
50029 MacroAssembler _masm(&cbuf);
50030
50031#line 6748 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50032
50033 int vector_len = 2;
50034 __ vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50035
50036#line 50036 "ad_x86.cpp"
50037 }
50038}
50039
50040void vsub2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50041 cbuf.set_insts_mark();
50042 // Start at oper_input_base() and count operands
50043 unsigned idx0 = 1;
50044 unsigned idx1 = 1; // dst
50045 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50046 {
50047 MacroAssembler _masm(&cbuf);
50048
50049#line 6760 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50050
50051 __ psubw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50052
50053#line 50053 "ad_x86.cpp"
50054 }
50055}
50056
50057void vsub2S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50058 cbuf.set_insts_mark();
50059 // Start at oper_input_base() and count operands
50060 unsigned idx0 = 1;
50061 unsigned idx1 = 1; // src1
50062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50063 {
50064 MacroAssembler _masm(&cbuf);
50065
50066#line 6770 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50067
50068 int vector_len = 0;
50069 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50070
50071#line 50071 "ad_x86.cpp"
50072 }
50073}
50074
50075void vsub2S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50076 cbuf.set_insts_mark();
50077 // Start at oper_input_base() and count operands
50078 unsigned idx0 = 2;
50079 unsigned idx1 = 2; // src
50080 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50081 {
50082 MacroAssembler _masm(&cbuf);
50083
50084#line 6781 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50085
50086 int vector_len = 0;
50087 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50088
50089#line 50089 "ad_x86.cpp"
50090 }
50091}
50092
50093void vsub4SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50094 cbuf.set_insts_mark();
50095 // Start at oper_input_base() and count operands
50096 unsigned idx0 = 1;
50097 unsigned idx1 = 1; // dst
50098 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50099 {
50100 MacroAssembler _masm(&cbuf);
50101
50102#line 6792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50103
50104 __ psubw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50105
50106#line 50106 "ad_x86.cpp"
50107 }
50108}
50109
50110void vsub4S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50111 cbuf.set_insts_mark();
50112 // Start at oper_input_base() and count operands
50113 unsigned idx0 = 1;
50114 unsigned idx1 = 1; // src1
50115 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50116 {
50117 MacroAssembler _masm(&cbuf);
50118
50119#line 6802 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50120
50121 int vector_len = 0;
50122 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50123
50124#line 50124 "ad_x86.cpp"
50125 }
50126}
50127
50128void vsub4S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50129 cbuf.set_insts_mark();
50130 // Start at oper_input_base() and count operands
50131 unsigned idx0 = 2;
50132 unsigned idx1 = 2; // src
50133 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50134 {
50135 MacroAssembler _masm(&cbuf);
50136
50137#line 6813 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50138
50139 int vector_len = 0;
50140 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50141
50142#line 50142 "ad_x86.cpp"
50143 }
50144}
50145
50146void vsub8SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50147 cbuf.set_insts_mark();
50148 // Start at oper_input_base() and count operands
50149 unsigned idx0 = 1;
50150 unsigned idx1 = 1; // dst
50151 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50152 {
50153 MacroAssembler _masm(&cbuf);
50154
50155#line 6824 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50156
50157 __ psubw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50158
50159#line 50159 "ad_x86.cpp"
50160 }
50161}
50162
50163void vsub8S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50164 cbuf.set_insts_mark();
50165 // Start at oper_input_base() and count operands
50166 unsigned idx0 = 1;
50167 unsigned idx1 = 1; // src1
50168 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50169 {
50170 MacroAssembler _masm(&cbuf);
50171
50172#line 6834 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50173
50174 int vector_len = 0;
50175 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50176
50177#line 50177 "ad_x86.cpp"
50178 }
50179}
50180
50181void vsub8S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50182 cbuf.set_insts_mark();
50183 // Start at oper_input_base() and count operands
50184 unsigned idx0 = 2;
50185 unsigned idx1 = 2; // src
50186 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50187 {
50188 MacroAssembler _masm(&cbuf);
50189
50190#line 6845 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50191
50192 int vector_len = 0;
50193 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50194
50195#line 50195 "ad_x86.cpp"
50196 }
50197}
50198
50199void vsub16S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50200 cbuf.set_insts_mark();
50201 // Start at oper_input_base() and count operands
50202 unsigned idx0 = 1;
50203 unsigned idx1 = 1; // src1
50204 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50205 {
50206 MacroAssembler _masm(&cbuf);
50207
50208#line 6856 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50209
50210 int vector_len = 1;
50211 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50212
50213#line 50213 "ad_x86.cpp"
50214 }
50215}
50216
50217void vsub16S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50218 cbuf.set_insts_mark();
50219 // Start at oper_input_base() and count operands
50220 unsigned idx0 = 2;
50221 unsigned idx1 = 2; // src
50222 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50223 {
50224 MacroAssembler _masm(&cbuf);
50225
50226#line 6867 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50227
50228 int vector_len = 1;
50229 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50230
50231#line 50231 "ad_x86.cpp"
50232 }
50233}
50234
50235void vsub32S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50236 cbuf.set_insts_mark();
50237 // Start at oper_input_base() and count operands
50238 unsigned idx0 = 1;
50239 unsigned idx1 = 1; // src1
50240 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50241 {
50242 MacroAssembler _masm(&cbuf);
50243
50244#line 6878 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50245
50246 int vector_len = 2;
50247 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50248
50249#line 50249 "ad_x86.cpp"
50250 }
50251}
50252
50253void vsub32S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50254 cbuf.set_insts_mark();
50255 // Start at oper_input_base() and count operands
50256 unsigned idx0 = 2;
50257 unsigned idx1 = 2; // src
50258 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50259 {
50260 MacroAssembler _masm(&cbuf);
50261
50262#line 6889 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50263
50264 int vector_len = 2;
50265 __ vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50266
50267#line 50267 "ad_x86.cpp"
50268 }
50269}
50270
50271void vsub2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50272 cbuf.set_insts_mark();
50273 // Start at oper_input_base() and count operands
50274 unsigned idx0 = 1;
50275 unsigned idx1 = 1; // dst
50276 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50277 {
50278 MacroAssembler _masm(&cbuf);
50279
50280#line 6901 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50281
50282 __ psubd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50283
50284#line 50284 "ad_x86.cpp"
50285 }
50286}
50287
50288void vsub2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50289 cbuf.set_insts_mark();
50290 // Start at oper_input_base() and count operands
50291 unsigned idx0 = 1;
50292 unsigned idx1 = 1; // src1
50293 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50294 {
50295 MacroAssembler _masm(&cbuf);
50296
50297#line 6911 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50298
50299 int vector_len = 0;
50300 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50301
50302#line 50302 "ad_x86.cpp"
50303 }
50304}
50305
50306void vsub2I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50307 cbuf.set_insts_mark();
50308 // Start at oper_input_base() and count operands
50309 unsigned idx0 = 2;
50310 unsigned idx1 = 2; // src
50311 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50312 {
50313 MacroAssembler _masm(&cbuf);
50314
50315#line 6922 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50316
50317 int vector_len = 0;
50318 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50319
50320#line 50320 "ad_x86.cpp"
50321 }
50322}
50323
50324void vsub4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50325 cbuf.set_insts_mark();
50326 // Start at oper_input_base() and count operands
50327 unsigned idx0 = 1;
50328 unsigned idx1 = 1; // dst
50329 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50330 {
50331 MacroAssembler _masm(&cbuf);
50332
50333#line 6933 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50334
50335 __ psubd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50336
50337#line 50337 "ad_x86.cpp"
50338 }
50339}
50340
50341void vsub4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50342 cbuf.set_insts_mark();
50343 // Start at oper_input_base() and count operands
50344 unsigned idx0 = 1;
50345 unsigned idx1 = 1; // src1
50346 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50347 {
50348 MacroAssembler _masm(&cbuf);
50349
50350#line 6943 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50351
50352 int vector_len = 0;
50353 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50354
50355#line 50355 "ad_x86.cpp"
50356 }
50357}
50358
50359void vsub4I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50360 cbuf.set_insts_mark();
50361 // Start at oper_input_base() and count operands
50362 unsigned idx0 = 2;
50363 unsigned idx1 = 2; // src
50364 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50365 {
50366 MacroAssembler _masm(&cbuf);
50367
50368#line 6954 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50369
50370 int vector_len = 0;
50371 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50372
50373#line 50373 "ad_x86.cpp"
50374 }
50375}
50376
50377void vsub8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50378 cbuf.set_insts_mark();
50379 // Start at oper_input_base() and count operands
50380 unsigned idx0 = 1;
50381 unsigned idx1 = 1; // src1
50382 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50383 {
50384 MacroAssembler _masm(&cbuf);
50385
50386#line 6965 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50387
50388 int vector_len = 1;
50389 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50390
50391#line 50391 "ad_x86.cpp"
50392 }
50393}
50394
50395void vsub8I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50396 cbuf.set_insts_mark();
50397 // Start at oper_input_base() and count operands
50398 unsigned idx0 = 2;
50399 unsigned idx1 = 2; // src
50400 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50401 {
50402 MacroAssembler _masm(&cbuf);
50403
50404#line 6976 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50405
50406 int vector_len = 1;
50407 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50408
50409#line 50409 "ad_x86.cpp"
50410 }
50411}
50412
50413void vsub16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50414 cbuf.set_insts_mark();
50415 // Start at oper_input_base() and count operands
50416 unsigned idx0 = 1;
50417 unsigned idx1 = 1; // src1
50418 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50419 {
50420 MacroAssembler _masm(&cbuf);
50421
50422#line 6987 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50423
50424 int vector_len = 2;
50425 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50426
50427#line 50427 "ad_x86.cpp"
50428 }
50429}
50430
50431void vsub16I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50432 cbuf.set_insts_mark();
50433 // Start at oper_input_base() and count operands
50434 unsigned idx0 = 2;
50435 unsigned idx1 = 2; // src
50436 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50437 {
50438 MacroAssembler _masm(&cbuf);
50439
50440#line 6998 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50441
50442 int vector_len = 2;
50443 __ vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50444
50445#line 50445 "ad_x86.cpp"
50446 }
50447}
50448
50449void vsub2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50450 cbuf.set_insts_mark();
50451 // Start at oper_input_base() and count operands
50452 unsigned idx0 = 1;
50453 unsigned idx1 = 1; // dst
50454 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50455 {
50456 MacroAssembler _masm(&cbuf);
50457
50458#line 7010 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50459
50460 __ psubq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50461
50462#line 50462 "ad_x86.cpp"
50463 }
50464}
50465
50466void vsub2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50467 cbuf.set_insts_mark();
50468 // Start at oper_input_base() and count operands
50469 unsigned idx0 = 1;
50470 unsigned idx1 = 1; // src1
50471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50472 {
50473 MacroAssembler _masm(&cbuf);
50474
50475#line 7020 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50476
50477 int vector_len = 0;
50478 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50479
50480#line 50480 "ad_x86.cpp"
50481 }
50482}
50483
50484void vsub2L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50485 cbuf.set_insts_mark();
50486 // Start at oper_input_base() and count operands
50487 unsigned idx0 = 2;
50488 unsigned idx1 = 2; // src
50489 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50490 {
50491 MacroAssembler _masm(&cbuf);
50492
50493#line 7031 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50494
50495 int vector_len = 0;
50496 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50497
50498#line 50498 "ad_x86.cpp"
50499 }
50500}
50501
50502void vsub4L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50503 cbuf.set_insts_mark();
50504 // Start at oper_input_base() and count operands
50505 unsigned idx0 = 1;
50506 unsigned idx1 = 1; // src1
50507 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50508 {
50509 MacroAssembler _masm(&cbuf);
50510
50511#line 7042 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50512
50513 int vector_len = 1;
50514 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50515
50516#line 50516 "ad_x86.cpp"
50517 }
50518}
50519
50520void vsub4L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50521 cbuf.set_insts_mark();
50522 // Start at oper_input_base() and count operands
50523 unsigned idx0 = 2;
50524 unsigned idx1 = 2; // src
50525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50526 {
50527 MacroAssembler _masm(&cbuf);
50528
50529#line 7053 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50530
50531 int vector_len = 1;
50532 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50533
50534#line 50534 "ad_x86.cpp"
50535 }
50536}
50537
50538void vsub8L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50539 cbuf.set_insts_mark();
50540 // Start at oper_input_base() and count operands
50541 unsigned idx0 = 1;
50542 unsigned idx1 = 1; // src1
50543 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50544 {
50545 MacroAssembler _masm(&cbuf);
50546
50547#line 7064 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50548
50549 int vector_len = 2;
50550 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50551
50552#line 50552 "ad_x86.cpp"
50553 }
50554}
50555
50556void vsub8L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50557 cbuf.set_insts_mark();
50558 // Start at oper_input_base() and count operands
50559 unsigned idx0 = 2;
50560 unsigned idx1 = 2; // src
50561 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50562 {
50563 MacroAssembler _masm(&cbuf);
50564
50565#line 7075 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50566
50567 int vector_len = 2;
50568 __ vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50569
50570#line 50570 "ad_x86.cpp"
50571 }
50572}
50573
50574void vsub2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50575 cbuf.set_insts_mark();
50576 // Start at oper_input_base() and count operands
50577 unsigned idx0 = 1;
50578 unsigned idx1 = 1; // dst
50579 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50580 {
50581 MacroAssembler _masm(&cbuf);
50582
50583#line 7087 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50584
50585 __ subps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50586
50587#line 50587 "ad_x86.cpp"
50588 }
50589}
50590
50591void vsub2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50592 cbuf.set_insts_mark();
50593 // Start at oper_input_base() and count operands
50594 unsigned idx0 = 1;
50595 unsigned idx1 = 1; // src1
50596 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50597 {
50598 MacroAssembler _masm(&cbuf);
50599
50600#line 7097 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50601
50602 int vector_len = 0;
50603 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50604
50605#line 50605 "ad_x86.cpp"
50606 }
50607}
50608
50609void vsub2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50610 cbuf.set_insts_mark();
50611 // Start at oper_input_base() and count operands
50612 unsigned idx0 = 2;
50613 unsigned idx1 = 2; // src
50614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50615 {
50616 MacroAssembler _masm(&cbuf);
50617
50618#line 7108 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50619
50620 int vector_len = 0;
50621 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50622
50623#line 50623 "ad_x86.cpp"
50624 }
50625}
50626
50627void vsub4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50628 cbuf.set_insts_mark();
50629 // Start at oper_input_base() and count operands
50630 unsigned idx0 = 1;
50631 unsigned idx1 = 1; // dst
50632 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50633 {
50634 MacroAssembler _masm(&cbuf);
50635
50636#line 7119 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50637
50638 __ subps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50639
50640#line 50640 "ad_x86.cpp"
50641 }
50642}
50643
50644void vsub4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50645 cbuf.set_insts_mark();
50646 // Start at oper_input_base() and count operands
50647 unsigned idx0 = 1;
50648 unsigned idx1 = 1; // src1
50649 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50650 {
50651 MacroAssembler _masm(&cbuf);
50652
50653#line 7129 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50654
50655 int vector_len = 0;
50656 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50657
50658#line 50658 "ad_x86.cpp"
50659 }
50660}
50661
50662void vsub4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50663 cbuf.set_insts_mark();
50664 // Start at oper_input_base() and count operands
50665 unsigned idx0 = 2;
50666 unsigned idx1 = 2; // src
50667 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50668 {
50669 MacroAssembler _masm(&cbuf);
50670
50671#line 7140 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50672
50673 int vector_len = 0;
50674 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50675
50676#line 50676 "ad_x86.cpp"
50677 }
50678}
50679
50680void vsub8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50681 cbuf.set_insts_mark();
50682 // Start at oper_input_base() and count operands
50683 unsigned idx0 = 1;
50684 unsigned idx1 = 1; // src1
50685 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50686 {
50687 MacroAssembler _masm(&cbuf);
50688
50689#line 7151 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50690
50691 int vector_len = 1;
50692 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50693
50694#line 50694 "ad_x86.cpp"
50695 }
50696}
50697
50698void vsub8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50699 cbuf.set_insts_mark();
50700 // Start at oper_input_base() and count operands
50701 unsigned idx0 = 2;
50702 unsigned idx1 = 2; // src
50703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50704 {
50705 MacroAssembler _masm(&cbuf);
50706
50707#line 7162 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50708
50709 int vector_len = 1;
50710 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50711
50712#line 50712 "ad_x86.cpp"
50713 }
50714}
50715
50716void vsub16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50717 cbuf.set_insts_mark();
50718 // Start at oper_input_base() and count operands
50719 unsigned idx0 = 1;
50720 unsigned idx1 = 1; // src1
50721 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50722 {
50723 MacroAssembler _masm(&cbuf);
50724
50725#line 7173 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50726
50727 int vector_len = 2;
50728 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50729
50730#line 50730 "ad_x86.cpp"
50731 }
50732}
50733
50734void vsub16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50735 cbuf.set_insts_mark();
50736 // Start at oper_input_base() and count operands
50737 unsigned idx0 = 2;
50738 unsigned idx1 = 2; // src
50739 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50740 {
50741 MacroAssembler _masm(&cbuf);
50742
50743#line 7184 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50744
50745 int vector_len = 2;
50746 __ vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50747
50748#line 50748 "ad_x86.cpp"
50749 }
50750}
50751
50752void vsub2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50753 cbuf.set_insts_mark();
50754 // Start at oper_input_base() and count operands
50755 unsigned idx0 = 1;
50756 unsigned idx1 = 1; // dst
50757 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
50758 {
50759 MacroAssembler _masm(&cbuf);
50760
50761#line 7196 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50762
50763 __ subpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
50764
50765#line 50765 "ad_x86.cpp"
50766 }
50767}
50768
50769void vsub2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50770 cbuf.set_insts_mark();
50771 // Start at oper_input_base() and count operands
50772 unsigned idx0 = 1;
50773 unsigned idx1 = 1; // src1
50774 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50775 {
50776 MacroAssembler _masm(&cbuf);
50777
50778#line 7206 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50779
50780 int vector_len = 0;
50781 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50782
50783#line 50783 "ad_x86.cpp"
50784 }
50785}
50786
50787void vsub2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50788 cbuf.set_insts_mark();
50789 // Start at oper_input_base() and count operands
50790 unsigned idx0 = 2;
50791 unsigned idx1 = 2; // src
50792 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50793 {
50794 MacroAssembler _masm(&cbuf);
50795
50796#line 7217 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50797
50798 int vector_len = 0;
50799 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50800
50801#line 50801 "ad_x86.cpp"
50802 }
50803}
50804
50805void vsub4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50806 cbuf.set_insts_mark();
50807 // Start at oper_input_base() and count operands
50808 unsigned idx0 = 1;
50809 unsigned idx1 = 1; // src1
50810 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50811 {
50812 MacroAssembler _masm(&cbuf);
50813
50814#line 7228 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50815
50816 int vector_len = 1;
50817 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50818
50819#line 50819 "ad_x86.cpp"
50820 }
50821}
50822
50823void vsub4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50824 cbuf.set_insts_mark();
50825 // Start at oper_input_base() and count operands
50826 unsigned idx0 = 2;
50827 unsigned idx1 = 2; // src
50828 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50829 {
50830 MacroAssembler _masm(&cbuf);
50831
50832#line 7239 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50833
50834 int vector_len = 1;
50835 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50836
50837#line 50837 "ad_x86.cpp"
50838 }
50839}
50840
50841void vsub8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50842 cbuf.set_insts_mark();
50843 // Start at oper_input_base() and count operands
50844 unsigned idx0 = 1;
50845 unsigned idx1 = 1; // src1
50846 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50847 {
50848 MacroAssembler _masm(&cbuf);
50849
50850#line 7250 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50851
50852 int vector_len = 2;
50853 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50854
50855#line 50855 "ad_x86.cpp"
50856 }
50857}
50858
50859void vsub8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50860 cbuf.set_insts_mark();
50861 // Start at oper_input_base() and count operands
50862 unsigned idx0 = 2;
50863 unsigned idx1 = 2; // src
50864 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
50865 {
50866 MacroAssembler _masm(&cbuf);
50867
50868#line 7261 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50869
50870 int vector_len = 2;
50871 __ vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
50872
50873#line 50873 "ad_x86.cpp"
50874 }
50875}
50876
50877void mul4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50878 cbuf.set_insts_mark();
50879 // Start at oper_input_base() and count operands
50880 unsigned idx0 = 1;
50881 unsigned idx1 = 1; // src1
50882 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50883 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
50884 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
50885 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
50886 {
50887 MacroAssembler _masm(&cbuf);
50888
50889#line 7281 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50890
50891 __ pmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
50892 __ pmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
50893 __ pmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50894 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
50895 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
50896 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50897
50898#line 50898 "ad_x86.cpp"
50899 }
50900}
50901
50902void mul8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50903 cbuf.set_insts_mark();
50904 // Start at oper_input_base() and count operands
50905 unsigned idx0 = 1;
50906 unsigned idx1 = 1; // src1
50907 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50908 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
50909 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
50910 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
50911 {
50912 MacroAssembler _masm(&cbuf);
50913
50914#line 7302 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50915
50916 __ pmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
50917 __ pmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
50918 __ pmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50919 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
50920 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
50921 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50922
50923#line 50923 "ad_x86.cpp"
50924 }
50925}
50926
50927void mul16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50928 cbuf.set_insts_mark();
50929 // Start at oper_input_base() and count operands
50930 unsigned idx0 = 1;
50931 unsigned idx1 = 1; // src1
50932 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50933 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
50934 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
50935 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
50936 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
50937 {
50938 MacroAssembler _masm(&cbuf);
50939
50940#line 7329 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50941
50942 __ pmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
50943 __ pmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
50944 __ pmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
50945 __ pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, 0xEE);
50946 __ pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xEE);
50947 __ pmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
50948 __ pmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50949 __ pmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50950 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
50951 __ pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50952 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
50953 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
50954
50955#line 50955 "ad_x86.cpp"
50956 }
50957}
50958
50959void vmul16B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50960 cbuf.set_insts_mark();
50961 // Start at oper_input_base() and count operands
50962 unsigned idx0 = 1;
50963 unsigned idx1 = 1; // src1
50964 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50965 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
50966 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
50967 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
50968 {
50969 MacroAssembler _masm(&cbuf);
50970
50971#line 7357 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
50972
50973 int vector_len = 1;
50974 __ vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vector_len);
50975 __ vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
50976 __ vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
50977 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
50978 __ vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
50979 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
50980 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, 0);
50981
50982#line 50982 "ad_x86.cpp"
50983 }
50984}
50985
50986void vmul32B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
50987 cbuf.set_insts_mark();
50988 // Start at oper_input_base() and count operands
50989 unsigned idx0 = 1;
50990 unsigned idx1 = 1; // src1
50991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
50992 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
50993 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
50994 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
50995 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
50996 {
50997 MacroAssembler _masm(&cbuf);
50998
50999#line 7388 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51000
51001 int vector_len = 1;
51002 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
51003 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
51004 __ vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
51005 __ vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51006 __ vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51007 __ vpmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vector_len);
51008 __ vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51009 __ vpmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51010 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
51011 __ vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51012 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51013 __ vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vector_len);
51014 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
51015 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vector_len);
51016
51017#line 51017 "ad_x86.cpp"
51018 }
51019}
51020
51021void vmul64B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51022 cbuf.set_insts_mark();
51023 // Start at oper_input_base() and count operands
51024 unsigned idx0 = 1;
51025 unsigned idx1 = 1; // src1
51026 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51027 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
51028 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
51029 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
51030 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
51031 {
51032 MacroAssembler _masm(&cbuf);
51033
51034#line 7428 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51035
51036 int vector_len = 2;
51037 __ vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
51038 __ vextracti64x4_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
51039 __ vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
51040 __ vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51041 __ vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51042 __ vpmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vector_len);
51043 __ vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51044 __ vpmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51045 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
51046 __ vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51047 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51048 __ vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51049 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vector_len);
51050 __ evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vector_len, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
51051 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
51052
51053
51054#line 51054 "ad_x86.cpp"
51055 }
51056}
51057
51058void vmul2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51059 cbuf.set_insts_mark();
51060 // Start at oper_input_base() and count operands
51061 unsigned idx0 = 1;
51062 unsigned idx1 = 1; // dst
51063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51064 {
51065 MacroAssembler _masm(&cbuf);
51066
51067#line 7455 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51068
51069 __ pmullw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51070
51071#line 51071 "ad_x86.cpp"
51072 }
51073}
51074
51075void vmul2S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51076 cbuf.set_insts_mark();
51077 // Start at oper_input_base() and count operands
51078 unsigned idx0 = 1;
51079 unsigned idx1 = 1; // src1
51080 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51081 {
51082 MacroAssembler _masm(&cbuf);
51083
51084#line 7465 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51085
51086 int vector_len = 0;
51087 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51088
51089#line 51089 "ad_x86.cpp"
51090 }
51091}
51092
51093void vmul2S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51094 cbuf.set_insts_mark();
51095 // Start at oper_input_base() and count operands
51096 unsigned idx0 = 2;
51097 unsigned idx1 = 2; // src
51098 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51099 {
51100 MacroAssembler _masm(&cbuf);
51101
51102#line 7476 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51103
51104 int vector_len = 0;
51105 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51106
51107#line 51107 "ad_x86.cpp"
51108 }
51109}
51110
51111void vmul2S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51112 cbuf.set_insts_mark();
51113 // Start at oper_input_base() and count operands
51114 unsigned idx0 = 2;
51115 unsigned idx1 = 2; // mem
51116 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51117 {
51118 MacroAssembler _masm(&cbuf);
51119
51120#line 7476 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51121
51122 int vector_len = 0;
51123 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51124
51125#line 51125 "ad_x86.cpp"
51126 }
51127}
51128
51129void vmul4SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51130 cbuf.set_insts_mark();
51131 // Start at oper_input_base() and count operands
51132 unsigned idx0 = 1;
51133 unsigned idx1 = 1; // dst
51134 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51135 {
51136 MacroAssembler _masm(&cbuf);
51137
51138#line 7487 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51139
51140 __ pmullw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51141
51142#line 51142 "ad_x86.cpp"
51143 }
51144}
51145
51146void vmul4S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51147 cbuf.set_insts_mark();
51148 // Start at oper_input_base() and count operands
51149 unsigned idx0 = 1;
51150 unsigned idx1 = 1; // src1
51151 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51152 {
51153 MacroAssembler _masm(&cbuf);
51154
51155#line 7497 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51156
51157 int vector_len = 0;
51158 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51159
51160#line 51160 "ad_x86.cpp"
51161 }
51162}
51163
51164void vmul4S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51165 cbuf.set_insts_mark();
51166 // Start at oper_input_base() and count operands
51167 unsigned idx0 = 2;
51168 unsigned idx1 = 2; // src
51169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51170 {
51171 MacroAssembler _masm(&cbuf);
51172
51173#line 7508 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51174
51175 int vector_len = 0;
51176 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51177
51178#line 51178 "ad_x86.cpp"
51179 }
51180}
51181
51182void vmul4S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51183 cbuf.set_insts_mark();
51184 // Start at oper_input_base() and count operands
51185 unsigned idx0 = 2;
51186 unsigned idx1 = 2; // mem
51187 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51188 {
51189 MacroAssembler _masm(&cbuf);
51190
51191#line 7508 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51192
51193 int vector_len = 0;
51194 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51195
51196#line 51196 "ad_x86.cpp"
51197 }
51198}
51199
51200void vmul8SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51201 cbuf.set_insts_mark();
51202 // Start at oper_input_base() and count operands
51203 unsigned idx0 = 1;
51204 unsigned idx1 = 1; // dst
51205 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51206 {
51207 MacroAssembler _masm(&cbuf);
51208
51209#line 7519 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51210
51211 __ pmullw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51212
51213#line 51213 "ad_x86.cpp"
51214 }
51215}
51216
51217void vmul8S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51218 cbuf.set_insts_mark();
51219 // Start at oper_input_base() and count operands
51220 unsigned idx0 = 1;
51221 unsigned idx1 = 1; // src1
51222 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51223 {
51224 MacroAssembler _masm(&cbuf);
51225
51226#line 7529 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51227
51228 int vector_len = 0;
51229 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51230
51231#line 51231 "ad_x86.cpp"
51232 }
51233}
51234
51235void vmul8S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51236 cbuf.set_insts_mark();
51237 // Start at oper_input_base() and count operands
51238 unsigned idx0 = 2;
51239 unsigned idx1 = 2; // src
51240 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51241 {
51242 MacroAssembler _masm(&cbuf);
51243
51244#line 7540 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51245
51246 int vector_len = 0;
51247 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51248
51249#line 51249 "ad_x86.cpp"
51250 }
51251}
51252
51253void vmul8S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51254 cbuf.set_insts_mark();
51255 // Start at oper_input_base() and count operands
51256 unsigned idx0 = 2;
51257 unsigned idx1 = 2; // mem
51258 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51259 {
51260 MacroAssembler _masm(&cbuf);
51261
51262#line 7540 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51263
51264 int vector_len = 0;
51265 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51266
51267#line 51267 "ad_x86.cpp"
51268 }
51269}
51270
51271void vmul16S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51272 cbuf.set_insts_mark();
51273 // Start at oper_input_base() and count operands
51274 unsigned idx0 = 1;
51275 unsigned idx1 = 1; // src1
51276 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51277 {
51278 MacroAssembler _masm(&cbuf);
51279
51280#line 7551 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51281
51282 int vector_len = 1;
51283 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51284
51285#line 51285 "ad_x86.cpp"
51286 }
51287}
51288
51289void vmul16S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51290 cbuf.set_insts_mark();
51291 // Start at oper_input_base() and count operands
51292 unsigned idx0 = 2;
51293 unsigned idx1 = 2; // src
51294 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51295 {
51296 MacroAssembler _masm(&cbuf);
51297
51298#line 7562 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51299
51300 int vector_len = 1;
51301 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51302
51303#line 51303 "ad_x86.cpp"
51304 }
51305}
51306
51307void vmul16S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51308 cbuf.set_insts_mark();
51309 // Start at oper_input_base() and count operands
51310 unsigned idx0 = 2;
51311 unsigned idx1 = 2; // mem
51312 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51313 {
51314 MacroAssembler _masm(&cbuf);
51315
51316#line 7562 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51317
51318 int vector_len = 1;
51319 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51320
51321#line 51321 "ad_x86.cpp"
51322 }
51323}
51324
51325void vmul32S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51326 cbuf.set_insts_mark();
51327 // Start at oper_input_base() and count operands
51328 unsigned idx0 = 1;
51329 unsigned idx1 = 1; // src1
51330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51331 {
51332 MacroAssembler _masm(&cbuf);
51333
51334#line 7573 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51335
51336 int vector_len = 2;
51337 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51338
51339#line 51339 "ad_x86.cpp"
51340 }
51341}
51342
51343void vmul32S_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51344 cbuf.set_insts_mark();
51345 // Start at oper_input_base() and count operands
51346 unsigned idx0 = 2;
51347 unsigned idx1 = 2; // src
51348 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51349 {
51350 MacroAssembler _masm(&cbuf);
51351
51352#line 7584 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51353
51354 int vector_len = 2;
51355 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51356
51357#line 51357 "ad_x86.cpp"
51358 }
51359}
51360
51361void vmul32S_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51362 cbuf.set_insts_mark();
51363 // Start at oper_input_base() and count operands
51364 unsigned idx0 = 2;
51365 unsigned idx1 = 2; // mem
51366 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51367 {
51368 MacroAssembler _masm(&cbuf);
51369
51370#line 7584 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51371
51372 int vector_len = 2;
51373 __ vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51374
51375#line 51375 "ad_x86.cpp"
51376 }
51377}
51378
51379void vmul2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51380 cbuf.set_insts_mark();
51381 // Start at oper_input_base() and count operands
51382 unsigned idx0 = 1;
51383 unsigned idx1 = 1; // dst
51384 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51385 {
51386 MacroAssembler _masm(&cbuf);
51387
51388#line 7596 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51389
51390 __ pmulld(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51391
51392#line 51392 "ad_x86.cpp"
51393 }
51394}
51395
51396void vmul2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51397 cbuf.set_insts_mark();
51398 // Start at oper_input_base() and count operands
51399 unsigned idx0 = 1;
51400 unsigned idx1 = 1; // src1
51401 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51402 {
51403 MacroAssembler _masm(&cbuf);
51404
51405#line 7606 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51406
51407 int vector_len = 0;
51408 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51409
51410#line 51410 "ad_x86.cpp"
51411 }
51412}
51413
51414void vmul2I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51415 cbuf.set_insts_mark();
51416 // Start at oper_input_base() and count operands
51417 unsigned idx0 = 2;
51418 unsigned idx1 = 2; // src
51419 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51420 {
51421 MacroAssembler _masm(&cbuf);
51422
51423#line 7617 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51424
51425 int vector_len = 0;
51426 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51427
51428#line 51428 "ad_x86.cpp"
51429 }
51430}
51431
51432void vmul2I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51433 cbuf.set_insts_mark();
51434 // Start at oper_input_base() and count operands
51435 unsigned idx0 = 2;
51436 unsigned idx1 = 2; // mem
51437 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51438 {
51439 MacroAssembler _masm(&cbuf);
51440
51441#line 7617 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51442
51443 int vector_len = 0;
51444 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51445
51446#line 51446 "ad_x86.cpp"
51447 }
51448}
51449
51450void vmul4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51451 cbuf.set_insts_mark();
51452 // Start at oper_input_base() and count operands
51453 unsigned idx0 = 1;
51454 unsigned idx1 = 1; // dst
51455 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51456 {
51457 MacroAssembler _masm(&cbuf);
51458
51459#line 7628 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51460
51461 __ pmulld(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51462
51463#line 51463 "ad_x86.cpp"
51464 }
51465}
51466
51467void vmul4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51468 cbuf.set_insts_mark();
51469 // Start at oper_input_base() and count operands
51470 unsigned idx0 = 1;
51471 unsigned idx1 = 1; // src1
51472 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51473 {
51474 MacroAssembler _masm(&cbuf);
51475
51476#line 7638 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51477
51478 int vector_len = 0;
51479 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51480
51481#line 51481 "ad_x86.cpp"
51482 }
51483}
51484
51485void vmul4I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51486 cbuf.set_insts_mark();
51487 // Start at oper_input_base() and count operands
51488 unsigned idx0 = 2;
51489 unsigned idx1 = 2; // src
51490 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51491 {
51492 MacroAssembler _masm(&cbuf);
51493
51494#line 7649 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51495
51496 int vector_len = 0;
51497 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51498
51499#line 51499 "ad_x86.cpp"
51500 }
51501}
51502
51503void vmul4I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51504 cbuf.set_insts_mark();
51505 // Start at oper_input_base() and count operands
51506 unsigned idx0 = 2;
51507 unsigned idx1 = 2; // mem
51508 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51509 {
51510 MacroAssembler _masm(&cbuf);
51511
51512#line 7649 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51513
51514 int vector_len = 0;
51515 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51516
51517#line 51517 "ad_x86.cpp"
51518 }
51519}
51520
51521void vmul2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51522 cbuf.set_insts_mark();
51523 // Start at oper_input_base() and count operands
51524 unsigned idx0 = 1;
51525 unsigned idx1 = 1; // src1
51526 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51527 {
51528 MacroAssembler _masm(&cbuf);
51529
51530#line 7660 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51531
51532 int vector_len = 0;
51533 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51534
51535#line 51535 "ad_x86.cpp"
51536 }
51537}
51538
51539void vmul2L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51540 cbuf.set_insts_mark();
51541 // Start at oper_input_base() and count operands
51542 unsigned idx0 = 2;
51543 unsigned idx1 = 2; // src
51544 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51545 {
51546 MacroAssembler _masm(&cbuf);
51547
51548#line 7671 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51549
51550 int vector_len = 0;
51551 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51552
51553#line 51553 "ad_x86.cpp"
51554 }
51555}
51556
51557void vmul2L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51558 cbuf.set_insts_mark();
51559 // Start at oper_input_base() and count operands
51560 unsigned idx0 = 2;
51561 unsigned idx1 = 2; // mem
51562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51563 {
51564 MacroAssembler _masm(&cbuf);
51565
51566#line 7671 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51567
51568 int vector_len = 0;
51569 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51570
51571#line 51571 "ad_x86.cpp"
51572 }
51573}
51574
51575void vmul4L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51576 cbuf.set_insts_mark();
51577 // Start at oper_input_base() and count operands
51578 unsigned idx0 = 1;
51579 unsigned idx1 = 1; // src1
51580 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51581 {
51582 MacroAssembler _masm(&cbuf);
51583
51584#line 7682 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51585
51586 int vector_len = 1;
51587 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51588
51589#line 51589 "ad_x86.cpp"
51590 }
51591}
51592
51593void vmul4L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51594 cbuf.set_insts_mark();
51595 // Start at oper_input_base() and count operands
51596 unsigned idx0 = 2;
51597 unsigned idx1 = 2; // src
51598 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51599 {
51600 MacroAssembler _masm(&cbuf);
51601
51602#line 7693 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51603
51604 int vector_len = 1;
51605 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51606
51607#line 51607 "ad_x86.cpp"
51608 }
51609}
51610
51611void vmul4L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51612 cbuf.set_insts_mark();
51613 // Start at oper_input_base() and count operands
51614 unsigned idx0 = 2;
51615 unsigned idx1 = 2; // mem
51616 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51617 {
51618 MacroAssembler _masm(&cbuf);
51619
51620#line 7693 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51621
51622 int vector_len = 1;
51623 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51624
51625#line 51625 "ad_x86.cpp"
51626 }
51627}
51628
51629void vmul8L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51630 cbuf.set_insts_mark();
51631 // Start at oper_input_base() and count operands
51632 unsigned idx0 = 1;
51633 unsigned idx1 = 1; // src1
51634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51635 {
51636 MacroAssembler _masm(&cbuf);
51637
51638#line 7704 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51639
51640 int vector_len = 2;
51641 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51642
51643#line 51643 "ad_x86.cpp"
51644 }
51645}
51646
51647void vmul8L_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51648 cbuf.set_insts_mark();
51649 // Start at oper_input_base() and count operands
51650 unsigned idx0 = 2;
51651 unsigned idx1 = 2; // src
51652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51653 {
51654 MacroAssembler _masm(&cbuf);
51655
51656#line 7715 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51657
51658 int vector_len = 2;
51659 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51660
51661#line 51661 "ad_x86.cpp"
51662 }
51663}
51664
51665void vmul8L_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51666 cbuf.set_insts_mark();
51667 // Start at oper_input_base() and count operands
51668 unsigned idx0 = 2;
51669 unsigned idx1 = 2; // mem
51670 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51671 {
51672 MacroAssembler _masm(&cbuf);
51673
51674#line 7715 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51675
51676 int vector_len = 2;
51677 __ vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51678
51679#line 51679 "ad_x86.cpp"
51680 }
51681}
51682
51683void vmul8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51684 cbuf.set_insts_mark();
51685 // Start at oper_input_base() and count operands
51686 unsigned idx0 = 1;
51687 unsigned idx1 = 1; // src1
51688 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51689 {
51690 MacroAssembler _masm(&cbuf);
51691
51692#line 7726 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51693
51694 int vector_len = 1;
51695 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51696
51697#line 51697 "ad_x86.cpp"
51698 }
51699}
51700
51701void vmul8I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51702 cbuf.set_insts_mark();
51703 // Start at oper_input_base() and count operands
51704 unsigned idx0 = 2;
51705 unsigned idx1 = 2; // src
51706 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51707 {
51708 MacroAssembler _masm(&cbuf);
51709
51710#line 7737 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51711
51712 int vector_len = 1;
51713 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51714
51715#line 51715 "ad_x86.cpp"
51716 }
51717}
51718
51719void vmul8I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51720 cbuf.set_insts_mark();
51721 // Start at oper_input_base() and count operands
51722 unsigned idx0 = 2;
51723 unsigned idx1 = 2; // mem
51724 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51725 {
51726 MacroAssembler _masm(&cbuf);
51727
51728#line 7737 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51729
51730 int vector_len = 1;
51731 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51732
51733#line 51733 "ad_x86.cpp"
51734 }
51735}
51736
51737void vmul16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51738 cbuf.set_insts_mark();
51739 // Start at oper_input_base() and count operands
51740 unsigned idx0 = 1;
51741 unsigned idx1 = 1; // src1
51742 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51743 {
51744 MacroAssembler _masm(&cbuf);
51745
51746#line 7748 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51747
51748 int vector_len = 2;
51749 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51750
51751#line 51751 "ad_x86.cpp"
51752 }
51753}
51754
51755void vmul16I_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51756 cbuf.set_insts_mark();
51757 // Start at oper_input_base() and count operands
51758 unsigned idx0 = 2;
51759 unsigned idx1 = 2; // src
51760 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51761 {
51762 MacroAssembler _masm(&cbuf);
51763
51764#line 7759 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51765
51766 int vector_len = 2;
51767 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51768
51769#line 51769 "ad_x86.cpp"
51770 }
51771}
51772
51773void vmul16I_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51774 cbuf.set_insts_mark();
51775 // Start at oper_input_base() and count operands
51776 unsigned idx0 = 2;
51777 unsigned idx1 = 2; // mem
51778 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51779 {
51780 MacroAssembler _masm(&cbuf);
51781
51782#line 7759 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51783
51784 int vector_len = 2;
51785 __ vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51786
51787#line 51787 "ad_x86.cpp"
51788 }
51789}
51790
51791void vmul2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51792 cbuf.set_insts_mark();
51793 // Start at oper_input_base() and count operands
51794 unsigned idx0 = 1;
51795 unsigned idx1 = 1; // dst
51796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51797 {
51798 MacroAssembler _masm(&cbuf);
51799
51800#line 7771 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51801
51802 __ mulps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51803
51804#line 51804 "ad_x86.cpp"
51805 }
51806}
51807
51808void vmul2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51809 cbuf.set_insts_mark();
51810 // Start at oper_input_base() and count operands
51811 unsigned idx0 = 1;
51812 unsigned idx1 = 1; // src1
51813 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51814 {
51815 MacroAssembler _masm(&cbuf);
51816
51817#line 7781 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51818
51819 int vector_len = 0;
51820 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51821
51822#line 51822 "ad_x86.cpp"
51823 }
51824}
51825
51826void vmul2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51827 cbuf.set_insts_mark();
51828 // Start at oper_input_base() and count operands
51829 unsigned idx0 = 2;
51830 unsigned idx1 = 2; // src
51831 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51832 {
51833 MacroAssembler _masm(&cbuf);
51834
51835#line 7792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51836
51837 int vector_len = 0;
51838 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51839
51840#line 51840 "ad_x86.cpp"
51841 }
51842}
51843
51844void vmul2F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51845 cbuf.set_insts_mark();
51846 // Start at oper_input_base() and count operands
51847 unsigned idx0 = 2;
51848 unsigned idx1 = 2; // mem
51849 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51850 {
51851 MacroAssembler _masm(&cbuf);
51852
51853#line 7792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51854
51855 int vector_len = 0;
51856 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51857
51858#line 51858 "ad_x86.cpp"
51859 }
51860}
51861
51862void vmul4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51863 cbuf.set_insts_mark();
51864 // Start at oper_input_base() and count operands
51865 unsigned idx0 = 1;
51866 unsigned idx1 = 1; // dst
51867 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51868 {
51869 MacroAssembler _masm(&cbuf);
51870
51871#line 7803 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51872
51873 __ mulps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
51874
51875#line 51875 "ad_x86.cpp"
51876 }
51877}
51878
51879void vmul4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51880 cbuf.set_insts_mark();
51881 // Start at oper_input_base() and count operands
51882 unsigned idx0 = 1;
51883 unsigned idx1 = 1; // src1
51884 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51885 {
51886 MacroAssembler _masm(&cbuf);
51887
51888#line 7813 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51889
51890 int vector_len = 0;
51891 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51892
51893#line 51893 "ad_x86.cpp"
51894 }
51895}
51896
51897void vmul4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51898 cbuf.set_insts_mark();
51899 // Start at oper_input_base() and count operands
51900 unsigned idx0 = 2;
51901 unsigned idx1 = 2; // src
51902 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51903 {
51904 MacroAssembler _masm(&cbuf);
51905
51906#line 7824 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51907
51908 int vector_len = 0;
51909 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51910
51911#line 51911 "ad_x86.cpp"
51912 }
51913}
51914
51915void vmul4F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51916 cbuf.set_insts_mark();
51917 // Start at oper_input_base() and count operands
51918 unsigned idx0 = 2;
51919 unsigned idx1 = 2; // mem
51920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51921 {
51922 MacroAssembler _masm(&cbuf);
51923
51924#line 7824 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51925
51926 int vector_len = 0;
51927 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51928
51929#line 51929 "ad_x86.cpp"
51930 }
51931}
51932
51933void vmul8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51934 cbuf.set_insts_mark();
51935 // Start at oper_input_base() and count operands
51936 unsigned idx0 = 1;
51937 unsigned idx1 = 1; // src1
51938 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51939 {
51940 MacroAssembler _masm(&cbuf);
51941
51942#line 7835 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51943
51944 int vector_len = 1;
51945 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
51946
51947#line 51947 "ad_x86.cpp"
51948 }
51949}
51950
51951void vmul8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51952 cbuf.set_insts_mark();
51953 // Start at oper_input_base() and count operands
51954 unsigned idx0 = 2;
51955 unsigned idx1 = 2; // src
51956 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
51957 {
51958 MacroAssembler _masm(&cbuf);
51959
51960#line 7846 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51961
51962 int vector_len = 1;
51963 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
51964
51965#line 51965 "ad_x86.cpp"
51966 }
51967}
51968
51969void vmul8F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51970 cbuf.set_insts_mark();
51971 // Start at oper_input_base() and count operands
51972 unsigned idx0 = 2;
51973 unsigned idx1 = 2; // mem
51974 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
51975 {
51976 MacroAssembler _masm(&cbuf);
51977
51978#line 7846 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51979
51980 int vector_len = 1;
51981 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
51982
51983#line 51983 "ad_x86.cpp"
51984 }
51985}
51986
51987void vmul16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
51988 cbuf.set_insts_mark();
51989 // Start at oper_input_base() and count operands
51990 unsigned idx0 = 1;
51991 unsigned idx1 = 1; // src1
51992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
51993 {
51994 MacroAssembler _masm(&cbuf);
51995
51996#line 7857 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
51997
51998 int vector_len = 2;
51999 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52000
52001#line 52001 "ad_x86.cpp"
52002 }
52003}
52004
52005void vmul16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52006 cbuf.set_insts_mark();
52007 // Start at oper_input_base() and count operands
52008 unsigned idx0 = 2;
52009 unsigned idx1 = 2; // src
52010 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52011 {
52012 MacroAssembler _masm(&cbuf);
52013
52014#line 7868 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52015
52016 int vector_len = 2;
52017 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52018
52019#line 52019 "ad_x86.cpp"
52020 }
52021}
52022
52023void vmul16F_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52024 cbuf.set_insts_mark();
52025 // Start at oper_input_base() and count operands
52026 unsigned idx0 = 2;
52027 unsigned idx1 = 2; // mem
52028 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52029 {
52030 MacroAssembler _masm(&cbuf);
52031
52032#line 7868 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52033
52034 int vector_len = 2;
52035 __ vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52036
52037#line 52037 "ad_x86.cpp"
52038 }
52039}
52040
52041void vmul2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52042 cbuf.set_insts_mark();
52043 // Start at oper_input_base() and count operands
52044 unsigned idx0 = 1;
52045 unsigned idx1 = 1; // dst
52046 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52047 {
52048 MacroAssembler _masm(&cbuf);
52049
52050#line 7880 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52051
52052 __ mulpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
52053
52054#line 52054 "ad_x86.cpp"
52055 }
52056}
52057
52058void vmul2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52059 cbuf.set_insts_mark();
52060 // Start at oper_input_base() and count operands
52061 unsigned idx0 = 1;
52062 unsigned idx1 = 1; // src1
52063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52064 {
52065 MacroAssembler _masm(&cbuf);
52066
52067#line 7890 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52068
52069 int vector_len = 0;
52070 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52071
52072#line 52072 "ad_x86.cpp"
52073 }
52074}
52075
52076void vmul2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52077 cbuf.set_insts_mark();
52078 // Start at oper_input_base() and count operands
52079 unsigned idx0 = 2;
52080 unsigned idx1 = 2; // src
52081 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52082 {
52083 MacroAssembler _masm(&cbuf);
52084
52085#line 7901 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52086
52087 int vector_len = 0;
52088 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52089
52090#line 52090 "ad_x86.cpp"
52091 }
52092}
52093
52094void vmul2D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52095 cbuf.set_insts_mark();
52096 // Start at oper_input_base() and count operands
52097 unsigned idx0 = 2;
52098 unsigned idx1 = 2; // mem
52099 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52100 {
52101 MacroAssembler _masm(&cbuf);
52102
52103#line 7901 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52104
52105 int vector_len = 0;
52106 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52107
52108#line 52108 "ad_x86.cpp"
52109 }
52110}
52111
52112void vmul4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52113 cbuf.set_insts_mark();
52114 // Start at oper_input_base() and count operands
52115 unsigned idx0 = 1;
52116 unsigned idx1 = 1; // src1
52117 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52118 {
52119 MacroAssembler _masm(&cbuf);
52120
52121#line 7912 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52122
52123 int vector_len = 1;
52124 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52125
52126#line 52126 "ad_x86.cpp"
52127 }
52128}
52129
52130void vmul4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52131 cbuf.set_insts_mark();
52132 // Start at oper_input_base() and count operands
52133 unsigned idx0 = 2;
52134 unsigned idx1 = 2; // src
52135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52136 {
52137 MacroAssembler _masm(&cbuf);
52138
52139#line 7923 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52140
52141 int vector_len = 1;
52142 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52143
52144#line 52144 "ad_x86.cpp"
52145 }
52146}
52147
52148void vmul4D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52149 cbuf.set_insts_mark();
52150 // Start at oper_input_base() and count operands
52151 unsigned idx0 = 2;
52152 unsigned idx1 = 2; // mem
52153 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52154 {
52155 MacroAssembler _masm(&cbuf);
52156
52157#line 7923 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52158
52159 int vector_len = 1;
52160 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52161
52162#line 52162 "ad_x86.cpp"
52163 }
52164}
52165
52166void vmul8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52167 cbuf.set_insts_mark();
52168 // Start at oper_input_base() and count operands
52169 unsigned idx0 = 1;
52170 unsigned idx1 = 1; // src1
52171 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52172 {
52173 MacroAssembler _masm(&cbuf);
52174
52175#line 7934 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52176
52177 int vector_len = 2;
52178 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52179
52180#line 52180 "ad_x86.cpp"
52181 }
52182}
52183
52184void vmul8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52185 cbuf.set_insts_mark();
52186 // Start at oper_input_base() and count operands
52187 unsigned idx0 = 2;
52188 unsigned idx1 = 2; // src
52189 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52190 {
52191 MacroAssembler _masm(&cbuf);
52192
52193#line 7945 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52194
52195 int vector_len = 2;
52196 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52197
52198#line 52198 "ad_x86.cpp"
52199 }
52200}
52201
52202void vmul8D_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52203 cbuf.set_insts_mark();
52204 // Start at oper_input_base() and count operands
52205 unsigned idx0 = 2;
52206 unsigned idx1 = 2; // mem
52207 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52208 {
52209 MacroAssembler _masm(&cbuf);
52210
52211#line 7945 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52212
52213 int vector_len = 2;
52214 __ vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52215
52216#line 52216 "ad_x86.cpp"
52217 }
52218}
52219
52220void vcmov8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52221 cbuf.set_insts_mark();
52222 // Start at oper_input_base() and count operands
52223 unsigned idx0 = 1;
52224 unsigned idx1 = 1; // copnd
52225 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
52226 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
52227 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
52228 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
52229 {
52230 MacroAssembler _masm(&cbuf);
52231
52232#line 7959 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52233
52234 int vector_len = 1;
52235 int cond = (Assembler::Condition)(opnd_array(1)->ccode());
52236 __ cmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, cond, vector_len);
52237 __ blendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, vector_len);
52238
52239#line 52239 "ad_x86.cpp"
52240 }
52241}
52242
52243void vcmov4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52244 cbuf.set_insts_mark();
52245 // Start at oper_input_base() and count operands
52246 unsigned idx0 = 1;
52247 unsigned idx1 = 1; // copnd
52248 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
52249 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
52250 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
52251 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
52252 {
52253 MacroAssembler _masm(&cbuf);
52254
52255#line 7975 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52256
52257 int vector_len = 1;
52258 int cond = (Assembler::Condition)(opnd_array(1)->ccode());
52259 __ cmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, cond, vector_len);
52260 __ blendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, vector_len);
52261
52262#line 52262 "ad_x86.cpp"
52263 }
52264}
52265
52266void vdiv2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52267 cbuf.set_insts_mark();
52268 // Start at oper_input_base() and count operands
52269 unsigned idx0 = 1;
52270 unsigned idx1 = 1; // dst
52271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52272 {
52273 MacroAssembler _masm(&cbuf);
52274
52275#line 7991 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52276
52277 __ divps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
52278
52279#line 52279 "ad_x86.cpp"
52280 }
52281}
52282
52283void vdiv2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52284 cbuf.set_insts_mark();
52285 // Start at oper_input_base() and count operands
52286 unsigned idx0 = 1;
52287 unsigned idx1 = 1; // src1
52288 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52289 {
52290 MacroAssembler _masm(&cbuf);
52291
52292#line 8001 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52293
52294 int vector_len = 0;
52295 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52296
52297#line 52297 "ad_x86.cpp"
52298 }
52299}
52300
52301void vdiv2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52302 cbuf.set_insts_mark();
52303 // Start at oper_input_base() and count operands
52304 unsigned idx0 = 2;
52305 unsigned idx1 = 2; // src
52306 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52307 {
52308 MacroAssembler _masm(&cbuf);
52309
52310#line 8012 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52311
52312 int vector_len = 0;
52313 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52314
52315#line 52315 "ad_x86.cpp"
52316 }
52317}
52318
52319void vdiv4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52320 cbuf.set_insts_mark();
52321 // Start at oper_input_base() and count operands
52322 unsigned idx0 = 1;
52323 unsigned idx1 = 1; // dst
52324 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52325 {
52326 MacroAssembler _masm(&cbuf);
52327
52328#line 8023 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52329
52330 __ divps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
52331
52332#line 52332 "ad_x86.cpp"
52333 }
52334}
52335
52336void vdiv4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52337 cbuf.set_insts_mark();
52338 // Start at oper_input_base() and count operands
52339 unsigned idx0 = 1;
52340 unsigned idx1 = 1; // src1
52341 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52342 {
52343 MacroAssembler _masm(&cbuf);
52344
52345#line 8033 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52346
52347 int vector_len = 0;
52348 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52349
52350#line 52350 "ad_x86.cpp"
52351 }
52352}
52353
52354void vdiv4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52355 cbuf.set_insts_mark();
52356 // Start at oper_input_base() and count operands
52357 unsigned idx0 = 2;
52358 unsigned idx1 = 2; // src
52359 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52360 {
52361 MacroAssembler _masm(&cbuf);
52362
52363#line 8044 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52364
52365 int vector_len = 0;
52366 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52367
52368#line 52368 "ad_x86.cpp"
52369 }
52370}
52371
52372void vdiv8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52373 cbuf.set_insts_mark();
52374 // Start at oper_input_base() and count operands
52375 unsigned idx0 = 1;
52376 unsigned idx1 = 1; // src1
52377 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52378 {
52379 MacroAssembler _masm(&cbuf);
52380
52381#line 8055 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52382
52383 int vector_len = 1;
52384 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52385
52386#line 52386 "ad_x86.cpp"
52387 }
52388}
52389
52390void vdiv8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52391 cbuf.set_insts_mark();
52392 // Start at oper_input_base() and count operands
52393 unsigned idx0 = 2;
52394 unsigned idx1 = 2; // src
52395 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52396 {
52397 MacroAssembler _masm(&cbuf);
52398
52399#line 8066 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52400
52401 int vector_len = 1;
52402 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52403
52404#line 52404 "ad_x86.cpp"
52405 }
52406}
52407
52408void vdiv16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52409 cbuf.set_insts_mark();
52410 // Start at oper_input_base() and count operands
52411 unsigned idx0 = 1;
52412 unsigned idx1 = 1; // src1
52413 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52414 {
52415 MacroAssembler _masm(&cbuf);
52416
52417#line 8077 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52418
52419 int vector_len = 2;
52420 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52421
52422#line 52422 "ad_x86.cpp"
52423 }
52424}
52425
52426void vdiv16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52427 cbuf.set_insts_mark();
52428 // Start at oper_input_base() and count operands
52429 unsigned idx0 = 2;
52430 unsigned idx1 = 2; // src
52431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52432 {
52433 MacroAssembler _masm(&cbuf);
52434
52435#line 8088 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52436
52437 int vector_len = 2;
52438 __ vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52439
52440#line 52440 "ad_x86.cpp"
52441 }
52442}
52443
52444void vdiv2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52445 cbuf.set_insts_mark();
52446 // Start at oper_input_base() and count operands
52447 unsigned idx0 = 1;
52448 unsigned idx1 = 1; // dst
52449 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
52450 {
52451 MacroAssembler _masm(&cbuf);
52452
52453#line 8100 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52454
52455 __ divpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
52456
52457#line 52457 "ad_x86.cpp"
52458 }
52459}
52460
52461void vdiv2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52462 cbuf.set_insts_mark();
52463 // Start at oper_input_base() and count operands
52464 unsigned idx0 = 1;
52465 unsigned idx1 = 1; // src1
52466 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52467 {
52468 MacroAssembler _masm(&cbuf);
52469
52470#line 8110 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52471
52472 int vector_len = 0;
52473 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52474
52475#line 52475 "ad_x86.cpp"
52476 }
52477}
52478
52479void vdiv2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52480 cbuf.set_insts_mark();
52481 // Start at oper_input_base() and count operands
52482 unsigned idx0 = 2;
52483 unsigned idx1 = 2; // src
52484 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52485 {
52486 MacroAssembler _masm(&cbuf);
52487
52488#line 8121 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52489
52490 int vector_len = 0;
52491 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52492
52493#line 52493 "ad_x86.cpp"
52494 }
52495}
52496
52497void vdiv4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52498 cbuf.set_insts_mark();
52499 // Start at oper_input_base() and count operands
52500 unsigned idx0 = 1;
52501 unsigned idx1 = 1; // src1
52502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52503 {
52504 MacroAssembler _masm(&cbuf);
52505
52506#line 8132 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52507
52508 int vector_len = 1;
52509 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52510
52511#line 52511 "ad_x86.cpp"
52512 }
52513}
52514
52515void vdiv4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52516 cbuf.set_insts_mark();
52517 // Start at oper_input_base() and count operands
52518 unsigned idx0 = 2;
52519 unsigned idx1 = 2; // src
52520 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52521 {
52522 MacroAssembler _masm(&cbuf);
52523
52524#line 8143 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52525
52526 int vector_len = 1;
52527 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52528
52529#line 52529 "ad_x86.cpp"
52530 }
52531}
52532
52533void vdiv8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52534 cbuf.set_insts_mark();
52535 // Start at oper_input_base() and count operands
52536 unsigned idx0 = 1;
52537 unsigned idx1 = 1; // src1
52538 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
52539 {
52540 MacroAssembler _masm(&cbuf);
52541
52542#line 8154 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52543
52544 int vector_len = 2;
52545 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
52546
52547#line 52547 "ad_x86.cpp"
52548 }
52549}
52550
52551void vdiv8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52552 cbuf.set_insts_mark();
52553 // Start at oper_input_base() and count operands
52554 unsigned idx0 = 2;
52555 unsigned idx1 = 2; // src
52556 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
52557 {
52558 MacroAssembler _masm(&cbuf);
52559
52560#line 8165 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52561
52562 int vector_len = 2;
52563 __ vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
52564
52565#line 52565 "ad_x86.cpp"
52566 }
52567}
52568
52569void vsqrt2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52570 cbuf.set_insts_mark();
52571 // Start at oper_input_base() and count operands
52572 unsigned idx0 = 1;
52573 unsigned idx1 = 1; // src
52574 {
52575 MacroAssembler _masm(&cbuf);
52576
52577#line 8179 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52578
52579 int vector_len = 0;
52580 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52581
52582#line 52582 "ad_x86.cpp"
52583 }
52584}
52585
52586void vsqrt2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52587 cbuf.set_insts_mark();
52588 // Start at oper_input_base() and count operands
52589 unsigned idx0 = 2;
52590 unsigned idx1 = 2; // mem
52591 {
52592 MacroAssembler _masm(&cbuf);
52593
52594#line 8190 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52595
52596 int vector_len = 0;
52597 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52598
52599#line 52599 "ad_x86.cpp"
52600 }
52601}
52602
52603void vsqrt4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52604 cbuf.set_insts_mark();
52605 // Start at oper_input_base() and count operands
52606 unsigned idx0 = 1;
52607 unsigned idx1 = 1; // src
52608 {
52609 MacroAssembler _masm(&cbuf);
52610
52611#line 8201 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52612
52613 int vector_len = 1;
52614 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52615
52616#line 52616 "ad_x86.cpp"
52617 }
52618}
52619
52620void vsqrt4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52621 cbuf.set_insts_mark();
52622 // Start at oper_input_base() and count operands
52623 unsigned idx0 = 2;
52624 unsigned idx1 = 2; // mem
52625 {
52626 MacroAssembler _masm(&cbuf);
52627
52628#line 8212 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52629
52630 int vector_len = 1;
52631 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52632
52633#line 52633 "ad_x86.cpp"
52634 }
52635}
52636
52637void vsqrt8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52638 cbuf.set_insts_mark();
52639 // Start at oper_input_base() and count operands
52640 unsigned idx0 = 1;
52641 unsigned idx1 = 1; // src
52642 {
52643 MacroAssembler _masm(&cbuf);
52644
52645#line 8223 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52646
52647 int vector_len = 2;
52648 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52649
52650#line 52650 "ad_x86.cpp"
52651 }
52652}
52653
52654void vsqrt8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52655 cbuf.set_insts_mark();
52656 // Start at oper_input_base() and count operands
52657 unsigned idx0 = 2;
52658 unsigned idx1 = 2; // mem
52659 {
52660 MacroAssembler _masm(&cbuf);
52661
52662#line 8234 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52663
52664 int vector_len = 2;
52665 __ vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52666
52667#line 52667 "ad_x86.cpp"
52668 }
52669}
52670
52671void vsqrt2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52672 cbuf.set_insts_mark();
52673 // Start at oper_input_base() and count operands
52674 unsigned idx0 = 1;
52675 unsigned idx1 = 1; // src
52676 {
52677 MacroAssembler _masm(&cbuf);
52678
52679#line 8245 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52680
52681 int vector_len = 0;
52682 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52683
52684#line 52684 "ad_x86.cpp"
52685 }
52686}
52687
52688void vsqrt2F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52689 cbuf.set_insts_mark();
52690 // Start at oper_input_base() and count operands
52691 unsigned idx0 = 2;
52692 unsigned idx1 = 2; // mem
52693 {
52694 MacroAssembler _masm(&cbuf);
52695
52696#line 8256 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52697
52698 int vector_len = 0;
52699 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52700
52701#line 52701 "ad_x86.cpp"
52702 }
52703}
52704
52705void vsqrt4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52706 cbuf.set_insts_mark();
52707 // Start at oper_input_base() and count operands
52708 unsigned idx0 = 1;
52709 unsigned idx1 = 1; // src
52710 {
52711 MacroAssembler _masm(&cbuf);
52712
52713#line 8267 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52714
52715 int vector_len = 0;
52716 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52717
52718#line 52718 "ad_x86.cpp"
52719 }
52720}
52721
52722void vsqrt4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52723 cbuf.set_insts_mark();
52724 // Start at oper_input_base() and count operands
52725 unsigned idx0 = 2;
52726 unsigned idx1 = 2; // mem
52727 {
52728 MacroAssembler _masm(&cbuf);
52729
52730#line 8278 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52731
52732 int vector_len = 0;
52733 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52734
52735#line 52735 "ad_x86.cpp"
52736 }
52737}
52738
52739void vsqrt8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52740 cbuf.set_insts_mark();
52741 // Start at oper_input_base() and count operands
52742 unsigned idx0 = 1;
52743 unsigned idx1 = 1; // src
52744 {
52745 MacroAssembler _masm(&cbuf);
52746
52747#line 8289 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52748
52749 int vector_len = 1;
52750 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52751
52752#line 52752 "ad_x86.cpp"
52753 }
52754}
52755
52756void vsqrt8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52757 cbuf.set_insts_mark();
52758 // Start at oper_input_base() and count operands
52759 unsigned idx0 = 2;
52760 unsigned idx1 = 2; // mem
52761 {
52762 MacroAssembler _masm(&cbuf);
52763
52764#line 8300 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52765
52766 int vector_len = 1;
52767 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52768
52769#line 52769 "ad_x86.cpp"
52770 }
52771}
52772
52773void vsqrt16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52774 cbuf.set_insts_mark();
52775 // Start at oper_input_base() and count operands
52776 unsigned idx0 = 1;
52777 unsigned idx1 = 1; // src
52778 {
52779 MacroAssembler _masm(&cbuf);
52780
52781#line 8311 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52782
52783 int vector_len = 2;
52784 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
52785
52786#line 52786 "ad_x86.cpp"
52787 }
52788}
52789
52790void vsqrt16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52791 cbuf.set_insts_mark();
52792 // Start at oper_input_base() and count operands
52793 unsigned idx0 = 2;
52794 unsigned idx1 = 2; // mem
52795 {
52796 MacroAssembler _masm(&cbuf);
52797
52798#line 8322 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52799
52800 int vector_len = 2;
52801 __ vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
52802
52803#line 52803 "ad_x86.cpp"
52804 }
52805}
52806
52807void vshiftcntNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52808 cbuf.set_insts_mark();
52809 // Start at oper_input_base() and count operands
52810 unsigned idx0 = 1;
52811 unsigned idx1 = 1; // cnt
52812 {
52813 MacroAssembler _masm(&cbuf);
52814
52815#line 8337 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52816
52817 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */);
52818
52819#line 52819 "ad_x86.cpp"
52820 }
52821}
52822
52823void vshiftcnt_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52824 cbuf.set_insts_mark();
52825 // Start at oper_input_base() and count operands
52826 unsigned idx0 = 1;
52827 unsigned idx1 = 1; // cnt
52828 {
52829 MacroAssembler _masm(&cbuf);
52830
52831#line 8337 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52832
52833 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */);
52834
52835#line 52835 "ad_x86.cpp"
52836 }
52837}
52838
52839void vshiftcntimmNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52840 cbuf.set_insts_mark();
52841 // Start at oper_input_base() and count operands
52842 unsigned idx0 = 1;
52843 unsigned idx1 = 1; // cnt
52844 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // tmp
52845 {
52846 MacroAssembler _masm(&cbuf);
52847
52848#line 8348 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52849
52850 __ movl(opnd_array(2)->as_Register(ra_,this,idx2)/* tmp */, opnd_array(1)->constant());
52851 __ movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* tmp */);
52852
52853#line 52853 "ad_x86.cpp"
52854 }
52855}
52856
52857void vshift4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52858 cbuf.set_insts_mark();
52859 // Start at oper_input_base() and count operands
52860 unsigned idx0 = 1;
52861 unsigned idx1 = 1; // src
52862 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52863 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52864 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52865 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52866 {
52867 MacroAssembler _masm(&cbuf);
52868
52869#line 8367 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52870
52871 int opcode = this->as_Mach()->ideal_Opcode();
52872
52873 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
52874 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
52875 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
52876 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
52877 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
52878
52879#line 52879 "ad_x86.cpp"
52880 }
52881}
52882
52883void vshift4B_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52884 cbuf.set_insts_mark();
52885 // Start at oper_input_base() and count operands
52886 unsigned idx0 = 1;
52887 unsigned idx1 = 1; // src
52888 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52889 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52890 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52891 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52892 {
52893 MacroAssembler _masm(&cbuf);
52894
52895#line 8367 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52896
52897 int opcode = this->as_Mach()->ideal_Opcode();
52898
52899 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
52900 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
52901 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
52902 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
52903 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
52904
52905#line 52905 "ad_x86.cpp"
52906 }
52907}
52908
52909void vshift4B_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52910 cbuf.set_insts_mark();
52911 // Start at oper_input_base() and count operands
52912 unsigned idx0 = 1;
52913 unsigned idx1 = 1; // src
52914 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52915 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52916 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52917 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52918 {
52919 MacroAssembler _masm(&cbuf);
52920
52921#line 8367 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52922
52923 int opcode = this->as_Mach()->ideal_Opcode();
52924
52925 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
52926 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
52927 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
52928 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
52929 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
52930
52931#line 52931 "ad_x86.cpp"
52932 }
52933}
52934
52935void vshift8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52936 cbuf.set_insts_mark();
52937 // Start at oper_input_base() and count operands
52938 unsigned idx0 = 1;
52939 unsigned idx1 = 1; // src
52940 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52941 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52942 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52943 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52944 {
52945 MacroAssembler _masm(&cbuf);
52946
52947#line 8390 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52948
52949 int opcode = this->as_Mach()->ideal_Opcode();
52950
52951 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
52952 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
52953 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
52954 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
52955 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
52956
52957#line 52957 "ad_x86.cpp"
52958 }
52959}
52960
52961void vshift8B_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52962 cbuf.set_insts_mark();
52963 // Start at oper_input_base() and count operands
52964 unsigned idx0 = 1;
52965 unsigned idx1 = 1; // src
52966 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52967 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52968 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52969 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52970 {
52971 MacroAssembler _masm(&cbuf);
52972
52973#line 8390 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
52974
52975 int opcode = this->as_Mach()->ideal_Opcode();
52976
52977 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
52978 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
52979 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
52980 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
52981 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
52982
52983#line 52983 "ad_x86.cpp"
52984 }
52985}
52986
52987void vshift8B_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
52988 cbuf.set_insts_mark();
52989 // Start at oper_input_base() and count operands
52990 unsigned idx0 = 1;
52991 unsigned idx1 = 1; // src
52992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
52993 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
52994 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
52995 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
52996 {
52997 MacroAssembler _masm(&cbuf);
52998
52999#line 8390 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53000
53001 int opcode = this->as_Mach()->ideal_Opcode();
53002
53003 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53004 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53005 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53006 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
53007 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
53008
53009#line 53009 "ad_x86.cpp"
53010 }
53011}
53012
53013void vshift16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53014 cbuf.set_insts_mark();
53015 // Start at oper_input_base() and count operands
53016 unsigned idx0 = 1;
53017 unsigned idx1 = 1; // src
53018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53019 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53020 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53021 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53022 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53023 {
53024 MacroAssembler _masm(&cbuf);
53025
53026#line 8417 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53027
53028 int opcode = this->as_Mach()->ideal_Opcode();
53029
53030 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53031 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53032 __ pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
53033 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53034 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53035 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53036 __ pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
53037 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
53038 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53039
53040#line 53040 "ad_x86.cpp"
53041 }
53042}
53043
53044void vshift16B_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53045 cbuf.set_insts_mark();
53046 // Start at oper_input_base() and count operands
53047 unsigned idx0 = 1;
53048 unsigned idx1 = 1; // src
53049 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53050 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53051 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53052 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53053 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53054 {
53055 MacroAssembler _masm(&cbuf);
53056
53057#line 8417 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53058
53059 int opcode = this->as_Mach()->ideal_Opcode();
53060
53061 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53062 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53063 __ pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
53064 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53065 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53066 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53067 __ pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
53068 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
53069 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53070
53071#line 53071 "ad_x86.cpp"
53072 }
53073}
53074
53075void vshift16B_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53076 cbuf.set_insts_mark();
53077 // Start at oper_input_base() and count operands
53078 unsigned idx0 = 1;
53079 unsigned idx1 = 1; // src
53080 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53081 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53082 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53083 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53084 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53085 {
53086 MacroAssembler _masm(&cbuf);
53087
53088#line 8417 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53089
53090 int opcode = this->as_Mach()->ideal_Opcode();
53091
53092 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53093 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53094 __ pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
53095 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53096 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53097 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53098 __ pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
53099 __ pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
53100 __ packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
53101
53102#line 53102 "ad_x86.cpp"
53103 }
53104}
53105
53106void vshift16B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53107 cbuf.set_insts_mark();
53108 // Start at oper_input_base() and count operands
53109 unsigned idx0 = 1;
53110 unsigned idx1 = 1; // src
53111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53112 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53113 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53114 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53115 {
53116 MacroAssembler _masm(&cbuf);
53117
53118#line 8444 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53119
53120 int opcode = this->as_Mach()->ideal_Opcode();
53121
53122 int vector_len = 1;
53123 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53124 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53125 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53126 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
53127 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
53128
53129#line 53129 "ad_x86.cpp"
53130 }
53131}
53132
53133void vshift16B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53134 cbuf.set_insts_mark();
53135 // Start at oper_input_base() and count operands
53136 unsigned idx0 = 1;
53137 unsigned idx1 = 1; // src
53138 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53139 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53140 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53141 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53142 {
53143 MacroAssembler _masm(&cbuf);
53144
53145#line 8444 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53146
53147 int opcode = this->as_Mach()->ideal_Opcode();
53148
53149 int vector_len = 1;
53150 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53151 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53152 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53153 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
53154 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
53155
53156#line 53156 "ad_x86.cpp"
53157 }
53158}
53159
53160void vshift16B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53161 cbuf.set_insts_mark();
53162 // Start at oper_input_base() and count operands
53163 unsigned idx0 = 1;
53164 unsigned idx1 = 1; // src
53165 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53166 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53167 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53168 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53169 {
53170 MacroAssembler _masm(&cbuf);
53171
53172#line 8444 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53173
53174 int opcode = this->as_Mach()->ideal_Opcode();
53175
53176 int vector_len = 1;
53177 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53178 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53179 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53180 __ vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
53181 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
53182
53183#line 53183 "ad_x86.cpp"
53184 }
53185}
53186
53187void vshift32B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53188 cbuf.set_insts_mark();
53189 // Start at oper_input_base() and count operands
53190 unsigned idx0 = 1;
53191 unsigned idx1 = 1; // src
53192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53193 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53194 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53195 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53196 {
53197 MacroAssembler _masm(&cbuf);
53198
53199#line 8472 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53200
53201 int opcode = this->as_Mach()->ideal_Opcode();
53202
53203 int vector_len = 1;
53204 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53205 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53206 __ vextendbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53207 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53208 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53209 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53210 __ vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53211 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53212 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vector_len);
53213
53214#line 53214 "ad_x86.cpp"
53215 }
53216}
53217
53218void vshift32B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53219 cbuf.set_insts_mark();
53220 // Start at oper_input_base() and count operands
53221 unsigned idx0 = 1;
53222 unsigned idx1 = 1; // src
53223 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53224 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53225 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53226 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53227 {
53228 MacroAssembler _masm(&cbuf);
53229
53230#line 8472 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53231
53232 int opcode = this->as_Mach()->ideal_Opcode();
53233
53234 int vector_len = 1;
53235 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53236 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53237 __ vextendbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53238 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53239 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53240 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53241 __ vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53242 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53243 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vector_len);
53244
53245#line 53245 "ad_x86.cpp"
53246 }
53247}
53248
53249void vshift32B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53250 cbuf.set_insts_mark();
53251 // Start at oper_input_base() and count operands
53252 unsigned idx0 = 1;
53253 unsigned idx1 = 1; // src
53254 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53255 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53256 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
53257 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
53258 {
53259 MacroAssembler _masm(&cbuf);
53260
53261#line 8472 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53262
53263 int opcode = this->as_Mach()->ideal_Opcode();
53264
53265 int vector_len = 1;
53266 __ vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53267 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53268 __ vextendbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53269 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53270 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53271 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53272 __ vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vector_len, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
53273 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
53274 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vector_len);
53275
53276#line 53276 "ad_x86.cpp"
53277 }
53278}
53279
53280void vshift64B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53281 cbuf.set_insts_mark();
53282 // Start at oper_input_base() and count operands
53283 unsigned idx0 = 1;
53284 unsigned idx1 = 1; // src
53285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53286 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53287 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53288 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53289 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53290 {
53291 MacroAssembler _masm(&cbuf);
53292
53293#line 8507 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53294
53295 int opcode = this->as_Mach()->ideal_Opcode();
53296
53297 int vector_len = 2;
53298 __ vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
53299 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
53300 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53301 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53302 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53303 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53304 __ vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53305 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53306 __ vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53307 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vector_len);
53308 __ evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vector_len, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53309 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53310
53311#line 53311 "ad_x86.cpp"
53312 }
53313}
53314
53315void vshift64B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53316 cbuf.set_insts_mark();
53317 // Start at oper_input_base() and count operands
53318 unsigned idx0 = 1;
53319 unsigned idx1 = 1; // src
53320 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53321 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53322 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53323 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53324 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53325 {
53326 MacroAssembler _masm(&cbuf);
53327
53328#line 8507 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53329
53330 int opcode = this->as_Mach()->ideal_Opcode();
53331
53332 int vector_len = 2;
53333 __ vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
53334 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
53335 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53336 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53337 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53338 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53339 __ vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53340 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53341 __ vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53342 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vector_len);
53343 __ evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vector_len, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53344 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53345
53346#line 53346 "ad_x86.cpp"
53347 }
53348}
53349
53350void vshift64B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53351 cbuf.set_insts_mark();
53352 // Start at oper_input_base() and count operands
53353 unsigned idx0 = 1;
53354 unsigned idx1 = 1; // src
53355 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53356 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53357 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
53358 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
53359 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
53360 {
53361 MacroAssembler _masm(&cbuf);
53362
53363#line 8507 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53364
53365 int opcode = this->as_Mach()->ideal_Opcode();
53366
53367 int vector_len = 2;
53368 __ vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
53369 __ vextendbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vector_len);
53370 __ vextendbw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
53371 __ vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53372 __ vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53373 __ vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53374 __ vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53375 __ vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53376 __ vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53377 __ vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vector_len);
53378 __ evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vector_len, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
53379 __ vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vector_len);
53380
53381#line 53381 "ad_x86.cpp"
53382 }
53383}
53384
53385void vshist2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53386 cbuf.set_insts_mark();
53387 // Start at oper_input_base() and count operands
53388 unsigned idx0 = 1;
53389 unsigned idx1 = 1; // src
53390 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53391 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53392 {
53393 MacroAssembler _masm(&cbuf);
53394
53395#line 8539 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53396
53397 int opcode = this->as_Mach()->ideal_Opcode();
53398 if (UseAVX == 0) {
53399 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53400 __ movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53401 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53402 } else {
53403 int vector_len = 0;
53404 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53405 }
53406
53407#line 53407 "ad_x86.cpp"
53408 }
53409}
53410
53411void vshist2S_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53412 cbuf.set_insts_mark();
53413 // Start at oper_input_base() and count operands
53414 unsigned idx0 = 1;
53415 unsigned idx1 = 1; // src
53416 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53417 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53418 {
53419 MacroAssembler _masm(&cbuf);
53420
53421#line 8539 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53422
53423 int opcode = this->as_Mach()->ideal_Opcode();
53424 if (UseAVX == 0) {
53425 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53426 __ movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53427 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53428 } else {
53429 int vector_len = 0;
53430 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53431 }
53432
53433#line 53433 "ad_x86.cpp"
53434 }
53435}
53436
53437void vshist2S_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53438 cbuf.set_insts_mark();
53439 // Start at oper_input_base() and count operands
53440 unsigned idx0 = 1;
53441 unsigned idx1 = 1; // src
53442 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53443 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53444 {
53445 MacroAssembler _masm(&cbuf);
53446
53447#line 8539 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53448
53449 int opcode = this->as_Mach()->ideal_Opcode();
53450 if (UseAVX == 0) {
53451 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53452 __ movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53453 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53454 } else {
53455 int vector_len = 0;
53456 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53457 }
53458
53459#line 53459 "ad_x86.cpp"
53460 }
53461}
53462
53463void vshift4SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53464 cbuf.set_insts_mark();
53465 // Start at oper_input_base() and count operands
53466 unsigned idx0 = 1;
53467 unsigned idx1 = 1; // src
53468 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53469 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53470 {
53471 MacroAssembler _masm(&cbuf);
53472
53473#line 8560 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53474
53475 int opcode = this->as_Mach()->ideal_Opcode();
53476 if (UseAVX == 0) {
53477 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53478 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53479 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53480
53481 } else {
53482 int vector_len = 0;
53483 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53484 }
53485
53486#line 53486 "ad_x86.cpp"
53487 }
53488}
53489
53490void vshift4S_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53491 cbuf.set_insts_mark();
53492 // Start at oper_input_base() and count operands
53493 unsigned idx0 = 1;
53494 unsigned idx1 = 1; // src
53495 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53496 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53497 {
53498 MacroAssembler _masm(&cbuf);
53499
53500#line 8560 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53501
53502 int opcode = this->as_Mach()->ideal_Opcode();
53503 if (UseAVX == 0) {
53504 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53505 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53506 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53507
53508 } else {
53509 int vector_len = 0;
53510 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53511 }
53512
53513#line 53513 "ad_x86.cpp"
53514 }
53515}
53516
53517void vshift4S_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53518 cbuf.set_insts_mark();
53519 // Start at oper_input_base() and count operands
53520 unsigned idx0 = 1;
53521 unsigned idx1 = 1; // src
53522 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53523 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53524 {
53525 MacroAssembler _masm(&cbuf);
53526
53527#line 8560 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53528
53529 int opcode = this->as_Mach()->ideal_Opcode();
53530 if (UseAVX == 0) {
53531 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53532 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53533 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53534
53535 } else {
53536 int vector_len = 0;
53537 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53538 }
53539
53540#line 53540 "ad_x86.cpp"
53541 }
53542}
53543
53544void vshift8SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53545 cbuf.set_insts_mark();
53546 // Start at oper_input_base() and count operands
53547 unsigned idx0 = 1;
53548 unsigned idx1 = 1; // src
53549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53550 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53551 {
53552 MacroAssembler _masm(&cbuf);
53553
53554#line 8582 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53555
53556 int opcode = this->as_Mach()->ideal_Opcode();
53557 if (UseAVX == 0) {
53558 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53559 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53560 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53561 } else {
53562 int vector_len = 0;
53563 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53564 }
53565
53566#line 53566 "ad_x86.cpp"
53567 }
53568}
53569
53570void vshift8S_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53571 cbuf.set_insts_mark();
53572 // Start at oper_input_base() and count operands
53573 unsigned idx0 = 1;
53574 unsigned idx1 = 1; // src
53575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53576 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53577 {
53578 MacroAssembler _masm(&cbuf);
53579
53580#line 8582 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53581
53582 int opcode = this->as_Mach()->ideal_Opcode();
53583 if (UseAVX == 0) {
53584 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53585 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53586 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53587 } else {
53588 int vector_len = 0;
53589 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53590 }
53591
53592#line 53592 "ad_x86.cpp"
53593 }
53594}
53595
53596void vshift8S_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53597 cbuf.set_insts_mark();
53598 // Start at oper_input_base() and count operands
53599 unsigned idx0 = 1;
53600 unsigned idx1 = 1; // src
53601 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53602 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53603 {
53604 MacroAssembler _masm(&cbuf);
53605
53606#line 8582 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53607
53608 int opcode = this->as_Mach()->ideal_Opcode();
53609 if (UseAVX == 0) {
53610 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53611 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53612 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53613 } else {
53614 int vector_len = 0;
53615 __ vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53616 }
53617
53618#line 53618 "ad_x86.cpp"
53619 }
53620}
53621
53622void vshift16SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53623 cbuf.set_insts_mark();
53624 // Start at oper_input_base() and count operands
53625 unsigned idx0 = 1;
53626 unsigned idx1 = 1; // src
53627 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53628 {
53629 MacroAssembler _masm(&cbuf);
53630
53631#line 8603 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53632
53633 int vector_len = 1;
53634 int opcode = this->as_Mach()->ideal_Opcode();
53635 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53636
53637#line 53637 "ad_x86.cpp"
53638 }
53639}
53640
53641void vshift16S_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53642 cbuf.set_insts_mark();
53643 // Start at oper_input_base() and count operands
53644 unsigned idx0 = 1;
53645 unsigned idx1 = 1; // src
53646 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53647 {
53648 MacroAssembler _masm(&cbuf);
53649
53650#line 8603 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53651
53652 int vector_len = 1;
53653 int opcode = this->as_Mach()->ideal_Opcode();
53654 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53655
53656#line 53656 "ad_x86.cpp"
53657 }
53658}
53659
53660void vshift16S_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53661 cbuf.set_insts_mark();
53662 // Start at oper_input_base() and count operands
53663 unsigned idx0 = 1;
53664 unsigned idx1 = 1; // src
53665 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53666 {
53667 MacroAssembler _masm(&cbuf);
53668
53669#line 8603 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53670
53671 int vector_len = 1;
53672 int opcode = this->as_Mach()->ideal_Opcode();
53673 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53674
53675#line 53675 "ad_x86.cpp"
53676 }
53677}
53678
53679void vshift32SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53680 cbuf.set_insts_mark();
53681 // Start at oper_input_base() and count operands
53682 unsigned idx0 = 1;
53683 unsigned idx1 = 1; // src
53684 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53685 {
53686 MacroAssembler _masm(&cbuf);
53687
53688#line 8618 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53689
53690 int vector_len = 2;
53691 int opcode = this->as_Mach()->ideal_Opcode();
53692 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53693
53694#line 53694 "ad_x86.cpp"
53695 }
53696}
53697
53698void vshift32S_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53699 cbuf.set_insts_mark();
53700 // Start at oper_input_base() and count operands
53701 unsigned idx0 = 1;
53702 unsigned idx1 = 1; // src
53703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53704 {
53705 MacroAssembler _masm(&cbuf);
53706
53707#line 8618 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53708
53709 int vector_len = 2;
53710 int opcode = this->as_Mach()->ideal_Opcode();
53711 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53712
53713#line 53713 "ad_x86.cpp"
53714 }
53715}
53716
53717void vshift32S_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53718 cbuf.set_insts_mark();
53719 // Start at oper_input_base() and count operands
53720 unsigned idx0 = 1;
53721 unsigned idx1 = 1; // src
53722 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53723 {
53724 MacroAssembler _masm(&cbuf);
53725
53726#line 8618 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53727
53728 int vector_len = 2;
53729 int opcode = this->as_Mach()->ideal_Opcode();
53730 __ vshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53731
53732#line 53732 "ad_x86.cpp"
53733 }
53734}
53735
53736void vshift2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53737 cbuf.set_insts_mark();
53738 // Start at oper_input_base() and count operands
53739 unsigned idx0 = 1;
53740 unsigned idx1 = 1; // src
53741 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53742 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53743 {
53744 MacroAssembler _masm(&cbuf);
53745
53746#line 8634 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53747
53748 int opcode = this->as_Mach()->ideal_Opcode();
53749 if (UseAVX == 0) {
53750 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53751 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53752 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53753 } else {
53754 int vector_len = 0;
53755 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53756 }
53757
53758#line 53758 "ad_x86.cpp"
53759 }
53760}
53761
53762void vshift2I_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53763 cbuf.set_insts_mark();
53764 // Start at oper_input_base() and count operands
53765 unsigned idx0 = 1;
53766 unsigned idx1 = 1; // src
53767 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53768 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53769 {
53770 MacroAssembler _masm(&cbuf);
53771
53772#line 8634 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53773
53774 int opcode = this->as_Mach()->ideal_Opcode();
53775 if (UseAVX == 0) {
53776 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53777 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53778 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53779 } else {
53780 int vector_len = 0;
53781 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53782 }
53783
53784#line 53784 "ad_x86.cpp"
53785 }
53786}
53787
53788void vshift2I_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53789 cbuf.set_insts_mark();
53790 // Start at oper_input_base() and count operands
53791 unsigned idx0 = 1;
53792 unsigned idx1 = 1; // src
53793 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53794 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53795 {
53796 MacroAssembler _masm(&cbuf);
53797
53798#line 8634 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53799
53800 int opcode = this->as_Mach()->ideal_Opcode();
53801 if (UseAVX == 0) {
53802 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53803 __ movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53804 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53805 } else {
53806 int vector_len = 0;
53807 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53808 }
53809
53810#line 53810 "ad_x86.cpp"
53811 }
53812}
53813
53814void vshift4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53815 cbuf.set_insts_mark();
53816 // Start at oper_input_base() and count operands
53817 unsigned idx0 = 1;
53818 unsigned idx1 = 1; // src
53819 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53820 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53821 {
53822 MacroAssembler _masm(&cbuf);
53823
53824#line 8655 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53825
53826 int opcode = this->as_Mach()->ideal_Opcode();
53827 if (UseAVX == 0) {
53828 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53829 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53830 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53831 } else {
53832 int vector_len = 0;
53833 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53834 }
53835
53836#line 53836 "ad_x86.cpp"
53837 }
53838}
53839
53840void vshift4I_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53841 cbuf.set_insts_mark();
53842 // Start at oper_input_base() and count operands
53843 unsigned idx0 = 1;
53844 unsigned idx1 = 1; // src
53845 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53846 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53847 {
53848 MacroAssembler _masm(&cbuf);
53849
53850#line 8655 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53851
53852 int opcode = this->as_Mach()->ideal_Opcode();
53853 if (UseAVX == 0) {
53854 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53855 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53856 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53857 } else {
53858 int vector_len = 0;
53859 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53860 }
53861
53862#line 53862 "ad_x86.cpp"
53863 }
53864}
53865
53866void vshift4I_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53867 cbuf.set_insts_mark();
53868 // Start at oper_input_base() and count operands
53869 unsigned idx0 = 1;
53870 unsigned idx1 = 1; // src
53871 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53872 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
53873 {
53874 MacroAssembler _masm(&cbuf);
53875
53876#line 8655 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53877
53878 int opcode = this->as_Mach()->ideal_Opcode();
53879 if (UseAVX == 0) {
53880 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
53881 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
53882 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
53883 } else {
53884 int vector_len = 0;
53885 __ vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53886 }
53887
53888#line 53888 "ad_x86.cpp"
53889 }
53890}
53891
53892void vshift8INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53893 cbuf.set_insts_mark();
53894 // Start at oper_input_base() and count operands
53895 unsigned idx0 = 1;
53896 unsigned idx1 = 1; // src
53897 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53898 {
53899 MacroAssembler _masm(&cbuf);
53900
53901#line 8676 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53902
53903 int vector_len = 1;
53904 int opcode = this->as_Mach()->ideal_Opcode();
53905 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53906
53907#line 53907 "ad_x86.cpp"
53908 }
53909}
53910
53911void vshift8I_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53912 cbuf.set_insts_mark();
53913 // Start at oper_input_base() and count operands
53914 unsigned idx0 = 1;
53915 unsigned idx1 = 1; // src
53916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53917 {
53918 MacroAssembler _masm(&cbuf);
53919
53920#line 8676 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53921
53922 int vector_len = 1;
53923 int opcode = this->as_Mach()->ideal_Opcode();
53924 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53925
53926#line 53926 "ad_x86.cpp"
53927 }
53928}
53929
53930void vshift8I_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53931 cbuf.set_insts_mark();
53932 // Start at oper_input_base() and count operands
53933 unsigned idx0 = 1;
53934 unsigned idx1 = 1; // src
53935 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53936 {
53937 MacroAssembler _masm(&cbuf);
53938
53939#line 8676 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53940
53941 int vector_len = 1;
53942 int opcode = this->as_Mach()->ideal_Opcode();
53943 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53944
53945#line 53945 "ad_x86.cpp"
53946 }
53947}
53948
53949void vshift16INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53950 cbuf.set_insts_mark();
53951 // Start at oper_input_base() and count operands
53952 unsigned idx0 = 1;
53953 unsigned idx1 = 1; // src
53954 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53955 {
53956 MacroAssembler _masm(&cbuf);
53957
53958#line 8691 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53959
53960 int vector_len = 2;
53961 int opcode = this->as_Mach()->ideal_Opcode();
53962 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53963
53964#line 53964 "ad_x86.cpp"
53965 }
53966}
53967
53968void vshift16I_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53969 cbuf.set_insts_mark();
53970 // Start at oper_input_base() and count operands
53971 unsigned idx0 = 1;
53972 unsigned idx1 = 1; // src
53973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53974 {
53975 MacroAssembler _masm(&cbuf);
53976
53977#line 8691 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53978
53979 int vector_len = 2;
53980 int opcode = this->as_Mach()->ideal_Opcode();
53981 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
53982
53983#line 53983 "ad_x86.cpp"
53984 }
53985}
53986
53987void vshift16I_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
53988 cbuf.set_insts_mark();
53989 // Start at oper_input_base() and count operands
53990 unsigned idx0 = 1;
53991 unsigned idx1 = 1; // src
53992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
53993 {
53994 MacroAssembler _masm(&cbuf);
53995
53996#line 8691 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
53997
53998 int vector_len = 2;
53999 int opcode = this->as_Mach()->ideal_Opcode();
54000 __ vshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54001
54002#line 54002 "ad_x86.cpp"
54003 }
54004}
54005
54006void vshift2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54007 cbuf.set_insts_mark();
54008 // Start at oper_input_base() and count operands
54009 unsigned idx0 = 1;
54010 unsigned idx1 = 1; // src
54011 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54012 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
54013 {
54014 MacroAssembler _masm(&cbuf);
54015
54016#line 8706 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54017
54018 int opcode = this->as_Mach()->ideal_Opcode();
54019 if (UseAVX == 0) {
54020 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
54021 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
54022 __ vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
54023 } else {
54024 int vector_len = 0;
54025 __ vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54026 }
54027
54028#line 54028 "ad_x86.cpp"
54029 }
54030}
54031
54032void vshift2L_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54033 cbuf.set_insts_mark();
54034 // Start at oper_input_base() and count operands
54035 unsigned idx0 = 1;
54036 unsigned idx1 = 1; // src
54037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54038 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
54039 {
54040 MacroAssembler _masm(&cbuf);
54041
54042#line 8706 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54043
54044 int opcode = this->as_Mach()->ideal_Opcode();
54045 if (UseAVX == 0) {
54046 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
54047 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
54048 __ vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
54049 } else {
54050 int vector_len = 0;
54051 __ vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54052 }
54053
54054#line 54054 "ad_x86.cpp"
54055 }
54056}
54057
54058void vshift4LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54059 cbuf.set_insts_mark();
54060 // Start at oper_input_base() and count operands
54061 unsigned idx0 = 1;
54062 unsigned idx1 = 1; // src
54063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54064 {
54065 MacroAssembler _masm(&cbuf);
54066
54067#line 8726 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54068
54069 int vector_len = 1;
54070 int opcode = this->as_Mach()->ideal_Opcode();
54071 __ vshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54072
54073#line 54073 "ad_x86.cpp"
54074 }
54075}
54076
54077void vshift4L_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54078 cbuf.set_insts_mark();
54079 // Start at oper_input_base() and count operands
54080 unsigned idx0 = 1;
54081 unsigned idx1 = 1; // src
54082 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54083 {
54084 MacroAssembler _masm(&cbuf);
54085
54086#line 8726 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54087
54088 int vector_len = 1;
54089 int opcode = this->as_Mach()->ideal_Opcode();
54090 __ vshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54091
54092#line 54092 "ad_x86.cpp"
54093 }
54094}
54095
54096void vshift8LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54097 cbuf.set_insts_mark();
54098 // Start at oper_input_base() and count operands
54099 unsigned idx0 = 1;
54100 unsigned idx1 = 1; // src
54101 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54102 {
54103 MacroAssembler _masm(&cbuf);
54104
54105#line 8741 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54106
54107 int vector_len = 2;
54108 int opcode = this->as_Mach()->ideal_Opcode();
54109 __ vshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54110
54111#line 54111 "ad_x86.cpp"
54112 }
54113}
54114
54115void vshift8L_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54116 cbuf.set_insts_mark();
54117 // Start at oper_input_base() and count operands
54118 unsigned idx0 = 1;
54119 unsigned idx1 = 1; // src
54120 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54121 {
54122 MacroAssembler _masm(&cbuf);
54123
54124#line 8741 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54125
54126 int vector_len = 2;
54127 int opcode = this->as_Mach()->ideal_Opcode();
54128 __ vshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54129
54130#line 54130 "ad_x86.cpp"
54131 }
54132}
54133
54134void vshift8L_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54135 cbuf.set_insts_mark();
54136 // Start at oper_input_base() and count operands
54137 unsigned idx0 = 1;
54138 unsigned idx1 = 1; // src
54139 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54140 {
54141 MacroAssembler _masm(&cbuf);
54142
54143#line 8741 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54144
54145 int vector_len = 2;
54146 int opcode = this->as_Mach()->ideal_Opcode();
54147 __ vshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54148
54149#line 54149 "ad_x86.cpp"
54150 }
54151}
54152
54153void vsra2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54154 cbuf.set_insts_mark();
54155 // Start at oper_input_base() and count operands
54156 unsigned idx0 = 1;
54157 unsigned idx1 = 1; // src
54158 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54159 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
54160 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
54161 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
54162 {
54163 MacroAssembler _masm(&cbuf);
54164
54165#line 8761 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54166
54167 __ movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
54168 __ psrlq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
54169 __ movdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_long_sign_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
54170 __ psrlq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
54171 __ pxor(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
54172 __ psubq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
54173
54174#line 54174 "ad_x86.cpp"
54175 }
54176}
54177
54178void vsra2L_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54179 cbuf.set_insts_mark();
54180 // Start at oper_input_base() and count operands
54181 unsigned idx0 = 1;
54182 unsigned idx1 = 1; // src
54183 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54184 {
54185 MacroAssembler _masm(&cbuf);
54186
54187#line 8776 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54188
54189 int vector_len = 0;
54190 __ evpsraq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54191
54192#line 54192 "ad_x86.cpp"
54193 }
54194}
54195
54196void vsra4L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54197 cbuf.set_insts_mark();
54198 // Start at oper_input_base() and count operands
54199 unsigned idx0 = 1;
54200 unsigned idx1 = 1; // src
54201 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54202 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
54203 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
54204 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
54205 {
54206 MacroAssembler _masm(&cbuf);
54207
54208#line 8792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54209
54210 int vector_len = 1;
54211 __ vpsrlq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54212 __ vmovdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_long_sign_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
54213 __ vpsrlq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54214 __ vpxor(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
54215 __ vpsubq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vector_len);
54216
54217#line 54217 "ad_x86.cpp"
54218 }
54219}
54220
54221void vsra4L_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54222 cbuf.set_insts_mark();
54223 // Start at oper_input_base() and count operands
54224 unsigned idx0 = 1;
54225 unsigned idx1 = 1; // src
54226 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
54227 {
54228 MacroAssembler _masm(&cbuf);
54229
54230#line 8807 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54231
54232 int vector_len = 1;
54233 __ evpsraq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
54234
54235#line 54235 "ad_x86.cpp"
54236 }
54237}
54238
54239void vand4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54240 cbuf.set_insts_mark();
54241 // Start at oper_input_base() and count operands
54242 unsigned idx0 = 1;
54243 unsigned idx1 = 1; // dst
54244 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54245 {
54246 MacroAssembler _masm(&cbuf);
54247
54248#line 8820 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54249
54250 __ pand(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54251
54252#line 54252 "ad_x86.cpp"
54253 }
54254}
54255
54256void vand4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54257 cbuf.set_insts_mark();
54258 // Start at oper_input_base() and count operands
54259 unsigned idx0 = 1;
54260 unsigned idx1 = 1; // src1
54261 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54262 {
54263 MacroAssembler _masm(&cbuf);
54264
54265#line 8830 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54266
54267 int vector_len = 0;
54268 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54269
54270#line 54270 "ad_x86.cpp"
54271 }
54272}
54273
54274void vand4B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54275 cbuf.set_insts_mark();
54276 // Start at oper_input_base() and count operands
54277 unsigned idx0 = 2;
54278 unsigned idx1 = 2; // src
54279 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54280 {
54281 MacroAssembler _masm(&cbuf);
54282
54283#line 8841 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54284
54285 int vector_len = 0;
54286 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54287
54288#line 54288 "ad_x86.cpp"
54289 }
54290}
54291
54292void vand4B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54293 cbuf.set_insts_mark();
54294 // Start at oper_input_base() and count operands
54295 unsigned idx0 = 2;
54296 unsigned idx1 = 2; // mem
54297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54298 {
54299 MacroAssembler _masm(&cbuf);
54300
54301#line 8841 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54302
54303 int vector_len = 0;
54304 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54305
54306#line 54306 "ad_x86.cpp"
54307 }
54308}
54309
54310void vand8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54311 cbuf.set_insts_mark();
54312 // Start at oper_input_base() and count operands
54313 unsigned idx0 = 1;
54314 unsigned idx1 = 1; // dst
54315 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54316 {
54317 MacroAssembler _masm(&cbuf);
54318
54319#line 8852 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54320
54321 __ pand(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54322
54323#line 54323 "ad_x86.cpp"
54324 }
54325}
54326
54327void vand8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54328 cbuf.set_insts_mark();
54329 // Start at oper_input_base() and count operands
54330 unsigned idx0 = 1;
54331 unsigned idx1 = 1; // src1
54332 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54333 {
54334 MacroAssembler _masm(&cbuf);
54335
54336#line 8862 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54337
54338 int vector_len = 0;
54339 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54340
54341#line 54341 "ad_x86.cpp"
54342 }
54343}
54344
54345void vand8B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54346 cbuf.set_insts_mark();
54347 // Start at oper_input_base() and count operands
54348 unsigned idx0 = 2;
54349 unsigned idx1 = 2; // src
54350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54351 {
54352 MacroAssembler _masm(&cbuf);
54353
54354#line 8873 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54355
54356 int vector_len = 0;
54357 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54358
54359#line 54359 "ad_x86.cpp"
54360 }
54361}
54362
54363void vand8B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54364 cbuf.set_insts_mark();
54365 // Start at oper_input_base() and count operands
54366 unsigned idx0 = 2;
54367 unsigned idx1 = 2; // mem
54368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54369 {
54370 MacroAssembler _masm(&cbuf);
54371
54372#line 8873 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54373
54374 int vector_len = 0;
54375 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54376
54377#line 54377 "ad_x86.cpp"
54378 }
54379}
54380
54381void vand16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54382 cbuf.set_insts_mark();
54383 // Start at oper_input_base() and count operands
54384 unsigned idx0 = 1;
54385 unsigned idx1 = 1; // dst
54386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54387 {
54388 MacroAssembler _masm(&cbuf);
54389
54390#line 8884 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54391
54392 __ pand(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54393
54394#line 54394 "ad_x86.cpp"
54395 }
54396}
54397
54398void vand16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54399 cbuf.set_insts_mark();
54400 // Start at oper_input_base() and count operands
54401 unsigned idx0 = 1;
54402 unsigned idx1 = 1; // src1
54403 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54404 {
54405 MacroAssembler _masm(&cbuf);
54406
54407#line 8894 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54408
54409 int vector_len = 0;
54410 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54411
54412#line 54412 "ad_x86.cpp"
54413 }
54414}
54415
54416void vand16B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54417 cbuf.set_insts_mark();
54418 // Start at oper_input_base() and count operands
54419 unsigned idx0 = 2;
54420 unsigned idx1 = 2; // src
54421 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54422 {
54423 MacroAssembler _masm(&cbuf);
54424
54425#line 8905 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54426
54427 int vector_len = 0;
54428 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54429
54430#line 54430 "ad_x86.cpp"
54431 }
54432}
54433
54434void vand16B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54435 cbuf.set_insts_mark();
54436 // Start at oper_input_base() and count operands
54437 unsigned idx0 = 2;
54438 unsigned idx1 = 2; // mem
54439 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54440 {
54441 MacroAssembler _masm(&cbuf);
54442
54443#line 8905 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54444
54445 int vector_len = 0;
54446 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54447
54448#line 54448 "ad_x86.cpp"
54449 }
54450}
54451
54452void vand32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54453 cbuf.set_insts_mark();
54454 // Start at oper_input_base() and count operands
54455 unsigned idx0 = 1;
54456 unsigned idx1 = 1; // src1
54457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54458 {
54459 MacroAssembler _masm(&cbuf);
54460
54461#line 8916 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54462
54463 int vector_len = 1;
54464 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54465
54466#line 54466 "ad_x86.cpp"
54467 }
54468}
54469
54470void vand32B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54471 cbuf.set_insts_mark();
54472 // Start at oper_input_base() and count operands
54473 unsigned idx0 = 2;
54474 unsigned idx1 = 2; // src
54475 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54476 {
54477 MacroAssembler _masm(&cbuf);
54478
54479#line 8927 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54480
54481 int vector_len = 1;
54482 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54483
54484#line 54484 "ad_x86.cpp"
54485 }
54486}
54487
54488void vand32B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54489 cbuf.set_insts_mark();
54490 // Start at oper_input_base() and count operands
54491 unsigned idx0 = 2;
54492 unsigned idx1 = 2; // mem
54493 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54494 {
54495 MacroAssembler _masm(&cbuf);
54496
54497#line 8927 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54498
54499 int vector_len = 1;
54500 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54501
54502#line 54502 "ad_x86.cpp"
54503 }
54504}
54505
54506void vand64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54507 cbuf.set_insts_mark();
54508 // Start at oper_input_base() and count operands
54509 unsigned idx0 = 1;
54510 unsigned idx1 = 1; // src1
54511 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54512 {
54513 MacroAssembler _masm(&cbuf);
54514
54515#line 8938 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54516
54517 int vector_len = 2;
54518 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54519
54520#line 54520 "ad_x86.cpp"
54521 }
54522}
54523
54524void vand64B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54525 cbuf.set_insts_mark();
54526 // Start at oper_input_base() and count operands
54527 unsigned idx0 = 2;
54528 unsigned idx1 = 2; // src
54529 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54530 {
54531 MacroAssembler _masm(&cbuf);
54532
54533#line 8949 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54534
54535 int vector_len = 2;
54536 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54537
54538#line 54538 "ad_x86.cpp"
54539 }
54540}
54541
54542void vand64B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54543 cbuf.set_insts_mark();
54544 // Start at oper_input_base() and count operands
54545 unsigned idx0 = 2;
54546 unsigned idx1 = 2; // mem
54547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54548 {
54549 MacroAssembler _masm(&cbuf);
54550
54551#line 8949 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54552
54553 int vector_len = 2;
54554 __ vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54555
54556#line 54556 "ad_x86.cpp"
54557 }
54558}
54559
54560void vor4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54561 cbuf.set_insts_mark();
54562 // Start at oper_input_base() and count operands
54563 unsigned idx0 = 1;
54564 unsigned idx1 = 1; // dst
54565 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54566 {
54567 MacroAssembler _masm(&cbuf);
54568
54569#line 8962 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54570
54571 __ por(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54572
54573#line 54573 "ad_x86.cpp"
54574 }
54575}
54576
54577void vor4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54578 cbuf.set_insts_mark();
54579 // Start at oper_input_base() and count operands
54580 unsigned idx0 = 1;
54581 unsigned idx1 = 1; // src1
54582 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54583 {
54584 MacroAssembler _masm(&cbuf);
54585
54586#line 8972 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54587
54588 int vector_len = 0;
54589 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54590
54591#line 54591 "ad_x86.cpp"
54592 }
54593}
54594
54595void vor4B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54596 cbuf.set_insts_mark();
54597 // Start at oper_input_base() and count operands
54598 unsigned idx0 = 2;
54599 unsigned idx1 = 2; // src
54600 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54601 {
54602 MacroAssembler _masm(&cbuf);
54603
54604#line 8983 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54605
54606 int vector_len = 0;
54607 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54608
54609#line 54609 "ad_x86.cpp"
54610 }
54611}
54612
54613void vor4B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54614 cbuf.set_insts_mark();
54615 // Start at oper_input_base() and count operands
54616 unsigned idx0 = 2;
54617 unsigned idx1 = 2; // mem
54618 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54619 {
54620 MacroAssembler _masm(&cbuf);
54621
54622#line 8983 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54623
54624 int vector_len = 0;
54625 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54626
54627#line 54627 "ad_x86.cpp"
54628 }
54629}
54630
54631void vor8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54632 cbuf.set_insts_mark();
54633 // Start at oper_input_base() and count operands
54634 unsigned idx0 = 1;
54635 unsigned idx1 = 1; // dst
54636 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54637 {
54638 MacroAssembler _masm(&cbuf);
54639
54640#line 8994 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54641
54642 __ por(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54643
54644#line 54644 "ad_x86.cpp"
54645 }
54646}
54647
54648void vor8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54649 cbuf.set_insts_mark();
54650 // Start at oper_input_base() and count operands
54651 unsigned idx0 = 1;
54652 unsigned idx1 = 1; // src1
54653 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54654 {
54655 MacroAssembler _masm(&cbuf);
54656
54657#line 9004 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54658
54659 int vector_len = 0;
54660 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54661
54662#line 54662 "ad_x86.cpp"
54663 }
54664}
54665
54666void vor8B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54667 cbuf.set_insts_mark();
54668 // Start at oper_input_base() and count operands
54669 unsigned idx0 = 2;
54670 unsigned idx1 = 2; // src
54671 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54672 {
54673 MacroAssembler _masm(&cbuf);
54674
54675#line 9015 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54676
54677 int vector_len = 0;
54678 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54679
54680#line 54680 "ad_x86.cpp"
54681 }
54682}
54683
54684void vor8B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54685 cbuf.set_insts_mark();
54686 // Start at oper_input_base() and count operands
54687 unsigned idx0 = 2;
54688 unsigned idx1 = 2; // mem
54689 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54690 {
54691 MacroAssembler _masm(&cbuf);
54692
54693#line 9015 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54694
54695 int vector_len = 0;
54696 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54697
54698#line 54698 "ad_x86.cpp"
54699 }
54700}
54701
54702void vor16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54703 cbuf.set_insts_mark();
54704 // Start at oper_input_base() and count operands
54705 unsigned idx0 = 1;
54706 unsigned idx1 = 1; // dst
54707 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54708 {
54709 MacroAssembler _masm(&cbuf);
54710
54711#line 9026 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54712
54713 __ por(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54714
54715#line 54715 "ad_x86.cpp"
54716 }
54717}
54718
54719void vor16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54720 cbuf.set_insts_mark();
54721 // Start at oper_input_base() and count operands
54722 unsigned idx0 = 1;
54723 unsigned idx1 = 1; // src1
54724 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54725 {
54726 MacroAssembler _masm(&cbuf);
54727
54728#line 9036 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54729
54730 int vector_len = 0;
54731 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54732
54733#line 54733 "ad_x86.cpp"
54734 }
54735}
54736
54737void vor16B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54738 cbuf.set_insts_mark();
54739 // Start at oper_input_base() and count operands
54740 unsigned idx0 = 2;
54741 unsigned idx1 = 2; // src
54742 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54743 {
54744 MacroAssembler _masm(&cbuf);
54745
54746#line 9047 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54747
54748 int vector_len = 0;
54749 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54750
54751#line 54751 "ad_x86.cpp"
54752 }
54753}
54754
54755void vor16B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54756 cbuf.set_insts_mark();
54757 // Start at oper_input_base() and count operands
54758 unsigned idx0 = 2;
54759 unsigned idx1 = 2; // mem
54760 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54761 {
54762 MacroAssembler _masm(&cbuf);
54763
54764#line 9047 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54765
54766 int vector_len = 0;
54767 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54768
54769#line 54769 "ad_x86.cpp"
54770 }
54771}
54772
54773void vor32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54774 cbuf.set_insts_mark();
54775 // Start at oper_input_base() and count operands
54776 unsigned idx0 = 1;
54777 unsigned idx1 = 1; // src1
54778 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54779 {
54780 MacroAssembler _masm(&cbuf);
54781
54782#line 9058 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54783
54784 int vector_len = 1;
54785 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54786
54787#line 54787 "ad_x86.cpp"
54788 }
54789}
54790
54791void vor32B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54792 cbuf.set_insts_mark();
54793 // Start at oper_input_base() and count operands
54794 unsigned idx0 = 2;
54795 unsigned idx1 = 2; // src
54796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54797 {
54798 MacroAssembler _masm(&cbuf);
54799
54800#line 9069 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54801
54802 int vector_len = 1;
54803 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54804
54805#line 54805 "ad_x86.cpp"
54806 }
54807}
54808
54809void vor32B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54810 cbuf.set_insts_mark();
54811 // Start at oper_input_base() and count operands
54812 unsigned idx0 = 2;
54813 unsigned idx1 = 2; // mem
54814 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54815 {
54816 MacroAssembler _masm(&cbuf);
54817
54818#line 9069 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54819
54820 int vector_len = 1;
54821 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54822
54823#line 54823 "ad_x86.cpp"
54824 }
54825}
54826
54827void vor64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54828 cbuf.set_insts_mark();
54829 // Start at oper_input_base() and count operands
54830 unsigned idx0 = 1;
54831 unsigned idx1 = 1; // src1
54832 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54833 {
54834 MacroAssembler _masm(&cbuf);
54835
54836#line 9080 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54837
54838 int vector_len = 2;
54839 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54840
54841#line 54841 "ad_x86.cpp"
54842 }
54843}
54844
54845void vor64B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54846 cbuf.set_insts_mark();
54847 // Start at oper_input_base() and count operands
54848 unsigned idx0 = 2;
54849 unsigned idx1 = 2; // src
54850 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54851 {
54852 MacroAssembler _masm(&cbuf);
54853
54854#line 9091 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54855
54856 int vector_len = 2;
54857 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54858
54859#line 54859 "ad_x86.cpp"
54860 }
54861}
54862
54863void vor64B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54864 cbuf.set_insts_mark();
54865 // Start at oper_input_base() and count operands
54866 unsigned idx0 = 2;
54867 unsigned idx1 = 2; // mem
54868 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54869 {
54870 MacroAssembler _masm(&cbuf);
54871
54872#line 9091 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54873
54874 int vector_len = 2;
54875 __ vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54876
54877#line 54877 "ad_x86.cpp"
54878 }
54879}
54880
54881void vxor4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54882 cbuf.set_insts_mark();
54883 // Start at oper_input_base() and count operands
54884 unsigned idx0 = 1;
54885 unsigned idx1 = 1; // dst
54886 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54887 {
54888 MacroAssembler _masm(&cbuf);
54889
54890#line 9104 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54891
54892 __ pxor(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54893
54894#line 54894 "ad_x86.cpp"
54895 }
54896}
54897
54898void vxor4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54899 cbuf.set_insts_mark();
54900 // Start at oper_input_base() and count operands
54901 unsigned idx0 = 1;
54902 unsigned idx1 = 1; // src1
54903 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54904 {
54905 MacroAssembler _masm(&cbuf);
54906
54907#line 9114 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54908
54909 int vector_len = 0;
54910 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54911
54912#line 54912 "ad_x86.cpp"
54913 }
54914}
54915
54916void vxor4B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54917 cbuf.set_insts_mark();
54918 // Start at oper_input_base() and count operands
54919 unsigned idx0 = 2;
54920 unsigned idx1 = 2; // src
54921 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54922 {
54923 MacroAssembler _masm(&cbuf);
54924
54925#line 9125 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54926
54927 int vector_len = 0;
54928 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
54929
54930#line 54930 "ad_x86.cpp"
54931 }
54932}
54933
54934void vxor4B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54935 cbuf.set_insts_mark();
54936 // Start at oper_input_base() and count operands
54937 unsigned idx0 = 2;
54938 unsigned idx1 = 2; // mem
54939 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54940 {
54941 MacroAssembler _masm(&cbuf);
54942
54943#line 9125 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54944
54945 int vector_len = 0;
54946 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
54947
54948#line 54948 "ad_x86.cpp"
54949 }
54950}
54951
54952void vxor8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54953 cbuf.set_insts_mark();
54954 // Start at oper_input_base() and count operands
54955 unsigned idx0 = 1;
54956 unsigned idx1 = 1; // dst
54957 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
54958 {
54959 MacroAssembler _masm(&cbuf);
54960
54961#line 9136 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54962
54963 __ pxor(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
54964
54965#line 54965 "ad_x86.cpp"
54966 }
54967}
54968
54969void vxor8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54970 cbuf.set_insts_mark();
54971 // Start at oper_input_base() and count operands
54972 unsigned idx0 = 1;
54973 unsigned idx1 = 1; // src1
54974 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
54975 {
54976 MacroAssembler _masm(&cbuf);
54977
54978#line 9146 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54979
54980 int vector_len = 0;
54981 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
54982
54983#line 54983 "ad_x86.cpp"
54984 }
54985}
54986
54987void vxor8B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
54988 cbuf.set_insts_mark();
54989 // Start at oper_input_base() and count operands
54990 unsigned idx0 = 2;
54991 unsigned idx1 = 2; // src
54992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
54993 {
54994 MacroAssembler _masm(&cbuf);
54995
54996#line 9157 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
54997
54998 int vector_len = 0;
54999 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
55000
55001#line 55001 "ad_x86.cpp"
55002 }
55003}
55004
55005void vxor8B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55006 cbuf.set_insts_mark();
55007 // Start at oper_input_base() and count operands
55008 unsigned idx0 = 2;
55009 unsigned idx1 = 2; // mem
55010 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
55011 {
55012 MacroAssembler _masm(&cbuf);
55013
55014#line 9157 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55015
55016 int vector_len = 0;
55017 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
55018
55019#line 55019 "ad_x86.cpp"
55020 }
55021}
55022
55023void vxor16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55024 cbuf.set_insts_mark();
55025 // Start at oper_input_base() and count operands
55026 unsigned idx0 = 1;
55027 unsigned idx1 = 1; // dst
55028 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
55029 {
55030 MacroAssembler _masm(&cbuf);
55031
55032#line 9168 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55033
55034 __ pxor(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
55035
55036#line 55036 "ad_x86.cpp"
55037 }
55038}
55039
55040void vxor16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55041 cbuf.set_insts_mark();
55042 // Start at oper_input_base() and count operands
55043 unsigned idx0 = 1;
55044 unsigned idx1 = 1; // src1
55045 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
55046 {
55047 MacroAssembler _masm(&cbuf);
55048
55049#line 9178 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55050
55051 int vector_len = 0;
55052 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
55053
55054#line 55054 "ad_x86.cpp"
55055 }
55056}
55057
55058void vxor16B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55059 cbuf.set_insts_mark();
55060 // Start at oper_input_base() and count operands
55061 unsigned idx0 = 2;
55062 unsigned idx1 = 2; // src
55063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
55064 {
55065 MacroAssembler _masm(&cbuf);
55066
55067#line 9189 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55068
55069 int vector_len = 0;
55070 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
55071
55072#line 55072 "ad_x86.cpp"
55073 }
55074}
55075
55076void vxor16B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55077 cbuf.set_insts_mark();
55078 // Start at oper_input_base() and count operands
55079 unsigned idx0 = 2;
55080 unsigned idx1 = 2; // mem
55081 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
55082 {
55083 MacroAssembler _masm(&cbuf);
55084
55085#line 9189 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55086
55087 int vector_len = 0;
55088 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
55089
55090#line 55090 "ad_x86.cpp"
55091 }
55092}
55093
55094void vxor32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55095 cbuf.set_insts_mark();
55096 // Start at oper_input_base() and count operands
55097 unsigned idx0 = 1;
55098 unsigned idx1 = 1; // src1
55099 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
55100 {
55101 MacroAssembler _masm(&cbuf);
55102
55103#line 9200 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55104
55105 int vector_len = 1;
55106 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
55107
55108#line 55108 "ad_x86.cpp"
55109 }
55110}
55111
55112void vxor32B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55113 cbuf.set_insts_mark();
55114 // Start at oper_input_base() and count operands
55115 unsigned idx0 = 2;
55116 unsigned idx1 = 2; // src
55117 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
55118 {
55119 MacroAssembler _masm(&cbuf);
55120
55121#line 9211 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55122
55123 int vector_len = 1;
55124 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
55125
55126#line 55126 "ad_x86.cpp"
55127 }
55128}
55129
55130void vxor32B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55131 cbuf.set_insts_mark();
55132 // Start at oper_input_base() and count operands
55133 unsigned idx0 = 2;
55134 unsigned idx1 = 2; // mem
55135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
55136 {
55137 MacroAssembler _masm(&cbuf);
55138
55139#line 9211 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55140
55141 int vector_len = 1;
55142 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
55143
55144#line 55144 "ad_x86.cpp"
55145 }
55146}
55147
55148void vxor64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55149 cbuf.set_insts_mark();
55150 // Start at oper_input_base() and count operands
55151 unsigned idx0 = 1;
55152 unsigned idx1 = 1; // src1
55153 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
55154 {
55155 MacroAssembler _masm(&cbuf);
55156
55157#line 9222 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55158
55159 int vector_len = 2;
55160 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
55161
55162#line 55162 "ad_x86.cpp"
55163 }
55164}
55165
55166void vxor64B_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55167 cbuf.set_insts_mark();
55168 // Start at oper_input_base() and count operands
55169 unsigned idx0 = 2;
55170 unsigned idx1 = 2; // src
55171 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
55172 {
55173 MacroAssembler _masm(&cbuf);
55174
55175#line 9233 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55176
55177 int vector_len = 2;
55178 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vector_len);
55179
55180#line 55180 "ad_x86.cpp"
55181 }
55182}
55183
55184void vxor64B_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55185 cbuf.set_insts_mark();
55186 // Start at oper_input_base() and count operands
55187 unsigned idx0 = 2;
55188 unsigned idx1 = 2; // mem
55189 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
55190 {
55191 MacroAssembler _masm(&cbuf);
55192
55193#line 9233 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55194
55195 int vector_len = 2;
55196 __ vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
55197
55198#line 55198 "ad_x86.cpp"
55199 }
55200}
55201
55202void vabs4B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55203 cbuf.set_insts_mark();
55204 // Start at oper_input_base() and count operands
55205 unsigned idx0 = 1;
55206 unsigned idx1 = 1; // src
55207 {
55208 MacroAssembler _masm(&cbuf);
55209
55210#line 9246 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55211
55212 __ pabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55213
55214#line 55214 "ad_x86.cpp"
55215 }
55216}
55217
55218void vabs8B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55219 cbuf.set_insts_mark();
55220 // Start at oper_input_base() and count operands
55221 unsigned idx0 = 1;
55222 unsigned idx1 = 1; // src
55223 {
55224 MacroAssembler _masm(&cbuf);
55225
55226#line 9256 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55227
55228 __ pabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55229
55230#line 55230 "ad_x86.cpp"
55231 }
55232}
55233
55234void vabs16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55235 cbuf.set_insts_mark();
55236 // Start at oper_input_base() and count operands
55237 unsigned idx0 = 1;
55238 unsigned idx1 = 1; // src
55239 {
55240 MacroAssembler _masm(&cbuf);
55241
55242#line 9266 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55243
55244 __ pabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55245
55246#line 55246 "ad_x86.cpp"
55247 }
55248}
55249
55250void vabs32B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55251 cbuf.set_insts_mark();
55252 // Start at oper_input_base() and count operands
55253 unsigned idx0 = 1;
55254 unsigned idx1 = 1; // src
55255 {
55256 MacroAssembler _masm(&cbuf);
55257
55258#line 9276 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55259
55260 int vector_len = 1;
55261 __ vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55262
55263#line 55263 "ad_x86.cpp"
55264 }
55265}
55266
55267void vabs64B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55268 cbuf.set_insts_mark();
55269 // Start at oper_input_base() and count operands
55270 unsigned idx0 = 1;
55271 unsigned idx1 = 1; // src
55272 {
55273 MacroAssembler _masm(&cbuf);
55274
55275#line 9287 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55276
55277 int vector_len = 2;
55278 __ vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55279
55280#line 55280 "ad_x86.cpp"
55281 }
55282}
55283
55284void vabs2S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55285 cbuf.set_insts_mark();
55286 // Start at oper_input_base() and count operands
55287 unsigned idx0 = 1;
55288 unsigned idx1 = 1; // src
55289 {
55290 MacroAssembler _masm(&cbuf);
55291
55292#line 9298 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55293
55294 __ pabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55295
55296#line 55296 "ad_x86.cpp"
55297 }
55298}
55299
55300void vabs4S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55301 cbuf.set_insts_mark();
55302 // Start at oper_input_base() and count operands
55303 unsigned idx0 = 1;
55304 unsigned idx1 = 1; // src
55305 {
55306 MacroAssembler _masm(&cbuf);
55307
55308#line 9308 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55309
55310 __ pabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55311
55312#line 55312 "ad_x86.cpp"
55313 }
55314}
55315
55316void vabs8S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55317 cbuf.set_insts_mark();
55318 // Start at oper_input_base() and count operands
55319 unsigned idx0 = 1;
55320 unsigned idx1 = 1; // src
55321 {
55322 MacroAssembler _masm(&cbuf);
55323
55324#line 9318 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55325
55326 __ pabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55327
55328#line 55328 "ad_x86.cpp"
55329 }
55330}
55331
55332void vabs16S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55333 cbuf.set_insts_mark();
55334 // Start at oper_input_base() and count operands
55335 unsigned idx0 = 1;
55336 unsigned idx1 = 1; // src
55337 {
55338 MacroAssembler _masm(&cbuf);
55339
55340#line 9328 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55341
55342 int vector_len = 1;
55343 __ vpabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55344
55345#line 55345 "ad_x86.cpp"
55346 }
55347}
55348
55349void vabs32S_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55350 cbuf.set_insts_mark();
55351 // Start at oper_input_base() and count operands
55352 unsigned idx0 = 1;
55353 unsigned idx1 = 1; // src
55354 {
55355 MacroAssembler _masm(&cbuf);
55356
55357#line 9339 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55358
55359 int vector_len = 2;
55360 __ vpabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55361
55362#line 55362 "ad_x86.cpp"
55363 }
55364}
55365
55366void vabs2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55367 cbuf.set_insts_mark();
55368 // Start at oper_input_base() and count operands
55369 unsigned idx0 = 1;
55370 unsigned idx1 = 1; // src
55371 {
55372 MacroAssembler _masm(&cbuf);
55373
55374#line 9350 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55375
55376 __ pabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55377
55378#line 55378 "ad_x86.cpp"
55379 }
55380}
55381
55382void vabs4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55383 cbuf.set_insts_mark();
55384 // Start at oper_input_base() and count operands
55385 unsigned idx0 = 1;
55386 unsigned idx1 = 1; // src
55387 {
55388 MacroAssembler _masm(&cbuf);
55389
55390#line 9360 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55391
55392 __ pabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55393
55394#line 55394 "ad_x86.cpp"
55395 }
55396}
55397
55398void vabs8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55399 cbuf.set_insts_mark();
55400 // Start at oper_input_base() and count operands
55401 unsigned idx0 = 1;
55402 unsigned idx1 = 1; // src
55403 {
55404 MacroAssembler _masm(&cbuf);
55405
55406#line 9370 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55407
55408 int vector_len = 1;
55409 __ vpabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55410
55411#line 55411 "ad_x86.cpp"
55412 }
55413}
55414
55415void vabs16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55416 cbuf.set_insts_mark();
55417 // Start at oper_input_base() and count operands
55418 unsigned idx0 = 1;
55419 unsigned idx1 = 1; // src
55420 {
55421 MacroAssembler _masm(&cbuf);
55422
55423#line 9381 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55424
55425 int vector_len = 2;
55426 __ vpabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55427
55428#line 55428 "ad_x86.cpp"
55429 }
55430}
55431
55432void vabs2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55433 cbuf.set_insts_mark();
55434 // Start at oper_input_base() and count operands
55435 unsigned idx0 = 1;
55436 unsigned idx1 = 1; // src
55437 {
55438 MacroAssembler _masm(&cbuf);
55439
55440#line 9392 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55441
55442 int vector_len = 0;
55443 __ evpabsq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55444
55445#line 55445 "ad_x86.cpp"
55446 }
55447}
55448
55449void vabs4L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55450 cbuf.set_insts_mark();
55451 // Start at oper_input_base() and count operands
55452 unsigned idx0 = 1;
55453 unsigned idx1 = 1; // src
55454 {
55455 MacroAssembler _masm(&cbuf);
55456
55457#line 9403 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55458
55459 int vector_len = 1;
55460 __ evpabsq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55461
55462#line 55462 "ad_x86.cpp"
55463 }
55464}
55465
55466void vabs8L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55467 cbuf.set_insts_mark();
55468 // Start at oper_input_base() and count operands
55469 unsigned idx0 = 1;
55470 unsigned idx1 = 1; // src
55471 {
55472 MacroAssembler _masm(&cbuf);
55473
55474#line 9414 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55475
55476 int vector_len = 2;
55477 __ evpabsq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
55478
55479#line 55479 "ad_x86.cpp"
55480 }
55481}
55482
55483void vabsneg2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55484 cbuf.set_insts_mark();
55485 // Start at oper_input_base() and count operands
55486 unsigned idx0 = 1;
55487 unsigned idx1 = 1; // src
55488 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55489 {
55490 MacroAssembler _masm(&cbuf);
55491
55492#line 9429 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55493
55494 int opcode = this->as_Mach()->ideal_Opcode();
55495 if (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
55496 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55497 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55498
55499#line 55499 "ad_x86.cpp"
55500 }
55501}
55502
55503void vabsneg2D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55504 cbuf.set_insts_mark();
55505 // Start at oper_input_base() and count operands
55506 unsigned idx0 = 1;
55507 unsigned idx1 = 1; // src
55508 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55509 {
55510 MacroAssembler _masm(&cbuf);
55511
55512#line 9429 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55513
55514 int opcode = this->as_Mach()->ideal_Opcode();
55515 if (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
55516 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55517 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55518
55519#line 55519 "ad_x86.cpp"
55520 }
55521}
55522
55523void vabsneg4DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55524 cbuf.set_insts_mark();
55525 // Start at oper_input_base() and count operands
55526 unsigned idx0 = 1;
55527 unsigned idx1 = 1; // src
55528 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55529 {
55530 MacroAssembler _masm(&cbuf);
55531
55532#line 9444 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55533
55534 int opcode = this->as_Mach()->ideal_Opcode();
55535 int vector_len = 1;
55536 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55537
55538#line 55538 "ad_x86.cpp"
55539 }
55540}
55541
55542void vabsneg4D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55543 cbuf.set_insts_mark();
55544 // Start at oper_input_base() and count operands
55545 unsigned idx0 = 1;
55546 unsigned idx1 = 1; // src
55547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55548 {
55549 MacroAssembler _masm(&cbuf);
55550
55551#line 9444 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55552
55553 int opcode = this->as_Mach()->ideal_Opcode();
55554 int vector_len = 1;
55555 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55556
55557#line 55557 "ad_x86.cpp"
55558 }
55559}
55560
55561void vabsneg8DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55562 cbuf.set_insts_mark();
55563 // Start at oper_input_base() and count operands
55564 unsigned idx0 = 1;
55565 unsigned idx1 = 1; // src
55566 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55567 {
55568 MacroAssembler _masm(&cbuf);
55569
55570#line 9458 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55571
55572 int opcode = this->as_Mach()->ideal_Opcode();
55573 int vector_len = 2;
55574 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55575
55576#line 55576 "ad_x86.cpp"
55577 }
55578}
55579
55580void vabsneg8D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55581 cbuf.set_insts_mark();
55582 // Start at oper_input_base() and count operands
55583 unsigned idx0 = 1;
55584 unsigned idx1 = 1; // src
55585 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55586 {
55587 MacroAssembler _masm(&cbuf);
55588
55589#line 9458 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55590
55591 int opcode = this->as_Mach()->ideal_Opcode();
55592 int vector_len = 2;
55593 __ vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55594
55595#line 55595 "ad_x86.cpp"
55596 }
55597}
55598
55599void vabsneg2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55600 cbuf.set_insts_mark();
55601 // Start at oper_input_base() and count operands
55602 unsigned idx0 = 1;
55603 unsigned idx1 = 1; // src
55604 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55605 {
55606 MacroAssembler _masm(&cbuf);
55607
55608#line 9472 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55609
55610 int opcode = this->as_Mach()->ideal_Opcode();
55611 if (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
55612 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55613 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55614
55615#line 55615 "ad_x86.cpp"
55616 }
55617}
55618
55619void vabsneg2F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55620 cbuf.set_insts_mark();
55621 // Start at oper_input_base() and count operands
55622 unsigned idx0 = 1;
55623 unsigned idx1 = 1; // src
55624 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55625 {
55626 MacroAssembler _masm(&cbuf);
55627
55628#line 9472 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55629
55630 int opcode = this->as_Mach()->ideal_Opcode();
55631 if (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */)
55632 __ movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
55633 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55634
55635#line 55635 "ad_x86.cpp"
55636 }
55637}
55638
55639void vabsneg4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55640 cbuf.set_insts_mark();
55641 // Start at oper_input_base() and count operands
55642 unsigned idx0 = 1;
55643 unsigned idx1 = 1; // dst
55644 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55645 {
55646 MacroAssembler _masm(&cbuf);
55647
55648#line 9488 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55649
55650 int opcode = this->as_Mach()->ideal_Opcode();
55651 __ vabsnegf(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55652
55653#line 55653 "ad_x86.cpp"
55654 }
55655}
55656
55657void vabsneg4F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55658 cbuf.set_insts_mark();
55659 // Start at oper_input_base() and count operands
55660 unsigned idx0 = 1;
55661 unsigned idx1 = 1; // dst
55662 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55663 {
55664 MacroAssembler _masm(&cbuf);
55665
55666#line 9488 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55667
55668 int opcode = this->as_Mach()->ideal_Opcode();
55669 __ vabsnegf(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55670
55671#line 55671 "ad_x86.cpp"
55672 }
55673}
55674
55675void vabsneg8FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55676 cbuf.set_insts_mark();
55677 // Start at oper_input_base() and count operands
55678 unsigned idx0 = 1;
55679 unsigned idx1 = 1; // src
55680 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55681 {
55682 MacroAssembler _masm(&cbuf);
55683
55684#line 9502 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55685
55686 int opcode = this->as_Mach()->ideal_Opcode();
55687 int vector_len = 1;
55688 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55689
55690#line 55690 "ad_x86.cpp"
55691 }
55692}
55693
55694void vabsneg8F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55695 cbuf.set_insts_mark();
55696 // Start at oper_input_base() and count operands
55697 unsigned idx0 = 1;
55698 unsigned idx1 = 1; // src
55699 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55700 {
55701 MacroAssembler _masm(&cbuf);
55702
55703#line 9502 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55704
55705 int opcode = this->as_Mach()->ideal_Opcode();
55706 int vector_len = 1;
55707 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55708
55709#line 55709 "ad_x86.cpp"
55710 }
55711}
55712
55713void vabsneg16FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55714 cbuf.set_insts_mark();
55715 // Start at oper_input_base() and count operands
55716 unsigned idx0 = 1;
55717 unsigned idx1 = 1; // src
55718 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55719 {
55720 MacroAssembler _masm(&cbuf);
55721
55722#line 9517 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55723
55724 int opcode = this->as_Mach()->ideal_Opcode();
55725 int vector_len = 2;
55726 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55727
55728#line 55728 "ad_x86.cpp"
55729 }
55730}
55731
55732void vabsneg16F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55733 cbuf.set_insts_mark();
55734 // Start at oper_input_base() and count operands
55735 unsigned idx0 = 1;
55736 unsigned idx1 = 1; // src
55737 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
55738 {
55739 MacroAssembler _masm(&cbuf);
55740
55741#line 9517 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55742
55743 int opcode = this->as_Mach()->ideal_Opcode();
55744 int vector_len = 2;
55745 __ vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
55746
55747#line 55747 "ad_x86.cpp"
55748 }
55749}
55750
55751void vfma2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55752 cbuf.set_insts_mark();
55753 // Start at oper_input_base() and count operands
55754 unsigned idx0 = 1;
55755 unsigned idx1 = 1; // c
55756 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55757 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55758 {
55759 MacroAssembler _masm(&cbuf);
55760
55761#line 9533 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55762
55763 int vector_len = 0;
55764 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55765
55766#line 55766 "ad_x86.cpp"
55767 }
55768}
55769
55770void vfma2D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55771 cbuf.set_insts_mark();
55772 // Start at oper_input_base() and count operands
55773 unsigned idx0 = 2;
55774 unsigned idx1 = 2; // c
55775 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55776 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55777 {
55778 MacroAssembler _masm(&cbuf);
55779
55780#line 9546 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55781
55782 int vector_len = 0;
55783 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55784
55785#line 55785 "ad_x86.cpp"
55786 }
55787}
55788
55789void vfma4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55790 cbuf.set_insts_mark();
55791 // Start at oper_input_base() and count operands
55792 unsigned idx0 = 1;
55793 unsigned idx1 = 1; // c
55794 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55795 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55796 {
55797 MacroAssembler _masm(&cbuf);
55798
55799#line 9560 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55800
55801 int vector_len = 1;
55802 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55803
55804#line 55804 "ad_x86.cpp"
55805 }
55806}
55807
55808void vfma4D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55809 cbuf.set_insts_mark();
55810 // Start at oper_input_base() and count operands
55811 unsigned idx0 = 2;
55812 unsigned idx1 = 2; // c
55813 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55814 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55815 {
55816 MacroAssembler _masm(&cbuf);
55817
55818#line 9573 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55819
55820 int vector_len = 1;
55821 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55822
55823#line 55823 "ad_x86.cpp"
55824 }
55825}
55826
55827void vfma8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55828 cbuf.set_insts_mark();
55829 // Start at oper_input_base() and count operands
55830 unsigned idx0 = 1;
55831 unsigned idx1 = 1; // c
55832 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55833 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55834 {
55835 MacroAssembler _masm(&cbuf);
55836
55837#line 9586 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55838
55839 int vector_len = 2;
55840 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55841
55842#line 55842 "ad_x86.cpp"
55843 }
55844}
55845
55846void vfma8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55847 cbuf.set_insts_mark();
55848 // Start at oper_input_base() and count operands
55849 unsigned idx0 = 2;
55850 unsigned idx1 = 2; // c
55851 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55852 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55853 {
55854 MacroAssembler _masm(&cbuf);
55855
55856#line 9599 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55857
55858 int vector_len = 2;
55859 __ vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55860
55861#line 55861 "ad_x86.cpp"
55862 }
55863}
55864
55865void vfma4F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55866 cbuf.set_insts_mark();
55867 // Start at oper_input_base() and count operands
55868 unsigned idx0 = 1;
55869 unsigned idx1 = 1; // c
55870 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55871 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55872 {
55873 MacroAssembler _masm(&cbuf);
55874
55875#line 9612 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55876
55877 int vector_len = 0;
55878 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55879
55880#line 55880 "ad_x86.cpp"
55881 }
55882}
55883
55884void vfma4F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55885 cbuf.set_insts_mark();
55886 // Start at oper_input_base() and count operands
55887 unsigned idx0 = 2;
55888 unsigned idx1 = 2; // c
55889 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55890 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55891 {
55892 MacroAssembler _masm(&cbuf);
55893
55894#line 9625 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55895
55896 int vector_len = 0;
55897 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55898
55899#line 55899 "ad_x86.cpp"
55900 }
55901}
55902
55903void vfma8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55904 cbuf.set_insts_mark();
55905 // Start at oper_input_base() and count operands
55906 unsigned idx0 = 1;
55907 unsigned idx1 = 1; // c
55908 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55909 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55910 {
55911 MacroAssembler _masm(&cbuf);
55912
55913#line 9638 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55914
55915 int vector_len = 1;
55916 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55917
55918#line 55918 "ad_x86.cpp"
55919 }
55920}
55921
55922void vfma8F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55923 cbuf.set_insts_mark();
55924 // Start at oper_input_base() and count operands
55925 unsigned idx0 = 2;
55926 unsigned idx1 = 2; // c
55927 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55928 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55929 {
55930 MacroAssembler _masm(&cbuf);
55931
55932#line 9651 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55933
55934 int vector_len = 1;
55935 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55936
55937#line 55937 "ad_x86.cpp"
55938 }
55939}
55940
55941void vfma16F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55942 cbuf.set_insts_mark();
55943 // Start at oper_input_base() and count operands
55944 unsigned idx0 = 1;
55945 unsigned idx1 = 1; // c
55946 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55947 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55948 {
55949 MacroAssembler _masm(&cbuf);
55950
55951#line 9664 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55952
55953 int vector_len = 2;
55954 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55955
55956#line 55956 "ad_x86.cpp"
55957 }
55958}
55959
55960void vfma16F_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55961 cbuf.set_insts_mark();
55962 // Start at oper_input_base() and count operands
55963 unsigned idx0 = 2;
55964 unsigned idx1 = 2; // c
55965 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
55966 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
55967 {
55968 MacroAssembler _masm(&cbuf);
55969
55970#line 9677 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55971
55972 int vector_len = 2;
55973 __ vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vector_len);
55974
55975#line 55975 "ad_x86.cpp"
55976 }
55977}
55978
55979void smuladd4S2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55980 cbuf.set_insts_mark();
55981 // Start at oper_input_base() and count operands
55982 unsigned idx0 = 1;
55983 unsigned idx1 = 1; // dst
55984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
55985 {
55986 MacroAssembler _masm(&cbuf);
55987
55988#line 9690 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
55989
55990 __ pmaddwd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */);
55991
55992#line 55992 "ad_x86.cpp"
55993 }
55994}
55995
55996void vmuladd4S2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
55997 cbuf.set_insts_mark();
55998 // Start at oper_input_base() and count operands
55999 unsigned idx0 = 1;
56000 unsigned idx1 = 1; // src1
56001 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56002 {
56003 MacroAssembler _masm(&cbuf);
56004
56005#line 9700 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56006
56007 int vector_len = 0;
56008 __ vpmaddwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56009
56010#line 56010 "ad_x86.cpp"
56011 }
56012}
56013
56014void smuladd8S4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56015 cbuf.set_insts_mark();
56016 // Start at oper_input_base() and count operands
56017 unsigned idx0 = 1;
56018 unsigned idx1 = 1; // dst
56019 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
56020 {
56021 MacroAssembler _masm(&cbuf);
56022
56023#line 9711 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56024
56025 __ pmaddwd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */);
56026
56027#line 56027 "ad_x86.cpp"
56028 }
56029}
56030
56031void vmuladd8S4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56032 cbuf.set_insts_mark();
56033 // Start at oper_input_base() and count operands
56034 unsigned idx0 = 1;
56035 unsigned idx1 = 1; // src1
56036 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56037 {
56038 MacroAssembler _masm(&cbuf);
56039
56040#line 9721 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56041
56042 int vector_len = 0;
56043 __ vpmaddwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56044
56045#line 56045 "ad_x86.cpp"
56046 }
56047}
56048
56049void vmuladd16S8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56050 cbuf.set_insts_mark();
56051 // Start at oper_input_base() and count operands
56052 unsigned idx0 = 1;
56053 unsigned idx1 = 1; // src1
56054 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56055 {
56056 MacroAssembler _masm(&cbuf);
56057
56058#line 9732 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56059
56060 int vector_len = 1;
56061 __ vpmaddwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56062
56063#line 56063 "ad_x86.cpp"
56064 }
56065}
56066
56067void vmuladd32S16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56068 cbuf.set_insts_mark();
56069 // Start at oper_input_base() and count operands
56070 unsigned idx0 = 1;
56071 unsigned idx1 = 1; // src1
56072 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56073 {
56074 MacroAssembler _masm(&cbuf);
56075
56076#line 9743 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56077
56078 int vector_len = 2;
56079 __ vpmaddwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56080
56081#line 56081 "ad_x86.cpp"
56082 }
56083}
56084
56085void vmuladdadd4S2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56086 cbuf.set_insts_mark();
56087 // Start at oper_input_base() and count operands
56088 unsigned idx0 = 1;
56089 unsigned idx1 = 1; // src1
56090 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56091 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
56092 {
56093 MacroAssembler _masm(&cbuf);
56094
56095#line 9756 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56096
56097 int vector_len = 0;
56098 __ evpdpwssd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56099
56100#line 56100 "ad_x86.cpp"
56101 }
56102}
56103
56104void vmuladdadd4S2I_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56105 cbuf.set_insts_mark();
56106 // Start at oper_input_base() and count operands
56107 unsigned idx0 = 1;
56108 unsigned idx1 = 1; // dst
56109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
56110 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
56111 {
56112 MacroAssembler _masm(&cbuf);
56113
56114#line 9756 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56115
56116 int vector_len = 0;
56117 __ evpdpwssd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src2 */, vector_len);
56118
56119#line 56119 "ad_x86.cpp"
56120 }
56121}
56122
56123void vmuladdadd8S4I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56124 cbuf.set_insts_mark();
56125 // Start at oper_input_base() and count operands
56126 unsigned idx0 = 1;
56127 unsigned idx1 = 1; // src1
56128 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56129 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
56130 {
56131 MacroAssembler _masm(&cbuf);
56132
56133#line 9768 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56134
56135 int vector_len = 0;
56136 __ evpdpwssd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56137
56138#line 56138 "ad_x86.cpp"
56139 }
56140}
56141
56142void vmuladdadd8S4I_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56143 cbuf.set_insts_mark();
56144 // Start at oper_input_base() and count operands
56145 unsigned idx0 = 1;
56146 unsigned idx1 = 1; // dst
56147 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
56148 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
56149 {
56150 MacroAssembler _masm(&cbuf);
56151
56152#line 9768 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56153
56154 int vector_len = 0;
56155 __ evpdpwssd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src2 */, vector_len);
56156
56157#line 56157 "ad_x86.cpp"
56158 }
56159}
56160
56161void vmuladdadd16S8I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56162 cbuf.set_insts_mark();
56163 // Start at oper_input_base() and count operands
56164 unsigned idx0 = 1;
56165 unsigned idx1 = 1; // src1
56166 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56167 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
56168 {
56169 MacroAssembler _masm(&cbuf);
56170
56171#line 9780 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56172
56173 int vector_len = 1;
56174 __ evpdpwssd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56175
56176#line 56176 "ad_x86.cpp"
56177 }
56178}
56179
56180void vmuladdadd16S8I_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56181 cbuf.set_insts_mark();
56182 // Start at oper_input_base() and count operands
56183 unsigned idx0 = 1;
56184 unsigned idx1 = 1; // dst
56185 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
56186 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
56187 {
56188 MacroAssembler _masm(&cbuf);
56189
56190#line 9780 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56191
56192 int vector_len = 1;
56193 __ evpdpwssd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src2 */, vector_len);
56194
56195#line 56195 "ad_x86.cpp"
56196 }
56197}
56198
56199void vmuladdadd32S16I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56200 cbuf.set_insts_mark();
56201 // Start at oper_input_base() and count operands
56202 unsigned idx0 = 1;
56203 unsigned idx1 = 1; // src1
56204 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
56205 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
56206 {
56207 MacroAssembler _masm(&cbuf);
56208
56209#line 9792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56210
56211 int vector_len = 2;
56212 __ evpdpwssd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vector_len);
56213
56214#line 56214 "ad_x86.cpp"
56215 }
56216}
56217
56218void vmuladdadd32S16I_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56219 cbuf.set_insts_mark();
56220 // Start at oper_input_base() and count operands
56221 unsigned idx0 = 1;
56222 unsigned idx1 = 1; // dst
56223 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
56224 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
56225 {
56226 MacroAssembler _masm(&cbuf);
56227
56228#line 9792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56229
56230 int vector_len = 2;
56231 __ evpdpwssd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src2 */, vector_len);
56232
56233#line 56233 "ad_x86.cpp"
56234 }
56235}
56236
56237void vpopcount2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56238 cbuf.set_insts_mark();
56239 // Start at oper_input_base() and count operands
56240 unsigned idx0 = 1;
56241 unsigned idx1 = 1; // src
56242 {
56243 MacroAssembler _masm(&cbuf);
56244
56245#line 9806 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56246
56247 int vector_len = 0;
56248 __ vpopcntd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
56249
56250#line 56250 "ad_x86.cpp"
56251 }
56252}
56253
56254void vpopcount4INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56255 cbuf.set_insts_mark();
56256 // Start at oper_input_base() and count operands
56257 unsigned idx0 = 1;
56258 unsigned idx1 = 1; // src
56259 {
56260 MacroAssembler _masm(&cbuf);
56261
56262#line 9817 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56263
56264 int vector_len = 0;
56265 __ vpopcntd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
56266
56267#line 56267 "ad_x86.cpp"
56268 }
56269}
56270
56271void vpopcount8INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56272 cbuf.set_insts_mark();
56273 // Start at oper_input_base() and count operands
56274 unsigned idx0 = 1;
56275 unsigned idx1 = 1; // src
56276 {
56277 MacroAssembler _masm(&cbuf);
56278
56279#line 9828 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56280
56281 int vector_len = 1;
56282 __ vpopcntd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
56283
56284#line 56284 "ad_x86.cpp"
56285 }
56286}
56287
56288void vpopcount16INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56289 cbuf.set_insts_mark();
56290 // Start at oper_input_base() and count operands
56291 unsigned idx0 = 1;
56292 unsigned idx1 = 1; // src
56293 {
56294 MacroAssembler _masm(&cbuf);
56295
56296#line 9839 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad"
56297
56298 int vector_len = 2;
56299 __ vpopcntd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vector_len);
56300
56301#line 56301 "ad_x86.cpp"
56302 }
56303}
56304
56305void compareAndSwapP_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56306 cbuf.set_insts_mark();
56307 // Start at oper_input_base() and count operands
56308 unsigned idx0 = 2;
56309 unsigned idx1 = 2; // mem_ptr
56310 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56311 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56312 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56313 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56314 {
56315 MacroAssembler _masm(&cbuf);
56316
56317#line 42 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56318
56319 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56320 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56321 false, // swap
56322 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56323
56324#line 56324 "ad_x86.cpp"
56325 }
56326}
56327
56328void compareAndSwapP_shenandoah_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56329 cbuf.set_insts_mark();
56330 // Start at oper_input_base() and count operands
56331 unsigned idx0 = 2;
56332 unsigned idx1 = 2; // mem_ptr
56333 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56334 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56335 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56336 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56337 {
56338 MacroAssembler _masm(&cbuf);
56339
56340#line 42 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56341
56342 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56343 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56344 false, // swap
56345 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56346
56347#line 56347 "ad_x86.cpp"
56348 }
56349}
56350
56351void compareAndSwapN_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56352 cbuf.set_insts_mark();
56353 // Start at oper_input_base() and count operands
56354 unsigned idx0 = 2;
56355 unsigned idx1 = 2; // mem_ptr
56356 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56357 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56358 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56359 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56360 {
56361 MacroAssembler _masm(&cbuf);
56362
56363#line 63 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56364
56365 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56366 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56367 false, // swap
56368 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56369
56370#line 56370 "ad_x86.cpp"
56371 }
56372}
56373
56374void compareAndSwapN_shenandoah_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56375 cbuf.set_insts_mark();
56376 // Start at oper_input_base() and count operands
56377 unsigned idx0 = 2;
56378 unsigned idx1 = 2; // mem_ptr
56379 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56380 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56381 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56382 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56383 {
56384 MacroAssembler _masm(&cbuf);
56385
56386#line 63 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56387
56388 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56389 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56390 false, // swap
56391 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56392
56393#line 56393 "ad_x86.cpp"
56394 }
56395}
56396
56397void compareAndExchangeN_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56398 cbuf.set_insts_mark();
56399 // Start at oper_input_base() and count operands
56400 unsigned idx0 = 2;
56401 unsigned idx1 = 2; // mem_ptr
56402 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56403 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56404 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56405 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56406 {
56407 MacroAssembler _masm(&cbuf);
56408
56409#line 82 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56410
56411 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56412 NULL, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56413 true, // exchange
56414 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56415
56416#line 56416 "ad_x86.cpp"
56417 }
56418}
56419
56420void compareAndExchangeP_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56421 cbuf.set_insts_mark();
56422 // Start at oper_input_base() and count operands
56423 unsigned idx0 = 2;
56424 unsigned idx1 = 2; // mem_ptr
56425 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
56426 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
56427 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
56428 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
56429 {
56430 MacroAssembler _masm(&cbuf);
56431
56432#line 104 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
56433
56434 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
56435 NULL, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
56436 true, // exchange
56437 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
56438
56439#line 56439 "ad_x86.cpp"
56440 }
56441}
56442
56443void zLoadBarrierSlowRegXmmAndYmmNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56444 cbuf.set_insts_mark();
56445 // Start at oper_input_base() and count operands
56446 unsigned idx0 = 1;
56447 unsigned idx1 = 1; // src
56448 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
56449 {
56450 MacroAssembler _masm(&cbuf);
56451
56452#line 64 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
56453
56454 z_load_barrier_slow_reg(_masm, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), false /* weak */);
56455
56456#line 56456 "ad_x86.cpp"
56457 }
56458}
56459
56460void zLoadBarrierSlowRegZmmNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56461 cbuf.set_insts_mark();
56462 // Start at oper_input_base() and count operands
56463 unsigned idx0 = 1;
56464 unsigned idx1 = 1; // src
56465 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
56466 {
56467 MacroAssembler _masm(&cbuf);
56468
56469#line 97 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
56470
56471 z_load_barrier_slow_reg(_masm, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), false /* weak */);
56472
56473#line 56473 "ad_x86.cpp"
56474 }
56475}
56476
56477void zLoadBarrierWeakSlowRegXmmAndYmmNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56478 cbuf.set_insts_mark();
56479 // Start at oper_input_base() and count operands
56480 unsigned idx0 = 1;
56481 unsigned idx1 = 1; // src
56482 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
56483 {
56484 MacroAssembler _masm(&cbuf);
56485
56486#line 121 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
56487
56488 z_load_barrier_slow_reg(_masm, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), true /* weak */);
56489
56490#line 56490 "ad_x86.cpp"
56491 }
56492}
56493
56494void zLoadBarrierWeakSlowRegZmmNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56495 cbuf.set_insts_mark();
56496 // Start at oper_input_base() and count operands
56497 unsigned idx0 = 1;
56498 unsigned idx1 = 1; // src
56499 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
56500 {
56501 MacroAssembler _masm(&cbuf);
56502
56503#line 154 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
56504
56505 z_load_barrier_slow_reg(_masm, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), true /* weak */);
56506
56507#line 56507 "ad_x86.cpp"
56508 }
56509}
56510
56511void z_compareAndExchangePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56512 cbuf.set_insts_mark();
56513 // Start at oper_input_base() and count operands
56514 unsigned idx0 = 2;
56515 unsigned idx1 = 2; // mem_ptr
56516 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
56517 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
56518 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
56519 {
56520
56521#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56522
56523 emit_opcode(cbuf, 0xF0); // lock
56524
56525#line 56525 "ad_x86.cpp"
56526 }
56527 {
56528
56529#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56530
56531 if (opnd_array(4)->reg(ra_,this,idx4)/* newval */ < 8) {
56532 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56533 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56534 emit_opcode(cbuf, Assembler::REX_W);
56535 } else {
56536 emit_opcode(cbuf, Assembler::REX_WX);
56537 }
56538 } else {
56539 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56540 emit_opcode(cbuf, Assembler::REX_WB);
56541 } else {
56542 emit_opcode(cbuf, Assembler::REX_WXB);
56543 }
56544 }
56545 } else {
56546 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56547 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56548 emit_opcode(cbuf, Assembler::REX_WR);
56549 } else {
56550 emit_opcode(cbuf, Assembler::REX_WRX);
56551 }
56552 } else {
56553 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56554 emit_opcode(cbuf, Assembler::REX_WRB);
56555 } else {
56556 emit_opcode(cbuf, Assembler::REX_WRXB);
56557 }
56558 }
56559 }
56560
56561#line 56561 "ad_x86.cpp"
56562 }
56563 {
56564
56565#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56566
56567 emit_opcode(cbuf, (0x0F /*primary()*/));
56568
56569#line 56569 "ad_x86.cpp"
56570 }
56571 {
56572
56573#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56574
56575 emit_opcode(cbuf, (0xB1 /*secondary()*/));
56576
56577#line 56577 "ad_x86.cpp"
56578 }
56579 {
56580
56581#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56582
56583 // High registers handle in encode_RegMem
56584 int reg = opnd_array(4)->reg(ra_,this,idx4)/* newval */;
56585 int base = opnd_array(1)->base(ra_,this,idx1);
56586 int index = opnd_array(1)->index(ra_,this,idx1);
56587 int scale = opnd_array(1)->scale();
56588 int disp = opnd_array(1)->disp(ra_,this,idx1);
56589 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
56590
56591 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
56592
56593#line 56593 "ad_x86.cpp"
56594 }
56595}
56596
56597void z_compareAndSwapPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56598 cbuf.set_insts_mark();
56599 // Start at oper_input_base() and count operands
56600 unsigned idx0 = 2;
56601 unsigned idx1 = 2; // mem_ptr
56602 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
56603 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
56604 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
56605 {
56606
56607#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56608
56609 emit_opcode(cbuf, 0xF0); // lock
56610
56611#line 56611 "ad_x86.cpp"
56612 }
56613 {
56614
56615#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56616
56617 if (opnd_array(4)->reg(ra_,this,idx4)/* newval */ < 8) {
56618 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56619 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56620 emit_opcode(cbuf, Assembler::REX_W);
56621 } else {
56622 emit_opcode(cbuf, Assembler::REX_WX);
56623 }
56624 } else {
56625 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56626 emit_opcode(cbuf, Assembler::REX_WB);
56627 } else {
56628 emit_opcode(cbuf, Assembler::REX_WXB);
56629 }
56630 }
56631 } else {
56632 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56633 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56634 emit_opcode(cbuf, Assembler::REX_WR);
56635 } else {
56636 emit_opcode(cbuf, Assembler::REX_WRX);
56637 }
56638 } else {
56639 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56640 emit_opcode(cbuf, Assembler::REX_WRB);
56641 } else {
56642 emit_opcode(cbuf, Assembler::REX_WRXB);
56643 }
56644 }
56645 }
56646
56647#line 56647 "ad_x86.cpp"
56648 }
56649 {
56650
56651#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56652
56653 emit_opcode(cbuf, (0x0F /*primary()*/));
56654
56655#line 56655 "ad_x86.cpp"
56656 }
56657 {
56658
56659#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56660
56661 emit_opcode(cbuf, (0xB1 /*secondary()*/));
56662
56663#line 56663 "ad_x86.cpp"
56664 }
56665 {
56666
56667#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56668
56669 // High registers handle in encode_RegMem
56670 int reg = opnd_array(4)->reg(ra_,this,idx4)/* newval */;
56671 int base = opnd_array(1)->base(ra_,this,idx1);
56672 int index = opnd_array(1)->index(ra_,this,idx1);
56673 int scale = opnd_array(1)->scale();
56674 int disp = opnd_array(1)->disp(ra_,this,idx1);
56675 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
56676
56677 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
56678
56679#line 56679 "ad_x86.cpp"
56680 }
56681 {
56682
56683#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56684
56685 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
56686 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
56687 }
56688
56689#line 56689 "ad_x86.cpp"
56690 }
56691 {
56692
56693#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56694
56695 emit_opcode(cbuf, (0x0F));
56696
56697#line 56697 "ad_x86.cpp"
56698 }
56699 {
56700
56701#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56702
56703 emit_opcode(cbuf, (0x94));
56704
56705#line 56705 "ad_x86.cpp"
56706 }
56707 {
56708
56709#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56710
56711 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
56712
56713#line 56713 "ad_x86.cpp"
56714 }
56715 {
56716
56717#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56718
56719 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
56720 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
56721 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
56722 }
56723 } else {
56724 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
56725 emit_opcode(cbuf, Assembler::REX_R);
56726 } else {
56727 emit_opcode(cbuf, Assembler::REX_RB);
56728 }
56729 }
56730
56731#line 56731 "ad_x86.cpp"
56732 }
56733 {
56734
56735#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56736
56737 emit_opcode(cbuf, (0xF));
56738
56739#line 56739 "ad_x86.cpp"
56740 }
56741 {
56742
56743#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56744
56745 emit_opcode(cbuf, (0xB6));
56746
56747#line 56747 "ad_x86.cpp"
56748 }
56749 {
56750
56751#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56752
56753 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
56754
56755#line 56755 "ad_x86.cpp"
56756 }
56757}
56758
56759void z_compareAndSwapP_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56760 cbuf.set_insts_mark();
56761 // Start at oper_input_base() and count operands
56762 unsigned idx0 = 2;
56763 unsigned idx1 = 2; // mem_ptr
56764 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
56765 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
56766 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
56767 {
56768
56769#line 2331 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56770
56771 emit_opcode(cbuf, 0xF0); // lock
56772
56773#line 56773 "ad_x86.cpp"
56774 }
56775 {
56776
56777#line 2505 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56778
56779 if (opnd_array(4)->reg(ra_,this,idx4)/* newval */ < 8) {
56780 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56781 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56782 emit_opcode(cbuf, Assembler::REX_W);
56783 } else {
56784 emit_opcode(cbuf, Assembler::REX_WX);
56785 }
56786 } else {
56787 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56788 emit_opcode(cbuf, Assembler::REX_WB);
56789 } else {
56790 emit_opcode(cbuf, Assembler::REX_WXB);
56791 }
56792 }
56793 } else {
56794 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
56795 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56796 emit_opcode(cbuf, Assembler::REX_WR);
56797 } else {
56798 emit_opcode(cbuf, Assembler::REX_WRX);
56799 }
56800 } else {
56801 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
56802 emit_opcode(cbuf, Assembler::REX_WRB);
56803 } else {
56804 emit_opcode(cbuf, Assembler::REX_WRXB);
56805 }
56806 }
56807 }
56808
56809#line 56809 "ad_x86.cpp"
56810 }
56811 {
56812
56813#line 1812 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56814
56815 emit_opcode(cbuf, (0x0F /*primary()*/));
56816
56817#line 56817 "ad_x86.cpp"
56818 }
56819 {
56820
56821#line 1818 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56822
56823 emit_opcode(cbuf, (0xB1 /*secondary()*/));
56824
56825#line 56825 "ad_x86.cpp"
56826 }
56827 {
56828
56829#line 2538 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56830
56831 // High registers handle in encode_RegMem
56832 int reg = opnd_array(4)->reg(ra_,this,idx4)/* newval */;
56833 int base = opnd_array(1)->base(ra_,this,idx1);
56834 int index = opnd_array(1)->index(ra_,this,idx1);
56835 int scale = opnd_array(1)->scale();
56836 int disp = opnd_array(1)->disp(ra_,this,idx1);
56837 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
56838
56839 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
56840
56841#line 56841 "ad_x86.cpp"
56842 }
56843 {
56844
56845#line 2369 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56846
56847 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
56848 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
56849 }
56850
56851#line 56851 "ad_x86.cpp"
56852 }
56853 {
56854
56855#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56856
56857 emit_opcode(cbuf, (0x0F));
56858
56859#line 56859 "ad_x86.cpp"
56860 }
56861 {
56862
56863#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56864
56865 emit_opcode(cbuf, (0x94));
56866
56867#line 56867 "ad_x86.cpp"
56868 }
56869 {
56870
56871#line 1841 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56872
56873 emit_rm(cbuf, 0x3, 0, opnd_array(0)->reg(ra_,this)/* res */ & 7);
56874
56875#line 56875 "ad_x86.cpp"
56876 }
56877 {
56878
56879#line 2377 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56880
56881 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
56882 if (opnd_array(0)->reg(ra_,this)/* res */ >= 4) {
56883 emit_opcode(cbuf, opnd_array(0)->reg(ra_,this)/* res */ < 8 ? Assembler::REX : Assembler::REX_B);
56884 }
56885 } else {
56886 if (opnd_array(0)->reg(ra_,this)/* res */ < 8) {
56887 emit_opcode(cbuf, Assembler::REX_R);
56888 } else {
56889 emit_opcode(cbuf, Assembler::REX_RB);
56890 }
56891 }
56892
56893#line 56893 "ad_x86.cpp"
56894 }
56895 {
56896
56897#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56898
56899 emit_opcode(cbuf, (0xF));
56900
56901#line 56901 "ad_x86.cpp"
56902 }
56903 {
56904
56905#line 1830 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56906
56907 emit_opcode(cbuf, (0xB6));
56908
56909#line 56909 "ad_x86.cpp"
56910 }
56911 {
56912
56913#line 1846 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
56914
56915 emit_rm(cbuf, 0x3, opnd_array(0)->reg(ra_,this)/* res */ & 7, opnd_array(0)->reg(ra_,this)/* res */ & 7);
56916
56917#line 56917 "ad_x86.cpp"
56918 }
56919}
56920
56921void z_xchgPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
56922 cbuf.set_insts_mark();
56923 // Start at oper_input_base() and count operands
56924 unsigned idx0 = 2;
56925 unsigned idx1 = 2; // mem
56926 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
56927 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // keepalive
56928 {
56929 MacroAssembler _masm(&cbuf);
56930
56931#line 209 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
56932
56933 __ xchgq(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
56934
56935#line 56935 "ad_x86.cpp"
56936 }
56937}
56938
56939const MachOper* loadBNode::memory_operand() const { return _opnds[1]; }
56940const MachOper* loadB2LNode::memory_operand() const { return _opnds[1]; }
56941const MachOper* loadUBNode::memory_operand() const { return _opnds[1]; }
56942const MachOper* loadUB2LNode::memory_operand() const { return _opnds[1]; }
56943const MachOper* loadUB2L_immINode::memory_operand() const { return _opnds[1]; }
56944const MachOper* loadSNode::memory_operand() const { return _opnds[1]; }
56945const MachOper* loadS2BNode::memory_operand() const { return _opnds[1]; }
56946const MachOper* loadS2LNode::memory_operand() const { return _opnds[1]; }
56947const MachOper* loadUSNode::memory_operand() const { return _opnds[1]; }
56948const MachOper* loadUS2BNode::memory_operand() const { return _opnds[1]; }
56949const MachOper* loadUS2LNode::memory_operand() const { return _opnds[1]; }
56950const MachOper* loadUS2L_immI_255Node::memory_operand() const { return _opnds[1]; }
56951const MachOper* loadUS2L_immINode::memory_operand() const { return _opnds[1]; }
56952const MachOper* loadINode::memory_operand() const { return _opnds[1]; }
56953const MachOper* loadI2BNode::memory_operand() const { return _opnds[1]; }
56954const MachOper* loadI2UBNode::memory_operand() const { return _opnds[1]; }
56955const MachOper* loadI2SNode::memory_operand() const { return _opnds[1]; }
56956const MachOper* loadI2USNode::memory_operand() const { return _opnds[1]; }
56957const MachOper* loadI2LNode::memory_operand() const { return _opnds[1]; }
56958const MachOper* loadI2L_immI_255Node::memory_operand() const { return _opnds[1]; }
56959const MachOper* loadI2L_immI_65535Node::memory_operand() const { return _opnds[1]; }
56960const MachOper* loadI2L_immU31Node::memory_operand() const { return _opnds[1]; }
56961const MachOper* loadUI2LNode::memory_operand() const { return _opnds[1]; }
56962const MachOper* loadLNode::memory_operand() const { return _opnds[1]; }
56963const MachOper* loadRangeNode::memory_operand() const { return _opnds[1]; }
56964const MachOper* loadPNode::memory_operand() const { return _opnds[1]; }
56965const MachOper* loadNNode::memory_operand() const { return _opnds[1]; }
56966const MachOper* loadKlassNode::memory_operand() const { return _opnds[1]; }
56967const MachOper* loadNKlassNode::memory_operand() const { return _opnds[1]; }
56968const MachOper* loadFNode::memory_operand() const { return _opnds[1]; }
56969const MachOper* loadD_partialNode::memory_operand() const { return _opnds[1]; }
56970const MachOper* loadDNode::memory_operand() const { return _opnds[1]; }
56971const MachOper* prefetchAllocNode::memory_operand() const { return _opnds[1]; }
56972const MachOper* prefetchAllocNTANode::memory_operand() const { return _opnds[1]; }
56973const MachOper* prefetchAllocT0Node::memory_operand() const { return _opnds[1]; }
56974const MachOper* prefetchAllocT2Node::memory_operand() const { return _opnds[1]; }
56975const MachOper* storeBNode::memory_operand() const { return _opnds[1]; }
56976const MachOper* storeCNode::memory_operand() const { return _opnds[1]; }
56977const MachOper* storeINode::memory_operand() const { return _opnds[1]; }
56978const MachOper* storeLNode::memory_operand() const { return _opnds[1]; }
56979const MachOper* storePNode::memory_operand() const { return _opnds[1]; }
56980const MachOper* storeImmP0Node::memory_operand() const { return _opnds[1]; }
56981const MachOper* storeImmPNode::memory_operand() const { return _opnds[1]; }
56982const MachOper* storeNNode::memory_operand() const { return _opnds[1]; }
56983const MachOper* storeNKlassNode::memory_operand() const { return _opnds[1]; }
56984const MachOper* storeImmN0Node::memory_operand() const { return _opnds[1]; }
56985const MachOper* storeImmNNode::memory_operand() const { return _opnds[1]; }
56986const MachOper* storeImmNKlassNode::memory_operand() const { return _opnds[1]; }
56987const MachOper* storeImmI0Node::memory_operand() const { return _opnds[1]; }
56988const MachOper* storeImmINode::memory_operand() const { return _opnds[1]; }
56989const MachOper* storeImmL0Node::memory_operand() const { return _opnds[1]; }
56990const MachOper* storeImmLNode::memory_operand() const { return _opnds[1]; }
56991const MachOper* storeImmC0Node::memory_operand() const { return _opnds[1]; }
56992const MachOper* storeImmI16Node::memory_operand() const { return _opnds[1]; }
56993const MachOper* storeImmB0Node::memory_operand() const { return _opnds[1]; }
56994const MachOper* storeImmBNode::memory_operand() const { return _opnds[1]; }
56995const MachOper* storeImmCM0_regNode::memory_operand() const { return _opnds[1]; }
56996const MachOper* storeImmCM0Node::memory_operand() const { return _opnds[1]; }
56997const MachOper* storeFNode::memory_operand() const { return _opnds[1]; }
56998const MachOper* storeF0Node::memory_operand() const { return _opnds[1]; }
56999const MachOper* storeF_immNode::memory_operand() const { return _opnds[1]; }
57000const MachOper* storeDNode::memory_operand() const { return _opnds[1]; }
57001const MachOper* storeD0_immNode::memory_operand() const { return _opnds[1]; }
57002const MachOper* storeD0Node::memory_operand() const { return _opnds[1]; }
57003const MachOper* popCountI_memNode::memory_operand() const { return _opnds[1]; }
57004const MachOper* popCountL_memNode::memory_operand() const { return _opnds[1]; }
57005const MachOper* cmovI_memNode::memory_operand() const { return _opnds[4]; }
57006const MachOper* cmovI_memUNode::memory_operand() const { return _opnds[4]; }
57007const MachOper* cmovI_memUCFNode::memory_operand() const { return _opnds[4]; }
57008const MachOper* cmovL_memNode::memory_operand() const { return _opnds[4]; }
57009const MachOper* cmovL_memUNode::memory_operand() const { return _opnds[4]; }
57010const MachOper* cmovL_memUCFNode::memory_operand() const { return _opnds[4]; }
57011const MachOper* addI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57012const MachOper* addI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57013const MachOper* addI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57014const MachOper* addI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57015const MachOper* addI_mem_immNode::memory_operand() const { return _opnds[1]; }
57016const MachOper* incI_memNode::memory_operand() const { return _opnds[1]; }
57017const MachOper* decI_memNode::memory_operand() const { return _opnds[1]; }
57018const MachOper* addL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57019const MachOper* addL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57020const MachOper* addL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57021const MachOper* addL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57022const MachOper* addL_mem_immNode::memory_operand() const { return _opnds[1]; }
57023const MachOper* incL_memNode::memory_operand() const { return _opnds[1]; }
57024const MachOper* decL_memNode::memory_operand() const { return _opnds[1]; }
57025const MachOper* loadPLockedNode::memory_operand() const { return _opnds[1]; }
57026const MachOper* storePConditionalNode::memory_operand() const { return _opnds[1]; }
57027const MachOper* storeIConditionalNode::memory_operand() const { return _opnds[1]; }
57028const MachOper* storeLConditionalNode::memory_operand() const { return _opnds[1]; }
57029const MachOper* compareAndSwapPNode::memory_operand() const { return _opnds[1]; }
57030const MachOper* compareAndSwapP_0Node::memory_operand() const { return _opnds[1]; }
57031const MachOper* compareAndSwapLNode::memory_operand() const { return _opnds[1]; }
57032const MachOper* compareAndSwapL_0Node::memory_operand() const { return _opnds[1]; }
57033const MachOper* compareAndSwapINode::memory_operand() const { return _opnds[1]; }
57034const MachOper* compareAndSwapI_0Node::memory_operand() const { return _opnds[1]; }
57035const MachOper* compareAndSwapBNode::memory_operand() const { return _opnds[1]; }
57036const MachOper* compareAndSwapB_0Node::memory_operand() const { return _opnds[1]; }
57037const MachOper* compareAndSwapSNode::memory_operand() const { return _opnds[1]; }
57038const MachOper* compareAndSwapS_0Node::memory_operand() const { return _opnds[1]; }
57039const MachOper* compareAndSwapNNode::memory_operand() const { return _opnds[1]; }
57040const MachOper* compareAndSwapN_0Node::memory_operand() const { return _opnds[1]; }
57041const MachOper* compareAndExchangeBNode::memory_operand() const { return _opnds[1]; }
57042const MachOper* compareAndExchangeSNode::memory_operand() const { return _opnds[1]; }
57043const MachOper* compareAndExchangeINode::memory_operand() const { return _opnds[1]; }
57044const MachOper* compareAndExchangeLNode::memory_operand() const { return _opnds[1]; }
57045const MachOper* compareAndExchangeNNode::memory_operand() const { return _opnds[1]; }
57046const MachOper* compareAndExchangePNode::memory_operand() const { return _opnds[1]; }
57047const MachOper* xaddB_no_resNode::memory_operand() const { return _opnds[1]; }
57048const MachOper* xaddBNode::memory_operand() const { return _opnds[1]; }
57049const MachOper* xaddS_no_resNode::memory_operand() const { return _opnds[1]; }
57050const MachOper* xaddSNode::memory_operand() const { return _opnds[1]; }
57051const MachOper* xaddI_no_resNode::memory_operand() const { return _opnds[1]; }
57052const MachOper* xaddINode::memory_operand() const { return _opnds[1]; }
57053const MachOper* xaddL_no_resNode::memory_operand() const { return _opnds[1]; }
57054const MachOper* xaddLNode::memory_operand() const { return _opnds[1]; }
57055const MachOper* xchgBNode::memory_operand() const { return _opnds[1]; }
57056const MachOper* xchgSNode::memory_operand() const { return _opnds[1]; }
57057const MachOper* xchgINode::memory_operand() const { return _opnds[1]; }
57058const MachOper* xchgLNode::memory_operand() const { return _opnds[1]; }
57059const MachOper* xchgPNode::memory_operand() const { return _opnds[1]; }
57060const MachOper* xchgNNode::memory_operand() const { return _opnds[1]; }
57061const MachOper* subI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57062const MachOper* subI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57063const MachOper* subI_mem_immNode::memory_operand() const { return _opnds[1]; }
57064const MachOper* subL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57065const MachOper* subL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57066const MachOper* subL_mem_immNode::memory_operand() const { return _opnds[1]; }
57067const MachOper* negI_memNode::memory_operand() const { return _opnds[1]; }
57068const MachOper* negL_memNode::memory_operand() const { return _opnds[1]; }
57069const MachOper* mulI_memNode::memory_operand() const { return _opnds[2]; }
57070const MachOper* mulI_mem_0Node::memory_operand() const { return _opnds[1]; }
57071const MachOper* mulI_mem_immNode::memory_operand() const { return _opnds[1]; }
57072const MachOper* mulL_memNode::memory_operand() const { return _opnds[2]; }
57073const MachOper* mulL_mem_0Node::memory_operand() const { return _opnds[1]; }
57074const MachOper* mulL_mem_immNode::memory_operand() const { return _opnds[1]; }
57075const MachOper* salI_mem_1Node::memory_operand() const { return _opnds[1]; }
57076const MachOper* salI_mem_immNode::memory_operand() const { return _opnds[1]; }
57077const MachOper* salI_mem_CLNode::memory_operand() const { return _opnds[1]; }
57078const MachOper* sarI_mem_1Node::memory_operand() const { return _opnds[1]; }
57079const MachOper* sarI_mem_immNode::memory_operand() const { return _opnds[1]; }
57080const MachOper* sarI_mem_CLNode::memory_operand() const { return _opnds[1]; }
57081const MachOper* shrI_mem_1Node::memory_operand() const { return _opnds[1]; }
57082const MachOper* shrI_mem_immNode::memory_operand() const { return _opnds[1]; }
57083const MachOper* shrI_mem_CLNode::memory_operand() const { return _opnds[1]; }
57084const MachOper* salL_mem_1Node::memory_operand() const { return _opnds[1]; }
57085const MachOper* salL_mem_immNode::memory_operand() const { return _opnds[1]; }
57086const MachOper* salL_mem_CLNode::memory_operand() const { return _opnds[1]; }
57087const MachOper* sarL_mem_1Node::memory_operand() const { return _opnds[1]; }
57088const MachOper* sarL_mem_immNode::memory_operand() const { return _opnds[1]; }
57089const MachOper* sarL_mem_CLNode::memory_operand() const { return _opnds[1]; }
57090const MachOper* shrL_mem_1Node::memory_operand() const { return _opnds[1]; }
57091const MachOper* shrL_mem_immNode::memory_operand() const { return _opnds[1]; }
57092const MachOper* shrL_mem_CLNode::memory_operand() const { return _opnds[1]; }
57093const MachOper* andI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57094const MachOper* andI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57095const MachOper* andB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57096const MachOper* andB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57097const MachOper* andI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57098const MachOper* andI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57099const MachOper* andI_mem_immNode::memory_operand() const { return _opnds[1]; }
57100const MachOper* andnI_rReg_rReg_memNode::memory_operand() const { return _opnds[3]; }
57101const MachOper* andnI_rReg_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57102const MachOper* blsiI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57103const MachOper* blsiI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57104const MachOper* blsmskI_rReg_memNode::memory_operand() const { return _opnds[1]; }
57105const MachOper* blsmskI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57106const MachOper* blsrI_rReg_memNode::memory_operand() const { return _opnds[1]; }
57107const MachOper* blsrI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57108const MachOper* orI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57109const MachOper* orI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57110const MachOper* orB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57111const MachOper* orB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57112const MachOper* orI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57113const MachOper* orI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57114const MachOper* orI_mem_immNode::memory_operand() const { return _opnds[1]; }
57115const MachOper* xorI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57116const MachOper* xorI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57117const MachOper* xorB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57118const MachOper* xorB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57119const MachOper* xorI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57120const MachOper* xorI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57121const MachOper* xorI_mem_immNode::memory_operand() const { return _opnds[1]; }
57122const MachOper* andL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57123const MachOper* andL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57124const MachOper* andL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57125const MachOper* andL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57126const MachOper* andL_mem_immNode::memory_operand() const { return _opnds[1]; }
57127const MachOper* andnL_rReg_rReg_memNode::memory_operand() const { return _opnds[3]; }
57128const MachOper* andnL_rReg_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57129const MachOper* blsiL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57130const MachOper* blsiL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57131const MachOper* blsmskL_rReg_memNode::memory_operand() const { return _opnds[1]; }
57132const MachOper* blsmskL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57133const MachOper* blsrL_rReg_memNode::memory_operand() const { return _opnds[1]; }
57134const MachOper* blsrL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57135const MachOper* orL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57136const MachOper* orL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57137const MachOper* orL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57138const MachOper* orL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57139const MachOper* orL_mem_immNode::memory_operand() const { return _opnds[1]; }
57140const MachOper* xorL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57141const MachOper* xorL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
57142const MachOper* xorL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
57143const MachOper* xorL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
57144const MachOper* xorL_mem_immNode::memory_operand() const { return _opnds[1]; }
57145const MachOper* cmpF_cc_memNode::memory_operand() const { return _opnds[2]; }
57146const MachOper* cmpF_cc_memCFNode::memory_operand() const { return _opnds[2]; }
57147const MachOper* cmpD_cc_memNode::memory_operand() const { return _opnds[2]; }
57148const MachOper* cmpD_cc_memCFNode::memory_operand() const { return _opnds[2]; }
57149const MachOper* cmpF_memNode::memory_operand() const { return _opnds[2]; }
57150const MachOper* cmpD_memNode::memory_operand() const { return _opnds[2]; }
57151const MachOper* convF2D_reg_memNode::memory_operand() const { return _opnds[1]; }
57152const MachOper* convD2F_reg_memNode::memory_operand() const { return _opnds[1]; }
57153const MachOper* convI2F_reg_memNode::memory_operand() const { return _opnds[1]; }
57154const MachOper* convI2D_reg_memNode::memory_operand() const { return _opnds[1]; }
57155const MachOper* convL2F_reg_memNode::memory_operand() const { return _opnds[1]; }
57156const MachOper* convL2D_reg_memNode::memory_operand() const { return _opnds[1]; }
57157const MachOper* convI2L_reg_mem_zexNode::memory_operand() const { return _opnds[1]; }
57158const MachOper* compI_rReg_memNode::memory_operand() const { return _opnds[2]; }
57159const MachOper* testI_reg_memNode::memory_operand() const { return _opnds[2]; }
57160const MachOper* testI_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57161const MachOper* compU_rReg_memNode::memory_operand() const { return _opnds[2]; }
57162const MachOper* compP_rReg_memNode::memory_operand() const { return _opnds[2]; }
57163const MachOper* compP_mem_rRegNode::memory_operand() const { return _opnds[2]; }
57164const MachOper* testP_memNode::memory_operand() const { return _opnds[1]; }
57165const MachOper* testP_mem_reg0Node::memory_operand() const { return _opnds[1]; }
57166const MachOper* compN_rReg_memNode::memory_operand() const { return _opnds[2]; }
57167const MachOper* compN_mem_immNode::memory_operand() const { return _opnds[2]; }
57168const MachOper* compN_mem_imm_klassNode::memory_operand() const { return _opnds[2]; }
57169const MachOper* testN_memNode::memory_operand() const { return _opnds[1]; }
57170const MachOper* testN_mem_reg0Node::memory_operand() const { return _opnds[1]; }
57171const MachOper* compL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57172const MachOper* testL_reg_memNode::memory_operand() const { return _opnds[2]; }
57173const MachOper* testL_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57174const MachOper* testL_reg_mem2Node::memory_operand() const { return _opnds[2]; }
57175const MachOper* testL_reg_mem2_0Node::memory_operand() const { return _opnds[1]; }
57176const MachOper* compUL_rReg_memNode::memory_operand() const { return _opnds[2]; }
57177const MachOper* compB_mem_immNode::memory_operand() const { return _opnds[1]; }
57178const MachOper* testUB_mem_immNode::memory_operand() const { return _opnds[1]; }
57179const MachOper* testB_mem_immNode::memory_operand() const { return _opnds[1]; }
57180const MachOper* addF_memNode::memory_operand() const { return _opnds[2]; }
57181const MachOper* addF_mem_0Node::memory_operand() const { return _opnds[1]; }
57182const MachOper* addF_reg_memNode::memory_operand() const { return _opnds[2]; }
57183const MachOper* addF_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57184const MachOper* addD_memNode::memory_operand() const { return _opnds[2]; }
57185const MachOper* addD_mem_0Node::memory_operand() const { return _opnds[1]; }
57186const MachOper* addD_reg_memNode::memory_operand() const { return _opnds[2]; }
57187const MachOper* addD_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57188const MachOper* subF_memNode::memory_operand() const { return _opnds[2]; }
57189const MachOper* subF_reg_memNode::memory_operand() const { return _opnds[2]; }
57190const MachOper* subD_memNode::memory_operand() const { return _opnds[2]; }
57191const MachOper* subD_reg_memNode::memory_operand() const { return _opnds[2]; }
57192const MachOper* mulF_memNode::memory_operand() const { return _opnds[2]; }
57193const MachOper* mulF_mem_0Node::memory_operand() const { return _opnds[1]; }
57194const MachOper* mulF_reg_memNode::memory_operand() const { return _opnds[2]; }
57195const MachOper* mulF_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57196const MachOper* mulD_memNode::memory_operand() const { return _opnds[2]; }
57197const MachOper* mulD_mem_0Node::memory_operand() const { return _opnds[1]; }
57198const MachOper* mulD_reg_memNode::memory_operand() const { return _opnds[2]; }
57199const MachOper* mulD_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
57200const MachOper* divF_memNode::memory_operand() const { return _opnds[2]; }
57201const MachOper* divF_reg_memNode::memory_operand() const { return _opnds[2]; }
57202const MachOper* divD_memNode::memory_operand() const { return _opnds[2]; }
57203const MachOper* divD_reg_memNode::memory_operand() const { return _opnds[2]; }
57204const MachOper* sqrtF_memNode::memory_operand() const { return _opnds[1]; }
57205const MachOper* sqrtD_memNode::memory_operand() const { return _opnds[1]; }
57206const MachOper* loadV4Node::memory_operand() const { return _opnds[1]; }
57207const MachOper* loadV8Node::memory_operand() const { return _opnds[1]; }
57208const MachOper* loadV16Node::memory_operand() const { return _opnds[1]; }
57209const MachOper* loadV32Node::memory_operand() const { return _opnds[1]; }
57210const MachOper* loadV64_dwordNode::memory_operand() const { return _opnds[1]; }
57211const MachOper* loadV64_qwordNode::memory_operand() const { return _opnds[1]; }
57212const MachOper* storeV4Node::memory_operand() const { return _opnds[1]; }
57213const MachOper* storeV8Node::memory_operand() const { return _opnds[1]; }
57214const MachOper* storeV16Node::memory_operand() const { return _opnds[1]; }
57215const MachOper* storeV32Node::memory_operand() const { return _opnds[1]; }
57216const MachOper* storeV64_dwordNode::memory_operand() const { return _opnds[1]; }
57217const MachOper* storeV64_qwordNode::memory_operand() const { return _opnds[1]; }
57218const MachOper* Repl4S_memNode::memory_operand() const { return _opnds[1]; }
57219const MachOper* Repl8S_memNode::memory_operand() const { return _opnds[1]; }
57220const MachOper* Repl16S_memNode::memory_operand() const { return _opnds[1]; }
57221const MachOper* Repl32S_memNode::memory_operand() const { return _opnds[1]; }
57222const MachOper* Repl4I_memNode::memory_operand() const { return _opnds[1]; }
57223const MachOper* Repl8I_memNode::memory_operand() const { return _opnds[1]; }
57224const MachOper* Repl16I_memNode::memory_operand() const { return _opnds[1]; }
57225const MachOper* Repl2L_memNode::memory_operand() const { return _opnds[1]; }
57226const MachOper* Repl4L_memNode::memory_operand() const { return _opnds[1]; }
57227const MachOper* Repl8L_memNode::memory_operand() const { return _opnds[1]; }
57228const MachOper* Repl2F_memNode::memory_operand() const { return _opnds[1]; }
57229const MachOper* Repl4F_memNode::memory_operand() const { return _opnds[1]; }
57230const MachOper* Repl8F_memNode::memory_operand() const { return _opnds[1]; }
57231const MachOper* Repl16F_memNode::memory_operand() const { return _opnds[1]; }
57232const MachOper* Repl2D_memNode::memory_operand() const { return _opnds[1]; }
57233const MachOper* Repl4D_memNode::memory_operand() const { return _opnds[1]; }
57234const MachOper* Repl8D_memNode::memory_operand() const { return _opnds[1]; }
57235const MachOper* Repl2I_memNode::memory_operand() const { return _opnds[1]; }
57236const MachOper* Repl4B_mem_evexNode::memory_operand() const { return _opnds[1]; }
57237const MachOper* Repl8B_mem_evexNode::memory_operand() const { return _opnds[1]; }
57238const MachOper* Repl16B_mem_evexNode::memory_operand() const { return _opnds[1]; }
57239const MachOper* Repl32B_mem_evexNode::memory_operand() const { return _opnds[1]; }
57240const MachOper* Repl64B_mem_evexNode::memory_operand() const { return _opnds[1]; }
57241const MachOper* Repl4S_mem_evexNode::memory_operand() const { return _opnds[1]; }
57242const MachOper* Repl8S_mem_evexNode::memory_operand() const { return _opnds[1]; }
57243const MachOper* Repl16S_mem_evexNode::memory_operand() const { return _opnds[1]; }
57244const MachOper* Repl32S_mem_evexNode::memory_operand() const { return _opnds[1]; }
57245const MachOper* Repl4I_mem_evexNode::memory_operand() const { return _opnds[1]; }
57246const MachOper* Repl8I_mem_evexNode::memory_operand() const { return _opnds[1]; }
57247const MachOper* Repl16I_mem_evexNode::memory_operand() const { return _opnds[1]; }
57248const MachOper* Repl2L_mem_evexNode::memory_operand() const { return _opnds[1]; }
57249const MachOper* Repl4L_mem_evexNode::memory_operand() const { return _opnds[1]; }
57250const MachOper* Repl8L_mem_evexNode::memory_operand() const { return _opnds[1]; }
57251const MachOper* Repl8F_mem_evexNode::memory_operand() const { return _opnds[1]; }
57252const MachOper* Repl16F_mem_evexNode::memory_operand() const { return _opnds[1]; }
57253const MachOper* Repl4D_mem_evexNode::memory_operand() const { return _opnds[1]; }
57254const MachOper* Repl8D_mem_evexNode::memory_operand() const { return _opnds[1]; }
57255const MachOper* vadd4B_memNode::memory_operand() const { return _opnds[2]; }
57256const MachOper* vadd4B_mem_0Node::memory_operand() const { return _opnds[1]; }
57257const MachOper* vadd8B_memNode::memory_operand() const { return _opnds[2]; }
57258const MachOper* vadd8B_mem_0Node::memory_operand() const { return _opnds[1]; }
57259const MachOper* vadd16B_memNode::memory_operand() const { return _opnds[2]; }
57260const MachOper* vadd16B_mem_0Node::memory_operand() const { return _opnds[1]; }
57261const MachOper* vadd32B_memNode::memory_operand() const { return _opnds[2]; }
57262const MachOper* vadd32B_mem_0Node::memory_operand() const { return _opnds[1]; }
57263const MachOper* vadd64B_memNode::memory_operand() const { return _opnds[2]; }
57264const MachOper* vadd64B_mem_0Node::memory_operand() const { return _opnds[1]; }
57265const MachOper* vadd2S_memNode::memory_operand() const { return _opnds[2]; }
57266const MachOper* vadd2S_mem_0Node::memory_operand() const { return _opnds[1]; }
57267const MachOper* vadd4S_memNode::memory_operand() const { return _opnds[2]; }
57268const MachOper* vadd4S_mem_0Node::memory_operand() const { return _opnds[1]; }
57269const MachOper* vadd8S_memNode::memory_operand() const { return _opnds[2]; }
57270const MachOper* vadd8S_mem_0Node::memory_operand() const { return _opnds[1]; }
57271const MachOper* vadd16S_memNode::memory_operand() const { return _opnds[2]; }
57272const MachOper* vadd16S_mem_0Node::memory_operand() const { return _opnds[1]; }
57273const MachOper* vadd32S_memNode::memory_operand() const { return _opnds[2]; }
57274const MachOper* vadd32S_mem_0Node::memory_operand() const { return _opnds[1]; }
57275const MachOper* vadd2I_memNode::memory_operand() const { return _opnds[2]; }
57276const MachOper* vadd2I_mem_0Node::memory_operand() const { return _opnds[1]; }
57277const MachOper* vadd4I_memNode::memory_operand() const { return _opnds[2]; }
57278const MachOper* vadd4I_mem_0Node::memory_operand() const { return _opnds[1]; }
57279const MachOper* vadd8I_memNode::memory_operand() const { return _opnds[2]; }
57280const MachOper* vadd8I_mem_0Node::memory_operand() const { return _opnds[1]; }
57281const MachOper* vadd16I_memNode::memory_operand() const { return _opnds[2]; }
57282const MachOper* vadd16I_mem_0Node::memory_operand() const { return _opnds[1]; }
57283const MachOper* vadd2L_memNode::memory_operand() const { return _opnds[2]; }
57284const MachOper* vadd2L_mem_0Node::memory_operand() const { return _opnds[1]; }
57285const MachOper* vadd4L_memNode::memory_operand() const { return _opnds[2]; }
57286const MachOper* vadd4L_mem_0Node::memory_operand() const { return _opnds[1]; }
57287const MachOper* vadd8L_memNode::memory_operand() const { return _opnds[2]; }
57288const MachOper* vadd8L_mem_0Node::memory_operand() const { return _opnds[1]; }
57289const MachOper* vadd2F_memNode::memory_operand() const { return _opnds[2]; }
57290const MachOper* vadd2F_mem_0Node::memory_operand() const { return _opnds[1]; }
57291const MachOper* vadd4F_memNode::memory_operand() const { return _opnds[2]; }
57292const MachOper* vadd4F_mem_0Node::memory_operand() const { return _opnds[1]; }
57293const MachOper* vadd8F_memNode::memory_operand() const { return _opnds[2]; }
57294const MachOper* vadd8F_mem_0Node::memory_operand() const { return _opnds[1]; }
57295const MachOper* vadd16F_memNode::memory_operand() const { return _opnds[2]; }
57296const MachOper* vadd16F_mem_0Node::memory_operand() const { return _opnds[1]; }
57297const MachOper* vadd2D_memNode::memory_operand() const { return _opnds[2]; }
57298const MachOper* vadd2D_mem_0Node::memory_operand() const { return _opnds[1]; }
57299const MachOper* vadd4D_memNode::memory_operand() const { return _opnds[2]; }
57300const MachOper* vadd4D_mem_0Node::memory_operand() const { return _opnds[1]; }
57301const MachOper* vadd8D_memNode::memory_operand() const { return _opnds[2]; }
57302const MachOper* vadd8D_mem_0Node::memory_operand() const { return _opnds[1]; }
57303const MachOper* vsub4B_memNode::memory_operand() const { return _opnds[2]; }
57304const MachOper* vsub8B_memNode::memory_operand() const { return _opnds[2]; }
57305const MachOper* vsub16B_memNode::memory_operand() const { return _opnds[2]; }
57306const MachOper* vsub32B_memNode::memory_operand() const { return _opnds[2]; }
57307const MachOper* vsub64B_memNode::memory_operand() const { return _opnds[2]; }
57308const MachOper* vsub2S_memNode::memory_operand() const { return _opnds[2]; }
57309const MachOper* vsub4S_memNode::memory_operand() const { return _opnds[2]; }
57310const MachOper* vsub8S_memNode::memory_operand() const { return _opnds[2]; }
57311const MachOper* vsub16S_memNode::memory_operand() const { return _opnds[2]; }
57312const MachOper* vsub32S_memNode::memory_operand() const { return _opnds[2]; }
57313const MachOper* vsub2I_memNode::memory_operand() const { return _opnds[2]; }
57314const MachOper* vsub4I_memNode::memory_operand() const { return _opnds[2]; }
57315const MachOper* vsub8I_memNode::memory_operand() const { return _opnds[2]; }
57316const MachOper* vsub16I_memNode::memory_operand() const { return _opnds[2]; }
57317const MachOper* vsub2L_memNode::memory_operand() const { return _opnds[2]; }
57318const MachOper* vsub4L_memNode::memory_operand() const { return _opnds[2]; }
57319const MachOper* vsub8L_memNode::memory_operand() const { return _opnds[2]; }
57320const MachOper* vsub2F_memNode::memory_operand() const { return _opnds[2]; }
57321const MachOper* vsub4F_memNode::memory_operand() const { return _opnds[2]; }
57322const MachOper* vsub8F_memNode::memory_operand() const { return _opnds[2]; }
57323const MachOper* vsub16F_memNode::memory_operand() const { return _opnds[2]; }
57324const MachOper* vsub2D_memNode::memory_operand() const { return _opnds[2]; }
57325const MachOper* vsub4D_memNode::memory_operand() const { return _opnds[2]; }
57326const MachOper* vsub8D_memNode::memory_operand() const { return _opnds[2]; }
57327const MachOper* vmul2S_memNode::memory_operand() const { return _opnds[2]; }
57328const MachOper* vmul2S_mem_0Node::memory_operand() const { return _opnds[1]; }
57329const MachOper* vmul4S_memNode::memory_operand() const { return _opnds[2]; }
57330const MachOper* vmul4S_mem_0Node::memory_operand() const { return _opnds[1]; }
57331const MachOper* vmul8S_memNode::memory_operand() const { return _opnds[2]; }
57332const MachOper* vmul8S_mem_0Node::memory_operand() const { return _opnds[1]; }
57333const MachOper* vmul16S_memNode::memory_operand() const { return _opnds[2]; }
57334const MachOper* vmul16S_mem_0Node::memory_operand() const { return _opnds[1]; }
57335const MachOper* vmul32S_memNode::memory_operand() const { return _opnds[2]; }
57336const MachOper* vmul32S_mem_0Node::memory_operand() const { return _opnds[1]; }
57337const MachOper* vmul2I_memNode::memory_operand() const { return _opnds[2]; }
57338const MachOper* vmul2I_mem_0Node::memory_operand() const { return _opnds[1]; }
57339const MachOper* vmul4I_memNode::memory_operand() const { return _opnds[2]; }
57340const MachOper* vmul4I_mem_0Node::memory_operand() const { return _opnds[1]; }
57341const MachOper* vmul2L_memNode::memory_operand() const { return _opnds[2]; }
57342const MachOper* vmul2L_mem_0Node::memory_operand() const { return _opnds[1]; }
57343const MachOper* vmul4L_memNode::memory_operand() const { return _opnds[2]; }
57344const MachOper* vmul4L_mem_0Node::memory_operand() const { return _opnds[1]; }
57345const MachOper* vmul8L_memNode::memory_operand() const { return _opnds[2]; }
57346const MachOper* vmul8L_mem_0Node::memory_operand() const { return _opnds[1]; }
57347const MachOper* vmul8I_memNode::memory_operand() const { return _opnds[2]; }
57348const MachOper* vmul8I_mem_0Node::memory_operand() const { return _opnds[1]; }
57349const MachOper* vmul16I_memNode::memory_operand() const { return _opnds[2]; }
57350const MachOper* vmul16I_mem_0Node::memory_operand() const { return _opnds[1]; }
57351const MachOper* vmul2F_memNode::memory_operand() const { return _opnds[2]; }
57352const MachOper* vmul2F_mem_0Node::memory_operand() const { return _opnds[1]; }
57353const MachOper* vmul4F_memNode::memory_operand() const { return _opnds[2]; }
57354const MachOper* vmul4F_mem_0Node::memory_operand() const { return _opnds[1]; }
57355const MachOper* vmul8F_memNode::memory_operand() const { return _opnds[2]; }
57356const MachOper* vmul8F_mem_0Node::memory_operand() const { return _opnds[1]; }
57357const MachOper* vmul16F_memNode::memory_operand() const { return _opnds[2]; }
57358const MachOper* vmul16F_mem_0Node::memory_operand() const { return _opnds[1]; }
57359const MachOper* vmul2D_memNode::memory_operand() const { return _opnds[2]; }
57360const MachOper* vmul2D_mem_0Node::memory_operand() const { return _opnds[1]; }
57361const MachOper* vmul4D_memNode::memory_operand() const { return _opnds[2]; }
57362const MachOper* vmul4D_mem_0Node::memory_operand() const { return _opnds[1]; }
57363const MachOper* vmul8D_memNode::memory_operand() const { return _opnds[2]; }
57364const MachOper* vmul8D_mem_0Node::memory_operand() const { return _opnds[1]; }
57365const MachOper* vdiv2F_memNode::memory_operand() const { return _opnds[2]; }
57366const MachOper* vdiv4F_memNode::memory_operand() const { return _opnds[2]; }
57367const MachOper* vdiv8F_memNode::memory_operand() const { return _opnds[2]; }
57368const MachOper* vdiv16F_memNode::memory_operand() const { return _opnds[2]; }
57369const MachOper* vdiv2D_memNode::memory_operand() const { return _opnds[2]; }
57370const MachOper* vdiv4D_memNode::memory_operand() const { return _opnds[2]; }
57371const MachOper* vdiv8D_memNode::memory_operand() const { return _opnds[2]; }
57372const MachOper* vsqrt2D_memNode::memory_operand() const { return _opnds[1]; }
57373const MachOper* vsqrt4D_memNode::memory_operand() const { return _opnds[1]; }
57374const MachOper* vsqrt8D_memNode::memory_operand() const { return _opnds[1]; }
57375const MachOper* vsqrt2F_memNode::memory_operand() const { return _opnds[1]; }
57376const MachOper* vsqrt4F_memNode::memory_operand() const { return _opnds[1]; }
57377const MachOper* vsqrt8F_memNode::memory_operand() const { return _opnds[1]; }
57378const MachOper* vsqrt16F_memNode::memory_operand() const { return _opnds[1]; }
57379const MachOper* vand4B_memNode::memory_operand() const { return _opnds[2]; }
57380const MachOper* vand4B_mem_0Node::memory_operand() const { return _opnds[1]; }
57381const MachOper* vand8B_memNode::memory_operand() const { return _opnds[2]; }
57382const MachOper* vand8B_mem_0Node::memory_operand() const { return _opnds[1]; }
57383const MachOper* vand16B_memNode::memory_operand() const { return _opnds[2]; }
57384const MachOper* vand16B_mem_0Node::memory_operand() const { return _opnds[1]; }
57385const MachOper* vand32B_memNode::memory_operand() const { return _opnds[2]; }
57386const MachOper* vand32B_mem_0Node::memory_operand() const { return _opnds[1]; }
57387const MachOper* vand64B_memNode::memory_operand() const { return _opnds[2]; }
57388const MachOper* vand64B_mem_0Node::memory_operand() const { return _opnds[1]; }
57389const MachOper* vor4B_memNode::memory_operand() const { return _opnds[2]; }
57390const MachOper* vor4B_mem_0Node::memory_operand() const { return _opnds[1]; }
57391const MachOper* vor8B_memNode::memory_operand() const { return _opnds[2]; }
57392const MachOper* vor8B_mem_0Node::memory_operand() const { return _opnds[1]; }
57393const MachOper* vor16B_memNode::memory_operand() const { return _opnds[2]; }
57394const MachOper* vor16B_mem_0Node::memory_operand() const { return _opnds[1]; }
57395const MachOper* vor32B_memNode::memory_operand() const { return _opnds[2]; }
57396const MachOper* vor32B_mem_0Node::memory_operand() const { return _opnds[1]; }
57397const MachOper* vor64B_memNode::memory_operand() const { return _opnds[2]; }
57398const MachOper* vor64B_mem_0Node::memory_operand() const { return _opnds[1]; }
57399const MachOper* vxor4B_memNode::memory_operand() const { return _opnds[2]; }
57400const MachOper* vxor4B_mem_0Node::memory_operand() const { return _opnds[1]; }
57401const MachOper* vxor8B_memNode::memory_operand() const { return _opnds[2]; }
57402const MachOper* vxor8B_mem_0Node::memory_operand() const { return _opnds[1]; }
57403const MachOper* vxor16B_memNode::memory_operand() const { return _opnds[2]; }
57404const MachOper* vxor16B_mem_0Node::memory_operand() const { return _opnds[1]; }
57405const MachOper* vxor32B_memNode::memory_operand() const { return _opnds[2]; }
57406const MachOper* vxor32B_mem_0Node::memory_operand() const { return _opnds[1]; }
57407const MachOper* vxor64B_memNode::memory_operand() const { return _opnds[2]; }
57408const MachOper* vxor64B_mem_0Node::memory_operand() const { return _opnds[1]; }
57409const MachOper* vfma2D_memNode::memory_operand() const { return _opnds[3]; }
57410const MachOper* vfma4D_memNode::memory_operand() const { return _opnds[3]; }
57411const MachOper* vfma8D_memNode::memory_operand() const { return _opnds[3]; }
57412const MachOper* vfma4F_memNode::memory_operand() const { return _opnds[3]; }
57413const MachOper* vfma8F_memNode::memory_operand() const { return _opnds[3]; }
57414const MachOper* vfma16F_memNode::memory_operand() const { return _opnds[3]; }
57415const MachOper* compareAndSwapP_shenandoahNode::memory_operand() const { return _opnds[1]; }
57416const MachOper* compareAndSwapP_shenandoah_0Node::memory_operand() const { return _opnds[1]; }
57417const MachOper* compareAndSwapN_shenandoahNode::memory_operand() const { return _opnds[1]; }
57418const MachOper* compareAndSwapN_shenandoah_0Node::memory_operand() const { return _opnds[1]; }
57419const MachOper* compareAndExchangeN_shenandoahNode::memory_operand() const { return _opnds[1]; }
57420const MachOper* compareAndExchangeP_shenandoahNode::memory_operand() const { return _opnds[1]; }
57421const MachOper* zLoadBarrierSlowRegXmmAndYmmNode::memory_operand() const { return _opnds[1]; }
57422const MachOper* zLoadBarrierSlowRegZmmNode::memory_operand() const { return _opnds[1]; }
57423const MachOper* zLoadBarrierWeakSlowRegXmmAndYmmNode::memory_operand() const { return _opnds[1]; }
57424const MachOper* zLoadBarrierWeakSlowRegZmmNode::memory_operand() const { return _opnds[1]; }
57425const MachOper* z_compareAndExchangePNode::memory_operand() const { return _opnds[1]; }
57426const MachOper* z_compareAndSwapPNode::memory_operand() const { return _opnds[1]; }
57427const MachOper* z_compareAndSwapP_0Node::memory_operand() const { return _opnds[1]; }
57428const MachOper* z_xchgPNode::memory_operand() const { return _opnds[1]; }
57429
57430
57431const bool Matcher::has_match_rule(int opcode) {
57432 assert(_last_machine_leaf < opcode && opcode < _last_opcode, "opcode in range");
57433 return _hasMatchRule[opcode];
57434}
57435
57436const bool Matcher::_hasMatchRule[_last_opcode] = {
57437 false, // Node
57438 false, // Set
57439 false, // RegN
57440 false, // RegI
57441 false, // RegP
57442 false, // RegF
57443 false, // RegD
57444 false, // RegL
57445 false, // RegFlags
57446 false, // VecS
57447 false, // VecD
57448 false, // VecX
57449 false, // VecY
57450 false, // VecZ
57451 false, // _last_machine_leaf
57452 true , // AbsD
57453 true , // AbsF
57454 true , // AbsI
57455 true , // AbsL
57456 true , // AddD
57457 true , // AddF
57458 true , // AddI
57459 true , // AddL
57460 true , // AddP
57461 false, // Allocate
57462 false, // AllocateArray
57463 true , // AndI
57464 true , // AndL
57465 false, // ArrayCopy
57466 true , // AryEq
57467 false, // AtanD
57468 true , // Binary
57469 true , // Bool
57470 false, // BoxLock
57471 true , // ReverseBytesI
57472 true , // ReverseBytesL
57473 true , // ReverseBytesUS
57474 true , // ReverseBytesS
57475 false, // CProj
57476 true , // CallDynamicJava
57477 false, // CallJava
57478 true , // CallLeaf
57479 true , // CallLeafNoFP
57480 true , // CallRuntime
57481 true , // CallStaticJava
57482 true , // CastII
57483 true , // CastX2P
57484 true , // CastP2X
57485 true , // CastPP
57486 false, // Catch
57487 false, // CatchProj
57488 true , // CheckCastPP
57489 true , // ClearArray
57490 false, // ConstraintCast
57491 true , // CMoveD
57492 true , // CMoveVD
57493 true , // CMoveF
57494 true , // CMoveVF
57495 true , // CMoveI
57496 true , // CMoveL
57497 true , // CMoveP
57498 true , // CMoveN
57499 true , // CmpN
57500 true , // CmpD
57501 true , // CmpD3
57502 true , // CmpF
57503 true , // CmpF3
57504 true , // CmpI
57505 true , // CmpL
57506 true , // CmpL3
57507 true , // CmpLTMask
57508 true , // CmpP
57509 true , // CmpU
57510 true , // CmpUL
57511 true , // CompareAndSwapB
57512 true , // CompareAndSwapS
57513 true , // CompareAndSwapI
57514 true , // CompareAndSwapL
57515 true , // CompareAndSwapP
57516 true , // CompareAndSwapN
57517 true , // WeakCompareAndSwapB
57518 true , // WeakCompareAndSwapS
57519 true , // WeakCompareAndSwapI
57520 true , // WeakCompareAndSwapL
57521 true , // WeakCompareAndSwapP
57522 true , // WeakCompareAndSwapN
57523 true , // CompareAndExchangeB
57524 true , // CompareAndExchangeS
57525 true , // CompareAndExchangeI
57526 true , // CompareAndExchangeL
57527 true , // CompareAndExchangeP
57528 true , // CompareAndExchangeN
57529 true , // GetAndAddB
57530 true , // GetAndAddS
57531 true , // GetAndAddI
57532 true , // GetAndAddL
57533 true , // GetAndSetB
57534 true , // GetAndSetS
57535 true , // GetAndSetI
57536 true , // GetAndSetL
57537 true , // GetAndSetP
57538 true , // GetAndSetN
57539 false, // Con
57540 true , // ConN
57541 true , // ConNKlass
57542 true , // ConD
57543 true , // ConF
57544 true , // ConI
57545 true , // ConL
57546 true , // ConP
57547 true , // Conv2B
57548 true , // ConvD2F
57549 true , // ConvD2I
57550 true , // ConvD2L
57551 true , // ConvF2D
57552 true , // ConvF2I
57553 true , // ConvF2L
57554 true , // ConvI2D
57555 true , // ConvI2F
57556 true , // ConvI2L
57557 true , // ConvL2D
57558 true , // ConvL2F
57559 true , // ConvL2I
57560 false, // CountedLoop
57561 true , // CountedLoopEnd
57562 false, // OuterStripMinedLoop
57563 false, // OuterStripMinedLoopEnd
57564 true , // CountLeadingZerosI
57565 true , // CountLeadingZerosL
57566 true , // CountTrailingZerosI
57567 true , // CountTrailingZerosL
57568 true , // CreateEx
57569 true , // DecodeN
57570 true , // DecodeNKlass
57571 true , // DivD
57572 true , // DivF
57573 true , // DivI
57574 true , // DivL
57575 false, // DivMod
57576 true , // DivModI
57577 true , // DivModL
57578 true , // EncodeISOArray
57579 true , // EncodeP
57580 true , // EncodePKlass
57581 true , // FastLock
57582 true , // FastUnlock
57583 true , // FmaD
57584 true , // FmaF
57585 true , // Goto
57586 true , // Halt
57587 true , // HasNegatives
57588 true , // If
57589 false, // RangeCheck
57590 false, // IfFalse
57591 false, // IfTrue
57592 false, // Initialize
57593 false, // JProj
57594 true , // Jump
57595 false, // JumpProj
57596 true , // LShiftI
57597 true , // LShiftL
57598 true , // LoadB
57599 true , // LoadUB
57600 true , // LoadUS
57601 true , // LoadD
57602 false, // LoadD_unaligned
57603 true , // LoadF
57604 true , // LoadI
57605 true , // LoadKlass
57606 true , // LoadNKlass
57607 true , // LoadL
57608 false, // LoadL_unaligned
57609 true , // LoadPLocked
57610 true , // LoadP
57611 true , // LoadN
57612 true , // LoadRange
57613 true , // LoadS
57614 false, // LoadBarrier
57615 true , // LoadBarrierSlowReg
57616 true , // ZCompareAndSwapP
57617 true , // ZWeakCompareAndSwapP
57618 true , // ZCompareAndExchangeP
57619 true , // ZGetAndSetP
57620 false, // Lock
57621 false, // Loop
57622 false, // LoopLimit
57623 false, // Mach
57624 false, // MachProj
57625 true , // MulAddS2I
57626 true , // MaxD
57627 true , // MaxF
57628 true , // MaxI
57629 true , // MemBarAcquire
57630 true , // LoadFence
57631 true , // SetVectMaskI
57632 true , // MemBarAcquireLock
57633 false, // MemBarCPUOrder
57634 true , // MemBarRelease
57635 true , // StoreFence
57636 true , // MemBarReleaseLock
57637 true , // MemBarVolatile
57638 true , // MemBarStoreStore
57639 false, // MergeMem
57640 true , // MinD
57641 true , // MinF
57642 true , // MinI
57643 false, // ModD
57644 false, // ModF
57645 true , // ModI
57646 true , // ModL
57647 true , // MoveI2F
57648 true , // MoveF2I
57649 true , // MoveL2D
57650 true , // MoveD2L
57651 true , // MulD
57652 true , // MulF
57653 true , // MulHiL
57654 true , // MulI
57655 true , // MulL
57656 false, // Multi
57657 true , // NegD
57658 true , // NegF
57659 false, // NeverBranch
57660 true , // OnSpinWait
57661 false, // Opaque1
57662 false, // Opaque2
57663 false, // Opaque3
57664 false, // Opaque4
57665 false, // ProfileBoolean
57666 true , // OrI
57667 true , // OrL
57668 true , // OverflowAddI
57669 true , // OverflowSubI
57670 true , // OverflowMulI
57671 true , // OverflowAddL
57672 true , // OverflowSubL
57673 true , // OverflowMulL
57674 false, // PCTable
57675 false, // Parm
57676 true , // PartialSubtypeCheck
57677 false, // Phi
57678 true , // PopCountI
57679 true , // PopCountL
57680 true , // PopCountVI
57681 true , // PrefetchAllocation
57682 false, // Proj
57683 true , // RShiftI
57684 true , // RShiftL
57685 false, // Region
57686 true , // Rethrow
57687 true , // Return
57688 false, // Root
57689 true , // RoundDouble
57690 true , // RoundFloat
57691 true , // SafePoint
57692 false, // SafePointScalarObject
57693 true , // ShenandoahCompareAndExchangeP
57694 true , // ShenandoahCompareAndExchangeN
57695 true , // ShenandoahCompareAndSwapN
57696 true , // ShenandoahCompareAndSwapP
57697 true , // ShenandoahWeakCompareAndSwapN
57698 true , // ShenandoahWeakCompareAndSwapP
57699 false, // ShenandoahEnqueueBarrier
57700 false, // ShenandoahLoadReferenceBarrier
57701 false, // SCMemProj
57702 true , // SqrtD
57703 true , // SqrtF
57704 false, // Start
57705 false, // StartOSR
57706 true , // StoreB
57707 true , // StoreC
57708 true , // StoreCM
57709 true , // StorePConditional
57710 true , // StoreIConditional
57711 true , // StoreLConditional
57712 true , // StoreD
57713 true , // StoreF
57714 true , // StoreI
57715 true , // StoreL
57716 true , // StoreP
57717 true , // StoreN
57718 true , // StoreNKlass
57719 true , // StrComp
57720 true , // StrCompressedCopy
57721 true , // StrEquals
57722 true , // StrIndexOf
57723 true , // StrIndexOfChar
57724 true , // StrInflatedCopy
57725 true , // SubD
57726 true , // SubF
57727 true , // SubI
57728 true , // SubL
57729 true , // TailCall
57730 true , // TailJump
57731 true , // ThreadLocal
57732 false, // Unlock
57733 true , // URShiftI
57734 true , // URShiftL
57735 true , // XorI
57736 true , // XorL
57737 false, // Vector
57738 true , // AddVB
57739 true , // AddVS
57740 true , // AddVI
57741 true , // AddReductionVI
57742 true , // AddVL
57743 true , // AddReductionVL
57744 true , // AddVF
57745 true , // AddReductionVF
57746 true , // AddVD
57747 true , // AddReductionVD
57748 true , // SubVB
57749 true , // SubVS
57750 true , // SubVI
57751 true , // SubVL
57752 true , // SubVF
57753 true , // SubVD
57754 true , // MulVB
57755 true , // MulVS
57756 true , // MulVI
57757 true , // MulReductionVI
57758 true , // MulVL
57759 true , // MulReductionVL
57760 true , // MulVF
57761 true , // MulReductionVF
57762 true , // MulVD
57763 true , // MulReductionVD
57764 true , // MulAddVS2VI
57765 true , // FmaVD
57766 true , // FmaVF
57767 true , // DivVF
57768 true , // DivVD
57769 true , // AbsVB
57770 true , // AbsVS
57771 true , // AbsVI
57772 true , // AbsVL
57773 true , // AbsVF
57774 true , // AbsVD
57775 true , // NegVF
57776 true , // NegVD
57777 true , // SqrtVD
57778 true , // SqrtVF
57779 true , // LShiftCntV
57780 true , // RShiftCntV
57781 true , // LShiftVB
57782 true , // LShiftVS
57783 true , // LShiftVI
57784 true , // LShiftVL
57785 true , // RShiftVB
57786 true , // RShiftVS
57787 true , // RShiftVI
57788 true , // RShiftVL
57789 true , // URShiftVB
57790 true , // URShiftVS
57791 true , // URShiftVI
57792 true , // URShiftVL
57793 true , // AndV
57794 true , // OrV
57795 true , // XorV
57796 false, // MinV
57797 false, // MaxV
57798 false, // MinReductionV
57799 false, // MaxReductionV
57800 true , // LoadVector
57801 true , // StoreVector
57802 false, // Pack
57803 false, // PackB
57804 false, // PackS
57805 false, // PackI
57806 false, // PackL
57807 false, // PackF
57808 false, // PackD
57809 false, // Pack2L
57810 false, // Pack2D
57811 true , // ReplicateB
57812 true , // ReplicateS
57813 true , // ReplicateI
57814 true , // ReplicateL
57815 true , // ReplicateF
57816 true , // ReplicateD
57817 false, // Extract
57818 false, // ExtractB
57819 false, // ExtractUB
57820 false, // ExtractC
57821 false, // ExtractS
57822 false, // ExtractI
57823 false, // ExtractL
57824 false, // ExtractF
57825 false, // ExtractD
57826 false, // Digit
57827 false, // LowerCase
57828 false, // UpperCase
57829 false // Whitespace
57830};
57831
57832
57833bool Matcher::stack_direction() const { return false; }
57834
57835int Compile::sync_stack_slots() const { return 2; }
57836
57837uint Matcher::stack_alignment_in_bytes() { return StackAlignmentInBytes; }
57838
57839OptoReg::Name Matcher::return_addr() const { return OptoReg::stack2reg(- 2 +
57840 align_up((Compile::current()->in_preserve_stack_slots() +
57841 Compile::current()->fixed_slots()),
57842 stack_alignment_in_slots())); }
57843
57844uint Compile::in_preserve_stack_slots() { return 4 + 2 * VerifyStackAtCalls; }
57845
57846uint Compile::out_preserve_stack_slots() { return SharedRuntime::out_preserve_stack_slots(); }
57847
57848uint Compile::varargs_C_out_slots_killed() const { return frame::arg_reg_save_area_bytes/BytesPerInt; }
57849
57850void Matcher::calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length, bool is_outgoing) {
57851
57852#line 2832 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
57853
57854 // No difference between ingoing/outgoing just pass false
57855 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
57856
57857#line 57857 "ad_x86.cpp"
57858
57859}
57860
57861void Matcher::c_calling_convention(BasicType *sig_bt, VMRegPair *regs, uint length) {
57862
57863#line 2838 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
57864
57865 // This is obviously always outgoing
57866 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
57867
57868#line 57868 "ad_x86.cpp"
57869
57870}
57871
57872OptoRegPair Matcher::return_value(uint ideal_reg, bool is_outgoing) {
57873
57874#line 2845 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
57875
57876 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
57877 "only return normal values");
57878
57879 static const int lo[Op_RegL + 1] = {
57880 0,
57881 0,
57882 RAX_num, // Op_RegN
57883 RAX_num, // Op_RegI
57884 RAX_num, // Op_RegP
57885 XMM0_num, // Op_RegF
57886 XMM0_num, // Op_RegD
57887 RAX_num // Op_RegL
57888 };
57889 static const int hi[Op_RegL + 1] = {
57890 0,
57891 0,
57892 OptoReg::Bad, // Op_RegN
57893 OptoReg::Bad, // Op_RegI
57894 RAX_H_num, // Op_RegP
57895 OptoReg::Bad, // Op_RegF
57896 XMM0b_num, // Op_RegD
57897 RAX_H_num // Op_RegL
57898 };
57899 // Excluded flags and vector registers.
57900 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
57901 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
57902
57903#line 57903 "ad_x86.cpp"
57904
57905}
57906
57907OptoRegPair Matcher::c_return_value(uint ideal_reg, bool is_outgoing) {
57908
57909#line 2845 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad"
57910
57911 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
57912 "only return normal values");
57913
57914 static const int lo[Op_RegL + 1] = {
57915 0,
57916 0,
57917 RAX_num, // Op_RegN
57918 RAX_num, // Op_RegI
57919 RAX_num, // Op_RegP
57920 XMM0_num, // Op_RegF
57921 XMM0_num, // Op_RegD
57922 RAX_num // Op_RegL
57923 };
57924 static const int hi[Op_RegL + 1] = {
57925 0,
57926 0,
57927 OptoReg::Bad, // Op_RegN
57928 OptoReg::Bad, // Op_RegI
57929 RAX_H_num, // Op_RegP
57930 OptoReg::Bad, // Op_RegF
57931 XMM0b_num, // Op_RegD
57932 RAX_H_num // Op_RegL
57933 };
57934 // Excluded flags and vector registers.
57935 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
57936 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
57937
57938#line 57938 "ad_x86.cpp"
57939
57940}
57941
57942OptoReg::Name Matcher::inline_cache_reg() { return OptoReg::Name(RAX_num); }
57943
57944int Matcher::inline_cache_reg_encode() { return _regEncode[inline_cache_reg()]; }
57945
57946OptoReg::Name Matcher::interpreter_method_oop_reg() { return OptoReg::Name(RBX_num); }
57947
57948int Matcher::interpreter_method_oop_reg_encode() { return _regEncode[interpreter_method_oop_reg()]; }
57949
57950OptoReg::Name Matcher::interpreter_frame_pointer_reg() { return OptoReg::Name(RBP_num); }
57951
57952OptoReg::Name Matcher::c_frame_pointer() const { return OptoReg::Name(RSP_num); }
57953
57954// Number of callee-save + always-save registers
57955int Matcher::number_of_saved_registers() {
57956 return 0;
57957};
57958
57959bool Compile::needs_clone_jvms() { return false; }
57960
57961// Check consistency of C++ compilation with ADLC options:
57962// Check adlc -DLINUX=1
57963#ifndef LINUX
57964# error "LINUX must be defined"
57965#endif // LINUX
57966// Check adlc -D_GNU_SOURCE=1
57967#ifndef _GNU_SOURCE
57968# error "_GNU_SOURCE must be defined"
57969#endif // _GNU_SOURCE
57970// Check adlc -DAMD64=1
57971#ifndef AMD64
57972# error "AMD64 must be defined"
57973#endif // AMD64
57974// Check adlc -D_LP64=1
57975#ifndef _LP64
57976# error "_LP64 must be defined"
57977#endif // _LP64
57978